1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2 /* 3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc. 4 * Copyright (c) 2014, Synopsys, Inc. 5 * All rights reserved 6 */ 7 8 #include <linux/interrupt.h> 9 #include <linux/module.h> 10 #include <linux/kmod.h> 11 #include <linux/mdio.h> 12 #include <linux/phy.h> 13 #include <linux/of.h> 14 #include <linux/bitops.h> 15 #include <linux/jiffies.h> 16 17 #include "xgbe.h" 18 #include "xgbe-common.h" 19 20 static int xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata, 21 struct ethtool_eeprom *eeprom, u8 *data) 22 { 23 if (!pdata->phy_if.phy_impl.module_eeprom) 24 return -ENXIO; 25 26 return pdata->phy_if.phy_impl.module_eeprom(pdata, eeprom, data); 27 } 28 29 static int xgbe_phy_module_info(struct xgbe_prv_data *pdata, 30 struct ethtool_modinfo *modinfo) 31 { 32 if (!pdata->phy_if.phy_impl.module_info) 33 return -ENXIO; 34 35 return pdata->phy_if.phy_impl.module_info(pdata, modinfo); 36 } 37 38 static void xgbe_an37_clear_interrupts(struct xgbe_prv_data *pdata) 39 { 40 int reg; 41 42 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT); 43 reg &= ~XGBE_AN_CL37_INT_MASK; 44 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg); 45 } 46 47 static void xgbe_an37_disable_interrupts(struct xgbe_prv_data *pdata) 48 { 49 int reg; 50 51 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); 52 reg &= ~XGBE_AN_CL37_INT_MASK; 53 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); 54 55 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL); 56 reg &= ~XGBE_PCS_CL37_BP; 57 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg); 58 } 59 60 static void xgbe_an37_enable_interrupts(struct xgbe_prv_data *pdata) 61 { 62 int reg; 63 64 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL); 65 reg |= XGBE_PCS_CL37_BP; 66 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg); 67 68 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); 69 reg |= XGBE_AN_CL37_INT_MASK; 70 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); 71 } 72 73 static void xgbe_an73_clear_interrupts(struct xgbe_prv_data *pdata) 74 { 75 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0); 76 } 77 78 static void xgbe_an73_disable_interrupts(struct xgbe_prv_data *pdata) 79 { 80 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0); 81 } 82 83 static void xgbe_an73_enable_interrupts(struct xgbe_prv_data *pdata) 84 { 85 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, XGBE_AN_CL73_INT_MASK); 86 } 87 88 static void xgbe_an_enable_interrupts(struct xgbe_prv_data *pdata) 89 { 90 switch (pdata->an_mode) { 91 case XGBE_AN_MODE_CL73: 92 case XGBE_AN_MODE_CL73_REDRV: 93 xgbe_an73_enable_interrupts(pdata); 94 break; 95 case XGBE_AN_MODE_CL37: 96 case XGBE_AN_MODE_CL37_SGMII: 97 xgbe_an37_enable_interrupts(pdata); 98 break; 99 default: 100 break; 101 } 102 } 103 104 static void xgbe_an_clear_interrupts_all(struct xgbe_prv_data *pdata) 105 { 106 xgbe_an73_clear_interrupts(pdata); 107 xgbe_an37_clear_interrupts(pdata); 108 } 109 110 static void xgbe_kr_mode(struct xgbe_prv_data *pdata) 111 { 112 /* Set MAC to 10G speed */ 113 pdata->hw_if.set_speed(pdata, SPEED_10000); 114 115 /* Call PHY implementation support to complete rate change */ 116 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KR); 117 } 118 119 static void xgbe_kx_2500_mode(struct xgbe_prv_data *pdata) 120 { 121 /* Set MAC to 2.5G speed */ 122 pdata->hw_if.set_speed(pdata, SPEED_2500); 123 124 /* Call PHY implementation support to complete rate change */ 125 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_2500); 126 } 127 128 static void xgbe_kx_1000_mode(struct xgbe_prv_data *pdata) 129 { 130 /* Set MAC to 1G speed */ 131 pdata->hw_if.set_speed(pdata, SPEED_1000); 132 133 /* Call PHY implementation support to complete rate change */ 134 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_1000); 135 } 136 137 static void xgbe_sfi_mode(struct xgbe_prv_data *pdata) 138 { 139 /* If a KR re-driver is present, change to KR mode instead */ 140 if (pdata->kr_redrv) 141 return xgbe_kr_mode(pdata); 142 143 /* Set MAC to 10G speed */ 144 pdata->hw_if.set_speed(pdata, SPEED_10000); 145 146 /* Call PHY implementation support to complete rate change */ 147 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SFI); 148 } 149 150 static void xgbe_x_mode(struct xgbe_prv_data *pdata) 151 { 152 /* Set MAC to 1G speed */ 153 pdata->hw_if.set_speed(pdata, SPEED_1000); 154 155 /* Call PHY implementation support to complete rate change */ 156 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_X); 157 } 158 159 static void xgbe_sgmii_1000_mode(struct xgbe_prv_data *pdata) 160 { 161 /* Set MAC to 1G speed */ 162 pdata->hw_if.set_speed(pdata, SPEED_1000); 163 164 /* Call PHY implementation support to complete rate change */ 165 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_1000); 166 } 167 168 static void xgbe_sgmii_10_mode(struct xgbe_prv_data *pdata) 169 { 170 /* Set MAC to 10M speed */ 171 pdata->hw_if.set_speed(pdata, SPEED_10); 172 173 /* Call PHY implementation support to complete rate change */ 174 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_10); 175 } 176 177 static void xgbe_sgmii_100_mode(struct xgbe_prv_data *pdata) 178 { 179 /* Set MAC to 1G speed */ 180 pdata->hw_if.set_speed(pdata, SPEED_1000); 181 182 /* Call PHY implementation support to complete rate change */ 183 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_100); 184 } 185 186 static enum xgbe_mode xgbe_cur_mode(struct xgbe_prv_data *pdata) 187 { 188 return pdata->phy_if.phy_impl.cur_mode(pdata); 189 } 190 191 static bool xgbe_in_kr_mode(struct xgbe_prv_data *pdata) 192 { 193 return (xgbe_cur_mode(pdata) == XGBE_MODE_KR); 194 } 195 196 static void xgbe_change_mode(struct xgbe_prv_data *pdata, 197 enum xgbe_mode mode) 198 { 199 switch (mode) { 200 case XGBE_MODE_KX_1000: 201 xgbe_kx_1000_mode(pdata); 202 break; 203 case XGBE_MODE_KX_2500: 204 xgbe_kx_2500_mode(pdata); 205 break; 206 case XGBE_MODE_KR: 207 xgbe_kr_mode(pdata); 208 break; 209 case XGBE_MODE_SGMII_10: 210 xgbe_sgmii_10_mode(pdata); 211 break; 212 case XGBE_MODE_SGMII_100: 213 xgbe_sgmii_100_mode(pdata); 214 break; 215 case XGBE_MODE_SGMII_1000: 216 xgbe_sgmii_1000_mode(pdata); 217 break; 218 case XGBE_MODE_X: 219 xgbe_x_mode(pdata); 220 break; 221 case XGBE_MODE_SFI: 222 xgbe_sfi_mode(pdata); 223 break; 224 case XGBE_MODE_UNKNOWN: 225 break; 226 default: 227 netif_dbg(pdata, link, pdata->netdev, 228 "invalid operation mode requested (%u)\n", mode); 229 } 230 } 231 232 static void xgbe_switch_mode(struct xgbe_prv_data *pdata) 233 { 234 xgbe_change_mode(pdata, pdata->phy_if.phy_impl.switch_mode(pdata)); 235 } 236 237 static bool xgbe_set_mode(struct xgbe_prv_data *pdata, 238 enum xgbe_mode mode) 239 { 240 if (mode == xgbe_cur_mode(pdata)) 241 return false; 242 243 xgbe_change_mode(pdata, mode); 244 245 return true; 246 } 247 248 static bool xgbe_use_mode(struct xgbe_prv_data *pdata, 249 enum xgbe_mode mode) 250 { 251 return pdata->phy_if.phy_impl.use_mode(pdata, mode); 252 } 253 254 static void xgbe_an37_set(struct xgbe_prv_data *pdata, bool enable, 255 bool restart) 256 { 257 unsigned int reg; 258 259 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1); 260 reg &= ~MDIO_VEND2_CTRL1_AN_ENABLE; 261 262 if (enable) 263 reg |= MDIO_VEND2_CTRL1_AN_ENABLE; 264 265 if (restart) 266 reg |= MDIO_VEND2_CTRL1_AN_RESTART; 267 268 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg); 269 } 270 271 static void xgbe_an37_restart(struct xgbe_prv_data *pdata) 272 { 273 xgbe_an37_enable_interrupts(pdata); 274 xgbe_an37_set(pdata, true, true); 275 276 netif_dbg(pdata, link, pdata->netdev, "CL37 AN enabled/restarted\n"); 277 } 278 279 static void xgbe_an37_disable(struct xgbe_prv_data *pdata) 280 { 281 xgbe_an37_set(pdata, false, false); 282 xgbe_an37_disable_interrupts(pdata); 283 284 netif_dbg(pdata, link, pdata->netdev, "CL37 AN disabled\n"); 285 } 286 287 static void xgbe_an73_set(struct xgbe_prv_data *pdata, bool enable, 288 bool restart) 289 { 290 unsigned int reg; 291 292 /* Disable KR training for now */ 293 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); 294 reg &= ~XGBE_KR_TRAINING_ENABLE; 295 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg); 296 297 /* Update AN settings */ 298 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1); 299 reg &= ~MDIO_AN_CTRL1_ENABLE; 300 301 if (enable) 302 reg |= MDIO_AN_CTRL1_ENABLE; 303 304 if (restart) 305 reg |= MDIO_AN_CTRL1_RESTART; 306 307 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg); 308 } 309 310 static void xgbe_an73_restart(struct xgbe_prv_data *pdata) 311 { 312 xgbe_an73_enable_interrupts(pdata); 313 xgbe_an73_set(pdata, true, true); 314 315 netif_dbg(pdata, link, pdata->netdev, "CL73 AN enabled/restarted\n"); 316 } 317 318 static void xgbe_an73_disable(struct xgbe_prv_data *pdata) 319 { 320 xgbe_an73_set(pdata, false, false); 321 xgbe_an73_disable_interrupts(pdata); 322 323 pdata->an_start = 0; 324 325 netif_dbg(pdata, link, pdata->netdev, "CL73 AN disabled\n"); 326 } 327 328 static void xgbe_an_restart(struct xgbe_prv_data *pdata) 329 { 330 if (pdata->phy_if.phy_impl.an_pre) 331 pdata->phy_if.phy_impl.an_pre(pdata); 332 333 switch (pdata->an_mode) { 334 case XGBE_AN_MODE_CL73: 335 case XGBE_AN_MODE_CL73_REDRV: 336 xgbe_an73_restart(pdata); 337 break; 338 case XGBE_AN_MODE_CL37: 339 case XGBE_AN_MODE_CL37_SGMII: 340 xgbe_an37_restart(pdata); 341 break; 342 default: 343 break; 344 } 345 } 346 347 static void xgbe_an_disable(struct xgbe_prv_data *pdata) 348 { 349 if (pdata->phy_if.phy_impl.an_post) 350 pdata->phy_if.phy_impl.an_post(pdata); 351 352 switch (pdata->an_mode) { 353 case XGBE_AN_MODE_CL73: 354 case XGBE_AN_MODE_CL73_REDRV: 355 xgbe_an73_disable(pdata); 356 break; 357 case XGBE_AN_MODE_CL37: 358 case XGBE_AN_MODE_CL37_SGMII: 359 xgbe_an37_disable(pdata); 360 break; 361 default: 362 break; 363 } 364 } 365 366 static void xgbe_an_disable_all(struct xgbe_prv_data *pdata) 367 { 368 xgbe_an73_disable(pdata); 369 xgbe_an37_disable(pdata); 370 } 371 372 static enum xgbe_an xgbe_an73_tx_training(struct xgbe_prv_data *pdata, 373 enum xgbe_rx *state) 374 { 375 unsigned int ad_reg, lp_reg, reg; 376 377 *state = XGBE_RX_COMPLETE; 378 379 /* If we're not in KR mode then we're done */ 380 if (!xgbe_in_kr_mode(pdata)) 381 return XGBE_AN_PAGE_RECEIVED; 382 383 /* Enable/Disable FEC */ 384 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 385 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 386 387 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL); 388 reg &= ~(MDIO_PMA_10GBR_FECABLE_ABLE | MDIO_PMA_10GBR_FECABLE_ERRABLE); 389 if ((ad_reg & 0xc000) && (lp_reg & 0xc000)) 390 reg |= pdata->fec_ability; 391 392 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg); 393 394 /* Start KR training */ 395 if (pdata->phy_if.phy_impl.kr_training_pre) 396 pdata->phy_if.phy_impl.kr_training_pre(pdata); 397 398 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); 399 reg |= XGBE_KR_TRAINING_ENABLE; 400 reg |= XGBE_KR_TRAINING_START; 401 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg); 402 pdata->kr_start_time = jiffies; 403 404 netif_dbg(pdata, link, pdata->netdev, 405 "KR training initiated\n"); 406 407 if (pdata->phy_if.phy_impl.kr_training_post) 408 pdata->phy_if.phy_impl.kr_training_post(pdata); 409 410 return XGBE_AN_PAGE_RECEIVED; 411 } 412 413 static enum xgbe_an xgbe_an73_tx_xnp(struct xgbe_prv_data *pdata, 414 enum xgbe_rx *state) 415 { 416 u16 msg; 417 418 *state = XGBE_RX_XNP; 419 420 msg = XGBE_XNP_MCF_NULL_MESSAGE; 421 msg |= XGBE_XNP_MP_FORMATTED; 422 423 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0); 424 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0); 425 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP, msg); 426 427 return XGBE_AN_PAGE_RECEIVED; 428 } 429 430 static enum xgbe_an xgbe_an73_rx_bpa(struct xgbe_prv_data *pdata, 431 enum xgbe_rx *state) 432 { 433 unsigned int link_support; 434 unsigned int reg, ad_reg, lp_reg; 435 436 /* Read Base Ability register 2 first */ 437 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 438 439 /* Check for a supported mode, otherwise restart in a different one */ 440 link_support = xgbe_in_kr_mode(pdata) ? 0x80 : 0x20; 441 if (!(reg & link_support)) 442 return XGBE_AN_INCOMPAT_LINK; 443 444 /* Check Extended Next Page support */ 445 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); 446 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); 447 448 return ((ad_reg & XGBE_XNP_NP_EXCHANGE) || 449 (lp_reg & XGBE_XNP_NP_EXCHANGE)) 450 ? xgbe_an73_tx_xnp(pdata, state) 451 : xgbe_an73_tx_training(pdata, state); 452 } 453 454 static enum xgbe_an xgbe_an73_rx_xnp(struct xgbe_prv_data *pdata, 455 enum xgbe_rx *state) 456 { 457 unsigned int ad_reg, lp_reg; 458 459 /* Check Extended Next Page support */ 460 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_XNP); 461 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPX); 462 463 return ((ad_reg & XGBE_XNP_NP_EXCHANGE) || 464 (lp_reg & XGBE_XNP_NP_EXCHANGE)) 465 ? xgbe_an73_tx_xnp(pdata, state) 466 : xgbe_an73_tx_training(pdata, state); 467 } 468 469 static enum xgbe_an xgbe_an73_page_received(struct xgbe_prv_data *pdata) 470 { 471 enum xgbe_rx *state; 472 unsigned long an_timeout; 473 enum xgbe_an ret; 474 475 if (!pdata->an_start) { 476 pdata->an_start = jiffies; 477 } else { 478 an_timeout = pdata->an_start + 479 msecs_to_jiffies(XGBE_AN_MS_TIMEOUT); 480 if (time_after(jiffies, an_timeout)) { 481 /* Auto-negotiation timed out, reset state */ 482 pdata->kr_state = XGBE_RX_BPA; 483 pdata->kx_state = XGBE_RX_BPA; 484 485 pdata->an_start = jiffies; 486 487 netif_dbg(pdata, link, pdata->netdev, 488 "CL73 AN timed out, resetting state\n"); 489 } 490 } 491 492 state = xgbe_in_kr_mode(pdata) ? &pdata->kr_state 493 : &pdata->kx_state; 494 495 switch (*state) { 496 case XGBE_RX_BPA: 497 ret = xgbe_an73_rx_bpa(pdata, state); 498 break; 499 500 case XGBE_RX_XNP: 501 ret = xgbe_an73_rx_xnp(pdata, state); 502 break; 503 504 default: 505 ret = XGBE_AN_ERROR; 506 } 507 508 return ret; 509 } 510 511 static enum xgbe_an xgbe_an73_incompat_link(struct xgbe_prv_data *pdata) 512 { 513 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 514 515 /* Be sure we aren't looping trying to negotiate */ 516 if (xgbe_in_kr_mode(pdata)) { 517 pdata->kr_state = XGBE_RX_ERROR; 518 519 if (!XGBE_ADV(lks, 1000baseKX_Full) && 520 !XGBE_ADV(lks, 2500baseX_Full)) 521 return XGBE_AN_NO_LINK; 522 523 if (pdata->kx_state != XGBE_RX_BPA) 524 return XGBE_AN_NO_LINK; 525 } else { 526 pdata->kx_state = XGBE_RX_ERROR; 527 528 if (!XGBE_ADV(lks, 10000baseKR_Full)) 529 return XGBE_AN_NO_LINK; 530 531 if (pdata->kr_state != XGBE_RX_BPA) 532 return XGBE_AN_NO_LINK; 533 } 534 535 xgbe_an_disable(pdata); 536 537 xgbe_switch_mode(pdata); 538 539 pdata->an_result = XGBE_AN_READY; 540 541 xgbe_an_restart(pdata); 542 543 return XGBE_AN_INCOMPAT_LINK; 544 } 545 546 static void xgbe_an37_isr(struct xgbe_prv_data *pdata) 547 { 548 unsigned int reg; 549 550 /* Disable AN interrupts */ 551 xgbe_an37_disable_interrupts(pdata); 552 553 /* Save the interrupt(s) that fired */ 554 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT); 555 pdata->an_int = reg & XGBE_AN_CL37_INT_MASK; 556 pdata->an_status = reg & ~XGBE_AN_CL37_INT_MASK; 557 558 if (pdata->an_int) { 559 /* Clear the interrupt(s) that fired and process them */ 560 reg &= ~XGBE_AN_CL37_INT_MASK; 561 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg); 562 563 queue_work(pdata->an_workqueue, &pdata->an_irq_work); 564 } else { 565 /* Enable AN interrupts */ 566 xgbe_an37_enable_interrupts(pdata); 567 568 /* Reissue interrupt if status is not clear */ 569 if (pdata->vdata->irq_reissue_support) 570 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3); 571 } 572 } 573 574 static void xgbe_an73_isr(struct xgbe_prv_data *pdata) 575 { 576 /* Disable AN interrupts */ 577 xgbe_an73_disable_interrupts(pdata); 578 579 /* Save the interrupt(s) that fired */ 580 pdata->an_int = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INT); 581 582 if (pdata->an_int) { 583 /* Clear the interrupt(s) that fired and process them */ 584 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, ~pdata->an_int); 585 586 queue_work(pdata->an_workqueue, &pdata->an_irq_work); 587 } else { 588 /* Enable AN interrupts */ 589 xgbe_an73_enable_interrupts(pdata); 590 591 /* Reissue interrupt if status is not clear */ 592 if (pdata->vdata->irq_reissue_support) 593 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3); 594 } 595 } 596 597 static void xgbe_an_isr_bh_work(struct work_struct *work) 598 { 599 struct xgbe_prv_data *pdata = from_work(pdata, work, an_bh_work); 600 601 netif_dbg(pdata, intr, pdata->netdev, "AN interrupt received\n"); 602 603 switch (pdata->an_mode) { 604 case XGBE_AN_MODE_CL73: 605 case XGBE_AN_MODE_CL73_REDRV: 606 xgbe_an73_isr(pdata); 607 break; 608 case XGBE_AN_MODE_CL37: 609 case XGBE_AN_MODE_CL37_SGMII: 610 xgbe_an37_isr(pdata); 611 break; 612 default: 613 break; 614 } 615 } 616 617 static irqreturn_t xgbe_an_isr(int irq, void *data) 618 { 619 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data; 620 621 if (pdata->isr_as_bh_work) 622 queue_work(system_bh_wq, &pdata->an_bh_work); 623 else 624 xgbe_an_isr_bh_work(&pdata->an_bh_work); 625 626 return IRQ_HANDLED; 627 } 628 629 static irqreturn_t xgbe_an_combined_isr(struct xgbe_prv_data *pdata) 630 { 631 xgbe_an_isr_bh_work(&pdata->an_bh_work); 632 633 return IRQ_HANDLED; 634 } 635 636 static void xgbe_an_irq_work(struct work_struct *work) 637 { 638 struct xgbe_prv_data *pdata = container_of(work, 639 struct xgbe_prv_data, 640 an_irq_work); 641 642 /* Avoid a race between enabling the IRQ and exiting the work by 643 * waiting for the work to finish and then queueing it 644 */ 645 flush_work(&pdata->an_work); 646 queue_work(pdata->an_workqueue, &pdata->an_work); 647 } 648 649 static const char *xgbe_state_as_string(enum xgbe_an state) 650 { 651 switch (state) { 652 case XGBE_AN_READY: 653 return "Ready"; 654 case XGBE_AN_PAGE_RECEIVED: 655 return "Page-Received"; 656 case XGBE_AN_INCOMPAT_LINK: 657 return "Incompatible-Link"; 658 case XGBE_AN_COMPLETE: 659 return "Complete"; 660 case XGBE_AN_NO_LINK: 661 return "No-Link"; 662 case XGBE_AN_ERROR: 663 return "Error"; 664 default: 665 return "Undefined"; 666 } 667 } 668 669 static void xgbe_an37_state_machine(struct xgbe_prv_data *pdata) 670 { 671 enum xgbe_an cur_state = pdata->an_state; 672 673 if (!pdata->an_int) 674 return; 675 676 if (pdata->an_int & XGBE_AN_CL37_INT_CMPLT) { 677 pdata->an_state = XGBE_AN_COMPLETE; 678 pdata->an_int &= ~XGBE_AN_CL37_INT_CMPLT; 679 680 /* If SGMII is enabled, check the link status */ 681 if ((pdata->an_mode == XGBE_AN_MODE_CL37_SGMII) && 682 !(pdata->an_status & XGBE_SGMII_AN_LINK_STATUS)) 683 pdata->an_state = XGBE_AN_NO_LINK; 684 } 685 686 netif_dbg(pdata, link, pdata->netdev, "CL37 AN %s\n", 687 xgbe_state_as_string(pdata->an_state)); 688 689 cur_state = pdata->an_state; 690 691 switch (pdata->an_state) { 692 case XGBE_AN_READY: 693 break; 694 695 case XGBE_AN_COMPLETE: 696 netif_dbg(pdata, link, pdata->netdev, 697 "Auto negotiation successful\n"); 698 break; 699 700 case XGBE_AN_NO_LINK: 701 break; 702 703 default: 704 pdata->an_state = XGBE_AN_ERROR; 705 } 706 707 if (pdata->an_state == XGBE_AN_ERROR) { 708 netdev_err(pdata->netdev, 709 "error during auto-negotiation, state=%u\n", 710 cur_state); 711 712 pdata->an_int = 0; 713 xgbe_an37_clear_interrupts(pdata); 714 } 715 716 if (pdata->an_state >= XGBE_AN_COMPLETE) { 717 pdata->an_result = pdata->an_state; 718 pdata->an_state = XGBE_AN_READY; 719 720 if (pdata->phy_if.phy_impl.an_post) 721 pdata->phy_if.phy_impl.an_post(pdata); 722 723 netif_dbg(pdata, link, pdata->netdev, "CL37 AN result: %s\n", 724 xgbe_state_as_string(pdata->an_result)); 725 } 726 727 xgbe_an37_enable_interrupts(pdata); 728 } 729 730 static void xgbe_an73_state_machine(struct xgbe_prv_data *pdata) 731 { 732 enum xgbe_an cur_state = pdata->an_state; 733 734 if (!pdata->an_int) 735 return; 736 737 next_int: 738 if (pdata->an_int & XGBE_AN_CL73_PG_RCV) { 739 pdata->an_state = XGBE_AN_PAGE_RECEIVED; 740 pdata->an_int &= ~XGBE_AN_CL73_PG_RCV; 741 } else if (pdata->an_int & XGBE_AN_CL73_INC_LINK) { 742 pdata->an_state = XGBE_AN_INCOMPAT_LINK; 743 pdata->an_int &= ~XGBE_AN_CL73_INC_LINK; 744 } else if (pdata->an_int & XGBE_AN_CL73_INT_CMPLT) { 745 pdata->an_state = XGBE_AN_COMPLETE; 746 pdata->an_int &= ~XGBE_AN_CL73_INT_CMPLT; 747 } else { 748 pdata->an_state = XGBE_AN_ERROR; 749 } 750 751 again: 752 netif_dbg(pdata, link, pdata->netdev, "CL73 AN %s\n", 753 xgbe_state_as_string(pdata->an_state)); 754 755 cur_state = pdata->an_state; 756 757 switch (pdata->an_state) { 758 case XGBE_AN_READY: 759 pdata->an_supported = 0; 760 break; 761 762 case XGBE_AN_PAGE_RECEIVED: 763 pdata->an_state = xgbe_an73_page_received(pdata); 764 pdata->an_supported++; 765 break; 766 767 case XGBE_AN_INCOMPAT_LINK: 768 pdata->an_supported = 0; 769 pdata->parallel_detect = 0; 770 pdata->an_state = xgbe_an73_incompat_link(pdata); 771 break; 772 773 case XGBE_AN_COMPLETE: 774 pdata->parallel_detect = pdata->an_supported ? 0 : 1; 775 netif_dbg(pdata, link, pdata->netdev, "%s successful\n", 776 pdata->an_supported ? "Auto negotiation" 777 : "Parallel detection"); 778 break; 779 780 case XGBE_AN_NO_LINK: 781 break; 782 783 default: 784 pdata->an_state = XGBE_AN_ERROR; 785 } 786 787 if (pdata->an_state == XGBE_AN_NO_LINK) { 788 pdata->an_int = 0; 789 xgbe_an73_clear_interrupts(pdata); 790 } else if (pdata->an_state == XGBE_AN_ERROR) { 791 netdev_err(pdata->netdev, 792 "error during auto-negotiation, state=%u\n", 793 cur_state); 794 795 pdata->an_int = 0; 796 xgbe_an73_clear_interrupts(pdata); 797 } 798 799 if (pdata->an_state >= XGBE_AN_COMPLETE) { 800 pdata->an_result = pdata->an_state; 801 pdata->an_state = XGBE_AN_READY; 802 pdata->kr_state = XGBE_RX_BPA; 803 pdata->kx_state = XGBE_RX_BPA; 804 pdata->an_start = 0; 805 806 if (pdata->phy_if.phy_impl.an_post) 807 pdata->phy_if.phy_impl.an_post(pdata); 808 809 netif_dbg(pdata, link, pdata->netdev, "CL73 AN result: %s\n", 810 xgbe_state_as_string(pdata->an_result)); 811 } 812 813 if (cur_state != pdata->an_state) 814 goto again; 815 816 if (pdata->an_int) 817 goto next_int; 818 819 xgbe_an73_enable_interrupts(pdata); 820 } 821 822 static void xgbe_an_state_machine(struct work_struct *work) 823 { 824 struct xgbe_prv_data *pdata = container_of(work, 825 struct xgbe_prv_data, 826 an_work); 827 828 mutex_lock(&pdata->an_mutex); 829 830 switch (pdata->an_mode) { 831 case XGBE_AN_MODE_CL73: 832 case XGBE_AN_MODE_CL73_REDRV: 833 xgbe_an73_state_machine(pdata); 834 break; 835 case XGBE_AN_MODE_CL37: 836 case XGBE_AN_MODE_CL37_SGMII: 837 xgbe_an37_state_machine(pdata); 838 break; 839 default: 840 break; 841 } 842 843 /* Reissue interrupt if status is not clear */ 844 if (pdata->vdata->irq_reissue_support) 845 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3); 846 847 mutex_unlock(&pdata->an_mutex); 848 } 849 850 static void xgbe_an37_init(struct xgbe_prv_data *pdata) 851 { 852 struct ethtool_link_ksettings lks; 853 unsigned int reg; 854 855 pdata->phy_if.phy_impl.an_advertising(pdata, &lks); 856 857 /* Set up Advertisement register */ 858 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE); 859 if (XGBE_ADV(&lks, Pause)) 860 reg |= 0x100; 861 else 862 reg &= ~0x100; 863 864 if (XGBE_ADV(&lks, Asym_Pause)) 865 reg |= 0x80; 866 else 867 reg &= ~0x80; 868 869 /* Full duplex, but not half */ 870 reg |= XGBE_AN_CL37_FD_MASK; 871 reg &= ~XGBE_AN_CL37_HD_MASK; 872 873 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE, reg); 874 875 /* Set up the Control register */ 876 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); 877 reg &= ~XGBE_AN_CL37_TX_CONFIG_MASK; 878 reg &= ~XGBE_AN_CL37_PCS_MODE_MASK; 879 880 switch (pdata->an_mode) { 881 case XGBE_AN_MODE_CL37: 882 reg |= XGBE_AN_CL37_PCS_MODE_BASEX; 883 break; 884 case XGBE_AN_MODE_CL37_SGMII: 885 reg |= XGBE_AN_CL37_PCS_MODE_SGMII; 886 break; 887 default: 888 break; 889 } 890 891 reg |= XGBE_AN_CL37_MII_CTRL_8BIT; 892 893 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); 894 895 netif_dbg(pdata, link, pdata->netdev, "CL37 AN (%s) initialized\n", 896 (pdata->an_mode == XGBE_AN_MODE_CL37) ? "BaseX" : "SGMII"); 897 } 898 899 static void xgbe_an73_init(struct xgbe_prv_data *pdata) 900 { 901 struct ethtool_link_ksettings lks; 902 unsigned int reg; 903 904 pdata->phy_if.phy_impl.an_advertising(pdata, &lks); 905 906 /* Set up Advertisement register 3 first */ 907 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 908 if (XGBE_ADV(&lks, 10000baseR_FEC)) 909 reg |= 0xc000; 910 else 911 reg &= ~0xc000; 912 913 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, reg); 914 915 /* Set up Advertisement register 2 next */ 916 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 917 if (XGBE_ADV(&lks, 10000baseKR_Full)) 918 reg |= 0x80; 919 else 920 reg &= ~0x80; 921 922 if (XGBE_ADV(&lks, 1000baseKX_Full) || 923 XGBE_ADV(&lks, 2500baseX_Full)) 924 reg |= 0x20; 925 else 926 reg &= ~0x20; 927 928 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, reg); 929 930 /* Set up Advertisement register 1 last */ 931 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); 932 if (XGBE_ADV(&lks, Pause)) 933 reg |= 0x400; 934 else 935 reg &= ~0x400; 936 937 if (XGBE_ADV(&lks, Asym_Pause)) 938 reg |= 0x800; 939 else 940 reg &= ~0x800; 941 942 /* We don't intend to perform XNP */ 943 reg &= ~XGBE_XNP_NP_EXCHANGE; 944 945 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg); 946 947 netif_dbg(pdata, link, pdata->netdev, "CL73 AN initialized\n"); 948 } 949 950 static void xgbe_an_init(struct xgbe_prv_data *pdata) 951 { 952 /* Set up advertisement registers based on current settings */ 953 pdata->an_mode = pdata->phy_if.phy_impl.an_mode(pdata); 954 switch (pdata->an_mode) { 955 case XGBE_AN_MODE_CL73: 956 case XGBE_AN_MODE_CL73_REDRV: 957 xgbe_an73_init(pdata); 958 break; 959 case XGBE_AN_MODE_CL37: 960 case XGBE_AN_MODE_CL37_SGMII: 961 xgbe_an37_init(pdata); 962 break; 963 default: 964 break; 965 } 966 } 967 968 static const char *xgbe_phy_fc_string(struct xgbe_prv_data *pdata) 969 { 970 if (pdata->tx_pause && pdata->rx_pause) 971 return "rx/tx"; 972 else if (pdata->rx_pause) 973 return "rx"; 974 else if (pdata->tx_pause) 975 return "tx"; 976 else 977 return "off"; 978 } 979 980 static const char *xgbe_phy_speed_string(int speed) 981 { 982 switch (speed) { 983 case SPEED_10: 984 return "10Mbps"; 985 case SPEED_100: 986 return "100Mbps"; 987 case SPEED_1000: 988 return "1Gbps"; 989 case SPEED_2500: 990 return "2.5Gbps"; 991 case SPEED_10000: 992 return "10Gbps"; 993 case SPEED_UNKNOWN: 994 return "Unknown"; 995 default: 996 return "Unsupported"; 997 } 998 } 999 1000 static void xgbe_phy_print_status(struct xgbe_prv_data *pdata) 1001 { 1002 if (pdata->phy.link) 1003 netdev_info(pdata->netdev, 1004 "Link is Up - %s/%s - flow control %s\n", 1005 xgbe_phy_speed_string(pdata->phy.speed), 1006 pdata->phy.duplex == DUPLEX_FULL ? "Full" : "Half", 1007 xgbe_phy_fc_string(pdata)); 1008 else 1009 netdev_info(pdata->netdev, "Link is Down\n"); 1010 } 1011 1012 static void xgbe_phy_adjust_link(struct xgbe_prv_data *pdata) 1013 { 1014 int new_state = 0; 1015 1016 if (pdata->phy.link) { 1017 /* Flow control support */ 1018 pdata->pause_autoneg = pdata->phy.pause_autoneg; 1019 1020 if (pdata->tx_pause != pdata->phy.tx_pause) { 1021 new_state = 1; 1022 pdata->tx_pause = pdata->phy.tx_pause; 1023 pdata->hw_if.config_tx_flow_control(pdata); 1024 } 1025 1026 if (pdata->rx_pause != pdata->phy.rx_pause) { 1027 new_state = 1; 1028 pdata->rx_pause = pdata->phy.rx_pause; 1029 pdata->hw_if.config_rx_flow_control(pdata); 1030 } 1031 1032 /* Speed support */ 1033 if (pdata->phy_speed != pdata->phy.speed) { 1034 new_state = 1; 1035 pdata->phy_speed = pdata->phy.speed; 1036 } 1037 1038 if (pdata->phy_link != pdata->phy.link) { 1039 new_state = 1; 1040 pdata->phy_link = pdata->phy.link; 1041 } 1042 } else if (pdata->phy_link) { 1043 new_state = 1; 1044 pdata->phy_link = 0; 1045 pdata->phy_speed = SPEED_UNKNOWN; 1046 } 1047 1048 if (new_state && netif_msg_link(pdata)) 1049 xgbe_phy_print_status(pdata); 1050 } 1051 1052 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed) 1053 { 1054 return pdata->phy_if.phy_impl.valid_speed(pdata, speed); 1055 } 1056 1057 static int xgbe_phy_config_fixed(struct xgbe_prv_data *pdata) 1058 { 1059 enum xgbe_mode mode; 1060 1061 netif_dbg(pdata, link, pdata->netdev, "fixed PHY configuration\n"); 1062 1063 /* Disable auto-negotiation */ 1064 xgbe_an_disable(pdata); 1065 1066 /* Set specified mode for specified speed */ 1067 mode = pdata->phy_if.phy_impl.get_mode(pdata, pdata->phy.speed); 1068 switch (mode) { 1069 case XGBE_MODE_KX_1000: 1070 case XGBE_MODE_KX_2500: 1071 case XGBE_MODE_KR: 1072 case XGBE_MODE_SGMII_10: 1073 case XGBE_MODE_SGMII_100: 1074 case XGBE_MODE_SGMII_1000: 1075 case XGBE_MODE_X: 1076 case XGBE_MODE_SFI: 1077 break; 1078 case XGBE_MODE_UNKNOWN: 1079 default: 1080 return -EINVAL; 1081 } 1082 1083 /* Validate duplex mode */ 1084 if (pdata->phy.duplex != DUPLEX_FULL) 1085 return -EINVAL; 1086 1087 /* Force the mode change for SFI in Fixed PHY config. 1088 * Fixed PHY configs needs PLL to be enabled while doing mode set. 1089 * When the SFP module isn't connected during boot, driver assumes 1090 * AN is ON and attempts autonegotiation. However, if the connected 1091 * SFP comes up in Fixed PHY config, the link will not come up as 1092 * PLL isn't enabled while the initial mode set command is issued. 1093 * So, force the mode change for SFI in Fixed PHY configuration to 1094 * fix link issues. 1095 */ 1096 if (mode == XGBE_MODE_SFI) 1097 xgbe_change_mode(pdata, mode); 1098 else 1099 xgbe_set_mode(pdata, mode); 1100 1101 return 0; 1102 } 1103 1104 static int __xgbe_phy_config_aneg(struct xgbe_prv_data *pdata, bool set_mode) 1105 { 1106 int ret; 1107 1108 mutex_lock(&pdata->an_mutex); 1109 1110 set_bit(XGBE_LINK_INIT, &pdata->dev_state); 1111 pdata->link_check = jiffies; 1112 1113 ret = pdata->phy_if.phy_impl.an_config(pdata); 1114 if (ret) 1115 goto out; 1116 1117 if (pdata->phy.autoneg != AUTONEG_ENABLE) { 1118 ret = xgbe_phy_config_fixed(pdata); 1119 if (ret || !pdata->kr_redrv) 1120 goto out; 1121 1122 netif_dbg(pdata, link, pdata->netdev, "AN redriver support\n"); 1123 } else { 1124 netif_dbg(pdata, link, pdata->netdev, "AN PHY configuration\n"); 1125 } 1126 1127 /* Disable auto-negotiation interrupt */ 1128 disable_irq(pdata->an_irq); 1129 1130 if (set_mode) { 1131 /* Start auto-negotiation in a supported mode */ 1132 if (xgbe_use_mode(pdata, XGBE_MODE_KR)) { 1133 xgbe_set_mode(pdata, XGBE_MODE_KR); 1134 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) { 1135 xgbe_set_mode(pdata, XGBE_MODE_KX_2500); 1136 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) { 1137 xgbe_set_mode(pdata, XGBE_MODE_KX_1000); 1138 } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) { 1139 xgbe_set_mode(pdata, XGBE_MODE_SFI); 1140 } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) { 1141 xgbe_set_mode(pdata, XGBE_MODE_X); 1142 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) { 1143 xgbe_set_mode(pdata, XGBE_MODE_SGMII_1000); 1144 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) { 1145 xgbe_set_mode(pdata, XGBE_MODE_SGMII_100); 1146 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_10)) { 1147 xgbe_set_mode(pdata, XGBE_MODE_SGMII_10); 1148 } else { 1149 enable_irq(pdata->an_irq); 1150 ret = -EINVAL; 1151 goto out; 1152 } 1153 } 1154 1155 /* Disable and stop any in progress auto-negotiation */ 1156 xgbe_an_disable_all(pdata); 1157 1158 /* Clear any auto-negotitation interrupts */ 1159 xgbe_an_clear_interrupts_all(pdata); 1160 1161 pdata->an_result = XGBE_AN_READY; 1162 pdata->an_state = XGBE_AN_READY; 1163 pdata->kr_state = XGBE_RX_BPA; 1164 pdata->kx_state = XGBE_RX_BPA; 1165 1166 /* Re-enable auto-negotiation interrupt */ 1167 enable_irq(pdata->an_irq); 1168 1169 xgbe_an_init(pdata); 1170 xgbe_an_restart(pdata); 1171 1172 out: 1173 if (ret) 1174 set_bit(XGBE_LINK_ERR, &pdata->dev_state); 1175 else 1176 clear_bit(XGBE_LINK_ERR, &pdata->dev_state); 1177 1178 mutex_unlock(&pdata->an_mutex); 1179 1180 return ret; 1181 } 1182 1183 static int xgbe_phy_config_aneg(struct xgbe_prv_data *pdata) 1184 { 1185 return __xgbe_phy_config_aneg(pdata, true); 1186 } 1187 1188 static int xgbe_phy_reconfig_aneg(struct xgbe_prv_data *pdata) 1189 { 1190 return __xgbe_phy_config_aneg(pdata, false); 1191 } 1192 1193 static bool xgbe_phy_aneg_done(struct xgbe_prv_data *pdata) 1194 { 1195 return (pdata->an_result == XGBE_AN_COMPLETE); 1196 } 1197 1198 static void xgbe_check_link_timeout(struct xgbe_prv_data *pdata) 1199 { 1200 unsigned long link_timeout; 1201 unsigned long kr_time; 1202 int wait; 1203 1204 link_timeout = pdata->link_check + (XGBE_LINK_TIMEOUT * HZ); 1205 if (time_after(jiffies, link_timeout)) { 1206 if ((xgbe_cur_mode(pdata) == XGBE_MODE_KR) && 1207 pdata->phy.autoneg == AUTONEG_ENABLE) { 1208 /* AN restart should not happen while KR training is in progress. 1209 * The while loop ensures no AN restart during KR training, 1210 * waits up to 500ms and AN restart is triggered only if KR 1211 * training is failed. 1212 */ 1213 wait = XGBE_KR_TRAINING_WAIT_ITER; 1214 while (wait--) { 1215 kr_time = pdata->kr_start_time + 1216 msecs_to_jiffies(XGBE_AN_MS_TIMEOUT); 1217 if (time_after(jiffies, kr_time)) 1218 break; 1219 /* AN restart is not required, if AN result is COMPLETE */ 1220 if (pdata->an_result == XGBE_AN_COMPLETE) 1221 return; 1222 usleep_range(10000, 11000); 1223 } 1224 } 1225 netif_dbg(pdata, link, pdata->netdev, "AN link timeout\n"); 1226 xgbe_phy_config_aneg(pdata); 1227 } 1228 } 1229 1230 static enum xgbe_mode xgbe_phy_status_aneg(struct xgbe_prv_data *pdata) 1231 { 1232 return pdata->phy_if.phy_impl.an_outcome(pdata); 1233 } 1234 1235 static bool xgbe_phy_status_result(struct xgbe_prv_data *pdata) 1236 { 1237 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1238 enum xgbe_mode mode; 1239 1240 XGBE_ZERO_LP_ADV(lks); 1241 1242 if ((pdata->phy.autoneg != AUTONEG_ENABLE) || pdata->parallel_detect) 1243 mode = xgbe_cur_mode(pdata); 1244 else 1245 mode = xgbe_phy_status_aneg(pdata); 1246 1247 switch (mode) { 1248 case XGBE_MODE_SGMII_10: 1249 pdata->phy.speed = SPEED_10; 1250 break; 1251 case XGBE_MODE_SGMII_100: 1252 pdata->phy.speed = SPEED_100; 1253 break; 1254 case XGBE_MODE_X: 1255 case XGBE_MODE_KX_1000: 1256 case XGBE_MODE_SGMII_1000: 1257 pdata->phy.speed = SPEED_1000; 1258 break; 1259 case XGBE_MODE_KX_2500: 1260 pdata->phy.speed = SPEED_2500; 1261 break; 1262 case XGBE_MODE_KR: 1263 case XGBE_MODE_SFI: 1264 pdata->phy.speed = SPEED_10000; 1265 break; 1266 case XGBE_MODE_UNKNOWN: 1267 default: 1268 pdata->phy.speed = SPEED_UNKNOWN; 1269 } 1270 1271 pdata->phy.duplex = DUPLEX_FULL; 1272 1273 if (!xgbe_set_mode(pdata, mode)) 1274 return false; 1275 1276 if (pdata->an_again) 1277 xgbe_phy_reconfig_aneg(pdata); 1278 1279 return true; 1280 } 1281 1282 static void xgbe_phy_status(struct xgbe_prv_data *pdata) 1283 { 1284 unsigned int link_aneg; 1285 int an_restart; 1286 1287 if (test_bit(XGBE_LINK_ERR, &pdata->dev_state)) { 1288 netif_carrier_off(pdata->netdev); 1289 1290 pdata->phy.link = 0; 1291 goto adjust_link; 1292 } 1293 1294 link_aneg = (pdata->phy.autoneg == AUTONEG_ENABLE); 1295 1296 pdata->phy.link = pdata->phy_if.phy_impl.link_status(pdata, 1297 &an_restart); 1298 if (an_restart) { 1299 xgbe_phy_config_aneg(pdata); 1300 goto adjust_link; 1301 } 1302 1303 if (pdata->phy.link) { 1304 if (link_aneg && !xgbe_phy_aneg_done(pdata)) { 1305 xgbe_check_link_timeout(pdata); 1306 return; 1307 } 1308 1309 if (xgbe_phy_status_result(pdata)) 1310 return; 1311 1312 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) 1313 clear_bit(XGBE_LINK_INIT, &pdata->dev_state); 1314 1315 netif_carrier_on(pdata->netdev); 1316 } else { 1317 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) { 1318 xgbe_check_link_timeout(pdata); 1319 1320 if (link_aneg) 1321 return; 1322 } 1323 1324 xgbe_phy_status_result(pdata); 1325 1326 netif_carrier_off(pdata->netdev); 1327 } 1328 1329 adjust_link: 1330 xgbe_phy_adjust_link(pdata); 1331 } 1332 1333 static void xgbe_phy_stop(struct xgbe_prv_data *pdata) 1334 { 1335 netif_dbg(pdata, link, pdata->netdev, "stopping PHY\n"); 1336 1337 if (!pdata->phy_started) 1338 return; 1339 1340 /* Indicate the PHY is down */ 1341 pdata->phy_started = 0; 1342 1343 /* Disable auto-negotiation */ 1344 xgbe_an_disable_all(pdata); 1345 1346 if (pdata->dev_irq != pdata->an_irq) { 1347 devm_free_irq(pdata->dev, pdata->an_irq, pdata); 1348 cancel_work_sync(&pdata->an_bh_work); 1349 } 1350 1351 pdata->phy_if.phy_impl.stop(pdata); 1352 1353 pdata->phy.link = 0; 1354 1355 xgbe_phy_adjust_link(pdata); 1356 } 1357 1358 static int xgbe_phy_start(struct xgbe_prv_data *pdata) 1359 { 1360 struct net_device *netdev = pdata->netdev; 1361 int ret; 1362 1363 netif_dbg(pdata, link, pdata->netdev, "starting PHY\n"); 1364 1365 ret = pdata->phy_if.phy_impl.start(pdata); 1366 if (ret) 1367 return ret; 1368 1369 /* If we have a separate AN irq, enable it */ 1370 if (pdata->dev_irq != pdata->an_irq) { 1371 INIT_WORK(&pdata->an_bh_work, xgbe_an_isr_bh_work); 1372 1373 ret = devm_request_irq(pdata->dev, pdata->an_irq, 1374 xgbe_an_isr, 0, pdata->an_name, 1375 pdata); 1376 if (ret) { 1377 netdev_err(netdev, "phy irq request failed\n"); 1378 goto err_stop; 1379 } 1380 } 1381 1382 /* Set initial mode - call the mode setting routines 1383 * directly to insure we are properly configured 1384 */ 1385 if (xgbe_use_mode(pdata, XGBE_MODE_KR)) { 1386 xgbe_kr_mode(pdata); 1387 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) { 1388 xgbe_kx_2500_mode(pdata); 1389 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) { 1390 xgbe_kx_1000_mode(pdata); 1391 } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) { 1392 xgbe_sfi_mode(pdata); 1393 } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) { 1394 xgbe_x_mode(pdata); 1395 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) { 1396 xgbe_sgmii_1000_mode(pdata); 1397 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) { 1398 xgbe_sgmii_100_mode(pdata); 1399 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_10)) { 1400 xgbe_sgmii_10_mode(pdata); 1401 } else { 1402 ret = -EINVAL; 1403 goto err_irq; 1404 } 1405 1406 /* Indicate the PHY is up and running */ 1407 pdata->phy_started = 1; 1408 1409 xgbe_an_init(pdata); 1410 xgbe_an_enable_interrupts(pdata); 1411 1412 return xgbe_phy_config_aneg(pdata); 1413 1414 err_irq: 1415 if (pdata->dev_irq != pdata->an_irq) 1416 devm_free_irq(pdata->dev, pdata->an_irq, pdata); 1417 1418 err_stop: 1419 pdata->phy_if.phy_impl.stop(pdata); 1420 1421 return ret; 1422 } 1423 1424 static int xgbe_phy_reset(struct xgbe_prv_data *pdata) 1425 { 1426 int ret; 1427 1428 ret = pdata->phy_if.phy_impl.reset(pdata); 1429 if (ret) 1430 return ret; 1431 1432 /* Disable auto-negotiation for now */ 1433 xgbe_an_disable_all(pdata); 1434 1435 /* Clear auto-negotiation interrupts */ 1436 xgbe_an_clear_interrupts_all(pdata); 1437 1438 return 0; 1439 } 1440 1441 static void xgbe_dump_phy_registers(struct xgbe_prv_data *pdata) 1442 { 1443 struct device *dev = pdata->dev; 1444 1445 dev_dbg(dev, "\n************* PHY Reg dump **********************\n"); 1446 1447 dev_dbg(dev, "PCS Control Reg (%#06x) = %#06x\n", MDIO_CTRL1, 1448 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1)); 1449 dev_dbg(dev, "PCS Status Reg (%#06x) = %#06x\n", MDIO_STAT1, 1450 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1)); 1451 dev_dbg(dev, "Phy Id (PHYS ID 1 %#06x)= %#06x\n", MDIO_DEVID1, 1452 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1)); 1453 dev_dbg(dev, "Phy Id (PHYS ID 2 %#06x)= %#06x\n", MDIO_DEVID2, 1454 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2)); 1455 dev_dbg(dev, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS1, 1456 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1)); 1457 dev_dbg(dev, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS2, 1458 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2)); 1459 1460 dev_dbg(dev, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1, 1461 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1)); 1462 dev_dbg(dev, "Auto-Neg Status Reg (%#06x) = %#06x\n", MDIO_STAT1, 1463 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1)); 1464 dev_dbg(dev, "Auto-Neg Ad Reg 1 (%#06x) = %#06x\n", 1465 MDIO_AN_ADVERTISE, 1466 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE)); 1467 dev_dbg(dev, "Auto-Neg Ad Reg 2 (%#06x) = %#06x\n", 1468 MDIO_AN_ADVERTISE + 1, 1469 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1)); 1470 dev_dbg(dev, "Auto-Neg Ad Reg 3 (%#06x) = %#06x\n", 1471 MDIO_AN_ADVERTISE + 2, 1472 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2)); 1473 dev_dbg(dev, "Auto-Neg Completion Reg (%#06x) = %#06x\n", 1474 MDIO_AN_COMP_STAT, 1475 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT)); 1476 1477 dev_dbg(dev, "\n*************************************************\n"); 1478 } 1479 1480 static int xgbe_phy_best_advertised_speed(struct xgbe_prv_data *pdata) 1481 { 1482 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1483 1484 if (XGBE_ADV(lks, 10000baseKR_Full)) 1485 return SPEED_10000; 1486 else if (XGBE_ADV(lks, 10000baseT_Full)) 1487 return SPEED_10000; 1488 else if (XGBE_ADV(lks, 2500baseX_Full)) 1489 return SPEED_2500; 1490 else if (XGBE_ADV(lks, 2500baseT_Full)) 1491 return SPEED_2500; 1492 else if (XGBE_ADV(lks, 1000baseKX_Full)) 1493 return SPEED_1000; 1494 else if (XGBE_ADV(lks, 1000baseT_Full)) 1495 return SPEED_1000; 1496 else if (XGBE_ADV(lks, 100baseT_Full)) 1497 return SPEED_100; 1498 else if (XGBE_ADV(lks, 10baseT_Full)) 1499 return SPEED_10; 1500 1501 return SPEED_UNKNOWN; 1502 } 1503 1504 static void xgbe_phy_exit(struct xgbe_prv_data *pdata) 1505 { 1506 pdata->phy_if.phy_impl.exit(pdata); 1507 } 1508 1509 static int xgbe_phy_init(struct xgbe_prv_data *pdata) 1510 { 1511 struct ethtool_link_ksettings *lks = &pdata->phy.lks; 1512 int ret; 1513 1514 mutex_init(&pdata->an_mutex); 1515 INIT_WORK(&pdata->an_irq_work, xgbe_an_irq_work); 1516 INIT_WORK(&pdata->an_work, xgbe_an_state_machine); 1517 pdata->mdio_mmd = MDIO_MMD_PCS; 1518 1519 /* Check for FEC support */ 1520 pdata->fec_ability = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, 1521 MDIO_PMA_10GBR_FECABLE); 1522 pdata->fec_ability &= (MDIO_PMA_10GBR_FECABLE_ABLE | 1523 MDIO_PMA_10GBR_FECABLE_ERRABLE); 1524 1525 /* Setup the phy (including supported features) */ 1526 ret = pdata->phy_if.phy_impl.init(pdata); 1527 if (ret) 1528 return ret; 1529 1530 /* Copy supported link modes to advertising link modes */ 1531 XGBE_LM_COPY(lks, advertising, lks, supported); 1532 1533 pdata->phy.address = 0; 1534 1535 if (XGBE_ADV(lks, Autoneg)) { 1536 pdata->phy.autoneg = AUTONEG_ENABLE; 1537 pdata->phy.speed = SPEED_UNKNOWN; 1538 pdata->phy.duplex = DUPLEX_UNKNOWN; 1539 } else { 1540 pdata->phy.autoneg = AUTONEG_DISABLE; 1541 pdata->phy.speed = xgbe_phy_best_advertised_speed(pdata); 1542 pdata->phy.duplex = DUPLEX_FULL; 1543 } 1544 1545 pdata->phy.link = 0; 1546 1547 pdata->phy.pause_autoneg = pdata->pause_autoneg; 1548 pdata->phy.tx_pause = pdata->tx_pause; 1549 pdata->phy.rx_pause = pdata->rx_pause; 1550 1551 /* Fix up Flow Control advertising */ 1552 XGBE_CLR_ADV(lks, Pause); 1553 XGBE_CLR_ADV(lks, Asym_Pause); 1554 1555 if (pdata->rx_pause) { 1556 XGBE_SET_ADV(lks, Pause); 1557 XGBE_SET_ADV(lks, Asym_Pause); 1558 } 1559 1560 if (pdata->tx_pause) { 1561 /* Equivalent to XOR of Asym_Pause */ 1562 if (XGBE_ADV(lks, Asym_Pause)) 1563 XGBE_CLR_ADV(lks, Asym_Pause); 1564 else 1565 XGBE_SET_ADV(lks, Asym_Pause); 1566 } 1567 1568 if (netif_msg_drv(pdata)) 1569 xgbe_dump_phy_registers(pdata); 1570 1571 return 0; 1572 } 1573 1574 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *phy_if) 1575 { 1576 phy_if->phy_init = xgbe_phy_init; 1577 phy_if->phy_exit = xgbe_phy_exit; 1578 1579 phy_if->phy_reset = xgbe_phy_reset; 1580 phy_if->phy_start = xgbe_phy_start; 1581 phy_if->phy_stop = xgbe_phy_stop; 1582 1583 phy_if->phy_status = xgbe_phy_status; 1584 phy_if->phy_config_aneg = xgbe_phy_config_aneg; 1585 1586 phy_if->phy_valid_speed = xgbe_phy_valid_speed; 1587 1588 phy_if->an_isr = xgbe_an_combined_isr; 1589 1590 phy_if->module_info = xgbe_phy_module_info; 1591 phy_if->module_eeprom = xgbe_phy_module_eeprom; 1592 } 1593