1ee00b24fSGeorge McCollister /* SPDX-License-Identifier: GPL-2.0 */ 2ee00b24fSGeorge McCollister 3ee00b24fSGeorge McCollister /* Register Base Addresses */ 4ee00b24fSGeorge McCollister #define XRS_DEVICE_ID_BASE 0x0 5ee00b24fSGeorge McCollister #define XRS_GPIO_BASE 0x10000 6ee00b24fSGeorge McCollister #define XRS_PORT_OFFSET 0x10000 7ee00b24fSGeorge McCollister #define XRS_PORT_BASE(x) (0x200000 + XRS_PORT_OFFSET * (x)) 8ee00b24fSGeorge McCollister #define XRS_RTC_BASE 0x280000 9ee00b24fSGeorge McCollister #define XRS_TS_OFFSET 0x8000 10ee00b24fSGeorge McCollister #define XRS_TS_BASE(x) (0x290000 + XRS_TS_OFFSET * (x)) 11ee00b24fSGeorge McCollister #define XRS_SWITCH_CONF_BASE 0x300000 12ee00b24fSGeorge McCollister 13ee00b24fSGeorge McCollister /* Device Identification Registers */ 14ee00b24fSGeorge McCollister #define XRS_DEV_ID0 (XRS_DEVICE_ID_BASE + 0) 15ee00b24fSGeorge McCollister #define XRS_DEV_ID1 (XRS_DEVICE_ID_BASE + 2) 16ee00b24fSGeorge McCollister #define XRS_INT_ID0 (XRS_DEVICE_ID_BASE + 4) 17ee00b24fSGeorge McCollister #define XRS_INT_ID1 (XRS_DEVICE_ID_BASE + 6) 18ee00b24fSGeorge McCollister #define XRS_REV_ID (XRS_DEVICE_ID_BASE + 8) 19ee00b24fSGeorge McCollister 20ee00b24fSGeorge McCollister /* GPIO Registers */ 21ee00b24fSGeorge McCollister #define XRS_CONFIG0 (XRS_GPIO_BASE + 0x1000) 22ee00b24fSGeorge McCollister #define XRS_INPUT_STATUS0 (XRS_GPIO_BASE + 0x1002) 23ee00b24fSGeorge McCollister #define XRS_CONFIG1 (XRS_GPIO_BASE + 0x1004) 24ee00b24fSGeorge McCollister #define XRS_INPUT_STATUS1 (XRS_GPIO_BASE + 0x1006) 25ee00b24fSGeorge McCollister #define XRS_CONFIG2 (XRS_GPIO_BASE + 0x1008) 26ee00b24fSGeorge McCollister #define XRS_INPUT_STATUS2 (XRS_GPIO_BASE + 0x100a) 27ee00b24fSGeorge McCollister 28ee00b24fSGeorge McCollister /* Port Configuration Registers */ 29ee00b24fSGeorge McCollister #define XRS_PORT_GEN_BASE(x) (XRS_PORT_BASE(x) + 0x0) 30ee00b24fSGeorge McCollister #define XRS_PORT_HSR_BASE(x) (XRS_PORT_BASE(x) + 0x2000) 31ee00b24fSGeorge McCollister #define XRS_PORT_PTP_BASE(x) (XRS_PORT_BASE(x) + 0x4000) 32ee00b24fSGeorge McCollister #define XRS_PORT_CNT_BASE(x) (XRS_PORT_BASE(x) + 0x6000) 33ee00b24fSGeorge McCollister #define XRS_PORT_IPO_BASE(x) (XRS_PORT_BASE(x) + 0x8000) 34ee00b24fSGeorge McCollister 35ee00b24fSGeorge McCollister /* Port Configuration Registers - General and State */ 36ee00b24fSGeorge McCollister #define XRS_PORT_STATE(x) (XRS_PORT_GEN_BASE(x) + 0x0) 37ee00b24fSGeorge McCollister #define XRS_PORT_FORWARDING 0 38ee00b24fSGeorge McCollister #define XRS_PORT_LEARNING 1 39ee00b24fSGeorge McCollister #define XRS_PORT_DISABLED 2 40ee00b24fSGeorge McCollister #define XRS_PORT_MODE_NORMAL 0 41ee00b24fSGeorge McCollister #define XRS_PORT_MODE_MANAGEMENT 1 42ee00b24fSGeorge McCollister #define XRS_PORT_SPEED_1000 0x12 43ee00b24fSGeorge McCollister #define XRS_PORT_SPEED_100 0x20 44ee00b24fSGeorge McCollister #define XRS_PORT_SPEED_10 0x30 45ee00b24fSGeorge McCollister #define XRS_PORT_VLAN(x) (XRS_PORT_GEN_BASE(x) + 0x10) 46ee00b24fSGeorge McCollister #define XRS_PORT_VLAN0_MAPPING(x) (XRS_PORT_GEN_BASE(x) + 0x12) 47ee00b24fSGeorge McCollister #define XRS_PORT_FWD_MASK(x) (XRS_PORT_GEN_BASE(x) + 0x14) 48ee00b24fSGeorge McCollister #define XRS_PORT_VLAN_PRIO(x) (XRS_PORT_GEN_BASE(x) + 0x16) 49ee00b24fSGeorge McCollister 50ee00b24fSGeorge McCollister /* Port Configuration Registers - HSR/PRP */ 51ee00b24fSGeorge McCollister #define XRS_HSR_CFG(x) (XRS_PORT_HSR_BASE(x) + 0x0) 52bd62e6f5SGeorge McCollister #define XRS_HSR_CFG_HSR_PRP BIT(0) 53bd62e6f5SGeorge McCollister #define XRS_HSR_CFG_HSR 0 54bd62e6f5SGeorge McCollister #define XRS_HSR_CFG_PRP BIT(8) 55bd62e6f5SGeorge McCollister #define XRS_HSR_CFG_LANID_A 0 56bd62e6f5SGeorge McCollister #define XRS_HSR_CFG_LANID_B BIT(10) 57ee00b24fSGeorge McCollister 58ee00b24fSGeorge McCollister /* Port Configuration Registers - PTP */ 59ee00b24fSGeorge McCollister #define XRS_PTP_RX_SYNC_DELAY_NS_LO(x) (XRS_PORT_PTP_BASE(x) + 0x2) 60ee00b24fSGeorge McCollister #define XRS_PTP_RX_SYNC_DELAY_NS_HI(x) (XRS_PORT_PTP_BASE(x) + 0x4) 61ee00b24fSGeorge McCollister #define XRS_PTP_RX_EVENT_DELAY_NS(x) (XRS_PORT_PTP_BASE(x) + 0xa) 62ee00b24fSGeorge McCollister #define XRS_PTP_TX_EVENT_DELAY_NS(x) (XRS_PORT_PTP_BASE(x) + 0x12) 63ee00b24fSGeorge McCollister 64ee00b24fSGeorge McCollister /* Port Configuration Registers - Counter */ 65ee00b24fSGeorge McCollister #define XRS_CNT_CTRL(x) (XRS_PORT_CNT_BASE(x) + 0x0) 66ee00b24fSGeorge McCollister #define XRS_RX_GOOD_OCTETS_L (XRS_PORT_CNT_BASE(0) + 0x200) 67ee00b24fSGeorge McCollister #define XRS_RX_GOOD_OCTETS_H (XRS_PORT_CNT_BASE(0) + 0x202) 68ee00b24fSGeorge McCollister #define XRS_RX_BAD_OCTETS_L (XRS_PORT_CNT_BASE(0) + 0x204) 69ee00b24fSGeorge McCollister #define XRS_RX_BAD_OCTETS_H (XRS_PORT_CNT_BASE(0) + 0x206) 70ee00b24fSGeorge McCollister #define XRS_RX_UNICAST_L (XRS_PORT_CNT_BASE(0) + 0x208) 71ee00b24fSGeorge McCollister #define XRS_RX_UNICAST_H (XRS_PORT_CNT_BASE(0) + 0x20a) 72ee00b24fSGeorge McCollister #define XRS_RX_BROADCAST_L (XRS_PORT_CNT_BASE(0) + 0x20c) 73ee00b24fSGeorge McCollister #define XRS_RX_BROADCAST_H (XRS_PORT_CNT_BASE(0) + 0x20e) 74ee00b24fSGeorge McCollister #define XRS_RX_MULTICAST_L (XRS_PORT_CNT_BASE(0) + 0x210) 75ee00b24fSGeorge McCollister #define XRS_RX_MULTICAST_H (XRS_PORT_CNT_BASE(0) + 0x212) 76ee00b24fSGeorge McCollister #define XRS_RX_UNDERSIZE_L (XRS_PORT_CNT_BASE(0) + 0x214) 77ee00b24fSGeorge McCollister #define XRS_RX_UNDERSIZE_H (XRS_PORT_CNT_BASE(0) + 0x216) 78ee00b24fSGeorge McCollister #define XRS_RX_FRAGMENTS_L (XRS_PORT_CNT_BASE(0) + 0x218) 79ee00b24fSGeorge McCollister #define XRS_RX_FRAGMENTS_H (XRS_PORT_CNT_BASE(0) + 0x21a) 80ee00b24fSGeorge McCollister #define XRS_RX_OVERSIZE_L (XRS_PORT_CNT_BASE(0) + 0x21c) 81ee00b24fSGeorge McCollister #define XRS_RX_OVERSIZE_H (XRS_PORT_CNT_BASE(0) + 0x21e) 82ee00b24fSGeorge McCollister #define XRS_RX_JABBER_L (XRS_PORT_CNT_BASE(0) + 0x220) 83ee00b24fSGeorge McCollister #define XRS_RX_JABBER_H (XRS_PORT_CNT_BASE(0) + 0x222) 84ee00b24fSGeorge McCollister #define XRS_RX_ERR_L (XRS_PORT_CNT_BASE(0) + 0x224) 85ee00b24fSGeorge McCollister #define XRS_RX_ERR_H (XRS_PORT_CNT_BASE(0) + 0x226) 86ee00b24fSGeorge McCollister #define XRS_RX_CRC_L (XRS_PORT_CNT_BASE(0) + 0x228) 87ee00b24fSGeorge McCollister #define XRS_RX_CRC_H (XRS_PORT_CNT_BASE(0) + 0x22a) 88ee00b24fSGeorge McCollister #define XRS_RX_64_L (XRS_PORT_CNT_BASE(0) + 0x22c) 89ee00b24fSGeorge McCollister #define XRS_RX_64_H (XRS_PORT_CNT_BASE(0) + 0x22e) 90ee00b24fSGeorge McCollister #define XRS_RX_65_127_L (XRS_PORT_CNT_BASE(0) + 0x230) 91ee00b24fSGeorge McCollister #define XRS_RX_65_127_H (XRS_PORT_CNT_BASE(0) + 0x232) 92ee00b24fSGeorge McCollister #define XRS_RX_128_255_L (XRS_PORT_CNT_BASE(0) + 0x234) 93ee00b24fSGeorge McCollister #define XRS_RX_128_255_H (XRS_PORT_CNT_BASE(0) + 0x236) 94ee00b24fSGeorge McCollister #define XRS_RX_256_511_L (XRS_PORT_CNT_BASE(0) + 0x238) 95ee00b24fSGeorge McCollister #define XRS_RX_256_511_H (XRS_PORT_CNT_BASE(0) + 0x23a) 96ee00b24fSGeorge McCollister #define XRS_RX_512_1023_L (XRS_PORT_CNT_BASE(0) + 0x23c) 97ee00b24fSGeorge McCollister #define XRS_RX_512_1023_H (XRS_PORT_CNT_BASE(0) + 0x23e) 98ee00b24fSGeorge McCollister #define XRS_RX_1024_1536_L (XRS_PORT_CNT_BASE(0) + 0x240) 99ee00b24fSGeorge McCollister #define XRS_RX_1024_1536_H (XRS_PORT_CNT_BASE(0) + 0x242) 100ee00b24fSGeorge McCollister #define XRS_RX_HSR_PRP_L (XRS_PORT_CNT_BASE(0) + 0x244) 101ee00b24fSGeorge McCollister #define XRS_RX_HSR_PRP_H (XRS_PORT_CNT_BASE(0) + 0x246) 102ee00b24fSGeorge McCollister #define XRS_RX_WRONGLAN_L (XRS_PORT_CNT_BASE(0) + 0x248) 103ee00b24fSGeorge McCollister #define XRS_RX_WRONGLAN_H (XRS_PORT_CNT_BASE(0) + 0x24a) 104ee00b24fSGeorge McCollister #define XRS_RX_DUPLICATE_L (XRS_PORT_CNT_BASE(0) + 0x24c) 105ee00b24fSGeorge McCollister #define XRS_RX_DUPLICATE_H (XRS_PORT_CNT_BASE(0) + 0x24e) 106ee00b24fSGeorge McCollister #define XRS_TX_OCTETS_L (XRS_PORT_CNT_BASE(0) + 0x280) 107ee00b24fSGeorge McCollister #define XRS_TX_OCTETS_H (XRS_PORT_CNT_BASE(0) + 0x282) 108ee00b24fSGeorge McCollister #define XRS_TX_UNICAST_L (XRS_PORT_CNT_BASE(0) + 0x284) 109ee00b24fSGeorge McCollister #define XRS_TX_UNICAST_H (XRS_PORT_CNT_BASE(0) + 0x286) 110ee00b24fSGeorge McCollister #define XRS_TX_BROADCAST_L (XRS_PORT_CNT_BASE(0) + 0x288) 111ee00b24fSGeorge McCollister #define XRS_TX_BROADCAST_H (XRS_PORT_CNT_BASE(0) + 0x28a) 112ee00b24fSGeorge McCollister #define XRS_TX_MULTICAST_L (XRS_PORT_CNT_BASE(0) + 0x28c) 113ee00b24fSGeorge McCollister #define XRS_TX_MULTICAST_H (XRS_PORT_CNT_BASE(0) + 0x28e) 114ee00b24fSGeorge McCollister #define XRS_TX_HSR_PRP_L (XRS_PORT_CNT_BASE(0) + 0x290) 115ee00b24fSGeorge McCollister #define XRS_TX_HSR_PRP_H (XRS_PORT_CNT_BASE(0) + 0x292) 116ee00b24fSGeorge McCollister #define XRS_PRIQ_DROP_L (XRS_PORT_CNT_BASE(0) + 0x2c0) 117ee00b24fSGeorge McCollister #define XRS_PRIQ_DROP_H (XRS_PORT_CNT_BASE(0) + 0x2c2) 118ee00b24fSGeorge McCollister #define XRS_EARLY_DROP_L (XRS_PORT_CNT_BASE(0) + 0x2c4) 119ee00b24fSGeorge McCollister #define XRS_EARLY_DROP_H (XRS_PORT_CNT_BASE(0) + 0x2c6) 120ee00b24fSGeorge McCollister 121ee00b24fSGeorge McCollister /* Port Configuration Registers - Inbound Policy 0 - 15 */ 122ee00b24fSGeorge McCollister #define XRS_ETH_ADDR_CFG(x, p) (XRS_PORT_IPO_BASE(x) + \ 123ee00b24fSGeorge McCollister (p) * 0x20 + 0x0) 124ee00b24fSGeorge McCollister #define XRS_ETH_ADDR_FWD_ALLOW(x, p) (XRS_PORT_IPO_BASE(x) + \ 125ee00b24fSGeorge McCollister (p) * 0x20 + 0x2) 126ee00b24fSGeorge McCollister #define XRS_ETH_ADDR_FWD_MIRROR(x, p) (XRS_PORT_IPO_BASE(x) + \ 127ee00b24fSGeorge McCollister (p) * 0x20 + 0x4) 128ee00b24fSGeorge McCollister #define XRS_ETH_ADDR_0(x, p) (XRS_PORT_IPO_BASE(x) + \ 129ee00b24fSGeorge McCollister (p) * 0x20 + 0x8) 130ee00b24fSGeorge McCollister #define XRS_ETH_ADDR_1(x, p) (XRS_PORT_IPO_BASE(x) + \ 131ee00b24fSGeorge McCollister (p) * 0x20 + 0xa) 132ee00b24fSGeorge McCollister #define XRS_ETH_ADDR_2(x, p) (XRS_PORT_IPO_BASE(x) + \ 133ee00b24fSGeorge McCollister (p) * 0x20 + 0xc) 134ee00b24fSGeorge McCollister 135ee00b24fSGeorge McCollister /* RTC Registers */ 136ee00b24fSGeorge McCollister #define XRS_CUR_NSEC0 (XRS_RTC_BASE + 0x1004) 137ee00b24fSGeorge McCollister #define XRS_CUR_NSEC1 (XRS_RTC_BASE + 0x1006) 138ee00b24fSGeorge McCollister #define XRS_CUR_SEC0 (XRS_RTC_BASE + 0x1008) 139ee00b24fSGeorge McCollister #define XRS_CUR_SEC1 (XRS_RTC_BASE + 0x100a) 140ee00b24fSGeorge McCollister #define XRS_CUR_SEC2 (XRS_RTC_BASE + 0x100c) 141ee00b24fSGeorge McCollister #define XRS_TIME_CC0 (XRS_RTC_BASE + 0x1010) 142ee00b24fSGeorge McCollister #define XRS_TIME_CC1 (XRS_RTC_BASE + 0x1012) 143ee00b24fSGeorge McCollister #define XRS_TIME_CC2 (XRS_RTC_BASE + 0x1014) 144ee00b24fSGeorge McCollister #define XRS_STEP_SIZE0 (XRS_RTC_BASE + 0x1020) 145ee00b24fSGeorge McCollister #define XRS_STEP_SIZE1 (XRS_RTC_BASE + 0x1022) 146ee00b24fSGeorge McCollister #define XRS_STEP_SIZE2 (XRS_RTC_BASE + 0x1024) 147ee00b24fSGeorge McCollister #define XRS_ADJUST_NSEC0 (XRS_RTC_BASE + 0x1034) 148ee00b24fSGeorge McCollister #define XRS_ADJUST_NSEC1 (XRS_RTC_BASE + 0x1036) 149ee00b24fSGeorge McCollister #define XRS_ADJUST_SEC0 (XRS_RTC_BASE + 0x1038) 150ee00b24fSGeorge McCollister #define XRS_ADJUST_SEC1 (XRS_RTC_BASE + 0x103a) 151ee00b24fSGeorge McCollister #define XRS_ADJUST_SEC2 (XRS_RTC_BASE + 0x103c) 152ee00b24fSGeorge McCollister #define XRS_TIME_CMD (XRS_RTC_BASE + 0x1040) 153ee00b24fSGeorge McCollister 154ee00b24fSGeorge McCollister /* Time Stamper Registers */ 155ee00b24fSGeorge McCollister #define XRS_TS_CTRL(x) (XRS_TS_BASE(x) + 0x1000) 156ee00b24fSGeorge McCollister #define XRS_TS_INT_MASK(x) (XRS_TS_BASE(x) + 0x1008) 157ee00b24fSGeorge McCollister #define XRS_TS_INT_STATUS(x) (XRS_TS_BASE(x) + 0x1010) 158ee00b24fSGeorge McCollister #define XRS_TS_NSEC0(x) (XRS_TS_BASE(x) + 0x1104) 159ee00b24fSGeorge McCollister #define XRS_TS_NSEC1(x) (XRS_TS_BASE(x) + 0x1106) 160ee00b24fSGeorge McCollister #define XRS_TS_SEC0(x) (XRS_TS_BASE(x) + 0x1108) 161ee00b24fSGeorge McCollister #define XRS_TS_SEC1(x) (XRS_TS_BASE(x) + 0x110a) 162ee00b24fSGeorge McCollister #define XRS_TS_SEC2(x) (XRS_TS_BASE(x) + 0x110c) 163ee00b24fSGeorge McCollister #define XRS_PNCT0(x) (XRS_TS_BASE(x) + 0x1110) 164ee00b24fSGeorge McCollister #define XRS_PNCT1(x) (XRS_TS_BASE(x) + 0x1112) 165ee00b24fSGeorge McCollister 166ee00b24fSGeorge McCollister /* Switch Configuration Registers */ 167ee00b24fSGeorge McCollister #define XRS_SWITCH_GEN_BASE (XRS_SWITCH_CONF_BASE + 0x0) 168ee00b24fSGeorge McCollister #define XRS_SWITCH_TS_BASE (XRS_SWITCH_CONF_BASE + 0x2000) 169ee00b24fSGeorge McCollister #define XRS_SWITCH_VLAN_BASE (XRS_SWITCH_CONF_BASE + 0x4000) 170ee00b24fSGeorge McCollister 171ee00b24fSGeorge McCollister /* Switch Configuration Registers - General */ 172ee00b24fSGeorge McCollister #define XRS_GENERAL (XRS_SWITCH_GEN_BASE + 0x10) 173ee00b24fSGeorge McCollister #define XRS_GENERAL_TIME_TRAILER BIT(9) 174ee00b24fSGeorge McCollister #define XRS_GENERAL_MOD_SYNC BIT(10) 175ee00b24fSGeorge McCollister #define XRS_GENERAL_CUT_THRU BIT(13) 176ee00b24fSGeorge McCollister #define XRS_GENERAL_CLR_MAC_TBL BIT(14) 177ee00b24fSGeorge McCollister #define XRS_GENERAL_RESET BIT(15) 178ee00b24fSGeorge McCollister #define XRS_MT_CLEAR_MASK (XRS_SWITCH_GEN_BASE + 0x12) 179ee00b24fSGeorge McCollister #define XRS_ADDRESS_AGING (XRS_SWITCH_GEN_BASE + 0x20) 180ee00b24fSGeorge McCollister #define XRS_TS_CTRL_TX (XRS_SWITCH_GEN_BASE + 0x28) 181ee00b24fSGeorge McCollister #define XRS_TS_CTRL_RX (XRS_SWITCH_GEN_BASE + 0x2a) 182ee00b24fSGeorge McCollister #define XRS_INT_MASK (XRS_SWITCH_GEN_BASE + 0x2c) 183ee00b24fSGeorge McCollister #define XRS_INT_STATUS (XRS_SWITCH_GEN_BASE + 0x2e) 184ee00b24fSGeorge McCollister #define XRS_MAC_TABLE0 (XRS_SWITCH_GEN_BASE + 0x200) 185ee00b24fSGeorge McCollister #define XRS_MAC_TABLE1 (XRS_SWITCH_GEN_BASE + 0x202) 186ee00b24fSGeorge McCollister #define XRS_MAC_TABLE2 (XRS_SWITCH_GEN_BASE + 0x204) 187ee00b24fSGeorge McCollister #define XRS_MAC_TABLE3 (XRS_SWITCH_GEN_BASE + 0x206) 188ee00b24fSGeorge McCollister 189ee00b24fSGeorge McCollister /* Switch Configuration Registers - Frame Timestamp */ 190ee00b24fSGeorge McCollister #define XRS_TX_TS_NS_LO(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + 0x0) 191ee00b24fSGeorge McCollister #define XRS_TX_TS_NS_HI(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + 0x2) 192ee00b24fSGeorge McCollister #define XRS_TX_TS_S_LO(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + 0x4) 193ee00b24fSGeorge McCollister #define XRS_TX_TS_S_HI(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + 0x6) 194ee00b24fSGeorge McCollister #define XRS_TX_TS_HDR(t, h) (XRS_SWITCH_TS_BASE + 0x80 * (t) + \ 195ee00b24fSGeorge McCollister 0x2 * (h) + 0xe) 196ee00b24fSGeorge McCollister #define XRS_RX_TS_NS_LO(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + \ 197ee00b24fSGeorge McCollister 0x200) 198ee00b24fSGeorge McCollister #define XRS_RX_TS_NS_HI(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + \ 199ee00b24fSGeorge McCollister 0x202) 200ee00b24fSGeorge McCollister #define XRS_RX_TS_S_LO(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + \ 201ee00b24fSGeorge McCollister 0x204) 202ee00b24fSGeorge McCollister #define XRS_RX_TS_S_HI(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + \ 203ee00b24fSGeorge McCollister 0x206) 204ee00b24fSGeorge McCollister #define XRS_RX_TS_HDR(t, h) (XRS_SWITCH_TS_BASE + 0x80 * (t) + \ 205ee00b24fSGeorge McCollister 0x2 * (h) + 0xe) 206ee00b24fSGeorge McCollister 207ee00b24fSGeorge McCollister /* Switch Configuration Registers - VLAN */ 208ee00b24fSGeorge McCollister #define XRS_VLAN(v) (XRS_SWITCH_VLAN_BASE + 0x2 * (v)) 209