xref: /linux/drivers/mtd/nand/raw/nand_toshiba.c (revision c942fddf8793b2013be8c901b47d0a8dc02bf99f)
1*c942fddfSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
29b2d61f8SBoris Brezillon /*
39b2d61f8SBoris Brezillon  * Copyright (C) 2017 Free Electrons
49b2d61f8SBoris Brezillon  * Copyright (C) 2017 NextThing Co
59b2d61f8SBoris Brezillon  *
69b2d61f8SBoris Brezillon  * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
79b2d61f8SBoris Brezillon  */
89b2d61f8SBoris Brezillon 
9348d56a8SBoris Brezillon #include "internals.h"
109b2d61f8SBoris Brezillon 
11f223713fSKOBAYASHI Yoshitake /* Bit for detecting BENAND */
12f223713fSKOBAYASHI Yoshitake #define TOSHIBA_NAND_ID4_IS_BENAND		BIT(7)
13f223713fSKOBAYASHI Yoshitake 
14f223713fSKOBAYASHI Yoshitake /* Recommended to rewrite for BENAND */
15f223713fSKOBAYASHI Yoshitake #define TOSHIBA_NAND_STATUS_REWRITE_RECOMMENDED	BIT(3)
16f223713fSKOBAYASHI Yoshitake 
17e9836761SMiquel Raynal static int toshiba_nand_benand_eccstatus(struct nand_chip *chip)
18f223713fSKOBAYASHI Yoshitake {
19e9836761SMiquel Raynal 	struct mtd_info *mtd = nand_to_mtd(chip);
20f223713fSKOBAYASHI Yoshitake 	int ret;
21f223713fSKOBAYASHI Yoshitake 	unsigned int max_bitflips = 0;
22f223713fSKOBAYASHI Yoshitake 	u8 status;
23f223713fSKOBAYASHI Yoshitake 
24f223713fSKOBAYASHI Yoshitake 	/* Check Status */
25f223713fSKOBAYASHI Yoshitake 	ret = nand_status_op(chip, &status);
26f223713fSKOBAYASHI Yoshitake 	if (ret)
27f223713fSKOBAYASHI Yoshitake 		return ret;
28f223713fSKOBAYASHI Yoshitake 
29f223713fSKOBAYASHI Yoshitake 	if (status & NAND_STATUS_FAIL) {
30f223713fSKOBAYASHI Yoshitake 		/* uncorrected */
31f223713fSKOBAYASHI Yoshitake 		mtd->ecc_stats.failed++;
32f223713fSKOBAYASHI Yoshitake 	} else if (status & TOSHIBA_NAND_STATUS_REWRITE_RECOMMENDED) {
33f223713fSKOBAYASHI Yoshitake 		/* corrected */
34f223713fSKOBAYASHI Yoshitake 		max_bitflips = mtd->bitflip_threshold;
35f223713fSKOBAYASHI Yoshitake 		mtd->ecc_stats.corrected += max_bitflips;
36f223713fSKOBAYASHI Yoshitake 	}
37f223713fSKOBAYASHI Yoshitake 
38f223713fSKOBAYASHI Yoshitake 	return max_bitflips;
39f223713fSKOBAYASHI Yoshitake }
40f223713fSKOBAYASHI Yoshitake 
41f223713fSKOBAYASHI Yoshitake static int
42b9761687SBoris Brezillon toshiba_nand_read_page_benand(struct nand_chip *chip, uint8_t *buf,
43f223713fSKOBAYASHI Yoshitake 			      int oob_required, int page)
44f223713fSKOBAYASHI Yoshitake {
45f223713fSKOBAYASHI Yoshitake 	int ret;
46f223713fSKOBAYASHI Yoshitake 
47b9761687SBoris Brezillon 	ret = nand_read_page_raw(chip, buf, oob_required, page);
48f223713fSKOBAYASHI Yoshitake 	if (ret)
49f223713fSKOBAYASHI Yoshitake 		return ret;
50f223713fSKOBAYASHI Yoshitake 
51e9836761SMiquel Raynal 	return toshiba_nand_benand_eccstatus(chip);
52f223713fSKOBAYASHI Yoshitake }
53f223713fSKOBAYASHI Yoshitake 
54f223713fSKOBAYASHI Yoshitake static int
55b9761687SBoris Brezillon toshiba_nand_read_subpage_benand(struct nand_chip *chip, uint32_t data_offs,
56f223713fSKOBAYASHI Yoshitake 				 uint32_t readlen, uint8_t *bufpoi, int page)
57f223713fSKOBAYASHI Yoshitake {
58f223713fSKOBAYASHI Yoshitake 	int ret;
59f223713fSKOBAYASHI Yoshitake 
60f223713fSKOBAYASHI Yoshitake 	ret = nand_read_page_op(chip, page, data_offs,
61f223713fSKOBAYASHI Yoshitake 				bufpoi + data_offs, readlen);
62f223713fSKOBAYASHI Yoshitake 	if (ret)
63f223713fSKOBAYASHI Yoshitake 		return ret;
64f223713fSKOBAYASHI Yoshitake 
65e9836761SMiquel Raynal 	return toshiba_nand_benand_eccstatus(chip);
66f223713fSKOBAYASHI Yoshitake }
67f223713fSKOBAYASHI Yoshitake 
68f223713fSKOBAYASHI Yoshitake static void toshiba_nand_benand_init(struct nand_chip *chip)
69f223713fSKOBAYASHI Yoshitake {
70f223713fSKOBAYASHI Yoshitake 	struct mtd_info *mtd = nand_to_mtd(chip);
71f223713fSKOBAYASHI Yoshitake 
72f223713fSKOBAYASHI Yoshitake 	/*
73f223713fSKOBAYASHI Yoshitake 	 * On BENAND, the entire OOB region can be used by the MTD user.
74f223713fSKOBAYASHI Yoshitake 	 * The calculated ECC bytes are stored into other isolated
75f223713fSKOBAYASHI Yoshitake 	 * area which is not accessible to users.
76f223713fSKOBAYASHI Yoshitake 	 * This is why chip->ecc.bytes = 0.
77f223713fSKOBAYASHI Yoshitake 	 */
78f223713fSKOBAYASHI Yoshitake 	chip->ecc.bytes = 0;
79f223713fSKOBAYASHI Yoshitake 	chip->ecc.size = 512;
80f223713fSKOBAYASHI Yoshitake 	chip->ecc.strength = 8;
81f223713fSKOBAYASHI Yoshitake 	chip->ecc.read_page = toshiba_nand_read_page_benand;
82f223713fSKOBAYASHI Yoshitake 	chip->ecc.read_subpage = toshiba_nand_read_subpage_benand;
83f223713fSKOBAYASHI Yoshitake 	chip->ecc.write_page = nand_write_page_raw;
84f223713fSKOBAYASHI Yoshitake 	chip->ecc.read_page_raw = nand_read_page_raw_notsupp;
85f223713fSKOBAYASHI Yoshitake 	chip->ecc.write_page_raw = nand_write_page_raw_notsupp;
86f223713fSKOBAYASHI Yoshitake 
87f223713fSKOBAYASHI Yoshitake 	chip->options |= NAND_SUBPAGE_READ;
88f223713fSKOBAYASHI Yoshitake 
89f223713fSKOBAYASHI Yoshitake 	mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
90f223713fSKOBAYASHI Yoshitake }
91f223713fSKOBAYASHI Yoshitake 
929b2d61f8SBoris Brezillon static void toshiba_nand_decode_id(struct nand_chip *chip)
939b2d61f8SBoris Brezillon {
949b2d61f8SBoris Brezillon 	struct mtd_info *mtd = nand_to_mtd(chip);
95629a442cSBoris Brezillon 	struct nand_memory_organization *memorg;
96629a442cSBoris Brezillon 
97629a442cSBoris Brezillon 	memorg = nanddev_get_memorg(&chip->base);
989b2d61f8SBoris Brezillon 
999b2d61f8SBoris Brezillon 	nand_decode_ext_id(chip);
1009b2d61f8SBoris Brezillon 
1019b2d61f8SBoris Brezillon 	/*
1029b2d61f8SBoris Brezillon 	 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
1039b2d61f8SBoris Brezillon 	 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
1049b2d61f8SBoris Brezillon 	 * follows:
1059b2d61f8SBoris Brezillon 	 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
1069b2d61f8SBoris Brezillon 	 *                         110b -> 24nm
1079b2d61f8SBoris Brezillon 	 * - ID byte 5, bit[7]:    1 -> BENAND, 0 -> raw SLC
1089b2d61f8SBoris Brezillon 	 */
1099b2d61f8SBoris Brezillon 	if (chip->id.len >= 6 && nand_is_slc(chip) &&
1109b2d61f8SBoris Brezillon 	    (chip->id.data[5] & 0x7) == 0x6 /* 24nm */ &&
111629a442cSBoris Brezillon 	    !(chip->id.data[4] & 0x80) /* !BENAND */) {
112629a442cSBoris Brezillon 		memorg->oobsize = 32 * memorg->pagesize >> 9;
113629a442cSBoris Brezillon 		mtd->oobsize = memorg->oobsize;
114629a442cSBoris Brezillon 	}
115fb3bff5bSKOBAYASHI Yoshitake 
116fb3bff5bSKOBAYASHI Yoshitake 	/*
117fb3bff5bSKOBAYASHI Yoshitake 	 * Extract ECC requirements from 6th id byte.
118fb3bff5bSKOBAYASHI Yoshitake 	 * For Toshiba SLC, ecc requrements are as follows:
119fb3bff5bSKOBAYASHI Yoshitake 	 *  - 43nm: 1 bit ECC for each 512Byte is required.
120fb3bff5bSKOBAYASHI Yoshitake 	 *  - 32nm: 4 bit ECC for each 512Byte is required.
121fb3bff5bSKOBAYASHI Yoshitake 	 *  - 24nm: 8 bit ECC for each 512Byte is required.
122fb3bff5bSKOBAYASHI Yoshitake 	 */
123fb3bff5bSKOBAYASHI Yoshitake 	if (chip->id.len >= 6 && nand_is_slc(chip)) {
1246a1b66d6SBoris Brezillon 		chip->base.eccreq.step_size = 512;
125fb3bff5bSKOBAYASHI Yoshitake 		switch (chip->id.data[5] & 0x7) {
126fb3bff5bSKOBAYASHI Yoshitake 		case 0x4:
1276a1b66d6SBoris Brezillon 			chip->base.eccreq.strength = 1;
128fb3bff5bSKOBAYASHI Yoshitake 			break;
129fb3bff5bSKOBAYASHI Yoshitake 		case 0x5:
1306a1b66d6SBoris Brezillon 			chip->base.eccreq.strength = 4;
131fb3bff5bSKOBAYASHI Yoshitake 			break;
132fb3bff5bSKOBAYASHI Yoshitake 		case 0x6:
1336a1b66d6SBoris Brezillon 			chip->base.eccreq.strength = 8;
134fb3bff5bSKOBAYASHI Yoshitake 			break;
135fb3bff5bSKOBAYASHI Yoshitake 		default:
136fb3bff5bSKOBAYASHI Yoshitake 			WARN(1, "Could not get ECC info");
1376a1b66d6SBoris Brezillon 			chip->base.eccreq.step_size = 0;
138fb3bff5bSKOBAYASHI Yoshitake 			break;
139fb3bff5bSKOBAYASHI Yoshitake 		}
140fb3bff5bSKOBAYASHI Yoshitake 	}
1419b2d61f8SBoris Brezillon }
1429b2d61f8SBoris Brezillon 
1439b2d61f8SBoris Brezillon static int toshiba_nand_init(struct nand_chip *chip)
1449b2d61f8SBoris Brezillon {
1459b2d61f8SBoris Brezillon 	if (nand_is_slc(chip))
146bb592548SFrieder Schrempf 		chip->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE;
1479b2d61f8SBoris Brezillon 
148f223713fSKOBAYASHI Yoshitake 	/* Check that chip is BENAND and ECC mode is on-die */
149f223713fSKOBAYASHI Yoshitake 	if (nand_is_slc(chip) && chip->ecc.mode == NAND_ECC_ON_DIE &&
150f223713fSKOBAYASHI Yoshitake 	    chip->id.data[4] & TOSHIBA_NAND_ID4_IS_BENAND)
151f223713fSKOBAYASHI Yoshitake 		toshiba_nand_benand_init(chip);
152f223713fSKOBAYASHI Yoshitake 
1539b2d61f8SBoris Brezillon 	return 0;
1549b2d61f8SBoris Brezillon }
1559b2d61f8SBoris Brezillon 
1569b2d61f8SBoris Brezillon const struct nand_manufacturer_ops toshiba_nand_manuf_ops = {
1579b2d61f8SBoris Brezillon 	.detect = toshiba_nand_decode_id,
1589b2d61f8SBoris Brezillon 	.init = toshiba_nand_init,
1599b2d61f8SBoris Brezillon };
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