1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas SDHI 4 * 5 * Copyright (C) 2015-19 Renesas Electronics Corporation 6 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang 7 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 8 * Copyright (C) 2009 Magnus Damm 9 * 10 * Based on "Compaq ASIC3 support": 11 * 12 * Copyright 2001 Compaq Computer Corporation. 13 * Copyright 2004-2005 Phil Blundell 14 * Copyright 2007-2008 OpenedHand Ltd. 15 * 16 * Authors: Phil Blundell <pb@handhelds.org>, 17 * Samuel Ortiz <sameo@openedhand.com> 18 * 19 */ 20 21 #include <linux/clk.h> 22 #include <linux/delay.h> 23 #include <linux/iopoll.h> 24 #include <linux/kernel.h> 25 #include <linux/mmc/host.h> 26 #include <linux/mmc/mmc.h> 27 #include <linux/mmc/slot-gpio.h> 28 #include <linux/module.h> 29 #include <linux/pinctrl/consumer.h> 30 #include <linux/pinctrl/pinctrl-state.h> 31 #include <linux/platform_data/tmio.h> 32 #include <linux/platform_device.h> 33 #include <linux/pm_domain.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/regulator/driver.h> 36 #include <linux/regulator/of_regulator.h> 37 #include <linux/reset.h> 38 #include <linux/sh_dma.h> 39 #include <linux/slab.h> 40 41 #include "renesas_sdhi.h" 42 #include "tmio_mmc.h" 43 44 #define CTL_HOST_MODE 0xe4 45 #define HOST_MODE_GEN2_SDR50_WMODE BIT(0) 46 #define HOST_MODE_GEN2_SDR104_WMODE BIT(0) 47 #define HOST_MODE_GEN3_WMODE BIT(0) 48 #define HOST_MODE_GEN3_BUSWIDTH BIT(8) 49 50 #define HOST_MODE_GEN3_16BIT HOST_MODE_GEN3_WMODE 51 #define HOST_MODE_GEN3_32BIT (HOST_MODE_GEN3_WMODE | HOST_MODE_GEN3_BUSWIDTH) 52 #define HOST_MODE_GEN3_64BIT 0 53 54 #define SDHI_VER_GEN2_SDR50 0x490c 55 #define SDHI_VER_RZ_A1 0x820b 56 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */ 57 #define SDHI_VER_GEN2_SDR104 0xcb0d 58 #define SDHI_VER_GEN3_SD 0xcc10 59 #define SDHI_VER_GEN3_SDMMC 0xcd10 60 61 #define SDHI_GEN3_MMC0_ADDR 0xee140000 62 63 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width) 64 { 65 u32 val; 66 67 /* 68 * see also 69 * renesas_sdhi_of_data :: dma_buswidth 70 */ 71 switch (sd_ctrl_read16(host, CTL_VERSION)) { 72 case SDHI_VER_GEN2_SDR50: 73 val = (width == 32) ? HOST_MODE_GEN2_SDR50_WMODE : 0; 74 break; 75 case SDHI_VER_GEN2_SDR104: 76 val = (width == 32) ? 0 : HOST_MODE_GEN2_SDR104_WMODE; 77 break; 78 case SDHI_VER_GEN3_SD: 79 case SDHI_VER_GEN3_SDMMC: 80 if (width == 64) 81 val = HOST_MODE_GEN3_64BIT; 82 else if (width == 32) 83 val = HOST_MODE_GEN3_32BIT; 84 else 85 val = HOST_MODE_GEN3_16BIT; 86 break; 87 default: 88 /* nothing to do */ 89 return; 90 } 91 92 sd_ctrl_write16(host, CTL_HOST_MODE, val); 93 } 94 95 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host) 96 { 97 struct mmc_host *mmc = host->mmc; 98 struct renesas_sdhi *priv = host_to_priv(host); 99 int ret; 100 101 ret = clk_prepare_enable(priv->clk_cd); 102 if (ret < 0) 103 return ret; 104 105 /* 106 * The clock driver may not know what maximum frequency 107 * actually works, so it should be set with the max-frequency 108 * property which will already have been read to f_max. If it 109 * was missing, assume the current frequency is the maximum. 110 */ 111 if (!mmc->f_max) 112 mmc->f_max = clk_get_rate(priv->clk); 113 114 /* 115 * Minimum frequency is the minimum input clock frequency 116 * divided by our maximum divider. 117 */ 118 mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L); 119 120 /* enable 16bit data access on SDBUF as default */ 121 renesas_sdhi_sdbuf_width(host, 16); 122 123 return 0; 124 } 125 126 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, 127 unsigned int wanted_clock) 128 { 129 struct renesas_sdhi *priv = host_to_priv(host); 130 struct clk *ref_clk = priv->clk; 131 unsigned int freq, diff, best_freq = 0, diff_min = ~0; 132 unsigned int new_clock, clkh_shift = 0; 133 unsigned int new_upper_limit; 134 int i; 135 136 /* 137 * We simply return the current rate if a) we are not on a R-Car Gen2+ 138 * SoC (may work for others, but untested) or b) if the SCC needs its 139 * clock during tuning, so we don't change the external clock setup. 140 */ 141 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc)) 142 return clk_get_rate(priv->clk); 143 144 if (priv->clkh) { 145 /* HS400 with 4TAP needs different clock settings */ 146 bool use_4tap = sdhi_has_quirk(priv, hs400_4taps); 147 bool need_slow_clkh = host->mmc->ios.timing == MMC_TIMING_MMC_HS400; 148 clkh_shift = use_4tap && need_slow_clkh ? 1 : 2; 149 ref_clk = priv->clkh; 150 } 151 152 new_clock = wanted_clock << clkh_shift; 153 154 /* 155 * We want the bus clock to be as close as possible to, but no 156 * greater than, new_clock. As we can divide by 1 << i for 157 * any i in [0, 9] we want the input clock to be as close as 158 * possible, but no greater than, new_clock << i. 159 * 160 * Add an upper limit of 1/1024 rate higher to the clock rate to fix 161 * clk rate jumping to lower rate due to rounding error (eg: RZ/G2L has 162 * 3 clk sources 533.333333 MHz, 400 MHz and 266.666666 MHz. The request 163 * for 533.333333 MHz will selects a slower 400 MHz due to rounding 164 * error (533333333 Hz / 4 * 4 = 533333332 Hz < 533333333 Hz)). 165 */ 166 for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) { 167 freq = clk_round_rate(ref_clk, new_clock << i); 168 new_upper_limit = (new_clock << i) + ((new_clock << i) >> 10); 169 if (freq > new_upper_limit) { 170 /* Too fast; look for a slightly slower option */ 171 freq = clk_round_rate(ref_clk, (new_clock << i) / 4 * 3); 172 if (freq > new_upper_limit) 173 continue; 174 } 175 176 diff = new_clock - (freq >> i); 177 if (diff <= diff_min) { 178 best_freq = freq; 179 diff_min = diff; 180 } 181 } 182 183 clk_set_rate(ref_clk, best_freq); 184 185 if (priv->clkh) 186 clk_set_rate(priv->clk, best_freq >> clkh_shift); 187 188 return clk_get_rate(priv->clk); 189 } 190 191 static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, 192 unsigned int new_clock) 193 { 194 unsigned int clk_margin; 195 u32 clk = 0, clock; 196 197 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 198 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 199 200 if (new_clock == 0) { 201 host->mmc->actual_clock = 0; 202 goto out; 203 } 204 205 host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock); 206 clock = host->mmc->actual_clock / 512; 207 208 /* 209 * Add a margin of 1/1024 rate higher to the clock rate in order 210 * to avoid clk variable setting a value of 0 due to the margin 211 * provided for actual_clock in renesas_sdhi_clk_update(). 212 */ 213 clk_margin = new_clock >> 10; 214 for (clk = 0x80000080; new_clock + clk_margin >= (clock << 1); clk >>= 1) 215 clock <<= 1; 216 217 /* 1/1 clock is option */ 218 if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) { 219 if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400)) 220 clk |= 0xff; 221 else 222 clk &= ~0xff; 223 } 224 225 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); 226 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 227 usleep_range(10000, 11000); 228 229 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 230 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 231 232 out: 233 /* HW engineers overrode docs: no sleep needed on R-Car2+ */ 234 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 235 usleep_range(10000, 11000); 236 } 237 238 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host) 239 { 240 struct renesas_sdhi *priv = host_to_priv(host); 241 242 clk_disable_unprepare(priv->clk_cd); 243 } 244 245 static int renesas_sdhi_card_busy(struct mmc_host *mmc) 246 { 247 struct tmio_mmc_host *host = mmc_priv(mmc); 248 249 return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & 250 TMIO_STAT_DAT0); 251 } 252 253 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, 254 struct mmc_ios *ios) 255 { 256 struct tmio_mmc_host *host = mmc_priv(mmc); 257 struct renesas_sdhi *priv = host_to_priv(host); 258 struct pinctrl_state *pin_state; 259 int ret; 260 261 switch (ios->signal_voltage) { 262 case MMC_SIGNAL_VOLTAGE_330: 263 pin_state = priv->pins_default; 264 break; 265 case MMC_SIGNAL_VOLTAGE_180: 266 pin_state = priv->pins_uhs; 267 break; 268 default: 269 return -EINVAL; 270 } 271 272 /* 273 * If anything is missing, assume signal voltage is fixed at 274 * 3.3V and succeed/fail accordingly. 275 */ 276 if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) 277 return ios->signal_voltage == 278 MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; 279 280 ret = mmc_regulator_set_vqmmc(host->mmc, ios); 281 if (ret < 0) 282 return ret; 283 284 return pinctrl_select_state(priv->pinctrl, pin_state); 285 } 286 287 /* SCC registers */ 288 #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000 289 #define SH_MOBILE_SDHI_SCC_TAPSET 0x002 290 #define SH_MOBILE_SDHI_SCC_DT2FF 0x004 291 #define SH_MOBILE_SDHI_SCC_CKSEL 0x006 292 #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008 293 #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A 294 #define SH_MOBILE_SDHI_SCC_SMPCMP 0x00C 295 #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E 296 #define SH_MOBILE_SDHI_SCC_TMPPORT3 0x014 297 #define SH_MOBILE_SDHI_SCC_TMPPORT4 0x016 298 #define SH_MOBILE_SDHI_SCC_TMPPORT5 0x018 299 #define SH_MOBILE_SDHI_SCC_TMPPORT6 0x01A 300 #define SH_MOBILE_SDHI_SCC_TMPPORT7 0x01C 301 302 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) 303 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 304 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff 305 306 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0) 307 308 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0) 309 310 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0) 311 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP BIT(1) 312 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2) 313 314 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8) 315 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24) 316 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(8) | BIT(24)) 317 318 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4) 319 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31) 320 321 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */ 322 #define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0) 323 324 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT5 register */ 325 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8) 326 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8) 327 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F 328 329 /* Definitions for values the SH_MOBILE_SDHI_SCC register */ 330 #define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000 331 #define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f 332 #define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7) 333 334 static inline u32 sd_scc_read32(struct tmio_mmc_host *host, 335 struct renesas_sdhi *priv, int addr) 336 { 337 return readl(priv->scc_ctl + (addr << host->bus_shift)); 338 } 339 340 static inline void sd_scc_write32(struct tmio_mmc_host *host, 341 struct renesas_sdhi *priv, 342 int addr, u32 val) 343 { 344 writel(val, priv->scc_ctl + (addr << host->bus_shift)); 345 } 346 347 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host) 348 { 349 struct renesas_sdhi *priv; 350 351 priv = host_to_priv(host); 352 353 /* Initialize SCC */ 354 sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0); 355 356 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 357 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 358 359 /* set sampling clock selection range */ 360 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 361 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 362 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 363 364 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 365 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 366 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 367 368 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 369 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 370 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 371 372 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 373 374 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 375 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 376 377 /* Read TAPNUM */ 378 return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >> 379 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) & 380 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK; 381 } 382 383 static void renesas_sdhi_hs400_complete(struct mmc_host *mmc) 384 { 385 struct tmio_mmc_host *host = mmc_priv(mmc); 386 struct renesas_sdhi *priv = host_to_priv(host); 387 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 388 bool use_4tap = sdhi_has_quirk(priv, hs400_4taps); 389 390 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 391 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 392 393 /* Set HS400 mode */ 394 sd_ctrl_write16(host, CTL_SDIF_MODE, SDIF_MODE_HS400 | 395 sd_ctrl_read16(host, CTL_SDIF_MODE)); 396 397 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, 398 priv->scc_tappos_hs400); 399 400 if (sdhi_has_quirk(priv, manual_tap_correction)) 401 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 402 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 403 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 404 405 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 406 (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 407 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) | 408 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 409 410 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 411 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 412 sd_scc_read32(host, priv, 413 SH_MOBILE_SDHI_SCC_DTCNTL)); 414 415 /* Avoid bad TAP */ 416 if (bad_taps & BIT(priv->tap_set)) { 417 u32 new_tap = (priv->tap_set + 1) % priv->tap_num; 418 419 if (bad_taps & BIT(new_tap)) 420 new_tap = (priv->tap_set - 1) % priv->tap_num; 421 422 if (bad_taps & BIT(new_tap)) { 423 new_tap = priv->tap_set; 424 dev_dbg(&host->pdev->dev, "Can't handle three bad tap in a row\n"); 425 } 426 427 priv->tap_set = new_tap; 428 } 429 430 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 431 priv->tap_set / (use_4tap ? 2 : 1)); 432 433 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 434 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 435 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 436 437 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 438 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 439 440 if (priv->adjust_hs400_calib_table) 441 priv->needs_adjust_hs400 = true; 442 } 443 444 static void renesas_sdhi_disable_scc(struct mmc_host *mmc) 445 { 446 struct tmio_mmc_host *host = mmc_priv(mmc); 447 struct renesas_sdhi *priv = host_to_priv(host); 448 449 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 450 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 451 452 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 453 ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL & 454 sd_scc_read32(host, priv, 455 SH_MOBILE_SDHI_SCC_CKSEL)); 456 457 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 458 ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN & 459 sd_scc_read32(host, priv, 460 SH_MOBILE_SDHI_SCC_DTCNTL)); 461 462 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 463 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 464 } 465 466 static u32 sd_scc_tmpport_read32(struct tmio_mmc_host *host, 467 struct renesas_sdhi *priv, u32 addr) 468 { 469 /* read mode */ 470 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, 471 SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R | 472 (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); 473 474 /* access start and stop */ 475 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 476 SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); 477 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); 478 479 return sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT7); 480 } 481 482 static void sd_scc_tmpport_write32(struct tmio_mmc_host *host, 483 struct renesas_sdhi *priv, u32 addr, u32 val) 484 { 485 /* write mode */ 486 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, 487 SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W | 488 (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); 489 490 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT6, val); 491 492 /* access start and stop */ 493 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 494 SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); 495 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); 496 } 497 498 static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host *host) 499 { 500 struct renesas_sdhi *priv = host_to_priv(host); 501 u32 calib_code; 502 503 /* disable write protect */ 504 sd_scc_tmpport_write32(host, priv, 0x00, 505 SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); 506 /* read calibration code and adjust */ 507 calib_code = sd_scc_tmpport_read32(host, priv, 0x26); 508 calib_code &= SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK; 509 510 sd_scc_tmpport_write32(host, priv, 0x22, 511 SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE | 512 priv->adjust_hs400_calib_table[calib_code]); 513 514 /* set offset value to TMPPORT3, hardcoded to OFFSET0 (= 0x3) for now */ 515 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0x3); 516 517 /* adjustment done, clear flag */ 518 priv->needs_adjust_hs400 = false; 519 } 520 521 static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host *host) 522 { 523 struct renesas_sdhi *priv = host_to_priv(host); 524 525 /* disable write protect */ 526 sd_scc_tmpport_write32(host, priv, 0x00, 527 SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); 528 /* disable manual calibration */ 529 sd_scc_tmpport_write32(host, priv, 0x22, 0); 530 /* clear offset value of TMPPORT3 */ 531 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0); 532 } 533 534 static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host, 535 struct renesas_sdhi *priv) 536 { 537 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 538 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 539 540 /* Reset HS400 mode */ 541 sd_ctrl_write16(host, CTL_SDIF_MODE, ~SDIF_MODE_HS400 & 542 sd_ctrl_read16(host, CTL_SDIF_MODE)); 543 544 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 545 546 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 547 ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 548 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) & 549 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 550 551 if (sdhi_has_quirk(priv, hs400_calib_table) || sdhi_has_quirk(priv, hs400_bad_taps)) 552 renesas_sdhi_adjust_hs400_mode_disable(host); 553 554 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 555 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 556 } 557 558 static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 559 { 560 struct tmio_mmc_host *host = mmc_priv(mmc); 561 562 renesas_sdhi_reset_hs400_mode(host, host_to_priv(host)); 563 return 0; 564 } 565 566 static void renesas_sdhi_scc_reset(struct tmio_mmc_host *host, struct renesas_sdhi *priv) 567 { 568 renesas_sdhi_disable_scc(host->mmc); 569 renesas_sdhi_reset_hs400_mode(host, priv); 570 priv->needs_adjust_hs400 = false; 571 572 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 573 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 574 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 575 } 576 577 /* only populated for TMIO_MMC_MIN_RCAR2 */ 578 static void renesas_sdhi_reset(struct tmio_mmc_host *host, bool preserve) 579 { 580 struct renesas_sdhi *priv = host_to_priv(host); 581 int ret; 582 u16 val; 583 584 if (!preserve) { 585 if (priv->rstc) { 586 u32 sd_status; 587 /* 588 * HW reset might have toggled the regulator state in 589 * HW which regulator core might be unaware of so save 590 * and restore the regulator state during HW reset. 591 */ 592 if (priv->rdev) 593 sd_status = sd_ctrl_read32(host, CTL_SD_STATUS); 594 595 reset_control_reset(priv->rstc); 596 /* Unknown why but without polling reset status, it will hang */ 597 read_poll_timeout(reset_control_status, ret, ret == 0, 1, 100, 598 false, priv->rstc); 599 /* At least SDHI_VER_GEN2_SDR50 needs manual release of reset */ 600 sd_ctrl_write16(host, CTL_RESET_SD, 0x0001); 601 if (priv->rdev) 602 sd_ctrl_write32(host, CTL_SD_STATUS, sd_status); 603 604 priv->needs_adjust_hs400 = false; 605 renesas_sdhi_set_clock(host, host->clk_cache); 606 607 /* Ensure default value for this driver. */ 608 renesas_sdhi_sdbuf_width(host, 16); 609 } else if (priv->scc_ctl) { 610 renesas_sdhi_scc_reset(host, priv); 611 } 612 } 613 614 if (sd_ctrl_read16(host, CTL_VERSION) >= SDHI_VER_GEN3_SD) { 615 val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT); 616 val |= CARD_OPT_EXTOP; 617 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, val); 618 } 619 } 620 621 static unsigned int renesas_sdhi_gen3_get_cycles(struct tmio_mmc_host *host) 622 { 623 u16 num, val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT); 624 625 num = (val & CARD_OPT_TOP_MASK) >> CARD_OPT_TOP_SHIFT; 626 return 1 << ((val & CARD_OPT_EXTOP ? 14 : 13) + num); 627 628 } 629 630 #define SH_MOBILE_SDHI_MIN_TAP_ROW 3 631 632 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host) 633 { 634 struct renesas_sdhi *priv = host_to_priv(host); 635 unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i; 636 unsigned int taps_size = priv->tap_num * 2, min_tap_row; 637 unsigned long *bitmap; 638 639 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 640 641 /* 642 * When tuning CMD19 is issued twice for each tap, merge the 643 * result requiring the tap to be good in both runs before 644 * considering it for tuning selection. 645 */ 646 for (i = 0; i < taps_size; i++) { 647 int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1); 648 649 if (!test_bit(i, priv->taps)) 650 clear_bit(i + offset, priv->taps); 651 652 if (!test_bit(i, priv->smpcmp)) 653 clear_bit(i + offset, priv->smpcmp); 654 } 655 656 /* 657 * If all TAP are OK, the sampling clock position is selected by 658 * identifying the change point of data. 659 */ 660 if (bitmap_full(priv->taps, taps_size)) { 661 bitmap = priv->smpcmp; 662 min_tap_row = 1; 663 } else { 664 bitmap = priv->taps; 665 min_tap_row = SH_MOBILE_SDHI_MIN_TAP_ROW; 666 } 667 668 /* 669 * Find the longest consecutive run of successful probes. If that 670 * is at least SH_MOBILE_SDHI_MIN_TAP_ROW probes long then use the 671 * center index as the tap, otherwise bail out. 672 */ 673 for_each_set_bitrange(rs, re, bitmap, taps_size) { 674 if (re - rs > tap_cnt) { 675 tap_end = re; 676 tap_start = rs; 677 tap_cnt = tap_end - tap_start; 678 } 679 } 680 681 if (tap_cnt >= min_tap_row) 682 priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num; 683 else 684 return -EIO; 685 686 /* Set SCC */ 687 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set); 688 689 /* Enable auto re-tuning */ 690 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 691 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN | 692 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 693 694 return 0; 695 } 696 697 static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode) 698 { 699 struct tmio_mmc_host *host = mmc_priv(mmc); 700 struct renesas_sdhi *priv = host_to_priv(host); 701 int i, ret; 702 703 priv->tap_num = renesas_sdhi_init_tuning(host); 704 if (!priv->tap_num) 705 return 0; /* Tuning is not supported */ 706 707 if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) { 708 dev_err(&host->pdev->dev, 709 "Too many taps, please update 'taps' in tmio_mmc_host!\n"); 710 return -EINVAL; 711 } 712 713 bitmap_zero(priv->taps, priv->tap_num * 2); 714 bitmap_zero(priv->smpcmp, priv->tap_num * 2); 715 716 /* Issue CMD19 twice for each tap */ 717 for (i = 0; i < 2 * priv->tap_num; i++) { 718 int cmd_error = 0; 719 720 /* Set sampling clock position */ 721 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num); 722 723 if (mmc_send_tuning(mmc, opcode, &cmd_error) == 0) 724 set_bit(i, priv->taps); 725 726 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0) 727 set_bit(i, priv->smpcmp); 728 729 if (cmd_error) 730 mmc_send_abort_tuning(mmc, opcode); 731 } 732 733 ret = renesas_sdhi_select_tuning(host); 734 if (ret < 0) 735 renesas_sdhi_scc_reset(host, priv); 736 return ret; 737 } 738 739 static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap) 740 { 741 struct renesas_sdhi *priv = host_to_priv(host); 742 unsigned int new_tap = priv->tap_set, error_tap = priv->tap_set; 743 u32 val; 744 745 val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ); 746 if (!val) 747 return false; 748 749 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 750 751 /* Change TAP position according to correction status */ 752 if (sdhi_has_quirk(priv, manual_tap_correction) && 753 host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { 754 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 755 /* 756 * With HS400, the DAT signal is based on DS, not CLK. 757 * Therefore, use only CMD status. 758 */ 759 u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) & 760 SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR; 761 if (!smpcmp) { 762 return false; /* no error in CMD signal */ 763 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) { 764 new_tap++; 765 error_tap--; 766 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) { 767 new_tap--; 768 error_tap++; 769 } else { 770 return true; /* need retune */ 771 } 772 773 /* 774 * When new_tap is a bad tap, we cannot change. Then, we compare 775 * with the HS200 tuning result. When smpcmp[error_tap] is OK, 776 * we can at least retune. 777 */ 778 if (bad_taps & BIT(new_tap % priv->tap_num)) 779 return test_bit(error_tap % priv->tap_num, priv->smpcmp); 780 } else { 781 if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) 782 return true; /* need retune */ 783 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP) 784 new_tap++; 785 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN) 786 new_tap--; 787 else 788 return false; 789 } 790 791 priv->tap_set = (new_tap % priv->tap_num); 792 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 793 priv->tap_set / (use_4tap ? 2 : 1)); 794 795 return false; 796 } 797 798 static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host) 799 { 800 struct renesas_sdhi *priv = host_to_priv(host); 801 802 /* Check SCC error */ 803 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) & 804 SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) { 805 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 806 return true; 807 } 808 809 return false; 810 } 811 812 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host, 813 struct mmc_request *mrq) 814 { 815 struct renesas_sdhi *priv = host_to_priv(host); 816 bool use_4tap = sdhi_has_quirk(priv, hs400_4taps); 817 bool ret = false; 818 819 /* 820 * Skip checking SCC errors when running on 4 taps in HS400 mode as 821 * any retuning would still result in the same 4 taps being used. 822 */ 823 if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) && 824 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) && 825 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap)) 826 return false; 827 828 if (mmc_doing_tune(host->mmc)) 829 return false; 830 831 if (((mrq->cmd->error == -ETIMEDOUT) || 832 (mrq->data && mrq->data->error == -ETIMEDOUT)) && 833 ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || 834 (host->ops.get_cd && host->ops.get_cd(host->mmc)))) 835 ret |= true; 836 837 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) & 838 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN) 839 ret |= renesas_sdhi_auto_correction(host); 840 else 841 ret |= renesas_sdhi_manual_correction(host, use_4tap); 842 843 return ret; 844 } 845 846 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit) 847 { 848 int timeout = 1000; 849 /* CBSY is set when busy, SCLKDIVEN is cleared when busy */ 850 u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0); 851 852 while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) 853 & bit) == wait_state) 854 udelay(1); 855 856 if (!timeout) { 857 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n"); 858 return -EBUSY; 859 } 860 861 return 0; 862 } 863 864 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr) 865 { 866 u32 bit = TMIO_STAT_SCLKDIVEN; 867 868 switch (addr) { 869 case CTL_SD_CMD: 870 case CTL_STOP_INTERNAL_ACTION: 871 case CTL_XFER_BLK_COUNT: 872 case CTL_SD_XFER_LEN: 873 case CTL_SD_MEM_CARD_OPT: 874 case CTL_TRANSACTION_CTL: 875 case CTL_DMA_ENABLE: 876 case CTL_HOST_MODE: 877 if (host->pdata->flags & TMIO_MMC_HAVE_CBSY) 878 bit = TMIO_STAT_CMD_BUSY; 879 fallthrough; 880 case CTL_SD_CARD_CLK_CTL: 881 return renesas_sdhi_wait_idle(host, bit); 882 } 883 884 return 0; 885 } 886 887 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card, 888 unsigned int direction, int blk_size) 889 { 890 /* 891 * In Renesas controllers, when performing a 892 * multiple block read of one or two blocks, 893 * depending on the timing with which the 894 * response register is read, the response 895 * value may not be read properly. 896 * Use single block read for this HW bug 897 */ 898 if ((direction == MMC_DATA_READ) && 899 blk_size == 2) 900 return 1; 901 902 return blk_size; 903 } 904 905 static void renesas_sdhi_fixup_request(struct tmio_mmc_host *host, struct mmc_request *mrq) 906 { 907 struct renesas_sdhi *priv = host_to_priv(host); 908 909 if (priv->needs_adjust_hs400 && mrq->cmd->opcode == MMC_SEND_STATUS) 910 renesas_sdhi_adjust_hs400_mode_enable(host); 911 } 912 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) 913 { 914 /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */ 915 int width = (host->bus_shift == 2) ? 64 : 32; 916 917 sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0); 918 renesas_sdhi_sdbuf_width(host, enable ? width : 16); 919 } 920 921 static const unsigned int renesas_sdhi_vqmmc_voltages[] = { 922 3300000, 1800000 923 }; 924 925 static int renesas_sdhi_regulator_disable(struct regulator_dev *rdev) 926 { 927 struct tmio_mmc_host *host = rdev_get_drvdata(rdev); 928 u32 sd_status; 929 930 sd_status = sd_ctrl_read32(host, CTL_SD_STATUS); 931 sd_status &= ~SD_STATUS_PWEN; 932 sd_ctrl_write32(host, CTL_SD_STATUS, sd_status); 933 934 return 0; 935 } 936 937 static int renesas_sdhi_regulator_enable(struct regulator_dev *rdev) 938 { 939 struct tmio_mmc_host *host = rdev_get_drvdata(rdev); 940 u32 sd_status; 941 942 sd_status = sd_ctrl_read32(host, CTL_SD_STATUS); 943 sd_status |= SD_STATUS_PWEN; 944 sd_ctrl_write32(host, CTL_SD_STATUS, sd_status); 945 946 return 0; 947 } 948 949 static int renesas_sdhi_regulator_is_enabled(struct regulator_dev *rdev) 950 { 951 struct tmio_mmc_host *host = rdev_get_drvdata(rdev); 952 u32 sd_status; 953 954 sd_status = sd_ctrl_read32(host, CTL_SD_STATUS); 955 956 return (sd_status & SD_STATUS_PWEN) ? 1 : 0; 957 } 958 959 static int renesas_sdhi_regulator_get_voltage(struct regulator_dev *rdev) 960 { 961 struct tmio_mmc_host *host = rdev_get_drvdata(rdev); 962 u32 sd_status; 963 964 sd_status = sd_ctrl_read32(host, CTL_SD_STATUS); 965 966 return (sd_status & SD_STATUS_IOVS) ? 1800000 : 3300000; 967 } 968 969 static int renesas_sdhi_regulator_set_voltage(struct regulator_dev *rdev, 970 int min_uV, int max_uV, 971 unsigned int *selector) 972 { 973 struct tmio_mmc_host *host = rdev_get_drvdata(rdev); 974 u32 sd_status; 975 976 sd_status = sd_ctrl_read32(host, CTL_SD_STATUS); 977 if (min_uV >= 1700000 && max_uV <= 1950000) { 978 sd_status |= SD_STATUS_IOVS; 979 *selector = 1; 980 } else { 981 sd_status &= ~SD_STATUS_IOVS; 982 *selector = 0; 983 } 984 sd_ctrl_write32(host, CTL_SD_STATUS, sd_status); 985 986 return 0; 987 } 988 989 static int renesas_sdhi_regulator_list_voltage(struct regulator_dev *rdev, 990 unsigned int selector) 991 { 992 if (selector >= ARRAY_SIZE(renesas_sdhi_vqmmc_voltages)) 993 return -EINVAL; 994 995 return renesas_sdhi_vqmmc_voltages[selector]; 996 } 997 998 static const struct regulator_ops renesas_sdhi_regulator_voltage_ops = { 999 .enable = renesas_sdhi_regulator_enable, 1000 .disable = renesas_sdhi_regulator_disable, 1001 .is_enabled = renesas_sdhi_regulator_is_enabled, 1002 .list_voltage = renesas_sdhi_regulator_list_voltage, 1003 .get_voltage = renesas_sdhi_regulator_get_voltage, 1004 .set_voltage = renesas_sdhi_regulator_set_voltage, 1005 }; 1006 1007 static const struct regulator_desc renesas_sdhi_vqmmc_regulator = { 1008 .name = "sdhi-vqmmc-regulator", 1009 .of_match = of_match_ptr("vqmmc-regulator"), 1010 .type = REGULATOR_VOLTAGE, 1011 .owner = THIS_MODULE, 1012 .ops = &renesas_sdhi_regulator_voltage_ops, 1013 .volt_table = renesas_sdhi_vqmmc_voltages, 1014 .n_voltages = ARRAY_SIZE(renesas_sdhi_vqmmc_voltages), 1015 }; 1016 1017 int renesas_sdhi_probe(struct platform_device *pdev, 1018 const struct tmio_mmc_dma_ops *dma_ops, 1019 const struct renesas_sdhi_of_data *of_data, 1020 const struct renesas_sdhi_quirks *quirks) 1021 { 1022 struct tmio_mmc_data *mmd = pdev->dev.platform_data; 1023 struct tmio_mmc_data *mmc_data; 1024 struct regulator_config rcfg = { .dev = &pdev->dev, }; 1025 struct regulator_dev *rdev; 1026 struct renesas_sdhi_dma *dma_priv; 1027 struct device *dev = &pdev->dev; 1028 struct tmio_mmc_host *host; 1029 struct renesas_sdhi *priv; 1030 int num_irqs, irq, ret, i; 1031 struct resource *res; 1032 u16 ver; 1033 1034 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1035 if (!res) 1036 return -EINVAL; 1037 1038 priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi), 1039 GFP_KERNEL); 1040 if (!priv) 1041 return -ENOMEM; 1042 1043 priv->quirks = quirks; 1044 mmc_data = &priv->mmc_data; 1045 dma_priv = &priv->dma_priv; 1046 1047 priv->clk = devm_clk_get(&pdev->dev, NULL); 1048 if (IS_ERR(priv->clk)) 1049 return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk), "cannot get clock"); 1050 1051 priv->clkh = devm_clk_get_optional(&pdev->dev, "clkh"); 1052 if (IS_ERR(priv->clkh)) 1053 return dev_err_probe(&pdev->dev, PTR_ERR(priv->clkh), "cannot get clkh"); 1054 1055 /* 1056 * Some controllers provide a 2nd clock just to run the internal card 1057 * detection logic. Unfortunately, the existing driver architecture does 1058 * not support a separation of clocks for runtime PM usage. When 1059 * native hotplug is used, the tmio driver assumes that the core 1060 * must continue to run for card detect to stay active, so we cannot 1061 * disable it. 1062 * Additionally, it is prohibited to supply a clock to the core but not 1063 * to the card detect circuit. That leaves us with if separate clocks 1064 * are presented, we must treat them both as virtually 1 clock. 1065 */ 1066 priv->clk_cd = devm_clk_get_optional(&pdev->dev, "cd"); 1067 if (IS_ERR(priv->clk_cd)) 1068 return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk_cd), "cannot get cd clock"); 1069 1070 priv->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 1071 if (IS_ERR(priv->rstc)) 1072 return PTR_ERR(priv->rstc); 1073 1074 priv->pinctrl = devm_pinctrl_get(&pdev->dev); 1075 if (!IS_ERR(priv->pinctrl)) { 1076 priv->pins_default = pinctrl_lookup_state(priv->pinctrl, 1077 PINCTRL_STATE_DEFAULT); 1078 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl, 1079 "state_uhs"); 1080 } 1081 1082 host = tmio_mmc_host_alloc(pdev, mmc_data); 1083 if (IS_ERR(host)) 1084 return PTR_ERR(host); 1085 1086 priv->host = host; 1087 1088 if (of_data) { 1089 mmc_data->flags |= of_data->tmio_flags; 1090 mmc_data->ocr_mask = of_data->tmio_ocr_mask; 1091 mmc_data->capabilities |= of_data->capabilities; 1092 mmc_data->capabilities2 |= of_data->capabilities2; 1093 mmc_data->dma_rx_offset = of_data->dma_rx_offset; 1094 mmc_data->max_blk_count = of_data->max_blk_count; 1095 mmc_data->max_segs = of_data->max_segs; 1096 dma_priv->dma_buswidth = of_data->dma_buswidth; 1097 host->bus_shift = of_data->bus_shift; 1098 /* Fallback for old DTs */ 1099 if (!priv->clkh && of_data->sdhi_flags & SDHI_FLAG_NEED_CLKH_FALLBACK) 1100 priv->clkh = clk_get_parent(clk_get_parent(priv->clk)); 1101 1102 } 1103 1104 host->write16_hook = renesas_sdhi_write16_hook; 1105 host->clk_enable = renesas_sdhi_clk_enable; 1106 host->clk_disable = renesas_sdhi_clk_disable; 1107 host->set_clock = renesas_sdhi_set_clock; 1108 host->multi_io_quirk = renesas_sdhi_multi_io_quirk; 1109 host->dma_ops = dma_ops; 1110 1111 if (sdhi_has_quirk(priv, hs400_disabled)) 1112 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES); 1113 1114 /* For some SoC, we disable internal WP. GPIO may override this */ 1115 if (mmc_can_gpio_ro(host->mmc)) 1116 mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT; 1117 1118 /* SDR speeds are only available on Gen2+ */ 1119 if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) { 1120 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */ 1121 host->ops.card_busy = renesas_sdhi_card_busy; 1122 host->ops.start_signal_voltage_switch = 1123 renesas_sdhi_start_signal_voltage_switch; 1124 host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27; 1125 host->sdcard_irq_mask_all = TMIO_MASK_ALL_RCAR2; 1126 host->reset = renesas_sdhi_reset; 1127 } else { 1128 host->sdcard_irq_mask_all = TMIO_MASK_ALL; 1129 } 1130 1131 /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */ 1132 if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */ 1133 host->bus_shift = 1; 1134 1135 if (mmd) 1136 *mmc_data = *mmd; 1137 1138 dma_priv->filter = shdma_chan_filter; 1139 dma_priv->enable = renesas_sdhi_enable_dma; 1140 1141 mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED; 1142 1143 /* 1144 * All SDHI blocks support 2-byte and larger block sizes in 4-bit 1145 * bus width mode. 1146 */ 1147 mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES; 1148 1149 /* 1150 * All SDHI blocks support SDIO IRQ signalling. 1151 */ 1152 mmc_data->flags |= TMIO_MMC_SDIO_IRQ; 1153 1154 /* All SDHI have CMD12 control bit */ 1155 mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL; 1156 1157 /* All SDHI have SDIO status bits which must be 1 */ 1158 mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS; 1159 1160 /* All SDHI support HW busy detection */ 1161 mmc_data->flags |= TMIO_MMC_USE_BUSY_TIMEOUT; 1162 1163 dev_pm_domain_start(&pdev->dev); 1164 1165 ret = renesas_sdhi_clk_enable(host); 1166 if (ret) 1167 goto efree; 1168 1169 rcfg.of_node = of_get_child_by_name(dev->of_node, "vqmmc-regulator"); 1170 if (!of_device_is_available(rcfg.of_node)) { 1171 of_node_put(rcfg.of_node); 1172 rcfg.of_node = NULL; 1173 } 1174 1175 if (rcfg.of_node) { 1176 rcfg.driver_data = priv->host; 1177 rdev = devm_regulator_register(dev, &renesas_sdhi_vqmmc_regulator, &rcfg); 1178 of_node_put(rcfg.of_node); 1179 if (IS_ERR(rdev)) { 1180 dev_err(dev, "regulator register failed err=%ld", PTR_ERR(rdev)); 1181 ret = PTR_ERR(rdev); 1182 goto edisclk; 1183 } 1184 priv->rdev = rdev; 1185 } 1186 1187 ver = sd_ctrl_read16(host, CTL_VERSION); 1188 /* GEN2_SDR104 is first known SDHI to use 32bit block count */ 1189 if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX) 1190 mmc_data->max_blk_count = U16_MAX; 1191 1192 /* One Gen2 SDHI incarnation does NOT have a CBSY bit */ 1193 if (ver == SDHI_VER_GEN2_SDR50) 1194 mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY; 1195 1196 if (ver == SDHI_VER_GEN3_SDMMC && sdhi_has_quirk(priv, hs400_calib_table)) { 1197 host->fixup_request = renesas_sdhi_fixup_request; 1198 priv->adjust_hs400_calib_table = *( 1199 res->start == SDHI_GEN3_MMC0_ADDR ? 1200 quirks->hs400_calib_table : 1201 quirks->hs400_calib_table + 1); 1202 } 1203 1204 /* these have an EXTOP bit */ 1205 if (ver >= SDHI_VER_GEN3_SD) 1206 host->get_timeout_cycles = renesas_sdhi_gen3_get_cycles; 1207 1208 /* Check for SCC so we can reset it if needed */ 1209 if (of_data && of_data->scc_offset && ver >= SDHI_VER_GEN2_SDR104) 1210 priv->scc_ctl = host->ctl + of_data->scc_offset; 1211 1212 /* Enable tuning iff we have an SCC and a supported mode */ 1213 if (priv->scc_ctl && (host->mmc->caps & MMC_CAP_UHS_SDR104 || 1214 host->mmc->caps2 & MMC_CAP2_HSX00_1_8V)) { 1215 const struct renesas_sdhi_scc *taps = of_data->taps; 1216 bool use_4tap = sdhi_has_quirk(priv, hs400_4taps); 1217 bool hit = false; 1218 1219 for (i = 0; i < of_data->taps_num; i++) { 1220 if (taps[i].clk_rate == 0 || 1221 taps[i].clk_rate == host->mmc->f_max) { 1222 priv->scc_tappos = taps->tap; 1223 priv->scc_tappos_hs400 = use_4tap ? 1224 taps->tap_hs400_4tap : 1225 taps->tap; 1226 hit = true; 1227 break; 1228 } 1229 } 1230 1231 if (!hit) 1232 dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n"); 1233 1234 host->check_retune = renesas_sdhi_check_scc_error; 1235 host->ops.execute_tuning = renesas_sdhi_execute_tuning; 1236 host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning; 1237 host->ops.hs400_downgrade = renesas_sdhi_disable_scc; 1238 host->ops.hs400_complete = renesas_sdhi_hs400_complete; 1239 } 1240 1241 sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, host->sdcard_irq_mask_all); 1242 1243 num_irqs = platform_irq_count(pdev); 1244 if (num_irqs < 0) { 1245 ret = num_irqs; 1246 goto edisclk; 1247 } 1248 1249 /* There must be at least one IRQ source */ 1250 if (!num_irqs) { 1251 ret = -ENXIO; 1252 goto edisclk; 1253 } 1254 1255 for (i = 0; i < num_irqs; i++) { 1256 irq = platform_get_irq(pdev, i); 1257 if (irq < 0) { 1258 ret = irq; 1259 goto edisclk; 1260 } 1261 1262 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0, 1263 dev_name(&pdev->dev), host); 1264 if (ret) 1265 goto edisclk; 1266 } 1267 1268 ret = tmio_mmc_host_probe(host); 1269 if (ret < 0) 1270 goto edisclk; 1271 1272 dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n", 1273 mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000); 1274 1275 return ret; 1276 1277 edisclk: 1278 renesas_sdhi_clk_disable(host); 1279 efree: 1280 tmio_mmc_host_free(host); 1281 1282 return ret; 1283 } 1284 EXPORT_SYMBOL_GPL(renesas_sdhi_probe); 1285 1286 void renesas_sdhi_remove(struct platform_device *pdev) 1287 { 1288 struct tmio_mmc_host *host = platform_get_drvdata(pdev); 1289 1290 tmio_mmc_host_remove(host); 1291 renesas_sdhi_clk_disable(host); 1292 tmio_mmc_host_free(host); 1293 } 1294 EXPORT_SYMBOL_GPL(renesas_sdhi_remove); 1295 1296 MODULE_DESCRIPTION("Renesas SDHI core driver"); 1297 MODULE_LICENSE("GPL v2"); 1298