1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RPC-IF core driver 4 * 5 * Copyright (C) 2018-2019 Renesas Solutions Corp. 6 * Copyright (C) 2019 Macronix International Co., Ltd. 7 * Copyright (C) 2019-2020 Cogent Embedded, Inc. 8 */ 9 10 #include <linux/bitops.h> 11 #include <linux/clk.h> 12 #include <linux/io.h> 13 #include <linux/module.h> 14 #include <linux/platform_device.h> 15 #include <linux/of.h> 16 #include <linux/regmap.h> 17 #include <linux/reset.h> 18 19 #include <memory/renesas-rpc-if.h> 20 21 #include "renesas-rpc-if-regs.h" 22 #include "renesas-xspi-if-regs.h" 23 24 static const struct regmap_range rpcif_volatile_ranges[] = { 25 regmap_reg_range(RPCIF_SMRDR0, RPCIF_SMRDR1), 26 regmap_reg_range(RPCIF_SMWDR0, RPCIF_SMWDR1), 27 regmap_reg_range(RPCIF_CMNSR, RPCIF_CMNSR), 28 }; 29 30 static const struct regmap_access_table rpcif_volatile_table = { 31 .yes_ranges = rpcif_volatile_ranges, 32 .n_yes_ranges = ARRAY_SIZE(rpcif_volatile_ranges), 33 }; 34 35 static const struct regmap_range xspi_volatile_ranges[] = { 36 regmap_reg_range(XSPI_CDD0BUF0, XSPI_CDD0BUF0), 37 }; 38 39 static const struct regmap_access_table xspi_volatile_table = { 40 .yes_ranges = xspi_volatile_ranges, 41 .n_yes_ranges = ARRAY_SIZE(xspi_volatile_ranges), 42 }; 43 44 struct rpcif_priv; 45 46 struct rpcif_impl { 47 int (*hw_init)(struct rpcif_priv *rpc, bool hyperflash); 48 void (*prepare)(struct rpcif_priv *rpc, const struct rpcif_op *op, 49 u64 *offs, size_t *len); 50 int (*manual_xfer)(struct rpcif_priv *rpc); 51 size_t (*dirmap_read)(struct rpcif_priv *rpc, u64 offs, size_t len, 52 void *buf); 53 u32 status_reg; 54 u32 status_mask; 55 }; 56 57 struct rpcif_info { 58 const struct regmap_config *regmap_config; 59 const struct rpcif_impl *impl; 60 enum rpcif_type type; 61 u8 strtim; 62 }; 63 64 struct rpcif_priv { 65 struct device *dev; 66 void __iomem *base; 67 void __iomem *dirmap; 68 struct regmap *regmap; 69 struct reset_control *rstc; 70 struct platform_device *vdev; 71 size_t size; 72 const struct rpcif_info *info; 73 enum rpcif_data_dir dir; 74 u8 bus_size; 75 u8 xfer_size; 76 u8 addr_nbytes; /* Specified for xSPI */ 77 u32 proto; /* Specified for xSPI */ 78 void *buffer; 79 u32 xferlen; 80 u32 smcr; 81 u32 smadr; 82 u32 command; /* DRCMR or SMCMR */ 83 u32 option; /* DROPR or SMOPR */ 84 u32 enable; /* DRENR or SMENR */ 85 u32 dummy; /* DRDMCR or SMDMCR */ 86 u32 ddr; /* DRDRENR or SMDRENR */ 87 }; 88 89 /* 90 * Custom accessor functions to ensure SM[RW]DR[01] are always accessed with 91 * proper width. Requires rpcif_priv.xfer_size to be correctly set before! 92 */ 93 static int rpcif_reg_read(void *context, unsigned int reg, unsigned int *val) 94 { 95 struct rpcif_priv *rpc = context; 96 97 switch (reg) { 98 case RPCIF_SMRDR0: 99 case RPCIF_SMWDR0: 100 switch (rpc->xfer_size) { 101 case 1: 102 *val = readb(rpc->base + reg); 103 return 0; 104 105 case 2: 106 *val = readw(rpc->base + reg); 107 return 0; 108 109 case 4: 110 case 8: 111 *val = readl(rpc->base + reg); 112 return 0; 113 114 default: 115 return -EILSEQ; 116 } 117 118 case RPCIF_SMRDR1: 119 case RPCIF_SMWDR1: 120 if (rpc->xfer_size != 8) 121 return -EILSEQ; 122 break; 123 } 124 125 *val = readl(rpc->base + reg); 126 return 0; 127 } 128 129 static int rpcif_reg_write(void *context, unsigned int reg, unsigned int val) 130 { 131 struct rpcif_priv *rpc = context; 132 133 switch (reg) { 134 case RPCIF_SMWDR0: 135 switch (rpc->xfer_size) { 136 case 1: 137 writeb(val, rpc->base + reg); 138 return 0; 139 140 case 2: 141 writew(val, rpc->base + reg); 142 return 0; 143 144 case 4: 145 case 8: 146 writel(val, rpc->base + reg); 147 return 0; 148 149 default: 150 return -EILSEQ; 151 } 152 153 case RPCIF_SMWDR1: 154 if (rpc->xfer_size != 8) 155 return -EILSEQ; 156 break; 157 158 case RPCIF_SMRDR0: 159 case RPCIF_SMRDR1: 160 return -EPERM; 161 } 162 163 writel(val, rpc->base + reg); 164 return 0; 165 } 166 167 static const struct regmap_config rpcif_regmap_config = { 168 .reg_bits = 32, 169 .val_bits = 32, 170 .reg_stride = 4, 171 .reg_read = rpcif_reg_read, 172 .reg_write = rpcif_reg_write, 173 .fast_io = true, 174 .max_register = RPCIF_PHYINT, 175 .volatile_table = &rpcif_volatile_table, 176 }; 177 178 static int xspi_reg_read(void *context, unsigned int reg, unsigned int *val) 179 { 180 struct rpcif_priv *xspi = context; 181 182 *val = readl(xspi->base + reg); 183 return 0; 184 } 185 186 static int xspi_reg_write(void *context, unsigned int reg, unsigned int val) 187 { 188 struct rpcif_priv *xspi = context; 189 190 writel(val, xspi->base + reg); 191 return 0; 192 } 193 194 static const struct regmap_config xspi_regmap_config = { 195 .reg_bits = 32, 196 .val_bits = 32, 197 .reg_stride = 4, 198 .reg_read = xspi_reg_read, 199 .reg_write = xspi_reg_write, 200 .fast_io = true, 201 .max_register = XSPI_INTE, 202 .volatile_table = &xspi_volatile_table, 203 }; 204 205 int rpcif_sw_init(struct rpcif *rpcif, struct device *dev) 206 { 207 struct rpcif_priv *rpc = dev_get_drvdata(dev); 208 209 rpcif->dev = dev; 210 rpcif->dirmap = rpc->dirmap; 211 rpcif->size = rpc->size; 212 rpcif->xspi = rpc->info->type == XSPI_RZ_G3E; 213 return 0; 214 } 215 EXPORT_SYMBOL(rpcif_sw_init); 216 217 static void rpcif_rzg2l_timing_adjust_sdr(struct rpcif_priv *rpc) 218 { 219 regmap_write(rpc->regmap, RPCIF_PHYWR, 0xa5390000); 220 regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000000); 221 regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080); 222 regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000022); 223 regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080); 224 regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000024); 225 regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_CKSEL(3), 226 RPCIF_PHYCNT_CKSEL(3)); 227 regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00000030); 228 regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000032); 229 } 230 231 static int rpcif_hw_init_impl(struct rpcif_priv *rpc, bool hyperflash) 232 { 233 u32 dummy; 234 int ret; 235 236 if (rpc->info->type == RPCIF_RZ_G2L) { 237 ret = reset_control_reset(rpc->rstc); 238 if (ret) 239 return ret; 240 usleep_range(200, 300); 241 rpcif_rzg2l_timing_adjust_sdr(rpc); 242 } 243 244 regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_PHYMEM_MASK, 245 RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0)); 246 247 /* DMA Transfer is not supported */ 248 regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_HS, 0); 249 250 regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, 251 /* create mask with all affected bits set */ 252 RPCIF_PHYCNT_STRTIM(BIT(fls(rpc->info->strtim)) - 1), 253 RPCIF_PHYCNT_STRTIM(rpc->info->strtim)); 254 255 regmap_update_bits(rpc->regmap, RPCIF_PHYOFFSET1, RPCIF_PHYOFFSET1_DDRTMG(3), 256 RPCIF_PHYOFFSET1_DDRTMG(3)); 257 regmap_update_bits(rpc->regmap, RPCIF_PHYOFFSET2, RPCIF_PHYOFFSET2_OCTTMG(7), 258 RPCIF_PHYOFFSET2_OCTTMG(4)); 259 260 if (hyperflash) 261 regmap_update_bits(rpc->regmap, RPCIF_PHYINT, 262 RPCIF_PHYINT_WPVAL, 0); 263 264 if (rpc->info->type == RPCIF_RZ_G2L) 265 regmap_update_bits(rpc->regmap, RPCIF_CMNCR, 266 RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_IOFV(3) | 267 RPCIF_CMNCR_BSZ(3), 268 RPCIF_CMNCR_MOIIO(1) | RPCIF_CMNCR_IOFV(3) | 269 RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0)); 270 else 271 regmap_update_bits(rpc->regmap, RPCIF_CMNCR, 272 RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_BSZ(3), 273 RPCIF_CMNCR_MOIIO(3) | 274 RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0)); 275 276 /* Set RCF after BSZ update */ 277 regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF); 278 /* Dummy read according to spec */ 279 regmap_read(rpc->regmap, RPCIF_DRCR, &dummy); 280 regmap_write(rpc->regmap, RPCIF_SSLDR, RPCIF_SSLDR_SPNDL(7) | 281 RPCIF_SSLDR_SLNDL(7) | RPCIF_SSLDR_SCKDL(7)); 282 283 rpc->bus_size = hyperflash ? 2 : 1; 284 285 return 0; 286 } 287 288 static int xspi_hw_init_impl(struct rpcif_priv *xspi, bool hyperflash) 289 { 290 int ret; 291 292 ret = reset_control_reset(xspi->rstc); 293 if (ret) 294 return ret; 295 296 regmap_write(xspi->regmap, XSPI_WRAPCFG, 0x0); 297 298 regmap_update_bits(xspi->regmap, XSPI_LIOCFGCS0, 299 XSPI_LIOCFG_PRTMD(0x3ff) | XSPI_LIOCFG_CSMIN(0xf) | 300 XSPI_LIOCFG_CSASTEX | XSPI_LIOCFG_CSNEGEX, 301 XSPI_LIOCFG_PRTMD(0) | XSPI_LIOCFG_CSMIN(0) | 302 XSPI_LIOCFG_CSASTEX | XSPI_LIOCFG_CSNEGEX); 303 304 regmap_update_bits(xspi->regmap, XSPI_CCCTL0CS0, XSPI_CCCTL0_CAEN, 0); 305 306 regmap_update_bits(xspi->regmap, XSPI_CDCTL0, 307 XSPI_CDCTL0_TRREQ | XSPI_CDCTL0_CSSEL, 0); 308 309 regmap_update_bits(xspi->regmap, XSPI_INTE, XSPI_INTE_CMDCMPE, 310 XSPI_INTE_CMDCMPE); 311 312 return 0; 313 } 314 315 int rpcif_hw_init(struct device *dev, bool hyperflash) 316 { 317 struct rpcif_priv *rpc = dev_get_drvdata(dev); 318 int ret; 319 320 ret = pm_runtime_resume_and_get(dev); 321 if (ret) 322 return ret; 323 324 ret = rpc->info->impl->hw_init(rpc, hyperflash); 325 326 pm_runtime_put(dev); 327 328 return ret; 329 } 330 EXPORT_SYMBOL(rpcif_hw_init); 331 332 static int wait_msg_xfer_end(struct rpcif_priv *rpc) 333 { 334 u32 sts; 335 336 return regmap_read_poll_timeout(rpc->regmap, rpc->info->impl->status_reg, 337 sts, sts & rpc->info->impl->status_mask, 338 0, USEC_PER_SEC); 339 } 340 341 static u8 rpcif_bits_set(struct rpcif_priv *rpc, u32 nbytes) 342 { 343 if (rpc->bus_size == 2) 344 nbytes /= 2; 345 nbytes = clamp(nbytes, 1U, 4U); 346 return GENMASK(3, 4 - nbytes); 347 } 348 349 static u8 rpcif_bit_size(u8 buswidth) 350 { 351 return buswidth > 4 ? 2 : ilog2(buswidth); 352 } 353 354 static void rpcif_prepare_impl(struct rpcif_priv *rpc, const struct rpcif_op *op, 355 u64 *offs, size_t *len) 356 { 357 rpc->smcr = 0; 358 rpc->smadr = 0; 359 rpc->enable = 0; 360 rpc->command = 0; 361 rpc->option = 0; 362 rpc->dummy = 0; 363 rpc->ddr = 0; 364 rpc->xferlen = 0; 365 366 if (op->cmd.buswidth) { 367 rpc->enable = RPCIF_SMENR_CDE | 368 RPCIF_SMENR_CDB(rpcif_bit_size(op->cmd.buswidth)); 369 rpc->command = RPCIF_SMCMR_CMD(op->cmd.opcode); 370 if (op->cmd.ddr) 371 rpc->ddr = RPCIF_SMDRENR_HYPE(0x5); 372 } 373 if (op->ocmd.buswidth) { 374 rpc->enable |= RPCIF_SMENR_OCDE | 375 RPCIF_SMENR_OCDB(rpcif_bit_size(op->ocmd.buswidth)); 376 rpc->command |= RPCIF_SMCMR_OCMD(op->ocmd.opcode); 377 } 378 379 if (op->addr.buswidth) { 380 rpc->enable |= 381 RPCIF_SMENR_ADB(rpcif_bit_size(op->addr.buswidth)); 382 if (op->addr.nbytes == 4) 383 rpc->enable |= RPCIF_SMENR_ADE(0xF); 384 else 385 rpc->enable |= RPCIF_SMENR_ADE(GENMASK( 386 2, 3 - op->addr.nbytes)); 387 if (op->addr.ddr) 388 rpc->ddr |= RPCIF_SMDRENR_ADDRE; 389 390 if (offs && len) 391 rpc->smadr = *offs; 392 else 393 rpc->smadr = op->addr.val; 394 } 395 396 if (op->dummy.buswidth) { 397 rpc->enable |= RPCIF_SMENR_DME; 398 rpc->dummy = RPCIF_SMDMCR_DMCYC(op->dummy.ncycles); 399 } 400 401 if (op->option.buswidth) { 402 rpc->enable |= RPCIF_SMENR_OPDE( 403 rpcif_bits_set(rpc, op->option.nbytes)) | 404 RPCIF_SMENR_OPDB(rpcif_bit_size(op->option.buswidth)); 405 if (op->option.ddr) 406 rpc->ddr |= RPCIF_SMDRENR_OPDRE; 407 rpc->option = op->option.val; 408 } 409 410 rpc->dir = op->data.dir; 411 if (op->data.buswidth) { 412 u32 nbytes; 413 414 rpc->buffer = op->data.buf.in; 415 switch (op->data.dir) { 416 case RPCIF_DATA_IN: 417 rpc->smcr = RPCIF_SMCR_SPIRE; 418 break; 419 case RPCIF_DATA_OUT: 420 rpc->smcr = RPCIF_SMCR_SPIWE; 421 break; 422 default: 423 break; 424 } 425 if (op->data.ddr) 426 rpc->ddr |= RPCIF_SMDRENR_SPIDRE; 427 428 if (offs && len) 429 nbytes = *len; 430 else 431 nbytes = op->data.nbytes; 432 rpc->xferlen = nbytes; 433 434 rpc->enable |= RPCIF_SMENR_SPIDB(rpcif_bit_size(op->data.buswidth)); 435 } 436 } 437 438 static void xspi_prepare_impl(struct rpcif_priv *xspi, const struct rpcif_op *op, 439 u64 *offs, size_t *len) 440 { 441 xspi->smadr = 0; 442 xspi->addr_nbytes = 0; 443 xspi->command = 0; 444 xspi->option = 0; 445 xspi->dummy = 0; 446 xspi->xferlen = 0; 447 xspi->proto = 0; 448 449 if (op->cmd.buswidth) 450 xspi->command = op->cmd.opcode; 451 452 if (op->ocmd.buswidth) 453 xspi->command = (xspi->command << 8) | op->ocmd.opcode; 454 455 if (op->addr.buswidth) { 456 xspi->addr_nbytes = op->addr.nbytes; 457 if (offs && len) 458 xspi->smadr = *offs; 459 else 460 xspi->smadr = op->addr.val; 461 } 462 463 if (op->dummy.buswidth) 464 xspi->dummy = op->dummy.ncycles; 465 466 xspi->dir = op->data.dir; 467 if (op->data.buswidth) { 468 u32 nbytes; 469 470 xspi->buffer = op->data.buf.in; 471 472 if (offs && len) 473 nbytes = *len; 474 else 475 nbytes = op->data.nbytes; 476 xspi->xferlen = nbytes; 477 } 478 479 if (op->cmd.buswidth == 1) { 480 if (op->addr.buswidth == 2 || op->data.buswidth == 2) 481 xspi->proto = PROTO_1S_2S_2S; 482 else if (op->addr.buswidth == 4 || op->data.buswidth == 4) 483 xspi->proto = PROTO_1S_4S_4S; 484 } else if (op->cmd.buswidth == 2 && 485 (op->addr.buswidth == 2 || op->data.buswidth == 2)) { 486 xspi->proto = PROTO_2S_2S_2S; 487 } else if (op->cmd.buswidth == 4 && 488 (op->addr.buswidth == 4 || op->data.buswidth == 4)) { 489 xspi->proto = PROTO_4S_4S_4S; 490 } 491 } 492 493 void rpcif_prepare(struct device *dev, const struct rpcif_op *op, u64 *offs, 494 size_t *len) 495 { 496 struct rpcif_priv *rpc = dev_get_drvdata(dev); 497 498 rpc->info->impl->prepare(rpc, op, offs, len); 499 } 500 EXPORT_SYMBOL(rpcif_prepare); 501 502 static int rpcif_manual_xfer_impl(struct rpcif_priv *rpc) 503 { 504 u32 smenr, smcr, pos = 0, max = rpc->bus_size == 2 ? 8 : 4; 505 int ret = 0; 506 507 regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, 508 RPCIF_PHYCNT_CAL, RPCIF_PHYCNT_CAL); 509 regmap_update_bits(rpc->regmap, RPCIF_CMNCR, 510 RPCIF_CMNCR_MD, RPCIF_CMNCR_MD); 511 regmap_write(rpc->regmap, RPCIF_SMCMR, rpc->command); 512 regmap_write(rpc->regmap, RPCIF_SMOPR, rpc->option); 513 regmap_write(rpc->regmap, RPCIF_SMDMCR, rpc->dummy); 514 regmap_write(rpc->regmap, RPCIF_SMDRENR, rpc->ddr); 515 regmap_write(rpc->regmap, RPCIF_SMADR, rpc->smadr); 516 smenr = rpc->enable; 517 518 switch (rpc->dir) { 519 case RPCIF_DATA_OUT: 520 while (pos < rpc->xferlen) { 521 u32 bytes_left = rpc->xferlen - pos; 522 u32 nbytes, data[2], *p = data; 523 524 smcr = rpc->smcr | RPCIF_SMCR_SPIE; 525 526 /* nbytes may only be 1, 2, 4, or 8 */ 527 nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left)); 528 if (bytes_left > nbytes) 529 smcr |= RPCIF_SMCR_SSLKP; 530 531 smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes)); 532 regmap_write(rpc->regmap, RPCIF_SMENR, smenr); 533 rpc->xfer_size = nbytes; 534 535 memcpy(data, rpc->buffer + pos, nbytes); 536 if (nbytes == 8) 537 regmap_write(rpc->regmap, RPCIF_SMWDR1, *p++); 538 regmap_write(rpc->regmap, RPCIF_SMWDR0, *p); 539 540 regmap_write(rpc->regmap, RPCIF_SMCR, smcr); 541 ret = wait_msg_xfer_end(rpc); 542 if (ret) 543 goto err_out; 544 545 pos += nbytes; 546 smenr = rpc->enable & 547 ~RPCIF_SMENR_CDE & ~RPCIF_SMENR_ADE(0xF); 548 } 549 break; 550 case RPCIF_DATA_IN: 551 /* 552 * RPC-IF spoils the data for the commands without an address 553 * phase (like RDID) in the manual mode, so we'll have to work 554 * around this issue by using the external address space read 555 * mode instead. 556 */ 557 if (!(smenr & RPCIF_SMENR_ADE(0xF)) && rpc->dirmap) { 558 u32 dummy; 559 560 regmap_update_bits(rpc->regmap, RPCIF_CMNCR, 561 RPCIF_CMNCR_MD, 0); 562 regmap_write(rpc->regmap, RPCIF_DRCR, 563 RPCIF_DRCR_RBURST(32) | RPCIF_DRCR_RBE); 564 regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command); 565 regmap_write(rpc->regmap, RPCIF_DREAR, 566 RPCIF_DREAR_EAC(1)); 567 regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option); 568 regmap_write(rpc->regmap, RPCIF_DRENR, 569 smenr & ~RPCIF_SMENR_SPIDE(0xF)); 570 regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy); 571 regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr); 572 memcpy_fromio(rpc->buffer, rpc->dirmap, rpc->xferlen); 573 regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF); 574 /* Dummy read according to spec */ 575 regmap_read(rpc->regmap, RPCIF_DRCR, &dummy); 576 break; 577 } 578 while (pos < rpc->xferlen) { 579 u32 bytes_left = rpc->xferlen - pos; 580 u32 nbytes, data[2], *p = data; 581 582 /* nbytes may only be 1, 2, 4, or 8 */ 583 nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left)); 584 585 regmap_write(rpc->regmap, RPCIF_SMADR, 586 rpc->smadr + pos); 587 smenr &= ~RPCIF_SMENR_SPIDE(0xF); 588 smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes)); 589 regmap_write(rpc->regmap, RPCIF_SMENR, smenr); 590 regmap_write(rpc->regmap, RPCIF_SMCR, 591 rpc->smcr | RPCIF_SMCR_SPIE); 592 rpc->xfer_size = nbytes; 593 ret = wait_msg_xfer_end(rpc); 594 if (ret) 595 goto err_out; 596 597 if (nbytes == 8) 598 regmap_read(rpc->regmap, RPCIF_SMRDR1, p++); 599 regmap_read(rpc->regmap, RPCIF_SMRDR0, p); 600 memcpy(rpc->buffer + pos, data, nbytes); 601 602 pos += nbytes; 603 } 604 break; 605 default: 606 regmap_write(rpc->regmap, RPCIF_SMENR, rpc->enable); 607 regmap_write(rpc->regmap, RPCIF_SMCR, 608 rpc->smcr | RPCIF_SMCR_SPIE); 609 ret = wait_msg_xfer_end(rpc); 610 if (ret) 611 goto err_out; 612 } 613 614 return ret; 615 616 err_out: 617 if (reset_control_reset(rpc->rstc)) 618 dev_err(rpc->dev, "Failed to reset HW\n"); 619 rpcif_hw_init_impl(rpc, rpc->bus_size == 2); 620 return ret; 621 } 622 623 static int xspi_manual_xfer_impl(struct rpcif_priv *xspi) 624 { 625 u32 pos = 0, max = 8; 626 int ret = 0; 627 628 regmap_update_bits(xspi->regmap, XSPI_CDCTL0, XSPI_CDCTL0_TRNUM(0x3), 629 XSPI_CDCTL0_TRNUM(0)); 630 631 regmap_update_bits(xspi->regmap, XSPI_CDCTL0, XSPI_CDCTL0_TRREQ, 0); 632 633 regmap_write(xspi->regmap, XSPI_CDTBUF0, 634 XSPI_CDTBUF_CMDSIZE(0x1) | XSPI_CDTBUF_CMD_FIELD(xspi->command)); 635 636 regmap_write(xspi->regmap, XSPI_CDABUF0, 0); 637 638 regmap_update_bits(xspi->regmap, XSPI_CDTBUF0, XSPI_CDTBUF_ADDSIZE(0x7), 639 XSPI_CDTBUF_ADDSIZE(xspi->addr_nbytes)); 640 641 regmap_write(xspi->regmap, XSPI_CDABUF0, xspi->smadr); 642 643 regmap_update_bits(xspi->regmap, XSPI_LIOCFGCS0, XSPI_LIOCFG_PRTMD(0x3ff), 644 XSPI_LIOCFG_PRTMD(xspi->proto)); 645 646 switch (xspi->dir) { 647 case RPCIF_DATA_OUT: 648 while (pos < xspi->xferlen) { 649 u32 bytes_left = xspi->xferlen - pos; 650 u32 nbytes, data[2], *p = data; 651 652 regmap_update_bits(xspi->regmap, XSPI_CDTBUF0, 653 XSPI_CDTBUF_TRTYPE, XSPI_CDTBUF_TRTYPE); 654 655 nbytes = bytes_left >= max ? max : bytes_left; 656 657 regmap_update_bits(xspi->regmap, XSPI_CDTBUF0, 658 XSPI_CDTBUF_DATASIZE(0xf), 659 XSPI_CDTBUF_DATASIZE(nbytes)); 660 661 regmap_update_bits(xspi->regmap, XSPI_CDTBUF0, 662 XSPI_CDTBUF_ADDSIZE(0x7), 663 XSPI_CDTBUF_ADDSIZE(xspi->addr_nbytes)); 664 665 memcpy(data, xspi->buffer + pos, nbytes); 666 667 if (nbytes > 4) { 668 regmap_write(xspi->regmap, XSPI_CDD0BUF0, *p++); 669 regmap_write(xspi->regmap, XSPI_CDD1BUF0, *p); 670 } else { 671 regmap_write(xspi->regmap, XSPI_CDD0BUF0, *p); 672 } 673 674 regmap_write(xspi->regmap, XSPI_CDABUF0, xspi->smadr + pos); 675 676 regmap_update_bits(xspi->regmap, XSPI_CDCTL0, 677 XSPI_CDCTL0_TRREQ, XSPI_CDCTL0_TRREQ); 678 679 ret = wait_msg_xfer_end(xspi); 680 if (ret) 681 goto err_out; 682 683 regmap_update_bits(xspi->regmap, XSPI_INTC, 684 XSPI_INTC_CMDCMPC, XSPI_INTC_CMDCMPC); 685 686 pos += nbytes; 687 } 688 regmap_update_bits(xspi->regmap, XSPI_CDCTL0, XSPI_CDCTL0_TRREQ, 0); 689 break; 690 case RPCIF_DATA_IN: 691 while (pos < xspi->xferlen) { 692 u32 bytes_left = xspi->xferlen - pos; 693 u32 nbytes, data[2], *p = data; 694 695 regmap_update_bits(xspi->regmap, XSPI_CDTBUF0, 696 XSPI_CDTBUF_TRTYPE, 697 ~(u32)XSPI_CDTBUF_TRTYPE); 698 699 /* nbytes can be up to 8 bytes */ 700 nbytes = bytes_left >= max ? max : bytes_left; 701 702 regmap_update_bits(xspi->regmap, XSPI_CDTBUF0, 703 XSPI_CDTBUF_DATASIZE(0xf), 704 XSPI_CDTBUF_DATASIZE(nbytes)); 705 706 regmap_update_bits(xspi->regmap, XSPI_CDTBUF0, 707 XSPI_CDTBUF_ADDSIZE(0x7), 708 XSPI_CDTBUF_ADDSIZE(xspi->addr_nbytes)); 709 710 if (xspi->addr_nbytes) 711 regmap_write(xspi->regmap, XSPI_CDABUF0, 712 xspi->smadr + pos); 713 714 regmap_update_bits(xspi->regmap, XSPI_CDTBUF0, 715 XSPI_CDTBUF_LATE(0x1f), 716 XSPI_CDTBUF_LATE(xspi->dummy)); 717 718 regmap_update_bits(xspi->regmap, XSPI_CDCTL0, 719 XSPI_CDCTL0_TRREQ, XSPI_CDCTL0_TRREQ); 720 721 ret = wait_msg_xfer_end(xspi); 722 if (ret) 723 goto err_out; 724 725 if (nbytes > 4) { 726 regmap_read(xspi->regmap, XSPI_CDD0BUF0, p++); 727 regmap_read(xspi->regmap, XSPI_CDD1BUF0, p); 728 } else { 729 regmap_read(xspi->regmap, XSPI_CDD0BUF0, p); 730 } 731 732 memcpy(xspi->buffer + pos, data, nbytes); 733 734 regmap_update_bits(xspi->regmap, XSPI_INTC, 735 XSPI_INTC_CMDCMPC, XSPI_INTC_CMDCMPC); 736 737 pos += nbytes; 738 } 739 regmap_update_bits(xspi->regmap, XSPI_CDCTL0, 740 XSPI_CDCTL0_TRREQ, 0); 741 break; 742 default: 743 regmap_update_bits(xspi->regmap, XSPI_CDTBUF0, 744 XSPI_CDTBUF_TRTYPE, XSPI_CDTBUF_TRTYPE); 745 regmap_update_bits(xspi->regmap, XSPI_CDCTL0, 746 XSPI_CDCTL0_TRREQ, XSPI_CDCTL0_TRREQ); 747 748 ret = wait_msg_xfer_end(xspi); 749 if (ret) 750 goto err_out; 751 752 regmap_update_bits(xspi->regmap, XSPI_INTC, 753 XSPI_INTC_CMDCMPC, XSPI_INTC_CMDCMPC); 754 } 755 756 return ret; 757 758 err_out: 759 xspi_hw_init_impl(xspi, false); 760 return ret; 761 } 762 763 int rpcif_manual_xfer(struct device *dev) 764 { 765 struct rpcif_priv *rpc = dev_get_drvdata(dev); 766 int ret; 767 768 ret = pm_runtime_resume_and_get(dev); 769 if (ret) 770 return ret; 771 772 ret = rpc->info->impl->manual_xfer(rpc); 773 774 pm_runtime_put(dev); 775 776 return ret; 777 } 778 EXPORT_SYMBOL(rpcif_manual_xfer); 779 780 static void memcpy_fromio_readw(void *to, 781 const void __iomem *from, 782 size_t count) 783 { 784 const int maxw = (IS_ENABLED(CONFIG_64BIT)) ? 8 : 4; 785 u8 buf[2]; 786 787 if (count && ((unsigned long)from & 1)) { 788 *(u16 *)buf = __raw_readw((void __iomem *)((unsigned long)from & ~1)); 789 *(u8 *)to = buf[1]; 790 from++; 791 to++; 792 count--; 793 } 794 while (count >= 2 && !IS_ALIGNED((unsigned long)from, maxw)) { 795 *(u16 *)to = __raw_readw(from); 796 from += 2; 797 to += 2; 798 count -= 2; 799 } 800 while (count >= maxw) { 801 #ifdef CONFIG_64BIT 802 *(u64 *)to = __raw_readq(from); 803 #else 804 *(u32 *)to = __raw_readl(from); 805 #endif 806 from += maxw; 807 to += maxw; 808 count -= maxw; 809 } 810 while (count >= 2) { 811 *(u16 *)to = __raw_readw(from); 812 from += 2; 813 to += 2; 814 count -= 2; 815 } 816 if (count) { 817 *(u16 *)buf = __raw_readw(from); 818 *(u8 *)to = buf[0]; 819 } 820 } 821 822 static size_t rpcif_dirmap_read_impl(struct rpcif_priv *rpc, u64 offs, 823 size_t len, void *buf) 824 { 825 loff_t from = offs & (rpc->size - 1); 826 size_t size = rpc->size - from; 827 828 if (len > size) 829 len = size; 830 831 regmap_update_bits(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_MD, 0); 832 regmap_write(rpc->regmap, RPCIF_DRCR, 0); 833 regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command); 834 regmap_write(rpc->regmap, RPCIF_DREAR, 835 RPCIF_DREAR_EAV(offs >> 25) | RPCIF_DREAR_EAC(1)); 836 regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option); 837 regmap_write(rpc->regmap, RPCIF_DRENR, 838 rpc->enable & ~RPCIF_SMENR_SPIDE(0xF)); 839 regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy); 840 regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr); 841 842 if (rpc->bus_size == 2) 843 memcpy_fromio_readw(buf, rpc->dirmap + from, len); 844 else 845 memcpy_fromio(buf, rpc->dirmap + from, len); 846 847 return len; 848 } 849 850 static size_t xspi_dirmap_read_impl(struct rpcif_priv *xspi, u64 offs, 851 size_t len, void *buf) 852 { 853 loff_t from = offs & (xspi->size - 1); 854 size_t size = xspi->size - from; 855 u8 addsize = xspi->addr_nbytes - 1; 856 857 if (len > size) 858 len = size; 859 860 regmap_update_bits(xspi->regmap, XSPI_CMCFG0CS0, 861 XSPI_CMCFG0_FFMT(0x3) | XSPI_CMCFG0_ADDSIZE(0x3), 862 XSPI_CMCFG0_FFMT(0) | XSPI_CMCFG0_ADDSIZE(addsize)); 863 864 regmap_update_bits(xspi->regmap, XSPI_CMCFG1CS0, 865 XSPI_CMCFG1_RDCMD(0xffff) | XSPI_CMCFG1_RDLATE(0x1f), 866 XSPI_CMCFG1_RDCMD_UPPER_BYTE(xspi->command) | 867 XSPI_CMCFG1_RDLATE(xspi->dummy)); 868 869 regmap_update_bits(xspi->regmap, XSPI_BMCTL0, XSPI_BMCTL0_CS0ACC(0xff), 870 XSPI_BMCTL0_CS0ACC(0x01)); 871 872 regmap_update_bits(xspi->regmap, XSPI_BMCFG, 873 XSPI_BMCFG_WRMD | XSPI_BMCFG_MWRCOMB | 874 XSPI_BMCFG_MWRSIZE(0xff) | XSPI_BMCFG_PREEN, 875 0 | XSPI_BMCFG_MWRCOMB | XSPI_BMCFG_MWRSIZE(0x0f) | 876 XSPI_BMCFG_PREEN); 877 878 regmap_update_bits(xspi->regmap, XSPI_LIOCFGCS0, XSPI_LIOCFG_PRTMD(0x3ff), 879 XSPI_LIOCFG_PRTMD(xspi->proto)); 880 881 memcpy_fromio(buf, xspi->dirmap + from, len); 882 883 return len; 884 } 885 886 ssize_t rpcif_dirmap_read(struct device *dev, u64 offs, size_t len, void *buf) 887 { 888 struct rpcif_priv *rpc = dev_get_drvdata(dev); 889 size_t read; 890 int ret; 891 892 ret = pm_runtime_resume_and_get(dev); 893 if (ret) 894 return ret; 895 896 read = rpc->info->impl->dirmap_read(rpc, offs, len, buf); 897 898 pm_runtime_put(dev); 899 900 return read; 901 } 902 EXPORT_SYMBOL(rpcif_dirmap_read); 903 904 /** 905 * xspi_dirmap_write - Write data to xspi memory. 906 * @dev: xspi device 907 * @offs: offset 908 * @len: Number of bytes to be written. 909 * @buf: Buffer holding write data. 910 * 911 * This function writes data into xspi memory. 912 * 913 * Returns number of bytes written on success, else negative errno. 914 */ 915 ssize_t xspi_dirmap_write(struct device *dev, u64 offs, size_t len, const void *buf) 916 { 917 struct rpcif_priv *xspi = dev_get_drvdata(dev); 918 loff_t from = offs & (xspi->size - 1); 919 u8 addsize = xspi->addr_nbytes - 1; 920 size_t size = xspi->size - from; 921 ssize_t writebytes; 922 int ret; 923 924 ret = pm_runtime_resume_and_get(dev); 925 if (ret) 926 return ret; 927 928 if (len > size) 929 len = size; 930 931 if (len > MWRSIZE_MAX) 932 writebytes = MWRSIZE_MAX; 933 else 934 writebytes = len; 935 936 regmap_update_bits(xspi->regmap, XSPI_CMCFG0CS0, 937 XSPI_CMCFG0_FFMT(0x3) | XSPI_CMCFG0_ADDSIZE(0x3), 938 XSPI_CMCFG0_FFMT(0) | XSPI_CMCFG0_ADDSIZE(addsize)); 939 940 regmap_update_bits(xspi->regmap, XSPI_CMCFG2CS0, 941 XSPI_CMCFG2_WRCMD_UPPER(0xff) | XSPI_CMCFG2_WRLATE(0x1f), 942 XSPI_CMCFG2_WRCMD_UPPER(xspi->command) | 943 XSPI_CMCFG2_WRLATE(xspi->dummy)); 944 945 regmap_update_bits(xspi->regmap, XSPI_BMCTL0, 946 XSPI_BMCTL0_CS0ACC(0xff), XSPI_BMCTL0_CS0ACC(0x03)); 947 948 regmap_update_bits(xspi->regmap, XSPI_BMCFG, 949 XSPI_BMCFG_WRMD | XSPI_BMCFG_MWRCOMB | 950 XSPI_BMCFG_MWRSIZE(0xff) | XSPI_BMCFG_PREEN, 951 0 | XSPI_BMCFG_MWRCOMB | XSPI_BMCFG_MWRSIZE(0x0f) | 952 XSPI_BMCFG_PREEN); 953 954 regmap_update_bits(xspi->regmap, XSPI_LIOCFGCS0, XSPI_LIOCFG_PRTMD(0x3ff), 955 XSPI_LIOCFG_PRTMD(xspi->proto)); 956 957 memcpy_toio(xspi->dirmap + from, buf, writebytes); 958 959 /* Request to push the pending data */ 960 if (writebytes < MWRSIZE_MAX) 961 regmap_update_bits(xspi->regmap, XSPI_BMCTL1, 962 XSPI_BMCTL1_MWRPUSH, XSPI_BMCTL1_MWRPUSH); 963 964 pm_runtime_put(dev); 965 966 return writebytes; 967 } 968 EXPORT_SYMBOL_GPL(xspi_dirmap_write); 969 970 static int rpcif_probe(struct platform_device *pdev) 971 { 972 struct device *dev = &pdev->dev; 973 struct platform_device *vdev; 974 struct device_node *flash; 975 struct rpcif_priv *rpc; 976 struct resource *res; 977 const char *name; 978 int ret; 979 980 flash = of_get_next_child(dev->of_node, NULL); 981 if (!flash) { 982 dev_warn(dev, "no flash node found\n"); 983 return -ENODEV; 984 } 985 986 if (of_device_is_compatible(flash, "jedec,spi-nor")) { 987 name = "rpc-if-spi"; 988 } else if (of_device_is_compatible(flash, "cfi-flash")) { 989 name = "rpc-if-hyperflash"; 990 } else { 991 of_node_put(flash); 992 dev_warn(dev, "unknown flash type\n"); 993 return -ENODEV; 994 } 995 of_node_put(flash); 996 997 rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL); 998 if (!rpc) 999 return -ENOMEM; 1000 1001 rpc->base = devm_platform_ioremap_resource_byname(pdev, "regs"); 1002 if (IS_ERR(rpc->base)) 1003 return PTR_ERR(rpc->base); 1004 rpc->info = of_device_get_match_data(dev); 1005 rpc->regmap = devm_regmap_init(dev, NULL, rpc, rpc->info->regmap_config); 1006 if (IS_ERR(rpc->regmap)) { 1007 dev_err(dev, "failed to init regmap for rpcif, error %ld\n", 1008 PTR_ERR(rpc->regmap)); 1009 return PTR_ERR(rpc->regmap); 1010 } 1011 1012 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap"); 1013 rpc->dirmap = devm_ioremap_resource(dev, res); 1014 if (IS_ERR(rpc->dirmap)) 1015 return PTR_ERR(rpc->dirmap); 1016 1017 rpc->size = resource_size(res); 1018 rpc->rstc = devm_reset_control_array_get_exclusive(dev); 1019 if (IS_ERR(rpc->rstc)) 1020 return PTR_ERR(rpc->rstc); 1021 1022 /* 1023 * The enabling/disabling of spi/spix2 clocks at runtime leading to 1024 * flash write failure. So, enable these clocks during probe() and 1025 * disable it in remove(). 1026 */ 1027 if (rpc->info->type == XSPI_RZ_G3E) { 1028 struct clk *spi_clk; 1029 1030 spi_clk = devm_clk_get_enabled(dev, "spix2"); 1031 if (IS_ERR(spi_clk)) 1032 return dev_err_probe(dev, PTR_ERR(spi_clk), 1033 "cannot get enabled spix2 clk\n"); 1034 1035 spi_clk = devm_clk_get_enabled(dev, "spi"); 1036 if (IS_ERR(spi_clk)) 1037 return dev_err_probe(dev, PTR_ERR(spi_clk), 1038 "cannot get enabled spi clk\n"); 1039 } 1040 1041 vdev = platform_device_alloc(name, pdev->id); 1042 if (!vdev) 1043 return -ENOMEM; 1044 vdev->dev.parent = dev; 1045 1046 rpc->dev = dev; 1047 rpc->vdev = vdev; 1048 platform_set_drvdata(pdev, rpc); 1049 1050 ret = platform_device_add(vdev); 1051 if (ret) { 1052 platform_device_put(vdev); 1053 return ret; 1054 } 1055 1056 return 0; 1057 } 1058 1059 static void rpcif_remove(struct platform_device *pdev) 1060 { 1061 struct rpcif_priv *rpc = platform_get_drvdata(pdev); 1062 1063 platform_device_unregister(rpc->vdev); 1064 } 1065 1066 static const struct rpcif_impl rpcif_impl = { 1067 .hw_init = rpcif_hw_init_impl, 1068 .prepare = rpcif_prepare_impl, 1069 .manual_xfer = rpcif_manual_xfer_impl, 1070 .dirmap_read = rpcif_dirmap_read_impl, 1071 .status_reg = RPCIF_CMNSR, 1072 .status_mask = RPCIF_CMNSR_TEND, 1073 }; 1074 1075 static const struct rpcif_impl xspi_impl = { 1076 .hw_init = xspi_hw_init_impl, 1077 .prepare = xspi_prepare_impl, 1078 .manual_xfer = xspi_manual_xfer_impl, 1079 .dirmap_read = xspi_dirmap_read_impl, 1080 .status_reg = XSPI_INTS, 1081 .status_mask = XSPI_INTS_CMDCMP, 1082 }; 1083 1084 static const struct rpcif_info rpcif_info_r8a7796 = { 1085 .regmap_config = &rpcif_regmap_config, 1086 .impl = &rpcif_impl, 1087 .type = RPCIF_RCAR_GEN3, 1088 .strtim = 6, 1089 }; 1090 1091 static const struct rpcif_info rpcif_info_gen3 = { 1092 .regmap_config = &rpcif_regmap_config, 1093 .impl = &rpcif_impl, 1094 .type = RPCIF_RCAR_GEN3, 1095 .strtim = 7, 1096 }; 1097 1098 static const struct rpcif_info rpcif_info_rz_g2l = { 1099 .regmap_config = &rpcif_regmap_config, 1100 .impl = &rpcif_impl, 1101 .type = RPCIF_RZ_G2L, 1102 .strtim = 7, 1103 }; 1104 1105 static const struct rpcif_info rpcif_info_gen4 = { 1106 .regmap_config = &rpcif_regmap_config, 1107 .impl = &rpcif_impl, 1108 .type = RPCIF_RCAR_GEN4, 1109 .strtim = 15, 1110 }; 1111 1112 static const struct rpcif_info xspi_info_r9a09g047 = { 1113 .regmap_config = &xspi_regmap_config, 1114 .impl = &xspi_impl, 1115 .type = XSPI_RZ_G3E, 1116 }; 1117 1118 static const struct of_device_id rpcif_of_match[] = { 1119 { .compatible = "renesas,r8a7796-rpc-if", .data = &rpcif_info_r8a7796 }, 1120 { .compatible = "renesas,r9a09g047-xspi", .data = &xspi_info_r9a09g047 }, 1121 { .compatible = "renesas,rcar-gen3-rpc-if", .data = &rpcif_info_gen3 }, 1122 { .compatible = "renesas,rcar-gen4-rpc-if", .data = &rpcif_info_gen4 }, 1123 { .compatible = "renesas,rzg2l-rpc-if", .data = &rpcif_info_rz_g2l }, 1124 {}, 1125 }; 1126 MODULE_DEVICE_TABLE(of, rpcif_of_match); 1127 1128 static struct platform_driver rpcif_driver = { 1129 .probe = rpcif_probe, 1130 .remove = rpcif_remove, 1131 .driver = { 1132 .name = "rpc-if", 1133 .of_match_table = rpcif_of_match, 1134 }, 1135 }; 1136 module_platform_driver(rpcif_driver); 1137 1138 MODULE_DESCRIPTION("Renesas RPC-IF core driver"); 1139 MODULE_LICENSE("GPL v2"); 1140