1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015-2016 MediaTek Inc. 4 * Author: Yong Wu <yong.wu@mediatek.com> 5 */ 6 #include <linux/arm-smccc.h> 7 #include <linux/clk.h> 8 #include <linux/component.h> 9 #include <linux/device.h> 10 #include <linux/err.h> 11 #include <linux/io.h> 12 #include <linux/iopoll.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_platform.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/soc/mediatek/mtk_sip_svc.h> 19 #include <soc/mediatek/smi.h> 20 #include <dt-bindings/memory/mt2701-larb-port.h> 21 #include <dt-bindings/memory/mtk-memory-port.h> 22 23 /* SMI COMMON */ 24 #define SMI_L1LEN 0x100 25 26 #define SMI_L1_ARB 0x200 27 #define SMI_BUS_SEL 0x220 28 #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1) 29 /* All are MMU0 defaultly. Only specialize mmu1 here. */ 30 #define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid)) 31 32 #define SMI_READ_FIFO_TH 0x230 33 #define SMI_M4U_TH 0x234 34 #define SMI_FIFO_TH1 0x238 35 #define SMI_FIFO_TH2 0x23c 36 #define SMI_DCM 0x300 37 #define SMI_DUMMY 0x444 38 39 /* SMI LARB */ 40 #define SMI_LARB_SLP_CON 0xc 41 #define SLP_PROT_EN BIT(0) 42 #define SLP_PROT_RDY BIT(16) 43 44 #define SMI_LARB_CMD_THRT_CON 0x24 45 #define SMI_LARB_THRT_RD_NU_LMT_MSK GENMASK(7, 4) 46 #define SMI_LARB_THRT_RD_NU_LMT (5 << 4) 47 48 #define SMI_LARB_SW_FLAG 0x40 49 #define SMI_LARB_SW_FLAG_1 0x1 50 51 #define SMI_LARB_OSTDL_PORT 0x200 52 #define SMI_LARB_OSTDL_PORTx(id) (SMI_LARB_OSTDL_PORT + (((id) & 0x1f) << 2)) 53 54 /* Below are about mmu enable registers, they are different in SoCs */ 55 /* gen1: mt2701 */ 56 #define REG_SMI_SECUR_CON_BASE 0x5c0 57 58 /* every register control 8 port, register offset 0x4 */ 59 #define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2) 60 #define REG_SMI_SECUR_CON_ADDR(id) \ 61 (REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id)) 62 63 /* 64 * every port have 4 bit to control, bit[port + 3] control virtual or physical, 65 * bit[port + 2 : port + 1] control the domain, bit[port] control the security 66 * or non-security. 67 */ 68 #define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2))) 69 #define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3) 70 /* mt2701 domain should be set to 3 */ 71 #define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1)) 72 73 /* gen2: */ 74 /* mt8167 */ 75 #define MT8167_SMI_LARB_MMU_EN 0xfc0 76 77 /* mt8173 */ 78 #define MT8173_SMI_LARB_MMU_EN 0xf00 79 80 /* general */ 81 #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4)) 82 #define F_MMU_EN BIT(0) 83 #define BANK_SEL(id) ({ \ 84 u32 _id = (id) & 0x3; \ 85 (_id << 8 | _id << 10 | _id << 12 | _id << 14); \ 86 }) 87 88 #define SMI_COMMON_INIT_REGS_NR 6 89 #define SMI_LARB_PORT_NR_MAX 32 90 91 #define MTK_SMI_FLAG_THRT_UPDATE BIT(0) 92 #define MTK_SMI_FLAG_SW_FLAG BIT(1) 93 #define MTK_SMI_FLAG_SLEEP_CTL BIT(2) 94 #define MTK_SMI_FLAG_CFG_PORT_SEC_CTL BIT(3) 95 #define MTK_SMI_CAPS(flags, _x) (!!((flags) & (_x))) 96 97 struct mtk_smi_reg_pair { 98 unsigned int offset; 99 u32 value; 100 }; 101 102 enum mtk_smi_type { 103 MTK_SMI_GEN1, 104 MTK_SMI_GEN2, /* gen2 smi common */ 105 MTK_SMI_GEN2_SUB_COMM, /* gen2 smi sub common */ 106 }; 107 108 /* larbs: Require apb/smi clocks while gals is optional. */ 109 static const char * const mtk_smi_larb_clks[] = {"apb", "smi", "gals"}; 110 #define MTK_SMI_LARB_REQ_CLK_NR 2 111 #define MTK_SMI_LARB_OPT_CLK_NR 1 112 113 /* 114 * common: Require these four clocks in has_gals case. Otherwise, only apb/smi are required. 115 * sub common: Require apb/smi/gals0 clocks in has_gals case. Otherwise, only apb/smi are required. 116 */ 117 static const char * const mtk_smi_common_clks[] = {"apb", "smi", "gals0", "gals1"}; 118 #define MTK_SMI_CLK_NR_MAX ARRAY_SIZE(mtk_smi_common_clks) 119 #define MTK_SMI_COM_REQ_CLK_NR 2 120 #define MTK_SMI_COM_GALS_REQ_CLK_NR MTK_SMI_CLK_NR_MAX 121 #define MTK_SMI_SUB_COM_GALS_REQ_CLK_NR 3 122 123 struct mtk_smi_common_plat { 124 enum mtk_smi_type type; 125 bool has_gals; 126 u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */ 127 128 const struct mtk_smi_reg_pair *init; 129 }; 130 131 struct mtk_smi_larb_gen { 132 int port_in_larb[MTK_LARB_NR_MAX + 1]; 133 int (*config_port)(struct device *dev); 134 unsigned int larb_direct_to_common_mask; 135 unsigned int flags_general; 136 const u8 (*ostd)[SMI_LARB_PORT_NR_MAX]; 137 }; 138 139 struct mtk_smi { 140 struct device *dev; 141 unsigned int clk_num; 142 struct clk_bulk_data clks[MTK_SMI_CLK_NR_MAX]; 143 struct clk *clk_async; /*only needed by mt2701*/ 144 union { 145 void __iomem *smi_ao_base; /* only for gen1 */ 146 void __iomem *base; /* only for gen2 */ 147 }; 148 struct device *smi_common_dev; /* for sub common */ 149 const struct mtk_smi_common_plat *plat; 150 }; 151 152 struct mtk_smi_larb { /* larb: local arbiter */ 153 struct mtk_smi smi; 154 void __iomem *base; 155 struct device *smi_common_dev; /* common or sub-common dev */ 156 const struct mtk_smi_larb_gen *larb_gen; 157 int larbid; 158 u32 *mmu; 159 unsigned char *bank; 160 }; 161 162 static int 163 mtk_smi_larb_bind(struct device *dev, struct device *master, void *data) 164 { 165 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 166 struct mtk_smi_larb_iommu *larb_mmu = data; 167 unsigned int i; 168 169 for (i = 0; i < MTK_LARB_NR_MAX; i++) { 170 if (dev == larb_mmu[i].dev) { 171 larb->larbid = i; 172 larb->mmu = &larb_mmu[i].mmu; 173 larb->bank = larb_mmu[i].bank; 174 return 0; 175 } 176 } 177 return -ENODEV; 178 } 179 180 static void 181 mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data) 182 { 183 /* Do nothing as the iommu is always enabled. */ 184 } 185 186 static const struct component_ops mtk_smi_larb_component_ops = { 187 .bind = mtk_smi_larb_bind, 188 .unbind = mtk_smi_larb_unbind, 189 }; 190 191 static int mtk_smi_larb_config_port_gen1(struct device *dev) 192 { 193 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 194 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; 195 struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev); 196 int i, m4u_port_id, larb_port_num; 197 u32 sec_con_val, reg_val; 198 199 m4u_port_id = larb_gen->port_in_larb[larb->larbid]; 200 larb_port_num = larb_gen->port_in_larb[larb->larbid + 1] 201 - larb_gen->port_in_larb[larb->larbid]; 202 203 for (i = 0; i < larb_port_num; i++, m4u_port_id++) { 204 if (*larb->mmu & BIT(i)) { 205 /* bit[port + 3] controls the virtual or physical */ 206 sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id); 207 } else { 208 /* do not need to enable m4u for this port */ 209 continue; 210 } 211 reg_val = readl(common->smi_ao_base 212 + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); 213 reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id); 214 reg_val |= sec_con_val; 215 reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id); 216 writel(reg_val, 217 common->smi_ao_base 218 + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); 219 } 220 return 0; 221 } 222 223 static int mtk_smi_larb_config_port_mt8167(struct device *dev) 224 { 225 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 226 227 writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN); 228 return 0; 229 } 230 231 static int mtk_smi_larb_config_port_mt8173(struct device *dev) 232 { 233 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 234 235 writel(*larb->mmu, larb->base + MT8173_SMI_LARB_MMU_EN); 236 return 0; 237 } 238 239 static int mtk_smi_larb_config_port_gen2_general(struct device *dev) 240 { 241 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 242 u32 reg, flags_general = larb->larb_gen->flags_general; 243 const u8 *larbostd = larb->larb_gen->ostd ? larb->larb_gen->ostd[larb->larbid] : NULL; 244 struct arm_smccc_res res; 245 int i; 246 247 if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) 248 return 0; 249 250 if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_THRT_UPDATE)) { 251 reg = readl_relaxed(larb->base + SMI_LARB_CMD_THRT_CON); 252 reg &= ~SMI_LARB_THRT_RD_NU_LMT_MSK; 253 reg |= SMI_LARB_THRT_RD_NU_LMT; 254 writel_relaxed(reg, larb->base + SMI_LARB_CMD_THRT_CON); 255 } 256 257 if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_SW_FLAG)) 258 writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG); 259 260 for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++) 261 writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i)); 262 263 /* 264 * When mmu_en bits are in security world, the bank_sel still is in the 265 * LARB_NONSEC_CON below. And the mmu_en bits of LARB_NONSEC_CON have no 266 * effect in this case. 267 */ 268 if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_CFG_PORT_SEC_CTL)) { 269 arm_smccc_smc(MTK_SIP_KERNEL_IOMMU_CONTROL, IOMMU_ATF_CMD_CONFIG_SMI_LARB, 270 larb->larbid, *larb->mmu, 0, 0, 0, 0, &res); 271 if (res.a0 != 0) { 272 dev_err(dev, "Enable iommu fail, ret %ld\n", res.a0); 273 return -EINVAL; 274 } 275 } 276 277 for_each_set_bit(i, (unsigned long *)larb->mmu, 32) { 278 reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); 279 reg |= F_MMU_EN; 280 reg |= BANK_SEL(larb->bank[i]); 281 writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); 282 } 283 return 0; 284 } 285 286 static const u8 mtk_smi_larb_mt6893_ostd[][SMI_LARB_PORT_NR_MAX] = { 287 [0] = {0x2, 0x6, 0x2, 0x2, 0x2, 0x28, 0x18, 0x18, 0x1, 0x1, 0x1, 0x8, 288 0x8, 0x1, 0x3f}, 289 [1] = {0x2, 0x6, 0x2, 0x2, 0x2, 0x28, 0x18, 0x18, 0x1, 0x1, 0x1, 0x8, 290 0x8, 0x1, 0x3f}, 291 [2] = {0x5, 0x5, 0x5, 0x5, 0x1, 0x3f}, 292 [3] = {0x5, 0x5, 0x5, 0x5, 0x1, 0x3f}, 293 [4] = {0x28, 0x19, 0xb, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x4, 0x1}, 294 [5] = {0x1, 0x1, 0x4, 0x1, 0x1, 0x1, 0x1, 0x16}, 295 [6] = {}, 296 [7] = {0x1, 0x4, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x4, 0x4, 0x1, 297 0x4, 0x1, 0xa, 0x6, 0x1, 0xa, 0x6, 0x1, 0x1, 0x1, 0x1, 0x5, 298 0x3, 0x3, 0x4}, 299 [8] = {0x1, 0x4, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x4, 0x4, 0x1, 300 0x4, 0x1, 0xa, 0x6, 0x1, 0xa, 0x6, 0x1, 0x1, 0x1, 0x1, 0x5, 301 0x3, 0x3, 0x4}, 302 [9] = {0x9, 0x7, 0xf, 0x8, 0x1, 0x8, 0x9, 0x3, 0x3, 0x6, 0x7, 0x4, 303 0x9, 0x3, 0x4, 0xe, 0x1, 0x7, 0x8, 0x7, 0x7, 0x1, 0x6, 0x2, 304 0xf, 0x8, 0x1, 0x1, 0x1}, 305 [10] = {}, 306 [11] = {0x9, 0x7, 0xf, 0x8, 0x1, 0x8, 0x9, 0x3, 0x3, 0x6, 0x7, 0x4, 307 0x9, 0x3, 0x4, 0xe, 0x1, 0x7, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 308 0x1, 0x1, 0x1, 0x1, 0x1}, 309 [12] = {}, 310 [13] = {0x2, 0xc, 0xc, 0xe, 0x6, 0x6, 0x6, 0x6, 0x6, 0x12, 0x6, 0x1}, 311 [14] = {0x2, 0xc, 0xc, 0x28, 0x12, 0x6}, 312 [15] = {0x28, 0x1, 0x2, 0x28, 0x1}, 313 [16] = {0x28, 0x14, 0x2, 0xc, 0x18, 0x2, 0x14, 0x14, 0x4, 0x4, 0x4, 0x2, 314 0x4, 0x2, 0x8, 0x4, 0x4}, 315 [17] = {0x28, 0x14, 0x2, 0xc, 0x18, 0x2, 0x14, 0x14, 0x4, 0x4, 0x4, 0x2, 316 0x4, 0x2, 0x8, 0x4, 0x4}, 317 [18] = {0x28, 0x14, 0x2, 0xc, 0x18, 0x2, 0x14, 0x14, 0x4, 0x4, 0x4, 0x2, 318 0x4, 0x2, 0x8, 0x4, 0x4}, 319 [19] = {0x2, 0x2, 0x4, 0x2}, 320 [20] = {0x9, 0x9, 0x5, 0x5, 0x1, 0x1}, 321 }; 322 323 static const u8 mtk_smi_larb_mt8188_ostd[][SMI_LARB_PORT_NR_MAX] = { 324 [0] = {0x02, 0x18, 0x22, 0x22, 0x01, 0x02, 0x0a,}, 325 [1] = {0x12, 0x02, 0x14, 0x14, 0x01, 0x18, 0x0a,}, 326 [2] = {0x12, 0x12, 0x12, 0x12, 0x0a,}, 327 [3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,}, 328 [4] = {0x06, 0x01, 0x17, 0x06, 0x0a, 0x07, 0x07,}, 329 [5] = {0x02, 0x01, 0x04, 0x02, 0x06, 0x01, 0x06, 0x0a,}, 330 [6] = {0x06, 0x01, 0x06, 0x0a,}, 331 [7] = {0x0c, 0x0c, 0x12,}, 332 [8] = {0x0c, 0x01, 0x0a, 0x05, 0x02, 0x03, 0x01, 0x01, 0x14, 0x14, 333 0x0a, 0x14, 0x1e, 0x01, 0x0c, 0x0a, 0x05, 0x02, 0x02, 0x05, 334 0x03, 0x01, 0x1e, 0x01, 0x05,}, 335 [9] = {0x1e, 0x01, 0x0a, 0x0a, 0x01, 0x01, 0x03, 0x1e, 0x1e, 0x10, 336 0x07, 0x01, 0x0a, 0x06, 0x03, 0x03, 0x0e, 0x01, 0x04, 0x28,}, 337 [10] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c, 338 0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14, 339 0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,}, 340 [11] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c, 341 0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14, 342 0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,}, 343 [12] = {0x03, 0x20, 0x01, 0x20, 0x01, 0x01, 0x14, 0x0a, 0x0a, 0x0c, 344 0x0a, 0x05, 0x02, 0x03, 0x02, 0x14, 0x0a, 0x0a, 0x14, 0x14, 345 0x14, 0x01, 0x01, 0x14, 0x1e, 0x01, 0x05, 0x03, 0x02, 0x28,}, 346 [13] = {0x07, 0x02, 0x04, 0x02, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 347 0x07, 0x02, 0x04, 0x02, 0x05, 0x05,}, 348 [14] = {0x02, 0x02, 0x0c, 0x0c, 0x0c, 0x0c, 0x01, 0x01, 0x02, 0x02, 349 0x02, 0x02, 0x0c, 0x0c, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 350 0x02, 0x02, 0x01, 0x01,}, 351 [15] = {0x0c, 0x0c, 0x02, 0x02, 0x02, 0x02, 0x01, 0x01, 0x0c, 0x0c, 352 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x01, 0x02, 353 0x0c, 0x01, 0x01,}, 354 [16] = {0x28, 0x28, 0x03, 0x01, 0x01, 0x03, 0x14, 0x14, 0x0a, 0x0d, 355 0x03, 0x05, 0x0e, 0x01, 0x01, 0x05, 0x06, 0x0d, 0x01,}, 356 [17] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a, 357 0x12, 0x02, 0x02, 0x0a, 0x16, 0x02, 0x04,}, 358 [18] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a, 359 0x12, 0x02, 0x02, 0x0a, 0x16, 0x02, 0x04,}, 360 [19] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,}, 361 [20] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,}, 362 [21] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01, 363 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06, 364 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,}, 365 [22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 366 0x01,}, 367 [23] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x18, 0x01, 0x01,}, 368 [24] = {0x12, 0x06, 0x12, 0x06,}, 369 [25] = {0x01}, 370 }; 371 372 static const u8 mtk_smi_larb_mt8192_ostd[][SMI_LARB_PORT_NR_MAX] = { 373 [0] = {0x2, 0x2, 0x28, 0xa, 0xc, 0x28,}, 374 [1] = {0x2, 0x2, 0x18, 0x18, 0x18, 0xa, 0xc, 0x28,}, 375 [2] = {0x5, 0x5, 0x5, 0x5, 0x1,}, 376 [3] = {}, 377 [4] = {0x28, 0x19, 0xb, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x4, 0x1,}, 378 [5] = {0x1, 0x1, 0x4, 0x1, 0x1, 0x1, 0x1, 0x16,}, 379 [6] = {}, 380 [7] = {0x1, 0x3, 0x2, 0x1, 0x1, 0x5, 0x2, 0x12, 0x13, 0x4, 0x4, 0x1, 381 0x4, 0x2, 0x1,}, 382 [8] = {}, 383 [9] = {0xa, 0x7, 0xf, 0x8, 0x1, 0x8, 0x9, 0x3, 0x3, 0x6, 0x7, 0x4, 384 0xa, 0x3, 0x4, 0xe, 0x1, 0x7, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 385 0x1, 0x1, 0x1, 0x1, 0x1,}, 386 [10] = {}, 387 [11] = {0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 388 0x1, 0x1, 0x1, 0xe, 0x1, 0x7, 0x8, 0x7, 0x7, 0x1, 0x6, 0x2, 389 0xf, 0x8, 0x1, 0x1, 0x1,}, 390 [12] = {}, 391 [13] = {0x2, 0xc, 0xc, 0xe, 0x6, 0x6, 0x6, 0x6, 0x6, 0x12, 0x6, 0x28, 392 0x2, 0xc, 0xc, 0x28, 0x12, 0x6,}, 393 [14] = {}, 394 [15] = {0x28, 0x14, 0x2, 0xc, 0x18, 0x4, 0x28, 0x14, 0x4, 0x4, 0x4, 0x2, 395 0x4, 0x2, 0x8, 0x4, 0x4,}, 396 [16] = {0x28, 0x14, 0x2, 0xc, 0x18, 0x4, 0x28, 0x14, 0x4, 0x4, 0x4, 0x2, 397 0x4, 0x2, 0x8, 0x4, 0x4,}, 398 [17] = {0x28, 0x14, 0x2, 0xc, 0x18, 0x4, 0x28, 0x14, 0x4, 0x4, 0x4, 0x2, 399 0x4, 0x2, 0x8, 0x4, 0x4,}, 400 [18] = {0x2, 0x2, 0x4, 0x2,}, 401 [19] = {0x9, 0x9, 0x5, 0x5, 0x1, 0x1,}, 402 }; 403 404 static const u8 mtk_smi_larb_mt8195_ostd[][SMI_LARB_PORT_NR_MAX] = { 405 [0] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb0 */ 406 [1] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb1 */ 407 [2] = {0x12, 0x12, 0x12, 0x12, 0x0a,}, /* ... */ 408 [3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,}, 409 [4] = {0x06, 0x01, 0x17, 0x06, 0x0a,}, 410 [5] = {0x06, 0x01, 0x17, 0x06, 0x06, 0x01, 0x06, 0x0a,}, 411 [6] = {0x06, 0x01, 0x06, 0x0a,}, 412 [7] = {0x0c, 0x0c, 0x12,}, 413 [8] = {0x0c, 0x0c, 0x12,}, 414 [9] = {0x0a, 0x08, 0x04, 0x06, 0x01, 0x01, 0x10, 0x18, 0x11, 0x0a, 415 0x08, 0x04, 0x11, 0x06, 0x02, 0x06, 0x01, 0x11, 0x11, 0x06,}, 416 [10] = {0x18, 0x08, 0x01, 0x01, 0x20, 0x12, 0x18, 0x06, 0x05, 0x10, 417 0x08, 0x08, 0x10, 0x08, 0x08, 0x18, 0x0c, 0x09, 0x0b, 0x0d, 418 0x0d, 0x06, 0x10, 0x10,}, 419 [11] = {0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x01, 0x01, 0x01, 0x01,}, 420 [12] = {0x09, 0x09, 0x05, 0x05, 0x0c, 0x18, 0x02, 0x02, 0x04, 0x02,}, 421 [13] = {0x02, 0x02, 0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x08, 0x01,}, 422 [14] = {0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x16, 0x01, 0x16, 0x01, 423 0x01, 0x02, 0x02, 0x08, 0x02,}, 424 [15] = {}, 425 [16] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a, 426 0x12, 0x02, 0x0a, 0x16, 0x02, 0x04,}, 427 [17] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,}, 428 [18] = {0x12, 0x06, 0x12, 0x06,}, 429 [19] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01, 430 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06, 431 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,}, 432 [20] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01, 433 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06, 434 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,}, 435 [21] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,}, 436 [22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,}, 437 [23] = {0x18, 0x01,}, 438 [24] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x01, 439 0x01, 0x01,}, 440 [25] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, 441 0x02, 0x01,}, 442 [26] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, 443 0x02, 0x01,}, 444 [27] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, 445 0x02, 0x01,}, 446 [28] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,}, 447 }; 448 449 static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = { 450 .port_in_larb = { 451 LARB0_PORT_OFFSET, LARB1_PORT_OFFSET, 452 LARB2_PORT_OFFSET, LARB3_PORT_OFFSET 453 }, 454 .config_port = mtk_smi_larb_config_port_gen1, 455 }; 456 457 static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = { 458 .config_port = mtk_smi_larb_config_port_gen2_general, 459 .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */ 460 }; 461 462 static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = { 463 .config_port = mtk_smi_larb_config_port_gen2_general, 464 .larb_direct_to_common_mask = 465 BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13), 466 /* DUMMY | IPU0 | IPU1 | CCU | MDLA */ 467 }; 468 469 static const struct mtk_smi_larb_gen mtk_smi_larb_mt6893 = { 470 .config_port = mtk_smi_larb_config_port_gen2_general, 471 .flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG, 472 .ostd = mtk_smi_larb_mt6893_ostd, 473 }; 474 475 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = { 476 /* mt8167 do not need the port in larb */ 477 .config_port = mtk_smi_larb_config_port_mt8167, 478 }; 479 480 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = { 481 /* mt8173 do not need the port in larb */ 482 .config_port = mtk_smi_larb_config_port_mt8173, 483 }; 484 485 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = { 486 .config_port = mtk_smi_larb_config_port_gen2_general, 487 .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7), 488 /* IPU0 | IPU1 | CCU */ 489 }; 490 491 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8186 = { 492 .config_port = mtk_smi_larb_config_port_gen2_general, 493 .flags_general = MTK_SMI_FLAG_SLEEP_CTL, 494 }; 495 496 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8188 = { 497 .config_port = mtk_smi_larb_config_port_gen2_general, 498 .flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG | 499 MTK_SMI_FLAG_SLEEP_CTL | MTK_SMI_FLAG_CFG_PORT_SEC_CTL, 500 .ostd = mtk_smi_larb_mt8188_ostd, 501 }; 502 503 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = { 504 .config_port = mtk_smi_larb_config_port_gen2_general, 505 .ostd = mtk_smi_larb_mt8192_ostd, 506 }; 507 508 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8195 = { 509 .config_port = mtk_smi_larb_config_port_gen2_general, 510 .flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG | 511 MTK_SMI_FLAG_SLEEP_CTL, 512 .ostd = mtk_smi_larb_mt8195_ostd, 513 }; 514 515 static const struct of_device_id mtk_smi_larb_of_ids[] = { 516 {.compatible = "mediatek,mt2701-smi-larb", .data = &mtk_smi_larb_mt2701}, 517 {.compatible = "mediatek,mt2712-smi-larb", .data = &mtk_smi_larb_mt2712}, 518 {.compatible = "mediatek,mt6779-smi-larb", .data = &mtk_smi_larb_mt6779}, 519 {.compatible = "mediatek,mt6795-smi-larb", .data = &mtk_smi_larb_mt8173}, 520 {.compatible = "mediatek,mt6893-smi-larb", .data = &mtk_smi_larb_mt6893}, 521 {.compatible = "mediatek,mt8167-smi-larb", .data = &mtk_smi_larb_mt8167}, 522 {.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173}, 523 {.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183}, 524 {.compatible = "mediatek,mt8186-smi-larb", .data = &mtk_smi_larb_mt8186}, 525 {.compatible = "mediatek,mt8188-smi-larb", .data = &mtk_smi_larb_mt8188}, 526 {.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192}, 527 {.compatible = "mediatek,mt8195-smi-larb", .data = &mtk_smi_larb_mt8195}, 528 {} 529 }; 530 MODULE_DEVICE_TABLE(of, mtk_smi_larb_of_ids); 531 532 static int mtk_smi_larb_sleep_ctrl_enable(struct mtk_smi_larb *larb) 533 { 534 int ret; 535 u32 tmp; 536 537 writel_relaxed(SLP_PROT_EN, larb->base + SMI_LARB_SLP_CON); 538 ret = readl_poll_timeout_atomic(larb->base + SMI_LARB_SLP_CON, 539 tmp, !!(tmp & SLP_PROT_RDY), 10, 1000); 540 if (ret) { 541 /* TODO: Reset this larb if it fails here. */ 542 dev_err(larb->smi.dev, "sleep ctrl is not ready(0x%x).\n", tmp); 543 } 544 return ret; 545 } 546 547 static void mtk_smi_larb_sleep_ctrl_disable(struct mtk_smi_larb *larb) 548 { 549 writel_relaxed(0, larb->base + SMI_LARB_SLP_CON); 550 } 551 552 static int mtk_smi_device_link_common(struct device *dev, struct device **com_dev) 553 { 554 struct platform_device *smi_com_pdev; 555 struct device_node *smi_com_node; 556 struct device *smi_com_dev; 557 struct device_link *link; 558 559 smi_com_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0); 560 if (!smi_com_node) 561 return -EINVAL; 562 563 smi_com_pdev = of_find_device_by_node(smi_com_node); 564 of_node_put(smi_com_node); 565 if (smi_com_pdev) { 566 /* smi common is the supplier, Make sure it is ready before */ 567 if (!platform_get_drvdata(smi_com_pdev)) { 568 put_device(&smi_com_pdev->dev); 569 return -EPROBE_DEFER; 570 } 571 smi_com_dev = &smi_com_pdev->dev; 572 link = device_link_add(dev, smi_com_dev, 573 DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); 574 if (!link) { 575 dev_err(dev, "Unable to link smi-common dev\n"); 576 put_device(&smi_com_pdev->dev); 577 return -ENODEV; 578 } 579 *com_dev = smi_com_dev; 580 } else { 581 dev_err(dev, "Failed to get the smi_common device\n"); 582 return -EINVAL; 583 } 584 return 0; 585 } 586 587 static int mtk_smi_dts_clk_init(struct device *dev, struct mtk_smi *smi, 588 const char * const clks[], 589 unsigned int clk_nr_required, 590 unsigned int clk_nr_optional) 591 { 592 int i, ret; 593 594 for (i = 0; i < clk_nr_required; i++) 595 smi->clks[i].id = clks[i]; 596 ret = devm_clk_bulk_get(dev, clk_nr_required, smi->clks); 597 if (ret) 598 return ret; 599 600 for (i = clk_nr_required; i < clk_nr_required + clk_nr_optional; i++) 601 smi->clks[i].id = clks[i]; 602 ret = devm_clk_bulk_get_optional(dev, clk_nr_optional, 603 smi->clks + clk_nr_required); 604 smi->clk_num = clk_nr_required + clk_nr_optional; 605 return ret; 606 } 607 608 static int mtk_smi_larb_probe(struct platform_device *pdev) 609 { 610 struct mtk_smi_larb *larb; 611 struct device *dev = &pdev->dev; 612 int ret; 613 614 larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL); 615 if (!larb) 616 return -ENOMEM; 617 618 larb->larb_gen = of_device_get_match_data(dev); 619 larb->base = devm_platform_ioremap_resource(pdev, 0); 620 if (IS_ERR(larb->base)) 621 return PTR_ERR(larb->base); 622 623 ret = mtk_smi_dts_clk_init(dev, &larb->smi, mtk_smi_larb_clks, 624 MTK_SMI_LARB_REQ_CLK_NR, MTK_SMI_LARB_OPT_CLK_NR); 625 if (ret) 626 return ret; 627 628 larb->smi.dev = dev; 629 630 ret = mtk_smi_device_link_common(dev, &larb->smi_common_dev); 631 if (ret < 0) 632 return ret; 633 634 pm_runtime_enable(dev); 635 platform_set_drvdata(pdev, larb); 636 ret = component_add(dev, &mtk_smi_larb_component_ops); 637 if (ret) 638 goto err_pm_disable; 639 return 0; 640 641 err_pm_disable: 642 pm_runtime_disable(dev); 643 device_link_remove(dev, larb->smi_common_dev); 644 return ret; 645 } 646 647 static void mtk_smi_larb_remove(struct platform_device *pdev) 648 { 649 struct mtk_smi_larb *larb = platform_get_drvdata(pdev); 650 651 device_link_remove(&pdev->dev, larb->smi_common_dev); 652 pm_runtime_disable(&pdev->dev); 653 component_del(&pdev->dev, &mtk_smi_larb_component_ops); 654 } 655 656 static int __maybe_unused mtk_smi_larb_resume(struct device *dev) 657 { 658 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 659 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; 660 int ret; 661 662 ret = clk_bulk_prepare_enable(larb->smi.clk_num, larb->smi.clks); 663 if (ret) 664 return ret; 665 666 if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_SLEEP_CTL)) 667 mtk_smi_larb_sleep_ctrl_disable(larb); 668 669 /* Configure the basic setting for this larb */ 670 return larb_gen->config_port(dev); 671 } 672 673 static int __maybe_unused mtk_smi_larb_suspend(struct device *dev) 674 { 675 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 676 int ret; 677 678 if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_SLEEP_CTL)) { 679 ret = mtk_smi_larb_sleep_ctrl_enable(larb); 680 if (ret) 681 return ret; 682 } 683 684 clk_bulk_disable_unprepare(larb->smi.clk_num, larb->smi.clks); 685 return 0; 686 } 687 688 static const struct dev_pm_ops smi_larb_pm_ops = { 689 SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL) 690 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 691 pm_runtime_force_resume) 692 }; 693 694 static struct platform_driver mtk_smi_larb_driver = { 695 .probe = mtk_smi_larb_probe, 696 .remove = mtk_smi_larb_remove, 697 .driver = { 698 .name = "mtk-smi-larb", 699 .of_match_table = mtk_smi_larb_of_ids, 700 .pm = &smi_larb_pm_ops, 701 } 702 }; 703 704 static const struct mtk_smi_reg_pair mtk_smi_common_mt6795_init[SMI_COMMON_INIT_REGS_NR] = { 705 {SMI_L1_ARB, 0x1b}, 706 {SMI_M4U_TH, 0xce810c85}, 707 {SMI_FIFO_TH1, 0x43214c8}, 708 {SMI_READ_FIFO_TH, 0x191f}, 709 }; 710 711 static const struct mtk_smi_reg_pair mtk_smi_common_mt8195_init[SMI_COMMON_INIT_REGS_NR] = { 712 {SMI_L1LEN, 0xb}, 713 {SMI_M4U_TH, 0xe100e10}, 714 {SMI_FIFO_TH1, 0x506090a}, 715 {SMI_FIFO_TH2, 0x506090a}, 716 {SMI_DCM, 0x4f1}, 717 {SMI_DUMMY, 0x1}, 718 }; 719 720 static const struct mtk_smi_common_plat mtk_smi_common_gen1 = { 721 .type = MTK_SMI_GEN1, 722 }; 723 724 static const struct mtk_smi_common_plat mtk_smi_common_gen2 = { 725 .type = MTK_SMI_GEN2, 726 }; 727 728 static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = { 729 .type = MTK_SMI_GEN2, 730 .has_gals = true, 731 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) | 732 F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7), 733 }; 734 735 static const struct mtk_smi_common_plat mtk_smi_common_mt6795 = { 736 .type = MTK_SMI_GEN2, 737 .bus_sel = F_MMU1_LARB(0), 738 .init = mtk_smi_common_mt6795_init, 739 }; 740 741 static const struct mtk_smi_common_plat mtk_smi_common_mt6893 = { 742 .type = MTK_SMI_GEN2, 743 .has_gals = true, 744 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) | 745 F_MMU1_LARB(5) | F_MMU1_LARB(7), 746 }; 747 748 static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = { 749 .type = MTK_SMI_GEN2, 750 .has_gals = true, 751 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | 752 F_MMU1_LARB(7), 753 }; 754 755 static const struct mtk_smi_common_plat mtk_smi_common_mt8186 = { 756 .type = MTK_SMI_GEN2, 757 .has_gals = true, 758 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(4) | F_MMU1_LARB(7), 759 }; 760 761 static const struct mtk_smi_common_plat mtk_smi_common_mt8188_vdo = { 762 .type = MTK_SMI_GEN2, 763 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(5) | F_MMU1_LARB(7), 764 .init = mtk_smi_common_mt8195_init, 765 }; 766 767 static const struct mtk_smi_common_plat mtk_smi_common_mt8188_vpp = { 768 .type = MTK_SMI_GEN2, 769 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7), 770 .init = mtk_smi_common_mt8195_init, 771 }; 772 773 static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = { 774 .type = MTK_SMI_GEN2, 775 .has_gals = true, 776 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | 777 F_MMU1_LARB(6), 778 }; 779 780 static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vdo = { 781 .type = MTK_SMI_GEN2, 782 .has_gals = true, 783 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(5) | 784 F_MMU1_LARB(7), 785 .init = mtk_smi_common_mt8195_init, 786 }; 787 788 static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vpp = { 789 .type = MTK_SMI_GEN2, 790 .has_gals = true, 791 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7), 792 .init = mtk_smi_common_mt8195_init, 793 }; 794 795 static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8195 = { 796 .type = MTK_SMI_GEN2_SUB_COMM, 797 .has_gals = true, 798 }; 799 800 static const struct mtk_smi_common_plat mtk_smi_common_mt8365 = { 801 .type = MTK_SMI_GEN2, 802 .bus_sel = F_MMU1_LARB(2) | F_MMU1_LARB(4), 803 }; 804 805 static const struct of_device_id mtk_smi_common_of_ids[] = { 806 {.compatible = "mediatek,mt2701-smi-common", .data = &mtk_smi_common_gen1}, 807 {.compatible = "mediatek,mt2712-smi-common", .data = &mtk_smi_common_gen2}, 808 {.compatible = "mediatek,mt6779-smi-common", .data = &mtk_smi_common_mt6779}, 809 {.compatible = "mediatek,mt6795-smi-common", .data = &mtk_smi_common_mt6795}, 810 {.compatible = "mediatek,mt6893-smi-common", .data = &mtk_smi_common_mt6893}, 811 {.compatible = "mediatek,mt8167-smi-common", .data = &mtk_smi_common_gen2}, 812 {.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2}, 813 {.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183}, 814 {.compatible = "mediatek,mt8186-smi-common", .data = &mtk_smi_common_mt8186}, 815 {.compatible = "mediatek,mt8188-smi-common-vdo", .data = &mtk_smi_common_mt8188_vdo}, 816 {.compatible = "mediatek,mt8188-smi-common-vpp", .data = &mtk_smi_common_mt8188_vpp}, 817 {.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192}, 818 {.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo}, 819 {.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp}, 820 {.compatible = "mediatek,mt8195-smi-sub-common", .data = &mtk_smi_sub_common_mt8195}, 821 {.compatible = "mediatek,mt8365-smi-common", .data = &mtk_smi_common_mt8365}, 822 {} 823 }; 824 MODULE_DEVICE_TABLE(of, mtk_smi_common_of_ids); 825 826 static int mtk_smi_common_probe(struct platform_device *pdev) 827 { 828 struct device *dev = &pdev->dev; 829 struct mtk_smi *common; 830 int ret, clk_required = MTK_SMI_COM_REQ_CLK_NR; 831 832 common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL); 833 if (!common) 834 return -ENOMEM; 835 common->dev = dev; 836 common->plat = of_device_get_match_data(dev); 837 838 if (common->plat->has_gals) { 839 if (common->plat->type == MTK_SMI_GEN2) 840 clk_required = MTK_SMI_COM_GALS_REQ_CLK_NR; 841 else if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) 842 clk_required = MTK_SMI_SUB_COM_GALS_REQ_CLK_NR; 843 } 844 ret = mtk_smi_dts_clk_init(dev, common, mtk_smi_common_clks, clk_required, 0); 845 if (ret) 846 return ret; 847 848 /* 849 * for mtk smi gen 1, we need to get the ao(always on) base to config 850 * m4u port, and we need to enable the aync clock for transform the smi 851 * clock into emi clock domain, but for mtk smi gen2, there's no smi ao 852 * base. 853 */ 854 if (common->plat->type == MTK_SMI_GEN1) { 855 common->smi_ao_base = devm_platform_ioremap_resource(pdev, 0); 856 if (IS_ERR(common->smi_ao_base)) 857 return PTR_ERR(common->smi_ao_base); 858 859 common->clk_async = devm_clk_get_enabled(dev, "async"); 860 if (IS_ERR(common->clk_async)) 861 return PTR_ERR(common->clk_async); 862 } else { 863 common->base = devm_platform_ioremap_resource(pdev, 0); 864 if (IS_ERR(common->base)) 865 return PTR_ERR(common->base); 866 } 867 868 /* link its smi-common if this is smi-sub-common */ 869 if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) { 870 ret = mtk_smi_device_link_common(dev, &common->smi_common_dev); 871 if (ret < 0) 872 return ret; 873 } 874 875 pm_runtime_enable(dev); 876 platform_set_drvdata(pdev, common); 877 return 0; 878 } 879 880 static void mtk_smi_common_remove(struct platform_device *pdev) 881 { 882 struct mtk_smi *common = dev_get_drvdata(&pdev->dev); 883 884 if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) 885 device_link_remove(&pdev->dev, common->smi_common_dev); 886 pm_runtime_disable(&pdev->dev); 887 } 888 889 static int __maybe_unused mtk_smi_common_resume(struct device *dev) 890 { 891 struct mtk_smi *common = dev_get_drvdata(dev); 892 const struct mtk_smi_reg_pair *init = common->plat->init; 893 u32 bus_sel = common->plat->bus_sel; /* default is 0 */ 894 int ret, i; 895 896 ret = clk_bulk_prepare_enable(common->clk_num, common->clks); 897 if (ret) 898 return ret; 899 900 if (common->plat->type != MTK_SMI_GEN2) 901 return 0; 902 903 for (i = 0; i < SMI_COMMON_INIT_REGS_NR && init && init[i].offset; i++) 904 writel_relaxed(init[i].value, common->base + init[i].offset); 905 906 writel(bus_sel, common->base + SMI_BUS_SEL); 907 return 0; 908 } 909 910 static int __maybe_unused mtk_smi_common_suspend(struct device *dev) 911 { 912 struct mtk_smi *common = dev_get_drvdata(dev); 913 914 clk_bulk_disable_unprepare(common->clk_num, common->clks); 915 return 0; 916 } 917 918 static const struct dev_pm_ops smi_common_pm_ops = { 919 SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL) 920 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 921 pm_runtime_force_resume) 922 }; 923 924 static struct platform_driver mtk_smi_common_driver = { 925 .probe = mtk_smi_common_probe, 926 .remove = mtk_smi_common_remove, 927 .driver = { 928 .name = "mtk-smi-common", 929 .of_match_table = mtk_smi_common_of_ids, 930 .pm = &smi_common_pm_ops, 931 } 932 }; 933 934 static struct platform_driver * const smidrivers[] = { 935 &mtk_smi_common_driver, 936 &mtk_smi_larb_driver, 937 }; 938 939 static int __init mtk_smi_init(void) 940 { 941 return platform_register_drivers(smidrivers, ARRAY_SIZE(smidrivers)); 942 } 943 module_init(mtk_smi_init); 944 945 static void __exit mtk_smi_exit(void) 946 { 947 platform_unregister_drivers(smidrivers, ARRAY_SIZE(smidrivers)); 948 } 949 module_exit(mtk_smi_exit); 950 951 MODULE_DESCRIPTION("MediaTek SMI driver"); 952 MODULE_LICENSE("GPL v2"); 953