1*74ba9207SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2e0d3bafdSSri Deevi /* 3e0d3bafdSSri Deevi cx231xx_conf-reg.h - driver for Conexant Cx23100/101/102 USB 4e0d3bafdSSri Deevi video capture devices 5e0d3bafdSSri Deevi 6e0d3bafdSSri Deevi Copyright (C) 2008 <srinivasa.deevi at conexant dot com> 7e0d3bafdSSri Deevi 8e0d3bafdSSri Deevi */ 9e0d3bafdSSri Deevi 10e0d3bafdSSri Deevi #ifndef _POLARIS_REG_H_ 11e0d3bafdSSri Deevi #define _POLARIS_REG_H_ 12e0d3bafdSSri Deevi 13e0d3bafdSSri Deevi #define BOARD_CFG_STAT 0x0 14e0d3bafdSSri Deevi #define TS_MODE_REG 0x4 15e0d3bafdSSri Deevi #define TS1_CFG_REG 0x8 16e0d3bafdSSri Deevi #define TS1_LENGTH_REG 0xc 17e0d3bafdSSri Deevi #define TS2_CFG_REG 0x10 18e0d3bafdSSri Deevi #define TS2_LENGTH_REG 0x14 19e0d3bafdSSri Deevi #define EP_MODE_SET 0x18 20e0d3bafdSSri Deevi #define CIR_PWR_PTN1 0x1c 21e0d3bafdSSri Deevi #define CIR_PWR_PTN2 0x20 22e0d3bafdSSri Deevi #define CIR_PWR_PTN3 0x24 23e0d3bafdSSri Deevi #define CIR_PWR_MASK0 0x28 24e0d3bafdSSri Deevi #define CIR_PWR_MASK1 0x2c 25e0d3bafdSSri Deevi #define CIR_PWR_MASK2 0x30 26e0d3bafdSSri Deevi #define CIR_GAIN 0x34 27e0d3bafdSSri Deevi #define CIR_CAR_REG 0x38 28e0d3bafdSSri Deevi #define CIR_OT_CFG1 0x40 29e0d3bafdSSri Deevi #define CIR_OT_CFG2 0x44 3064fbf444SPalash Bandyopadhyay #define GBULK_BIT_EN 0x68 31e0d3bafdSSri Deevi #define PWR_CTL_EN 0x74 32e0d3bafdSSri Deevi 33e0d3bafdSSri Deevi /* Polaris Endpoints capture mask for register EP_MODE_SET */ 34e0d3bafdSSri Deevi #define ENABLE_EP1 0x01 /* Bit[0]=1 */ 35e0d3bafdSSri Deevi #define ENABLE_EP2 0x02 /* Bit[1]=1 */ 36e0d3bafdSSri Deevi #define ENABLE_EP3 0x04 /* Bit[2]=1 */ 37e0d3bafdSSri Deevi #define ENABLE_EP4 0x08 /* Bit[3]=1 */ 38e0d3bafdSSri Deevi #define ENABLE_EP5 0x10 /* Bit[4]=1 */ 39e0d3bafdSSri Deevi #define ENABLE_EP6 0x20 /* Bit[5]=1 */ 40e0d3bafdSSri Deevi 41e0d3bafdSSri Deevi /* Bit definition for register PWR_CTL_EN */ 42e0d3bafdSSri Deevi #define PWR_MODE_MASK 0x17f 43e0d3bafdSSri Deevi #define PWR_AV_EN 0x08 /* bit3 */ 44e0d3bafdSSri Deevi #define PWR_ISO_EN 0x40 /* bit6 */ 45e0d3bafdSSri Deevi #define PWR_AV_MODE 0x30 /* bit4,5 */ 46e0d3bafdSSri Deevi #define PWR_TUNER_EN 0x04 /* bit2 */ 47e0d3bafdSSri Deevi #define PWR_DEMOD_EN 0x02 /* bit1 */ 48e0d3bafdSSri Deevi #define I2C_DEMOD_EN 0x01 /* bit0 */ 49e0d3bafdSSri Deevi #define PWR_RESETOUT_EN 0x100 /* bit8 */ 50e0d3bafdSSri Deevi 516e4f574bSSri Deevi enum AV_MODE{ 52e0d3bafdSSri Deevi POLARIS_AVMODE_DEFAULT = 0, 53e0d3bafdSSri Deevi POLARIS_AVMODE_DIGITAL = 0x10, 54e0d3bafdSSri Deevi POLARIS_AVMODE_ANALOGT_TV = 0x20, 55e0d3bafdSSri Deevi POLARIS_AVMODE_ENXTERNAL_AV = 0x30, 56e0d3bafdSSri Deevi 576e4f574bSSri Deevi }; 58e0d3bafdSSri Deevi 59e0d3bafdSSri Deevi /* Colibri Registers */ 60e0d3bafdSSri Deevi 61e0d3bafdSSri Deevi #define SINGLE_ENDED 0x0 62e0d3bafdSSri Deevi #define LOW_IF 0x4 63e0d3bafdSSri Deevi #define EU_IF 0x9 64e0d3bafdSSri Deevi #define US_IF 0xa 65e0d3bafdSSri Deevi 66e0d3bafdSSri Deevi #define SUP_BLK_TUNE1 0x00 67e0d3bafdSSri Deevi #define SUP_BLK_TUNE2 0x01 68e0d3bafdSSri Deevi #define SUP_BLK_TUNE3 0x02 69e0d3bafdSSri Deevi #define SUP_BLK_XTAL 0x03 70e0d3bafdSSri Deevi #define SUP_BLK_PLL1 0x04 71e0d3bafdSSri Deevi #define SUP_BLK_PLL2 0x05 72e0d3bafdSSri Deevi #define SUP_BLK_PLL3 0x06 73e0d3bafdSSri Deevi #define SUP_BLK_REF 0x07 74e0d3bafdSSri Deevi #define SUP_BLK_PWRDN 0x08 75e0d3bafdSSri Deevi #define SUP_BLK_TESTPAD 0x09 76e0d3bafdSSri Deevi #define ADC_COM_INT5_STAB_REF 0x0a 77e0d3bafdSSri Deevi #define ADC_COM_QUANT 0x0b 78e0d3bafdSSri Deevi #define ADC_COM_BIAS1 0x0c 79e0d3bafdSSri Deevi #define ADC_COM_BIAS2 0x0d 80e0d3bafdSSri Deevi #define ADC_COM_BIAS3 0x0e 81e0d3bafdSSri Deevi #define TESTBUS_CTRL 0x12 82e0d3bafdSSri Deevi 836e4f574bSSri Deevi #define FLD_PWRDN_TUNING_BIAS 0x10 846e4f574bSSri Deevi #define FLD_PWRDN_ENABLE_PLL 0x08 856e4f574bSSri Deevi #define FLD_PWRDN_PD_BANDGAP 0x04 866e4f574bSSri Deevi #define FLD_PWRDN_PD_BIAS 0x02 876e4f574bSSri Deevi #define FLD_PWRDN_PD_TUNECK 0x01 886e4f574bSSri Deevi 896e4f574bSSri Deevi 90e0d3bafdSSri Deevi #define ADC_STATUS_CH1 0x20 91e0d3bafdSSri Deevi #define ADC_STATUS_CH2 0x40 92e0d3bafdSSri Deevi #define ADC_STATUS_CH3 0x60 93e0d3bafdSSri Deevi 94e0d3bafdSSri Deevi #define ADC_STATUS2_CH1 0x21 95e0d3bafdSSri Deevi #define ADC_STATUS2_CH2 0x41 96e0d3bafdSSri Deevi #define ADC_STATUS2_CH3 0x61 97e0d3bafdSSri Deevi 98e0d3bafdSSri Deevi #define ADC_CAL_ATEST_CH1 0x22 99e0d3bafdSSri Deevi #define ADC_CAL_ATEST_CH2 0x42 100e0d3bafdSSri Deevi #define ADC_CAL_ATEST_CH3 0x62 101e0d3bafdSSri Deevi 102e0d3bafdSSri Deevi #define ADC_PWRDN_CLAMP_CH1 0x23 103e0d3bafdSSri Deevi #define ADC_PWRDN_CLAMP_CH2 0x43 104e0d3bafdSSri Deevi #define ADC_PWRDN_CLAMP_CH3 0x63 105e0d3bafdSSri Deevi 106e0d3bafdSSri Deevi #define ADC_CTRL_DAC23_CH1 0x24 107e0d3bafdSSri Deevi #define ADC_CTRL_DAC23_CH2 0x44 108e0d3bafdSSri Deevi #define ADC_CTRL_DAC23_CH3 0x64 109e0d3bafdSSri Deevi 110e0d3bafdSSri Deevi #define ADC_CTRL_DAC1_CH1 0x25 111e0d3bafdSSri Deevi #define ADC_CTRL_DAC1_CH2 0x45 112e0d3bafdSSri Deevi #define ADC_CTRL_DAC1_CH3 0x65 113e0d3bafdSSri Deevi 114e0d3bafdSSri Deevi #define ADC_DCSERVO_DEM_CH1 0x26 115e0d3bafdSSri Deevi #define ADC_DCSERVO_DEM_CH2 0x46 116e0d3bafdSSri Deevi #define ADC_DCSERVO_DEM_CH3 0x66 117e0d3bafdSSri Deevi 118e0d3bafdSSri Deevi #define ADC_FB_FRCRST_CH1 0x27 119e0d3bafdSSri Deevi #define ADC_FB_FRCRST_CH2 0x47 120e0d3bafdSSri Deevi #define ADC_FB_FRCRST_CH3 0x67 121e0d3bafdSSri Deevi 122e0d3bafdSSri Deevi #define ADC_INPUT_CH1 0x28 123e0d3bafdSSri Deevi #define ADC_INPUT_CH2 0x48 124e0d3bafdSSri Deevi #define ADC_INPUT_CH3 0x68 125e0d3bafdSSri Deevi #define INPUT_SEL_MASK 0x30 /* [5:4] in_sel */ 126e0d3bafdSSri Deevi 127e0d3bafdSSri Deevi #define ADC_NTF_PRECLMP_EN_CH1 0x29 128e0d3bafdSSri Deevi #define ADC_NTF_PRECLMP_EN_CH2 0x49 129e0d3bafdSSri Deevi #define ADC_NTF_PRECLMP_EN_CH3 0x69 130e0d3bafdSSri Deevi 131e0d3bafdSSri Deevi #define ADC_QGAIN_RES_TRM_CH1 0x2a 132e0d3bafdSSri Deevi #define ADC_QGAIN_RES_TRM_CH2 0x4a 133e0d3bafdSSri Deevi #define ADC_QGAIN_RES_TRM_CH3 0x6a 134e0d3bafdSSri Deevi 135e0d3bafdSSri Deevi #define ADC_SOC_PRECLMP_TERM_CH1 0x2b 136e0d3bafdSSri Deevi #define ADC_SOC_PRECLMP_TERM_CH2 0x4b 137e0d3bafdSSri Deevi #define ADC_SOC_PRECLMP_TERM_CH3 0x6b 138e0d3bafdSSri Deevi 139e0d3bafdSSri Deevi #define TESTBUS_CTRL_CH1 0x32 140e0d3bafdSSri Deevi #define TESTBUS_CTRL_CH2 0x52 141e0d3bafdSSri Deevi #define TESTBUS_CTRL_CH3 0x72 142e0d3bafdSSri Deevi 143e0d3bafdSSri Deevi /****************************************************************************** 144e0d3bafdSSri Deevi * DIF registers * 145e0d3bafdSSri Deevi ******************************************************************************/ 146e0d3bafdSSri Deevi #define DIRECT_IF_REVB_BASE 0x00300 147e0d3bafdSSri Deevi 148e0d3bafdSSri Deevi /*****************************************************************************/ 1496e4f574bSSri Deevi #define DIF_PLL_FREQ_WORD (DIRECT_IF_REVB_BASE + 0x00000000) 150e0d3bafdSSri Deevi /*****************************************************************************/ 151e0d3bafdSSri Deevi #define FLD_DIF_PLL_LOCK 0x80000000 152e0d3bafdSSri Deevi /* Reserved [30:29] */ 153e0d3bafdSSri Deevi #define FLD_DIF_PLL_FREE_RUN 0x10000000 1546e4f574bSSri Deevi #define FLD_DIF_PLL_FREQ 0x0fffffff 155e0d3bafdSSri Deevi 156e0d3bafdSSri Deevi /*****************************************************************************/ 1576e4f574bSSri Deevi #define DIF_PLL_CTRL (DIRECT_IF_REVB_BASE + 0x00000004) 158e0d3bafdSSri Deevi /*****************************************************************************/ 1596e4f574bSSri Deevi #define FLD_DIF_KD_PD 0xff000000 160e0d3bafdSSri Deevi /* Reserved [23:20] */ 1616e4f574bSSri Deevi #define FLD_DIF_KDS_PD 0x000f0000 1626e4f574bSSri Deevi #define FLD_DIF_KI_PD 0x0000ff00 163e0d3bafdSSri Deevi /* Reserved [7:4] */ 1646e4f574bSSri Deevi #define FLD_DIF_KIS_PD 0x0000000f 165e0d3bafdSSri Deevi 166e0d3bafdSSri Deevi /*****************************************************************************/ 1676e4f574bSSri Deevi #define DIF_PLL_CTRL1 (DIRECT_IF_REVB_BASE + 0x00000008) 168e0d3bafdSSri Deevi /*****************************************************************************/ 1696e4f574bSSri Deevi #define FLD_DIF_KD_FD 0xff000000 170e0d3bafdSSri Deevi /* Reserved [23:20] */ 1716e4f574bSSri Deevi #define FLD_DIF_KDS_FD 0x000f0000 1726e4f574bSSri Deevi #define FLD_DIF_KI_FD 0x0000ff00 1736e4f574bSSri Deevi #define FLD_DIF_SIG_PROP_SZ 0x000000f0 1746e4f574bSSri Deevi #define FLD_DIF_KIS_FD 0x0000000f 175e0d3bafdSSri Deevi 176e0d3bafdSSri Deevi /*****************************************************************************/ 1776e4f574bSSri Deevi #define DIF_PLL_CTRL2 (DIRECT_IF_REVB_BASE + 0x0000000c) 178e0d3bafdSSri Deevi /*****************************************************************************/ 1796e4f574bSSri Deevi #define FLD_DIF_PLL_AGC_REF 0xfff00000 1806e4f574bSSri Deevi #define FLD_DIF_PLL_AGC_KI 0x000f0000 181e0d3bafdSSri Deevi /* Reserved [15] */ 182e0d3bafdSSri Deevi #define FLD_DIF_FREQ_LIMIT 0x00007000 1836e4f574bSSri Deevi #define FLD_DIF_K_FD 0x00000f00 1846e4f574bSSri Deevi #define FLD_DIF_DOWNSMPL_FD 0x000000ff 185e0d3bafdSSri Deevi 186e0d3bafdSSri Deevi /*****************************************************************************/ 1876e4f574bSSri Deevi #define DIF_PLL_CTRL3 (DIRECT_IF_REVB_BASE + 0x00000010) 188e0d3bafdSSri Deevi /*****************************************************************************/ 189e0d3bafdSSri Deevi /* Reserved [31:16] */ 190e0d3bafdSSri Deevi #define FLD_DIF_PLL_AGC_EN 0x00008000 191e0d3bafdSSri Deevi /* Reserved [14:12] */ 1926e4f574bSSri Deevi #define FLD_DIF_PLL_MAN_GAIN 0x00000fff 193e0d3bafdSSri Deevi 194e0d3bafdSSri Deevi /*****************************************************************************/ 1956e4f574bSSri Deevi #define DIF_AGC_IF_REF (DIRECT_IF_REVB_BASE + 0x00000014) 196e0d3bafdSSri Deevi /*****************************************************************************/ 1976e4f574bSSri Deevi #define FLD_DIF_K_AGC_RF 0xf0000000 1986e4f574bSSri Deevi #define FLD_DIF_K_AGC_IF 0x0f000000 1996e4f574bSSri Deevi #define FLD_DIF_K_AGC_INT 0x00f00000 200e0d3bafdSSri Deevi /* Reserved [19:12] */ 2016e4f574bSSri Deevi #define FLD_DIF_IF_REF 0x00000fff 202e0d3bafdSSri Deevi 203e0d3bafdSSri Deevi /*****************************************************************************/ 2046e4f574bSSri Deevi #define DIF_AGC_CTRL_IF (DIRECT_IF_REVB_BASE + 0x00000018) 205e0d3bafdSSri Deevi /*****************************************************************************/ 2066e4f574bSSri Deevi #define FLD_DIF_IF_MAX 0xff000000 2076e4f574bSSri Deevi #define FLD_DIF_IF_MIN 0x00ff0000 2086e4f574bSSri Deevi #define FLD_DIF_IF_AGC 0x0000ffff 209e0d3bafdSSri Deevi 210e0d3bafdSSri Deevi /*****************************************************************************/ 2116e4f574bSSri Deevi #define DIF_AGC_CTRL_INT (DIRECT_IF_REVB_BASE + 0x0000001c) 212e0d3bafdSSri Deevi /*****************************************************************************/ 2136e4f574bSSri Deevi #define FLD_DIF_INT_MAX 0xff000000 2146e4f574bSSri Deevi #define FLD_DIF_INT_MIN 0x00ff0000 2156e4f574bSSri Deevi #define FLD_DIF_INT_AGC 0x0000ffff 216e0d3bafdSSri Deevi 217e0d3bafdSSri Deevi /*****************************************************************************/ 2186e4f574bSSri Deevi #define DIF_AGC_CTRL_RF (DIRECT_IF_REVB_BASE + 0x00000020) 219e0d3bafdSSri Deevi /*****************************************************************************/ 2206e4f574bSSri Deevi #define FLD_DIF_RF_MAX 0xff000000 2216e4f574bSSri Deevi #define FLD_DIF_RF_MIN 0x00ff0000 2226e4f574bSSri Deevi #define FLD_DIF_RF_AGC 0x0000ffff 223e0d3bafdSSri Deevi 224e0d3bafdSSri Deevi /*****************************************************************************/ 2256e4f574bSSri Deevi #define DIF_AGC_IF_INT_CURRENT (DIRECT_IF_REVB_BASE + 0x00000024) 226e0d3bafdSSri Deevi /*****************************************************************************/ 2276e4f574bSSri Deevi #define FLD_DIF_IF_AGC_IN 0xffff0000 2286e4f574bSSri Deevi #define FLD_DIF_INT_AGC_IN 0x0000ffff 229e0d3bafdSSri Deevi 230e0d3bafdSSri Deevi /*****************************************************************************/ 2316e4f574bSSri Deevi #define DIF_AGC_RF_CURRENT (DIRECT_IF_REVB_BASE + 0x00000028) 232e0d3bafdSSri Deevi /*****************************************************************************/ 233e0d3bafdSSri Deevi /* Reserved [31:16] */ 2346e4f574bSSri Deevi #define FLD_DIF_RF_AGC_IN 0x0000ffff 235e0d3bafdSSri Deevi 236e0d3bafdSSri Deevi /*****************************************************************************/ 2376e4f574bSSri Deevi #define DIF_VIDEO_AGC_CTRL (DIRECT_IF_REVB_BASE + 0x0000002c) 238e0d3bafdSSri Deevi /*****************************************************************************/ 2396e4f574bSSri Deevi #define FLD_DIF_AFD 0xc0000000 240e0d3bafdSSri Deevi #define FLD_DIF_K_VID_AGC 0x30000000 2416e4f574bSSri Deevi #define FLD_DIF_LINE_LENGTH 0x0fff0000 2426e4f574bSSri Deevi #define FLD_DIF_AGC_GAIN 0x0000ffff 243e0d3bafdSSri Deevi 244e0d3bafdSSri Deevi /*****************************************************************************/ 2456e4f574bSSri Deevi #define DIF_VID_AUD_OVERRIDE (DIRECT_IF_REVB_BASE + 0x00000030) 246e0d3bafdSSri Deevi /*****************************************************************************/ 247e0d3bafdSSri Deevi #define FLD_DIF_AUDIO_AGC_OVERRIDE 0x80000000 248e0d3bafdSSri Deevi /* Reserved [30:30] */ 2496e4f574bSSri Deevi #define FLD_DIF_AUDIO_MAN_GAIN 0x3f000000 250e0d3bafdSSri Deevi /* Reserved [23:17] */ 251e0d3bafdSSri Deevi #define FLD_DIF_VID_AGC_OVERRIDE 0x00010000 2526e4f574bSSri Deevi #define FLD_DIF_VID_MAN_GAIN 0x0000ffff 253e0d3bafdSSri Deevi 254e0d3bafdSSri Deevi /*****************************************************************************/ 2556e4f574bSSri Deevi #define DIF_AV_SEP_CTRL (DIRECT_IF_REVB_BASE + 0x00000034) 256e0d3bafdSSri Deevi /*****************************************************************************/ 2576e4f574bSSri Deevi #define FLD_DIF_LPF_FREQ 0xc0000000 2586e4f574bSSri Deevi #define FLD_DIF_AV_PHASE_INC 0x3f000000 2596e4f574bSSri Deevi #define FLD_DIF_AUDIO_FREQ 0x00ffffff 260e0d3bafdSSri Deevi 261e0d3bafdSSri Deevi /*****************************************************************************/ 2626e4f574bSSri Deevi #define DIF_COMP_FLT_CTRL (DIRECT_IF_REVB_BASE + 0x00000038) 263e0d3bafdSSri Deevi /*****************************************************************************/ 264e0d3bafdSSri Deevi /* Reserved [31:24] */ 2656e4f574bSSri Deevi #define FLD_DIF_IIR23_R2 0x00ff0000 2666e4f574bSSri Deevi #define FLD_DIF_IIR23_R1 0x0000ff00 2676e4f574bSSri Deevi #define FLD_DIF_IIR1_R1 0x000000ff 268e0d3bafdSSri Deevi 269e0d3bafdSSri Deevi /*****************************************************************************/ 2706e4f574bSSri Deevi #define DIF_MISC_CTRL (DIRECT_IF_REVB_BASE + 0x0000003c) 271e0d3bafdSSri Deevi /*****************************************************************************/ 272e0d3bafdSSri Deevi #define FLD_DIF_DIF_BYPASS 0x80000000 273e0d3bafdSSri Deevi #define FLD_DIF_FM_NYQ_GAIN 0x40000000 274e0d3bafdSSri Deevi #define FLD_DIF_RF_AGC_ENA 0x20000000 275e0d3bafdSSri Deevi #define FLD_DIF_INT_AGC_ENA 0x10000000 276e0d3bafdSSri Deevi #define FLD_DIF_IF_AGC_ENA 0x08000000 277e0d3bafdSSri Deevi #define FLD_DIF_FORCE_RF_IF_LOCK 0x04000000 278e0d3bafdSSri Deevi #define FLD_DIF_VIDEO_AGC_ENA 0x02000000 279e0d3bafdSSri Deevi #define FLD_DIF_RF_AGC_INV 0x01000000 280e0d3bafdSSri Deevi #define FLD_DIF_INT_AGC_INV 0x00800000 281e0d3bafdSSri Deevi #define FLD_DIF_IF_AGC_INV 0x00400000 282e0d3bafdSSri Deevi #define FLD_DIF_SPEC_INV 0x00200000 283e0d3bafdSSri Deevi #define FLD_DIF_AUD_FULL_BW 0x00100000 284e0d3bafdSSri Deevi #define FLD_DIF_AUD_SRC_SEL 0x00080000 285e0d3bafdSSri Deevi /* Reserved [18] */ 286e0d3bafdSSri Deevi #define FLD_DIF_IF_FREQ 0x00030000 287e0d3bafdSSri Deevi /* Reserved [15:14] */ 2886e4f574bSSri Deevi #define FLD_DIF_TIP_OFFSET 0x00003f00 289e0d3bafdSSri Deevi /* Reserved [7:5] */ 290e0d3bafdSSri Deevi #define FLD_DIF_DITHER_ENA 0x00000010 291e0d3bafdSSri Deevi /* Reserved [3:1] */ 292e0d3bafdSSri Deevi #define FLD_DIF_RF_IF_LOCK 0x00000001 293e0d3bafdSSri Deevi 294e0d3bafdSSri Deevi /*****************************************************************************/ 2956e4f574bSSri Deevi #define DIF_SRC_PHASE_INC (DIRECT_IF_REVB_BASE + 0x00000040) 296e0d3bafdSSri Deevi /*****************************************************************************/ 297e0d3bafdSSri Deevi /* Reserved [31:29] */ 2986e4f574bSSri Deevi #define FLD_DIF_PHASE_INC 0x1fffffff 299e0d3bafdSSri Deevi 300e0d3bafdSSri Deevi /*****************************************************************************/ 3016e4f574bSSri Deevi #define DIF_SRC_GAIN_CONTROL (DIRECT_IF_REVB_BASE + 0x00000044) 302e0d3bafdSSri Deevi /*****************************************************************************/ 303e0d3bafdSSri Deevi /* Reserved [31:16] */ 3046e4f574bSSri Deevi #define FLD_DIF_SRC_KI 0x0000ff00 3056e4f574bSSri Deevi #define FLD_DIF_SRC_KD 0x000000ff 306e0d3bafdSSri Deevi 307e0d3bafdSSri Deevi /*****************************************************************************/ 3086e4f574bSSri Deevi #define DIF_BPF_COEFF01 (DIRECT_IF_REVB_BASE + 0x00000048) 309e0d3bafdSSri Deevi /*****************************************************************************/ 310e0d3bafdSSri Deevi /* Reserved [31:19] */ 311e0d3bafdSSri Deevi #define FLD_DIF_BPF_COEFF_0 0x00070000 312e0d3bafdSSri Deevi /* Reserved [15:4] */ 3136e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_1 0x0000000f 314e0d3bafdSSri Deevi 315e0d3bafdSSri Deevi /*****************************************************************************/ 3166e4f574bSSri Deevi #define DIF_BPF_COEFF23 (DIRECT_IF_REVB_BASE + 0x0000004c) 317e0d3bafdSSri Deevi /*****************************************************************************/ 318e0d3bafdSSri Deevi /* Reserved [31:22] */ 3196e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_2 0x003f0000 320e0d3bafdSSri Deevi /* Reserved [15:7] */ 3216e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_3 0x0000007f 322e0d3bafdSSri Deevi 323e0d3bafdSSri Deevi /*****************************************************************************/ 3246e4f574bSSri Deevi #define DIF_BPF_COEFF45 (DIRECT_IF_REVB_BASE + 0x00000050) 325e0d3bafdSSri Deevi /*****************************************************************************/ 326e0d3bafdSSri Deevi /* Reserved [31:24] */ 3276e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_4 0x00ff0000 328e0d3bafdSSri Deevi /* Reserved [15:8] */ 3296e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_5 0x000000ff 330e0d3bafdSSri Deevi 331e0d3bafdSSri Deevi /*****************************************************************************/ 3326e4f574bSSri Deevi #define DIF_BPF_COEFF67 (DIRECT_IF_REVB_BASE + 0x00000054) 333e0d3bafdSSri Deevi /*****************************************************************************/ 334e0d3bafdSSri Deevi /* Reserved [31:25] */ 3356e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_6 0x01ff0000 336e0d3bafdSSri Deevi /* Reserved [15:9] */ 3376e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_7 0x000001ff 338e0d3bafdSSri Deevi 339e0d3bafdSSri Deevi /*****************************************************************************/ 3406e4f574bSSri Deevi #define DIF_BPF_COEFF89 (DIRECT_IF_REVB_BASE + 0x00000058) 341e0d3bafdSSri Deevi /*****************************************************************************/ 342e0d3bafdSSri Deevi /* Reserved [31:26] */ 3436e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_8 0x03ff0000 344e0d3bafdSSri Deevi /* Reserved [15:10] */ 3456e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_9 0x000003ff 346e0d3bafdSSri Deevi 347e0d3bafdSSri Deevi /*****************************************************************************/ 3486e4f574bSSri Deevi #define DIF_BPF_COEFF1011 (DIRECT_IF_REVB_BASE + 0x0000005c) 349e0d3bafdSSri Deevi /*****************************************************************************/ 350e0d3bafdSSri Deevi /* Reserved [31:27] */ 3516e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_10 0x07ff0000 352e0d3bafdSSri Deevi /* Reserved [15:11] */ 3536e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_11 0x000007ff 354e0d3bafdSSri Deevi 355e0d3bafdSSri Deevi /*****************************************************************************/ 3566e4f574bSSri Deevi #define DIF_BPF_COEFF1213 (DIRECT_IF_REVB_BASE + 0x00000060) 357e0d3bafdSSri Deevi /*****************************************************************************/ 358e0d3bafdSSri Deevi /* Reserved [31:27] */ 3596e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_12 0x07ff0000 360e0d3bafdSSri Deevi /* Reserved [15:12] */ 3616e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_13 0x00000fff 362e0d3bafdSSri Deevi 363e0d3bafdSSri Deevi /*****************************************************************************/ 3646e4f574bSSri Deevi #define DIF_BPF_COEFF1415 (DIRECT_IF_REVB_BASE + 0x00000064) 365e0d3bafdSSri Deevi /*****************************************************************************/ 366e0d3bafdSSri Deevi /* Reserved [31:28] */ 3676e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_14 0x0fff0000 368e0d3bafdSSri Deevi /* Reserved [15:12] */ 3696e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_15 0x00000fff 370e0d3bafdSSri Deevi 371e0d3bafdSSri Deevi /*****************************************************************************/ 3726e4f574bSSri Deevi #define DIF_BPF_COEFF1617 (DIRECT_IF_REVB_BASE + 0x00000068) 373e0d3bafdSSri Deevi /*****************************************************************************/ 374e0d3bafdSSri Deevi /* Reserved [31:29] */ 3756e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_16 0x1fff0000 376e0d3bafdSSri Deevi /* Reserved [15:13] */ 3776e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_17 0x00001fff 378e0d3bafdSSri Deevi 379e0d3bafdSSri Deevi /*****************************************************************************/ 3806e4f574bSSri Deevi #define DIF_BPF_COEFF1819 (DIRECT_IF_REVB_BASE + 0x0000006c) 381e0d3bafdSSri Deevi /*****************************************************************************/ 382e0d3bafdSSri Deevi /* Reserved [31:29] */ 3836e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_18 0x1fff0000 384e0d3bafdSSri Deevi /* Reserved [15:13] */ 3856e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_19 0x00001fff 386e0d3bafdSSri Deevi 387e0d3bafdSSri Deevi /*****************************************************************************/ 3886e4f574bSSri Deevi #define DIF_BPF_COEFF2021 (DIRECT_IF_REVB_BASE + 0x00000070) 389e0d3bafdSSri Deevi /*****************************************************************************/ 390e0d3bafdSSri Deevi /* Reserved [31:29] */ 3916e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_20 0x1fff0000 392e0d3bafdSSri Deevi /* Reserved [15:14] */ 3936e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_21 0x00003fff 394e0d3bafdSSri Deevi 395e0d3bafdSSri Deevi /*****************************************************************************/ 3966e4f574bSSri Deevi #define DIF_BPF_COEFF2223 (DIRECT_IF_REVB_BASE + 0x00000074) 397e0d3bafdSSri Deevi /*****************************************************************************/ 398e0d3bafdSSri Deevi /* Reserved [31:30] */ 3996e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_22 0x3fff0000 400e0d3bafdSSri Deevi /* Reserved [15:14] */ 4016e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_23 0x00003fff 402e0d3bafdSSri Deevi 403e0d3bafdSSri Deevi /*****************************************************************************/ 4046e4f574bSSri Deevi #define DIF_BPF_COEFF2425 (DIRECT_IF_REVB_BASE + 0x00000078) 405e0d3bafdSSri Deevi /*****************************************************************************/ 406e0d3bafdSSri Deevi /* Reserved [31:30] */ 4076e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_24 0x3fff0000 408e0d3bafdSSri Deevi /* Reserved [15:14] */ 4096e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_25 0x00003fff 410e0d3bafdSSri Deevi 411e0d3bafdSSri Deevi /*****************************************************************************/ 4126e4f574bSSri Deevi #define DIF_BPF_COEFF2627 (DIRECT_IF_REVB_BASE + 0x0000007c) 413e0d3bafdSSri Deevi /*****************************************************************************/ 414e0d3bafdSSri Deevi /* Reserved [31:30] */ 4156e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_26 0x3fff0000 416e0d3bafdSSri Deevi /* Reserved [15:14] */ 4176e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_27 0x00003fff 418e0d3bafdSSri Deevi 419e0d3bafdSSri Deevi /*****************************************************************************/ 4206e4f574bSSri Deevi #define DIF_BPF_COEFF2829 (DIRECT_IF_REVB_BASE + 0x00000080) 421e0d3bafdSSri Deevi /*****************************************************************************/ 422e0d3bafdSSri Deevi /* Reserved [31:30] */ 4236e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_28 0x3fff0000 424e0d3bafdSSri Deevi /* Reserved [15:14] */ 4256e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_29 0x00003fff 426e0d3bafdSSri Deevi 427e0d3bafdSSri Deevi /*****************************************************************************/ 4286e4f574bSSri Deevi #define DIF_BPF_COEFF3031 (DIRECT_IF_REVB_BASE + 0x00000084) 429e0d3bafdSSri Deevi /*****************************************************************************/ 430e0d3bafdSSri Deevi /* Reserved [31:30] */ 4316e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_30 0x3fff0000 432e0d3bafdSSri Deevi /* Reserved [15:14] */ 4336e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_31 0x00003fff 434e0d3bafdSSri Deevi 435e0d3bafdSSri Deevi /*****************************************************************************/ 4366e4f574bSSri Deevi #define DIF_BPF_COEFF3233 (DIRECT_IF_REVB_BASE + 0x00000088) 437e0d3bafdSSri Deevi /*****************************************************************************/ 438e0d3bafdSSri Deevi /* Reserved [31:30] */ 4396e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_32 0x3fff0000 440e0d3bafdSSri Deevi /* Reserved [15:14] */ 4416e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_33 0x00003fff 442e0d3bafdSSri Deevi 443e0d3bafdSSri Deevi /*****************************************************************************/ 4446e4f574bSSri Deevi #define DIF_BPF_COEFF3435 (DIRECT_IF_REVB_BASE + 0x0000008c) 445e0d3bafdSSri Deevi /*****************************************************************************/ 446e0d3bafdSSri Deevi /* Reserved [31:30] */ 4476e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_34 0x3fff0000 448e0d3bafdSSri Deevi /* Reserved [15:14] */ 4496e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_35 0x00003fff 450e0d3bafdSSri Deevi 451e0d3bafdSSri Deevi /*****************************************************************************/ 4526e4f574bSSri Deevi #define DIF_BPF_COEFF36 (DIRECT_IF_REVB_BASE + 0x00000090) 453e0d3bafdSSri Deevi /*****************************************************************************/ 454e0d3bafdSSri Deevi /* Reserved [31:30] */ 4556e4f574bSSri Deevi #define FLD_DIF_BPF_COEFF_36 0x3fff0000 456e0d3bafdSSri Deevi /* Reserved [15:0] */ 457e0d3bafdSSri Deevi 458e0d3bafdSSri Deevi /*****************************************************************************/ 4596e4f574bSSri Deevi #define DIF_RPT_VARIANCE (DIRECT_IF_REVB_BASE + 0x00000094) 460e0d3bafdSSri Deevi /*****************************************************************************/ 461e0d3bafdSSri Deevi /* Reserved [31:20] */ 4626e4f574bSSri Deevi #define FLD_DIF_RPT_VARIANCE 0x000fffff 463e0d3bafdSSri Deevi 464e0d3bafdSSri Deevi /*****************************************************************************/ 4656e4f574bSSri Deevi #define DIF_SOFT_RST_CTRL_REVB (DIRECT_IF_REVB_BASE + 0x00000098) 466e0d3bafdSSri Deevi /*****************************************************************************/ 467e0d3bafdSSri Deevi /* Reserved [31:8] */ 468e0d3bafdSSri Deevi #define FLD_DIF_DIF_SOFT_RST 0x00000080 469e0d3bafdSSri Deevi #define FLD_DIF_DIF_REG_RST_MSK 0x00000040 470e0d3bafdSSri Deevi #define FLD_DIF_AGC_RST_MSK 0x00000020 471e0d3bafdSSri Deevi #define FLD_DIF_CMP_RST_MSK 0x00000010 472e0d3bafdSSri Deevi #define FLD_DIF_AVS_RST_MSK 0x00000008 473e0d3bafdSSri Deevi #define FLD_DIF_NYQ_RST_MSK 0x00000004 474e0d3bafdSSri Deevi #define FLD_DIF_DIF_SRC_RST_MSK 0x00000002 475e0d3bafdSSri Deevi #define FLD_DIF_PLL_RST_MSK 0x00000001 476e0d3bafdSSri Deevi 477e0d3bafdSSri Deevi /*****************************************************************************/ 4786e4f574bSSri Deevi #define DIF_PLL_FREQ_ERR (DIRECT_IF_REVB_BASE + 0x0000009c) 479e0d3bafdSSri Deevi /*****************************************************************************/ 480e0d3bafdSSri Deevi /* Reserved [31:25] */ 4816e4f574bSSri Deevi #define FLD_DIF_CTL_IP 0x01ffffff 482e0d3bafdSSri Deevi 483e0d3bafdSSri Deevi #endif 484