1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Renesas R-Car MIPI CSI-2 Receiver 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/interrupt.h> 10 #include <linux/io.h> 11 #include <linux/math64.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_graph.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/reset.h> 18 #include <linux/sys_soc.h> 19 #include <linux/units.h> 20 21 #include <media/mipi-csi2.h> 22 #include <media/v4l2-ctrls.h> 23 #include <media/v4l2-device.h> 24 #include <media/v4l2-fwnode.h> 25 #include <media/v4l2-mc.h> 26 #include <media/v4l2-subdev.h> 27 28 struct rcar_csi2; 29 30 /* Register offsets and bits */ 31 32 /* Control Timing Select */ 33 #define TREF_REG 0x00 34 #define TREF_TREF BIT(0) 35 36 /* Software Reset */ 37 #define SRST_REG 0x04 38 #define SRST_SRST BIT(0) 39 40 /* PHY Operation Control */ 41 #define PHYCNT_REG 0x08 42 #define PHYCNT_SHUTDOWNZ BIT(17) 43 #define PHYCNT_RSTZ BIT(16) 44 #define PHYCNT_ENABLECLK BIT(4) 45 #define PHYCNT_ENABLE_3 BIT(3) 46 #define PHYCNT_ENABLE_2 BIT(2) 47 #define PHYCNT_ENABLE_1 BIT(1) 48 #define PHYCNT_ENABLE_0 BIT(0) 49 50 /* Checksum Control */ 51 #define CHKSUM_REG 0x0c 52 #define CHKSUM_ECC_EN BIT(1) 53 #define CHKSUM_CRC_EN BIT(0) 54 55 /* 56 * Channel Data Type Select 57 * VCDT[0-15]: Channel 0 VCDT[16-31]: Channel 1 58 * VCDT2[0-15]: Channel 2 VCDT2[16-31]: Channel 3 59 */ 60 #define VCDT_REG 0x10 61 #define VCDT2_REG 0x14 62 #define VCDT_VCDTN_EN BIT(15) 63 #define VCDT_SEL_VC(n) (((n) & 0x3) << 8) 64 #define VCDT_SEL_DTN_ON BIT(6) 65 #define VCDT_SEL_DT(n) (((n) & 0x3f) << 0) 66 67 /* Frame Data Type Select */ 68 #define FRDT_REG 0x18 69 70 /* Field Detection Control */ 71 #define FLD_REG 0x1c 72 #define FLD_FLD_NUM(n) (((n) & 0xff) << 16) 73 #define FLD_DET_SEL(n) (((n) & 0x3) << 4) 74 #define FLD_FLD_EN4 BIT(3) 75 #define FLD_FLD_EN3 BIT(2) 76 #define FLD_FLD_EN2 BIT(1) 77 #define FLD_FLD_EN BIT(0) 78 79 /* Automatic Standby Control */ 80 #define ASTBY_REG 0x20 81 82 /* Long Data Type Setting 0 */ 83 #define LNGDT0_REG 0x28 84 85 /* Long Data Type Setting 1 */ 86 #define LNGDT1_REG 0x2c 87 88 /* Interrupt Enable */ 89 #define INTEN_REG 0x30 90 #define INTEN_INT_AFIFO_OF BIT(27) 91 #define INTEN_INT_ERRSOTHS BIT(4) 92 #define INTEN_INT_ERRSOTSYNCHS BIT(3) 93 94 /* Interrupt Source Mask */ 95 #define INTCLOSE_REG 0x34 96 97 /* Interrupt Status Monitor */ 98 #define INTSTATE_REG 0x38 99 #define INTSTATE_INT_ULPS_START BIT(7) 100 #define INTSTATE_INT_ULPS_END BIT(6) 101 102 /* Interrupt Error Status Monitor */ 103 #define INTERRSTATE_REG 0x3c 104 105 /* Short Packet Data */ 106 #define SHPDAT_REG 0x40 107 108 /* Short Packet Count */ 109 #define SHPCNT_REG 0x44 110 111 /* LINK Operation Control */ 112 #define LINKCNT_REG 0x48 113 #define LINKCNT_MONITOR_EN BIT(31) 114 #define LINKCNT_REG_MONI_PACT_EN BIT(25) 115 #define LINKCNT_ICLK_NONSTOP BIT(24) 116 117 /* Lane Swap */ 118 #define LSWAP_REG 0x4c 119 #define LSWAP_L3SEL(n) (((n) & 0x3) << 6) 120 #define LSWAP_L2SEL(n) (((n) & 0x3) << 4) 121 #define LSWAP_L1SEL(n) (((n) & 0x3) << 2) 122 #define LSWAP_L0SEL(n) (((n) & 0x3) << 0) 123 124 /* PHY Test Interface Write Register */ 125 #define PHTW_REG 0x50 126 #define PHTW_DWEN BIT(24) 127 #define PHTW_TESTDIN_DATA(n) (((n & 0xff)) << 16) 128 #define PHTW_CWEN BIT(8) 129 #define PHTW_TESTDIN_CODE(n) ((n & 0xff)) 130 131 #define PHYFRX_REG 0x64 132 #define PHYFRX_FORCERX_MODE_3 BIT(3) 133 #define PHYFRX_FORCERX_MODE_2 BIT(2) 134 #define PHYFRX_FORCERX_MODE_1 BIT(1) 135 #define PHYFRX_FORCERX_MODE_0 BIT(0) 136 137 /* V4H BASE registers */ 138 #define V4H_N_LANES_REG 0x0004 139 #define V4H_CSI2_RESETN_REG 0x0008 140 141 #define V4H_PHY_MODE_REG 0x001c 142 #define V4H_PHY_MODE_DPHY 0 143 #define V4H_PHY_MODE_CPHY 1 144 145 #define V4H_PHY_SHUTDOWNZ_REG 0x0040 146 #define V4H_DPHY_RSTZ_REG 0x0044 147 #define V4H_FLDC_REG 0x0804 148 #define V4H_FLDD_REG 0x0808 149 #define V4H_IDIC_REG 0x0810 150 151 #define V4H_PHY_EN_REG 0x2000 152 #define V4H_PHY_EN_ENABLE_3 BIT(7) 153 #define V4H_PHY_EN_ENABLE_2 BIT(6) 154 #define V4H_PHY_EN_ENABLE_1 BIT(5) 155 #define V4H_PHY_EN_ENABLE_0 BIT(4) 156 #define V4H_PHY_EN_ENABLE_CLK BIT(0) 157 158 #define V4H_ST_PHYST_REG 0x2814 159 #define V4H_ST_PHYST_ST_PHY_READY BIT(31) 160 #define V4H_ST_PHYST_ST_STOPSTATE_3 BIT(3) 161 #define V4H_ST_PHYST_ST_STOPSTATE_2 BIT(2) 162 #define V4H_ST_PHYST_ST_STOPSTATE_1 BIT(1) 163 #define V4H_ST_PHYST_ST_STOPSTATE_0 BIT(0) 164 165 /* V4H PPI registers */ 166 #define V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(n) (0x21800 + ((n) * 2)) /* n = 0 - 9 */ 167 #define V4H_PPI_STARTUP_RW_COMMON_STARTUP_1_1_REG 0x21822 168 #define V4H_PPI_CALIBCTRL_RW_COMMON_BG_0_REG 0x2184c 169 #define V4H_PPI_RW_LPDCOCAL_TIMEBASE_REG 0x21c02 170 #define V4H_PPI_RW_LPDCOCAL_NREF_REG 0x21c04 171 #define V4H_PPI_RW_LPDCOCAL_NREF_RANGE_REG 0x21c06 172 #define V4H_PPI_RW_LPDCOCAL_TWAIT_CONFIG_REG 0x21c0a 173 #define V4H_PPI_RW_LPDCOCAL_VT_CONFIG_REG 0x21c0c 174 #define V4H_PPI_RW_LPDCOCAL_COARSE_CFG_REG 0x21c10 175 #define V4H_PPI_RW_COMMON_CFG_REG 0x21c6c 176 #define V4H_PPI_RW_TERMCAL_CFG_0_REG 0x21c80 177 #define V4H_PPI_RW_OFFSETCAL_CFG_0_REG 0x21ca0 178 179 /* V4H CORE registers */ 180 #define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_REG(n) (0x22040 + ((n) * 2)) /* n = 0 - 15 */ 181 #define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_REG(n) (0x22440 + ((n) * 2)) /* n = 0 - 15 */ 182 #define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_REG(n) (0x22840 + ((n) * 2)) /* n = 0 - 15 */ 183 #define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_REG(n) (0x22c40 + ((n) * 2)) /* n = 0 - 15 */ 184 #define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_REG(n) (0x23040 + ((n) * 2)) /* n = 0 - 15 */ 185 #define V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(n) (0x23840 + ((n) * 2)) /* n = 0 - 11 */ 186 #define V4H_CORE_DIG_RW_COMMON_REG(n) (0x23880 + ((n) * 2)) /* n = 0 - 15 */ 187 #define V4H_CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_REG(n) (0x239e0 + ((n) * 2)) /* n = 0 - 3 */ 188 #define V4H_CORE_DIG_CLANE_1_RW_HS_TX_6_REG 0x2a60c 189 190 /* V4H C-PHY */ 191 #define V4H_CORE_DIG_RW_TRIO0_REG(n) (0x22100 + ((n) * 2)) /* n = 0 - 3 */ 192 #define V4H_CORE_DIG_RW_TRIO1_REG(n) (0x22500 + ((n) * 2)) /* n = 0 - 3 */ 193 #define V4H_CORE_DIG_RW_TRIO2_REG(n) (0x22900 + ((n) * 2)) /* n = 0 - 3 */ 194 #define V4H_CORE_DIG_CLANE_0_RW_CFG_0_REG 0x2a000 195 #define V4H_CORE_DIG_CLANE_0_RW_LP_0_REG 0x2a080 196 #define V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(n) (0x2a100 + ((n) * 2)) /* n = 0 - 6 */ 197 #define V4H_CORE_DIG_CLANE_1_RW_CFG_0_REG 0x2a400 198 #define V4H_CORE_DIG_CLANE_1_RW_LP_0_REG 0x2a480 199 #define V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(n) (0x2a500 + ((n) * 2)) /* n = 0 - 6 */ 200 #define V4H_CORE_DIG_CLANE_2_RW_CFG_0_REG 0x2a800 201 #define V4H_CORE_DIG_CLANE_2_RW_LP_0_REG 0x2a880 202 #define V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(n) (0x2a900 + ((n) * 2)) /* n = 0 - 6 */ 203 204 struct rcsi2_cphy_setting { 205 u16 msps; 206 u16 rx2; 207 u16 trio0; 208 u16 trio1; 209 u16 trio2; 210 u16 lane27; 211 u16 lane29; 212 }; 213 214 static const struct rcsi2_cphy_setting cphy_setting_table_r8a779g0[] = { 215 { .msps = 80, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0134, .trio2 = 0x6a, .lane27 = 0x0000, .lane29 = 0x0a24 }, 216 { .msps = 100, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x00f5, .trio2 = 0x55, .lane27 = 0x0000, .lane29 = 0x0a24 }, 217 { .msps = 200, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0077, .trio2 = 0x2b, .lane27 = 0x0000, .lane29 = 0x0a44 }, 218 { .msps = 300, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x004d, .trio2 = 0x1d, .lane27 = 0x0000, .lane29 = 0x0a44 }, 219 { .msps = 400, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0038, .trio2 = 0x16, .lane27 = 0x0000, .lane29 = 0x0a64 }, 220 { .msps = 500, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x002b, .trio2 = 0x12, .lane27 = 0x0000, .lane29 = 0x0a64 }, 221 { .msps = 600, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0023, .trio2 = 0x0f, .lane27 = 0x0000, .lane29 = 0x0a64 }, 222 { .msps = 700, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x001d, .trio2 = 0x0d, .lane27 = 0x0000, .lane29 = 0x0a84 }, 223 { .msps = 800, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0018, .trio2 = 0x0c, .lane27 = 0x0000, .lane29 = 0x0a84 }, 224 { .msps = 900, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0015, .trio2 = 0x0b, .lane27 = 0x0000, .lane29 = 0x0a84 }, 225 { .msps = 1000, .rx2 = 0x3e, .trio0 = 0x024a, .trio1 = 0x0012, .trio2 = 0x0a, .lane27 = 0x0400, .lane29 = 0x0a84 }, 226 { .msps = 1100, .rx2 = 0x44, .trio0 = 0x024a, .trio1 = 0x000f, .trio2 = 0x09, .lane27 = 0x0800, .lane29 = 0x0a84 }, 227 { .msps = 1200, .rx2 = 0x4a, .trio0 = 0x024a, .trio1 = 0x000e, .trio2 = 0x08, .lane27 = 0x0c00, .lane29 = 0x0a84 }, 228 { .msps = 1300, .rx2 = 0x51, .trio0 = 0x024a, .trio1 = 0x000c, .trio2 = 0x08, .lane27 = 0x0c00, .lane29 = 0x0aa4 }, 229 { .msps = 1400, .rx2 = 0x57, .trio0 = 0x024a, .trio1 = 0x000b, .trio2 = 0x07, .lane27 = 0x1000, .lane29 = 0x0aa4 }, 230 { .msps = 1500, .rx2 = 0x5d, .trio0 = 0x044a, .trio1 = 0x0009, .trio2 = 0x07, .lane27 = 0x1000, .lane29 = 0x0aa4 }, 231 { .msps = 1600, .rx2 = 0x63, .trio0 = 0x044a, .trio1 = 0x0008, .trio2 = 0x07, .lane27 = 0x1400, .lane29 = 0x0aa4 }, 232 { .msps = 1700, .rx2 = 0x6a, .trio0 = 0x044a, .trio1 = 0x0007, .trio2 = 0x06, .lane27 = 0x1400, .lane29 = 0x0aa4 }, 233 { .msps = 1800, .rx2 = 0x70, .trio0 = 0x044a, .trio1 = 0x0007, .trio2 = 0x06, .lane27 = 0x1400, .lane29 = 0x0aa4 }, 234 { .msps = 1900, .rx2 = 0x76, .trio0 = 0x044a, .trio1 = 0x0006, .trio2 = 0x06, .lane27 = 0x1400, .lane29 = 0x0aa4 }, 235 { .msps = 2000, .rx2 = 0x7c, .trio0 = 0x044a, .trio1 = 0x0005, .trio2 = 0x06, .lane27 = 0x1800, .lane29 = 0x0aa4 }, 236 { .msps = 2100, .rx2 = 0x83, .trio0 = 0x044a, .trio1 = 0x0005, .trio2 = 0x05, .lane27 = 0x1800, .lane29 = 0x0aa4 }, 237 { .msps = 2200, .rx2 = 0x89, .trio0 = 0x064a, .trio1 = 0x0004, .trio2 = 0x05, .lane27 = 0x1800, .lane29 = 0x0aa4 }, 238 { .msps = 2300, .rx2 = 0x8f, .trio0 = 0x064a, .trio1 = 0x0003, .trio2 = 0x05, .lane27 = 0x1800, .lane29 = 0x0aa4 }, 239 { .msps = 2400, .rx2 = 0x95, .trio0 = 0x064a, .trio1 = 0x0003, .trio2 = 0x05, .lane27 = 0x1800, .lane29 = 0x0aa4 }, 240 { .msps = 2500, .rx2 = 0x9c, .trio0 = 0x064a, .trio1 = 0x0003, .trio2 = 0x05, .lane27 = 0x1c00, .lane29 = 0x0aa4 }, 241 { .msps = 2600, .rx2 = 0xa2, .trio0 = 0x064a, .trio1 = 0x0002, .trio2 = 0x05, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 242 { .msps = 2700, .rx2 = 0xa8, .trio0 = 0x064a, .trio1 = 0x0002, .trio2 = 0x05, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 243 { .msps = 2800, .rx2 = 0xae, .trio0 = 0x064a, .trio1 = 0x0002, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 244 { .msps = 2900, .rx2 = 0xb5, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 245 { .msps = 3000, .rx2 = 0xbb, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 246 { .msps = 3100, .rx2 = 0xc1, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 247 { .msps = 3200, .rx2 = 0xc7, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 248 { .msps = 3300, .rx2 = 0xce, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 249 { .msps = 3400, .rx2 = 0xd4, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 250 { .msps = 3500, .rx2 = 0xda, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 }, 251 { /* sentinel */ }, 252 }; 253 254 /* V4M registers */ 255 #define V4M_OVR1_REG 0x0848 256 #define V4M_OVR1_FORCERXMODE_3 BIT(12) 257 #define V4M_OVR1_FORCERXMODE_2 BIT(11) 258 #define V4M_OVR1_FORCERXMODE_1 BIT(10) 259 #define V4M_OVR1_FORCERXMODE_0 BIT(9) 260 261 #define V4M_FRXM_REG 0x2004 262 #define V4M_FRXM_FORCERXMODE_3 BIT(3) 263 #define V4M_FRXM_FORCERXMODE_2 BIT(2) 264 #define V4M_FRXM_FORCERXMODE_1 BIT(1) 265 #define V4M_FRXM_FORCERXMODE_0 BIT(0) 266 267 #define V4M_PHYPLL_REG 0x02050 268 #define V4M_CSI0CLKFCPR_REG 0x02054 269 #define V4M_PHTW_REG 0x02060 270 #define V4M_PHTR_REG 0x02064 271 #define V4M_PHTC_REG 0x02068 272 273 struct phtw_value { 274 u8 data; 275 u8 code; 276 }; 277 278 struct rcsi2_mbps_info { 279 u16 mbps; 280 u8 reg; 281 u16 osc_freq; /* V4M */ 282 }; 283 284 static const struct rcsi2_mbps_info phtw_mbps_v3u[] = { 285 { .mbps = 1500, .reg = 0xcc }, 286 { .mbps = 1550, .reg = 0x1d }, 287 { .mbps = 1600, .reg = 0x27 }, 288 { .mbps = 1650, .reg = 0x30 }, 289 { .mbps = 1700, .reg = 0x39 }, 290 { .mbps = 1750, .reg = 0x42 }, 291 { .mbps = 1800, .reg = 0x4b }, 292 { .mbps = 1850, .reg = 0x55 }, 293 { .mbps = 1900, .reg = 0x5e }, 294 { .mbps = 1950, .reg = 0x67 }, 295 { .mbps = 2000, .reg = 0x71 }, 296 { .mbps = 2050, .reg = 0x79 }, 297 { .mbps = 2100, .reg = 0x83 }, 298 { .mbps = 2150, .reg = 0x8c }, 299 { .mbps = 2200, .reg = 0x95 }, 300 { .mbps = 2250, .reg = 0x9e }, 301 { .mbps = 2300, .reg = 0xa7 }, 302 { .mbps = 2350, .reg = 0xb0 }, 303 { .mbps = 2400, .reg = 0xba }, 304 { .mbps = 2450, .reg = 0xc3 }, 305 { .mbps = 2500, .reg = 0xcc }, 306 { /* sentinel */ }, 307 }; 308 309 static const struct rcsi2_mbps_info phtw_mbps_h3_v3h_m3n[] = { 310 { .mbps = 80, .reg = 0x86 }, 311 { .mbps = 90, .reg = 0x86 }, 312 { .mbps = 100, .reg = 0x87 }, 313 { .mbps = 110, .reg = 0x87 }, 314 { .mbps = 120, .reg = 0x88 }, 315 { .mbps = 130, .reg = 0x88 }, 316 { .mbps = 140, .reg = 0x89 }, 317 { .mbps = 150, .reg = 0x89 }, 318 { .mbps = 160, .reg = 0x8a }, 319 { .mbps = 170, .reg = 0x8a }, 320 { .mbps = 180, .reg = 0x8b }, 321 { .mbps = 190, .reg = 0x8b }, 322 { .mbps = 205, .reg = 0x8c }, 323 { .mbps = 220, .reg = 0x8d }, 324 { .mbps = 235, .reg = 0x8e }, 325 { .mbps = 250, .reg = 0x8e }, 326 { /* sentinel */ }, 327 }; 328 329 static const struct rcsi2_mbps_info phtw_mbps_v3m_e3[] = { 330 { .mbps = 80, .reg = 0x00 }, 331 { .mbps = 90, .reg = 0x20 }, 332 { .mbps = 100, .reg = 0x40 }, 333 { .mbps = 110, .reg = 0x02 }, 334 { .mbps = 130, .reg = 0x22 }, 335 { .mbps = 140, .reg = 0x42 }, 336 { .mbps = 150, .reg = 0x04 }, 337 { .mbps = 170, .reg = 0x24 }, 338 { .mbps = 180, .reg = 0x44 }, 339 { .mbps = 200, .reg = 0x06 }, 340 { .mbps = 220, .reg = 0x26 }, 341 { .mbps = 240, .reg = 0x46 }, 342 { .mbps = 250, .reg = 0x08 }, 343 { .mbps = 270, .reg = 0x28 }, 344 { .mbps = 300, .reg = 0x0a }, 345 { .mbps = 330, .reg = 0x2a }, 346 { .mbps = 360, .reg = 0x4a }, 347 { .mbps = 400, .reg = 0x0c }, 348 { .mbps = 450, .reg = 0x2c }, 349 { .mbps = 500, .reg = 0x0e }, 350 { .mbps = 550, .reg = 0x2e }, 351 { .mbps = 600, .reg = 0x10 }, 352 { .mbps = 650, .reg = 0x30 }, 353 { .mbps = 700, .reg = 0x12 }, 354 { .mbps = 750, .reg = 0x32 }, 355 { .mbps = 800, .reg = 0x52 }, 356 { .mbps = 850, .reg = 0x72 }, 357 { .mbps = 900, .reg = 0x14 }, 358 { .mbps = 950, .reg = 0x34 }, 359 { .mbps = 1000, .reg = 0x54 }, 360 { .mbps = 1050, .reg = 0x74 }, 361 { .mbps = 1125, .reg = 0x16 }, 362 { /* sentinel */ }, 363 }; 364 365 /* PHY Test Interface Clear */ 366 #define PHTC_REG 0x58 367 #define PHTC_TESTCLR BIT(0) 368 369 /* PHY Frequency Control */ 370 #define PHYPLL_REG 0x68 371 #define PHYPLL_HSFREQRANGE(n) ((n) << 16) 372 373 static const struct rcsi2_mbps_info hsfreqrange_v3u[] = { 374 { .mbps = 80, .reg = 0x00 }, 375 { .mbps = 90, .reg = 0x10 }, 376 { .mbps = 100, .reg = 0x20 }, 377 { .mbps = 110, .reg = 0x30 }, 378 { .mbps = 120, .reg = 0x01 }, 379 { .mbps = 130, .reg = 0x11 }, 380 { .mbps = 140, .reg = 0x21 }, 381 { .mbps = 150, .reg = 0x31 }, 382 { .mbps = 160, .reg = 0x02 }, 383 { .mbps = 170, .reg = 0x12 }, 384 { .mbps = 180, .reg = 0x22 }, 385 { .mbps = 190, .reg = 0x32 }, 386 { .mbps = 205, .reg = 0x03 }, 387 { .mbps = 220, .reg = 0x13 }, 388 { .mbps = 235, .reg = 0x23 }, 389 { .mbps = 250, .reg = 0x33 }, 390 { .mbps = 275, .reg = 0x04 }, 391 { .mbps = 300, .reg = 0x14 }, 392 { .mbps = 325, .reg = 0x25 }, 393 { .mbps = 350, .reg = 0x35 }, 394 { .mbps = 400, .reg = 0x05 }, 395 { .mbps = 450, .reg = 0x16 }, 396 { .mbps = 500, .reg = 0x26 }, 397 { .mbps = 550, .reg = 0x37 }, 398 { .mbps = 600, .reg = 0x07 }, 399 { .mbps = 650, .reg = 0x18 }, 400 { .mbps = 700, .reg = 0x28 }, 401 { .mbps = 750, .reg = 0x39 }, 402 { .mbps = 800, .reg = 0x09 }, 403 { .mbps = 850, .reg = 0x19 }, 404 { .mbps = 900, .reg = 0x29 }, 405 { .mbps = 950, .reg = 0x3a }, 406 { .mbps = 1000, .reg = 0x0a }, 407 { .mbps = 1050, .reg = 0x1a }, 408 { .mbps = 1100, .reg = 0x2a }, 409 { .mbps = 1150, .reg = 0x3b }, 410 { .mbps = 1200, .reg = 0x0b }, 411 { .mbps = 1250, .reg = 0x1b }, 412 { .mbps = 1300, .reg = 0x2b }, 413 { .mbps = 1350, .reg = 0x3c }, 414 { .mbps = 1400, .reg = 0x0c }, 415 { .mbps = 1450, .reg = 0x1c }, 416 { .mbps = 1500, .reg = 0x2c }, 417 { .mbps = 1550, .reg = 0x3d }, 418 { .mbps = 1600, .reg = 0x0d }, 419 { .mbps = 1650, .reg = 0x1d }, 420 { .mbps = 1700, .reg = 0x2e }, 421 { .mbps = 1750, .reg = 0x3e }, 422 { .mbps = 1800, .reg = 0x0e }, 423 { .mbps = 1850, .reg = 0x1e }, 424 { .mbps = 1900, .reg = 0x2f }, 425 { .mbps = 1950, .reg = 0x3f }, 426 { .mbps = 2000, .reg = 0x0f }, 427 { .mbps = 2050, .reg = 0x40 }, 428 { .mbps = 2100, .reg = 0x41 }, 429 { .mbps = 2150, .reg = 0x42 }, 430 { .mbps = 2200, .reg = 0x43 }, 431 { .mbps = 2300, .reg = 0x45 }, 432 { .mbps = 2350, .reg = 0x46 }, 433 { .mbps = 2400, .reg = 0x47 }, 434 { .mbps = 2450, .reg = 0x48 }, 435 { .mbps = 2500, .reg = 0x49 }, 436 { /* sentinel */ }, 437 }; 438 439 static const struct rcsi2_mbps_info hsfreqrange_h3_v3h_m3n[] = { 440 { .mbps = 80, .reg = 0x00 }, 441 { .mbps = 90, .reg = 0x10 }, 442 { .mbps = 100, .reg = 0x20 }, 443 { .mbps = 110, .reg = 0x30 }, 444 { .mbps = 120, .reg = 0x01 }, 445 { .mbps = 130, .reg = 0x11 }, 446 { .mbps = 140, .reg = 0x21 }, 447 { .mbps = 150, .reg = 0x31 }, 448 { .mbps = 160, .reg = 0x02 }, 449 { .mbps = 170, .reg = 0x12 }, 450 { .mbps = 180, .reg = 0x22 }, 451 { .mbps = 190, .reg = 0x32 }, 452 { .mbps = 205, .reg = 0x03 }, 453 { .mbps = 220, .reg = 0x13 }, 454 { .mbps = 235, .reg = 0x23 }, 455 { .mbps = 250, .reg = 0x33 }, 456 { .mbps = 275, .reg = 0x04 }, 457 { .mbps = 300, .reg = 0x14 }, 458 { .mbps = 325, .reg = 0x25 }, 459 { .mbps = 350, .reg = 0x35 }, 460 { .mbps = 400, .reg = 0x05 }, 461 { .mbps = 450, .reg = 0x16 }, 462 { .mbps = 500, .reg = 0x26 }, 463 { .mbps = 550, .reg = 0x37 }, 464 { .mbps = 600, .reg = 0x07 }, 465 { .mbps = 650, .reg = 0x18 }, 466 { .mbps = 700, .reg = 0x28 }, 467 { .mbps = 750, .reg = 0x39 }, 468 { .mbps = 800, .reg = 0x09 }, 469 { .mbps = 850, .reg = 0x19 }, 470 { .mbps = 900, .reg = 0x29 }, 471 { .mbps = 950, .reg = 0x3a }, 472 { .mbps = 1000, .reg = 0x0a }, 473 { .mbps = 1050, .reg = 0x1a }, 474 { .mbps = 1100, .reg = 0x2a }, 475 { .mbps = 1150, .reg = 0x3b }, 476 { .mbps = 1200, .reg = 0x0b }, 477 { .mbps = 1250, .reg = 0x1b }, 478 { .mbps = 1300, .reg = 0x2b }, 479 { .mbps = 1350, .reg = 0x3c }, 480 { .mbps = 1400, .reg = 0x0c }, 481 { .mbps = 1450, .reg = 0x1c }, 482 { .mbps = 1500, .reg = 0x2c }, 483 { /* sentinel */ }, 484 }; 485 486 static const struct rcsi2_mbps_info hsfreqrange_m3w[] = { 487 { .mbps = 80, .reg = 0x00 }, 488 { .mbps = 90, .reg = 0x10 }, 489 { .mbps = 100, .reg = 0x20 }, 490 { .mbps = 110, .reg = 0x30 }, 491 { .mbps = 120, .reg = 0x01 }, 492 { .mbps = 130, .reg = 0x11 }, 493 { .mbps = 140, .reg = 0x21 }, 494 { .mbps = 150, .reg = 0x31 }, 495 { .mbps = 160, .reg = 0x02 }, 496 { .mbps = 170, .reg = 0x12 }, 497 { .mbps = 180, .reg = 0x22 }, 498 { .mbps = 190, .reg = 0x32 }, 499 { .mbps = 205, .reg = 0x03 }, 500 { .mbps = 220, .reg = 0x13 }, 501 { .mbps = 235, .reg = 0x23 }, 502 { .mbps = 250, .reg = 0x33 }, 503 { .mbps = 275, .reg = 0x04 }, 504 { .mbps = 300, .reg = 0x14 }, 505 { .mbps = 325, .reg = 0x05 }, 506 { .mbps = 350, .reg = 0x15 }, 507 { .mbps = 400, .reg = 0x25 }, 508 { .mbps = 450, .reg = 0x06 }, 509 { .mbps = 500, .reg = 0x16 }, 510 { .mbps = 550, .reg = 0x07 }, 511 { .mbps = 600, .reg = 0x17 }, 512 { .mbps = 650, .reg = 0x08 }, 513 { .mbps = 700, .reg = 0x18 }, 514 { .mbps = 750, .reg = 0x09 }, 515 { .mbps = 800, .reg = 0x19 }, 516 { .mbps = 850, .reg = 0x29 }, 517 { .mbps = 900, .reg = 0x39 }, 518 { .mbps = 950, .reg = 0x0a }, 519 { .mbps = 1000, .reg = 0x1a }, 520 { .mbps = 1050, .reg = 0x2a }, 521 { .mbps = 1100, .reg = 0x3a }, 522 { .mbps = 1150, .reg = 0x0b }, 523 { .mbps = 1200, .reg = 0x1b }, 524 { .mbps = 1250, .reg = 0x2b }, 525 { .mbps = 1300, .reg = 0x3b }, 526 { .mbps = 1350, .reg = 0x0c }, 527 { .mbps = 1400, .reg = 0x1c }, 528 { .mbps = 1450, .reg = 0x2c }, 529 { .mbps = 1500, .reg = 0x3c }, 530 { /* sentinel */ }, 531 }; 532 533 static const struct rcsi2_mbps_info hsfreqrange_v4m[] = { 534 { .mbps = 80, .reg = 0x00, .osc_freq = 0x01a9 }, 535 { .mbps = 90, .reg = 0x10, .osc_freq = 0x01a9 }, 536 { .mbps = 100, .reg = 0x20, .osc_freq = 0x01a9 }, 537 { .mbps = 110, .reg = 0x30, .osc_freq = 0x01a9 }, 538 { .mbps = 120, .reg = 0x01, .osc_freq = 0x01a9 }, 539 { .mbps = 130, .reg = 0x11, .osc_freq = 0x01a9 }, 540 { .mbps = 140, .reg = 0x21, .osc_freq = 0x01a9 }, 541 { .mbps = 150, .reg = 0x31, .osc_freq = 0x01a9 }, 542 { .mbps = 160, .reg = 0x02, .osc_freq = 0x01a9 }, 543 { .mbps = 170, .reg = 0x12, .osc_freq = 0x01a9 }, 544 { .mbps = 180, .reg = 0x22, .osc_freq = 0x01a9 }, 545 { .mbps = 190, .reg = 0x32, .osc_freq = 0x01a9 }, 546 { .mbps = 205, .reg = 0x03, .osc_freq = 0x01a9 }, 547 { .mbps = 220, .reg = 0x13, .osc_freq = 0x01a9 }, 548 { .mbps = 235, .reg = 0x23, .osc_freq = 0x01a9 }, 549 { .mbps = 250, .reg = 0x33, .osc_freq = 0x01a9 }, 550 { .mbps = 275, .reg = 0x04, .osc_freq = 0x01a9 }, 551 { .mbps = 300, .reg = 0x14, .osc_freq = 0x01a9 }, 552 { .mbps = 325, .reg = 0x25, .osc_freq = 0x01a9 }, 553 { .mbps = 350, .reg = 0x35, .osc_freq = 0x01a9 }, 554 { .mbps = 400, .reg = 0x05, .osc_freq = 0x01a9 }, 555 { .mbps = 450, .reg = 0x16, .osc_freq = 0x01a9 }, 556 { .mbps = 500, .reg = 0x26, .osc_freq = 0x01a9 }, 557 { .mbps = 550, .reg = 0x37, .osc_freq = 0x01a9 }, 558 { .mbps = 600, .reg = 0x07, .osc_freq = 0x01a9 }, 559 { .mbps = 650, .reg = 0x18, .osc_freq = 0x01a9 }, 560 { .mbps = 700, .reg = 0x28, .osc_freq = 0x01a9 }, 561 { .mbps = 750, .reg = 0x39, .osc_freq = 0x01a9 }, 562 { .mbps = 800, .reg = 0x09, .osc_freq = 0x01a9 }, 563 { .mbps = 850, .reg = 0x19, .osc_freq = 0x01a9 }, 564 { .mbps = 900, .reg = 0x29, .osc_freq = 0x01a9 }, 565 { .mbps = 950, .reg = 0x3a, .osc_freq = 0x01a9 }, 566 { .mbps = 1000, .reg = 0x0a, .osc_freq = 0x01a9 }, 567 { .mbps = 1050, .reg = 0x1a, .osc_freq = 0x01a9 }, 568 { .mbps = 1100, .reg = 0x2a, .osc_freq = 0x01a9 }, 569 { .mbps = 1150, .reg = 0x3b, .osc_freq = 0x01a9 }, 570 { .mbps = 1200, .reg = 0x0b, .osc_freq = 0x01a9 }, 571 { .mbps = 1250, .reg = 0x1b, .osc_freq = 0x01a9 }, 572 { .mbps = 1300, .reg = 0x2b, .osc_freq = 0x01a9 }, 573 { .mbps = 1350, .reg = 0x3c, .osc_freq = 0x01a9 }, 574 { .mbps = 1400, .reg = 0x0c, .osc_freq = 0x01a9 }, 575 { .mbps = 1450, .reg = 0x1c, .osc_freq = 0x01a9 }, 576 { .mbps = 1500, .reg = 0x2c, .osc_freq = 0x01a9 }, 577 { .mbps = 1550, .reg = 0x3d, .osc_freq = 0x0108 }, 578 { .mbps = 1600, .reg = 0x0d, .osc_freq = 0x0110 }, 579 { .mbps = 1650, .reg = 0x1d, .osc_freq = 0x0119 }, 580 { .mbps = 1700, .reg = 0x2e, .osc_freq = 0x0121 }, 581 { .mbps = 1750, .reg = 0x3e, .osc_freq = 0x012a }, 582 { .mbps = 1800, .reg = 0x0e, .osc_freq = 0x0132 }, 583 { .mbps = 1850, .reg = 0x1e, .osc_freq = 0x013b }, 584 { .mbps = 1900, .reg = 0x2f, .osc_freq = 0x0143 }, 585 { .mbps = 1950, .reg = 0x3f, .osc_freq = 0x014c }, 586 { .mbps = 2000, .reg = 0x0f, .osc_freq = 0x0154 }, 587 { .mbps = 2050, .reg = 0x40, .osc_freq = 0x015d }, 588 { .mbps = 2100, .reg = 0x41, .osc_freq = 0x0165 }, 589 { .mbps = 2150, .reg = 0x42, .osc_freq = 0x016e }, 590 { .mbps = 2200, .reg = 0x43, .osc_freq = 0x0176 }, 591 { .mbps = 2250, .reg = 0x44, .osc_freq = 0x017f }, 592 { .mbps = 2300, .reg = 0x45, .osc_freq = 0x0187 }, 593 { .mbps = 2350, .reg = 0x46, .osc_freq = 0x0190 }, 594 { .mbps = 2400, .reg = 0x47, .osc_freq = 0x0198 }, 595 { .mbps = 2450, .reg = 0x48, .osc_freq = 0x01a1 }, 596 { .mbps = 2500, .reg = 0x49, .osc_freq = 0x01a9 }, 597 { /* sentinel */ }, 598 }; 599 600 /* PHY ESC Error Monitor */ 601 #define PHEERM_REG 0x74 602 603 /* PHY Clock Lane Monitor */ 604 #define PHCLM_REG 0x78 605 #define PHCLM_STOPSTATECKL BIT(0) 606 607 /* PHY Data Lane Monitor */ 608 #define PHDLM_REG 0x7c 609 610 /* CSI0CLK Frequency Configuration Preset Register */ 611 #define CSI0CLKFCPR_REG 0x260 612 #define CSI0CLKFREQRANGE(n) ((n & 0x3f) << 16) 613 614 struct rcar_csi2_format { 615 u32 code; 616 unsigned int datatype; 617 unsigned int bpp; 618 }; 619 620 static const struct rcar_csi2_format rcar_csi2_formats[] = { 621 { 622 .code = MEDIA_BUS_FMT_RGB888_1X24, 623 .datatype = MIPI_CSI2_DT_RGB888, 624 .bpp = 24, 625 }, { 626 .code = MEDIA_BUS_FMT_UYVY8_1X16, 627 .datatype = MIPI_CSI2_DT_YUV422_8B, 628 .bpp = 16, 629 }, { 630 .code = MEDIA_BUS_FMT_YUYV8_1X16, 631 .datatype = MIPI_CSI2_DT_YUV422_8B, 632 .bpp = 16, 633 }, { 634 .code = MEDIA_BUS_FMT_UYVY8_2X8, 635 .datatype = MIPI_CSI2_DT_YUV422_8B, 636 .bpp = 16, 637 }, { 638 .code = MEDIA_BUS_FMT_YUYV10_2X10, 639 .datatype = MIPI_CSI2_DT_YUV422_8B, 640 .bpp = 20, 641 }, { 642 .code = MEDIA_BUS_FMT_Y8_1X8, 643 .datatype = MIPI_CSI2_DT_RAW8, 644 .bpp = 8, 645 }, { 646 .code = MEDIA_BUS_FMT_Y10_1X10, 647 .datatype = MIPI_CSI2_DT_RAW10, 648 .bpp = 10, 649 }, { 650 .code = MEDIA_BUS_FMT_SBGGR8_1X8, 651 .datatype = MIPI_CSI2_DT_RAW8, 652 .bpp = 8, 653 }, { 654 .code = MEDIA_BUS_FMT_SGBRG8_1X8, 655 .datatype = MIPI_CSI2_DT_RAW8, 656 .bpp = 8, 657 }, { 658 .code = MEDIA_BUS_FMT_SGRBG8_1X8, 659 .datatype = MIPI_CSI2_DT_RAW8, 660 .bpp = 8, 661 }, { 662 .code = MEDIA_BUS_FMT_SRGGB8_1X8, 663 .datatype = MIPI_CSI2_DT_RAW8, 664 .bpp = 8, 665 }, { 666 .code = MEDIA_BUS_FMT_SBGGR10_1X10, 667 .datatype = MIPI_CSI2_DT_RAW10, 668 .bpp = 10, 669 }, { 670 .code = MEDIA_BUS_FMT_SGBRG10_1X10, 671 .datatype = MIPI_CSI2_DT_RAW10, 672 .bpp = 10, 673 }, { 674 .code = MEDIA_BUS_FMT_SGRBG10_1X10, 675 .datatype = MIPI_CSI2_DT_RAW10, 676 .bpp = 10, 677 }, { 678 .code = MEDIA_BUS_FMT_SRGGB10_1X10, 679 .datatype = MIPI_CSI2_DT_RAW10, 680 .bpp = 10, 681 }, { 682 .code = MEDIA_BUS_FMT_SBGGR12_1X12, 683 .datatype = MIPI_CSI2_DT_RAW12, 684 .bpp = 12, 685 }, { 686 .code = MEDIA_BUS_FMT_SGBRG12_1X12, 687 .datatype = MIPI_CSI2_DT_RAW12, 688 .bpp = 12, 689 }, { 690 .code = MEDIA_BUS_FMT_SGRBG12_1X12, 691 .datatype = MIPI_CSI2_DT_RAW12, 692 .bpp = 12, 693 }, { 694 .code = MEDIA_BUS_FMT_SRGGB12_1X12, 695 .datatype = MIPI_CSI2_DT_RAW12, 696 .bpp = 12, 697 }, 698 }; 699 700 static const struct rcar_csi2_format *rcsi2_code_to_fmt(unsigned int code) 701 { 702 unsigned int i; 703 704 for (i = 0; i < ARRAY_SIZE(rcar_csi2_formats); i++) 705 if (rcar_csi2_formats[i].code == code) 706 return &rcar_csi2_formats[i]; 707 708 return NULL; 709 } 710 711 struct rcsi2_cphy_line_order { 712 enum v4l2_mbus_csi2_cphy_line_orders_type order; 713 u16 cfg; 714 u16 ctrl29; 715 }; 716 717 static const struct rcsi2_cphy_line_order rcsi2_cphy_line_orders[] = { 718 { .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_ABC, .cfg = 0x0, .ctrl29 = 0x0 }, 719 { .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_ACB, .cfg = 0xa, .ctrl29 = 0x1 }, 720 { .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_BAC, .cfg = 0xc, .ctrl29 = 0x1 }, 721 { .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_BCA, .cfg = 0x5, .ctrl29 = 0x0 }, 722 { .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_CAB, .cfg = 0x3, .ctrl29 = 0x0 }, 723 { .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_CBA, .cfg = 0x9, .ctrl29 = 0x1 } 724 }; 725 726 enum rcar_csi2_pads { 727 RCAR_CSI2_SINK, 728 RCAR_CSI2_SOURCE_VC0, 729 RCAR_CSI2_SOURCE_VC1, 730 RCAR_CSI2_SOURCE_VC2, 731 RCAR_CSI2_SOURCE_VC3, 732 NR_OF_RCAR_CSI2_PAD, 733 }; 734 735 struct rcsi2_register_layout { 736 unsigned int phtw; 737 unsigned int phypll; 738 }; 739 740 struct rcar_csi2_info { 741 const struct rcsi2_register_layout *regs; 742 int (*init_phtw)(struct rcar_csi2 *priv, unsigned int mbps); 743 int (*phy_post_init)(struct rcar_csi2 *priv); 744 int (*start_receiver)(struct rcar_csi2 *priv, 745 struct v4l2_subdev_state *state); 746 void (*enter_standby)(struct rcar_csi2 *priv); 747 const struct rcsi2_mbps_info *hsfreqrange; 748 unsigned int csi0clkfreqrange; 749 unsigned int num_channels; 750 bool clear_ulps; 751 bool use_isp; 752 bool support_dphy; 753 bool support_cphy; 754 }; 755 756 struct rcar_csi2 { 757 struct device *dev; 758 void __iomem *base; 759 const struct rcar_csi2_info *info; 760 struct reset_control *rstc; 761 762 struct v4l2_subdev subdev; 763 struct media_pad pads[NR_OF_RCAR_CSI2_PAD]; 764 765 struct v4l2_async_notifier notifier; 766 struct v4l2_subdev *remote; 767 unsigned int remote_pad; 768 769 int channel_vc[4]; 770 771 int stream_count; 772 773 bool cphy; 774 unsigned short lanes; 775 unsigned char lane_swap[4]; 776 enum v4l2_mbus_csi2_cphy_line_orders_type line_orders[3]; 777 }; 778 779 static inline struct rcar_csi2 *sd_to_csi2(struct v4l2_subdev *sd) 780 { 781 return container_of(sd, struct rcar_csi2, subdev); 782 } 783 784 static inline struct rcar_csi2 *notifier_to_csi2(struct v4l2_async_notifier *n) 785 { 786 return container_of(n, struct rcar_csi2, notifier); 787 } 788 789 static unsigned int rcsi2_num_pads(const struct rcar_csi2 *priv) 790 { 791 /* Used together with R-Car ISP: one sink and one source pad. */ 792 if (priv->info->use_isp) 793 return 2; 794 795 /* Used together with R-Car VIN: one sink and four source pads. */ 796 return 5; 797 } 798 799 static u32 rcsi2_read(struct rcar_csi2 *priv, unsigned int reg) 800 { 801 return ioread32(priv->base + reg); 802 } 803 804 static void rcsi2_write(struct rcar_csi2 *priv, unsigned int reg, u32 data) 805 { 806 iowrite32(data, priv->base + reg); 807 } 808 809 static u16 rcsi2_read16(struct rcar_csi2 *priv, unsigned int reg) 810 { 811 return ioread16(priv->base + reg); 812 } 813 814 static void rcsi2_write16(struct rcar_csi2 *priv, unsigned int reg, u16 data) 815 { 816 iowrite16(data, priv->base + reg); 817 } 818 819 static void rcsi2_modify16(struct rcar_csi2 *priv, unsigned int reg, u16 data, u16 mask) 820 { 821 u16 val; 822 823 val = rcsi2_read16(priv, reg) & ~mask; 824 rcsi2_write16(priv, reg, val | data); 825 } 826 827 static int rcsi2_phtw_write(struct rcar_csi2 *priv, u8 data, u8 code) 828 { 829 unsigned int timeout; 830 831 rcsi2_write(priv, priv->info->regs->phtw, 832 PHTW_DWEN | PHTW_TESTDIN_DATA(data) | 833 PHTW_CWEN | PHTW_TESTDIN_CODE(code)); 834 835 /* Wait for DWEN and CWEN to be cleared by hardware. */ 836 for (timeout = 0; timeout <= 20; timeout++) { 837 if (!(rcsi2_read(priv, priv->info->regs->phtw) & (PHTW_DWEN | PHTW_CWEN))) 838 return 0; 839 840 usleep_range(1000, 2000); 841 } 842 843 dev_err(priv->dev, "Timeout waiting for PHTW_DWEN and/or PHTW_CWEN\n"); 844 845 return -ETIMEDOUT; 846 } 847 848 static int rcsi2_phtw_write_array(struct rcar_csi2 *priv, 849 const struct phtw_value *values, 850 unsigned int size) 851 { 852 int ret; 853 854 for (unsigned int i = 0; i < size; i++) { 855 ret = rcsi2_phtw_write(priv, values[i].data, values[i].code); 856 if (ret) 857 return ret; 858 } 859 860 return 0; 861 } 862 863 static const struct rcsi2_mbps_info * 864 rcsi2_mbps_to_info(struct rcar_csi2 *priv, 865 const struct rcsi2_mbps_info *infotable, unsigned int mbps) 866 { 867 const struct rcsi2_mbps_info *info; 868 const struct rcsi2_mbps_info *prev = NULL; 869 870 if (mbps < infotable->mbps) 871 dev_warn(priv->dev, "%u Mbps less than min PHY speed %u Mbps", 872 mbps, infotable->mbps); 873 874 for (info = infotable; info->mbps != 0; info++) { 875 if (info->mbps >= mbps) 876 break; 877 prev = info; 878 } 879 880 if (!info->mbps) { 881 dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps); 882 return NULL; 883 } 884 885 if (prev && ((mbps - prev->mbps) <= (info->mbps - mbps))) 886 info = prev; 887 888 return info; 889 } 890 891 static void rcsi2_enter_standby_gen3(struct rcar_csi2 *priv) 892 { 893 rcsi2_write(priv, PHYCNT_REG, 0); 894 rcsi2_write(priv, PHTC_REG, PHTC_TESTCLR); 895 } 896 897 static void rcsi2_enter_standby(struct rcar_csi2 *priv) 898 { 899 if (priv->info->enter_standby) 900 priv->info->enter_standby(priv); 901 902 reset_control_assert(priv->rstc); 903 usleep_range(100, 150); 904 pm_runtime_put(priv->dev); 905 } 906 907 static int rcsi2_exit_standby(struct rcar_csi2 *priv) 908 { 909 int ret; 910 911 ret = pm_runtime_resume_and_get(priv->dev); 912 if (ret < 0) 913 return ret; 914 915 reset_control_deassert(priv->rstc); 916 917 return 0; 918 } 919 920 static int rcsi2_wait_phy_start(struct rcar_csi2 *priv, 921 unsigned int lanes) 922 { 923 unsigned int timeout; 924 925 /* Wait for the clock and data lanes to enter LP-11 state. */ 926 for (timeout = 0; timeout <= 20; timeout++) { 927 const u32 lane_mask = (1 << lanes) - 1; 928 929 if ((rcsi2_read(priv, PHCLM_REG) & PHCLM_STOPSTATECKL) && 930 (rcsi2_read(priv, PHDLM_REG) & lane_mask) == lane_mask) 931 return 0; 932 933 usleep_range(1000, 2000); 934 } 935 936 dev_err(priv->dev, "Timeout waiting for LP-11 state\n"); 937 938 return -ETIMEDOUT; 939 } 940 941 static int rcsi2_set_phypll(struct rcar_csi2 *priv, unsigned int mbps) 942 { 943 const struct rcsi2_mbps_info *info; 944 945 info = rcsi2_mbps_to_info(priv, priv->info->hsfreqrange, mbps); 946 if (!info) 947 return -ERANGE; 948 949 rcsi2_write(priv, priv->info->regs->phypll, PHYPLL_HSFREQRANGE(info->reg)); 950 951 return 0; 952 } 953 954 static int rcsi2_calc_mbps(struct rcar_csi2 *priv, unsigned int bpp, 955 unsigned int lanes) 956 { 957 struct v4l2_subdev *source; 958 s64 freq; 959 u64 mbps; 960 961 if (!priv->remote) 962 return -ENODEV; 963 964 source = priv->remote; 965 966 freq = v4l2_get_link_freq(source->ctrl_handler, bpp, 2 * lanes); 967 if (freq < 0) { 968 int ret = (int)freq; 969 970 dev_err(priv->dev, "failed to get link freq for %s: %d\n", 971 source->name, ret); 972 973 return ret; 974 } 975 976 mbps = div_u64(freq * 2, MEGA); 977 978 /* Adjust for C-PHY, divide by 2.8. */ 979 if (priv->cphy) 980 mbps = div_u64(mbps * 5, 14); 981 982 return mbps; 983 } 984 985 static int rcsi2_get_active_lanes(struct rcar_csi2 *priv, 986 unsigned int *lanes) 987 { 988 struct v4l2_mbus_config mbus_config = { 0 }; 989 int ret; 990 991 *lanes = priv->lanes; 992 993 ret = v4l2_subdev_call(priv->remote, pad, get_mbus_config, 994 priv->remote_pad, &mbus_config); 995 if (ret == -ENOIOCTLCMD) { 996 dev_dbg(priv->dev, "No remote mbus configuration available\n"); 997 return 0; 998 } 999 1000 if (ret) { 1001 dev_err(priv->dev, "Failed to get remote mbus configuration\n"); 1002 return ret; 1003 } 1004 1005 switch (mbus_config.type) { 1006 case V4L2_MBUS_CSI2_CPHY: 1007 if (!priv->cphy) 1008 return -EINVAL; 1009 break; 1010 case V4L2_MBUS_CSI2_DPHY: 1011 if (priv->cphy) 1012 return -EINVAL; 1013 break; 1014 default: 1015 dev_err(priv->dev, "Unsupported media bus type %u\n", 1016 mbus_config.type); 1017 return -EINVAL; 1018 } 1019 1020 if (mbus_config.bus.mipi_csi2.num_data_lanes > priv->lanes) { 1021 dev_err(priv->dev, 1022 "Unsupported mbus config: too many data lanes %u\n", 1023 mbus_config.bus.mipi_csi2.num_data_lanes); 1024 return -EINVAL; 1025 } 1026 1027 *lanes = mbus_config.bus.mipi_csi2.num_data_lanes; 1028 1029 return 0; 1030 } 1031 1032 static int rcsi2_start_receiver_gen3(struct rcar_csi2 *priv, 1033 struct v4l2_subdev_state *state) 1034 { 1035 const struct rcar_csi2_format *format; 1036 u32 phycnt, vcdt = 0, vcdt2 = 0, fld = 0; 1037 const struct v4l2_mbus_framefmt *fmt; 1038 unsigned int lanes; 1039 unsigned int i; 1040 int mbps, ret; 1041 1042 /* Use the format on the sink pad to compute the receiver config. */ 1043 fmt = v4l2_subdev_state_get_format(state, RCAR_CSI2_SINK); 1044 1045 dev_dbg(priv->dev, "Input size (%ux%u%c)\n", 1046 fmt->width, fmt->height, 1047 fmt->field == V4L2_FIELD_NONE ? 'p' : 'i'); 1048 1049 /* Code is validated in set_fmt. */ 1050 format = rcsi2_code_to_fmt(fmt->code); 1051 if (!format) 1052 return -EINVAL; 1053 1054 /* 1055 * Enable all supported CSI-2 channels with virtual channel and 1056 * data type matching. 1057 * 1058 * NOTE: It's not possible to get individual datatype for each 1059 * source virtual channel. Once this is possible in V4L2 1060 * it should be used here. 1061 */ 1062 for (i = 0; i < priv->info->num_channels; i++) { 1063 u32 vcdt_part; 1064 1065 if (priv->channel_vc[i] < 0) 1066 continue; 1067 1068 vcdt_part = VCDT_SEL_VC(priv->channel_vc[i]) | VCDT_VCDTN_EN | 1069 VCDT_SEL_DTN_ON | VCDT_SEL_DT(format->datatype); 1070 1071 /* Store in correct reg and offset. */ 1072 if (i < 2) 1073 vcdt |= vcdt_part << ((i % 2) * 16); 1074 else 1075 vcdt2 |= vcdt_part << ((i % 2) * 16); 1076 } 1077 1078 if (fmt->field == V4L2_FIELD_ALTERNATE) { 1079 fld = FLD_DET_SEL(1) | FLD_FLD_EN4 | FLD_FLD_EN3 | FLD_FLD_EN2 1080 | FLD_FLD_EN; 1081 1082 if (fmt->height == 240) 1083 fld |= FLD_FLD_NUM(0); 1084 else 1085 fld |= FLD_FLD_NUM(1); 1086 } 1087 1088 /* 1089 * Get the number of active data lanes inspecting the remote mbus 1090 * configuration. 1091 */ 1092 ret = rcsi2_get_active_lanes(priv, &lanes); 1093 if (ret) 1094 return ret; 1095 1096 phycnt = PHYCNT_ENABLECLK; 1097 phycnt |= (1 << lanes) - 1; 1098 1099 mbps = rcsi2_calc_mbps(priv, format->bpp, lanes); 1100 if (mbps < 0) 1101 return mbps; 1102 1103 /* Enable interrupts. */ 1104 rcsi2_write(priv, INTEN_REG, INTEN_INT_AFIFO_OF | INTEN_INT_ERRSOTHS 1105 | INTEN_INT_ERRSOTSYNCHS); 1106 1107 /* Init */ 1108 rcsi2_write(priv, TREF_REG, TREF_TREF); 1109 rcsi2_write(priv, PHTC_REG, 0); 1110 1111 /* Configure */ 1112 if (!priv->info->use_isp) { 1113 rcsi2_write(priv, VCDT_REG, vcdt); 1114 if (vcdt2) 1115 rcsi2_write(priv, VCDT2_REG, vcdt2); 1116 } 1117 1118 /* Lanes are zero indexed. */ 1119 rcsi2_write(priv, LSWAP_REG, 1120 LSWAP_L0SEL(priv->lane_swap[0] - 1) | 1121 LSWAP_L1SEL(priv->lane_swap[1] - 1) | 1122 LSWAP_L2SEL(priv->lane_swap[2] - 1) | 1123 LSWAP_L3SEL(priv->lane_swap[3] - 1)); 1124 1125 /* Start */ 1126 if (priv->info->init_phtw) { 1127 ret = priv->info->init_phtw(priv, mbps); 1128 if (ret) 1129 return ret; 1130 } 1131 1132 if (priv->info->hsfreqrange) { 1133 ret = rcsi2_set_phypll(priv, mbps); 1134 if (ret) 1135 return ret; 1136 } 1137 1138 if (priv->info->csi0clkfreqrange) 1139 rcsi2_write(priv, CSI0CLKFCPR_REG, 1140 CSI0CLKFREQRANGE(priv->info->csi0clkfreqrange)); 1141 1142 if (priv->info->use_isp) 1143 rcsi2_write(priv, PHYFRX_REG, 1144 PHYFRX_FORCERX_MODE_3 | PHYFRX_FORCERX_MODE_2 | 1145 PHYFRX_FORCERX_MODE_1 | PHYFRX_FORCERX_MODE_0); 1146 1147 rcsi2_write(priv, PHYCNT_REG, phycnt); 1148 rcsi2_write(priv, LINKCNT_REG, LINKCNT_MONITOR_EN | 1149 LINKCNT_REG_MONI_PACT_EN | LINKCNT_ICLK_NONSTOP); 1150 rcsi2_write(priv, FLD_REG, fld); 1151 rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ); 1152 rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ | PHYCNT_RSTZ); 1153 1154 ret = rcsi2_wait_phy_start(priv, lanes); 1155 if (ret) 1156 return ret; 1157 1158 if (priv->info->use_isp) 1159 rcsi2_write(priv, PHYFRX_REG, 0); 1160 1161 /* Run post PHY start initialization, if needed. */ 1162 if (priv->info->phy_post_init) { 1163 ret = priv->info->phy_post_init(priv); 1164 if (ret) 1165 return ret; 1166 } 1167 1168 /* Clear Ultra Low Power interrupt. */ 1169 if (priv->info->clear_ulps) 1170 rcsi2_write(priv, INTSTATE_REG, 1171 INTSTATE_INT_ULPS_START | 1172 INTSTATE_INT_ULPS_END); 1173 return 0; 1174 } 1175 1176 static void rsci2_set_line_order(struct rcar_csi2 *priv, 1177 enum v4l2_mbus_csi2_cphy_line_orders_type order, 1178 unsigned int cfgreg, unsigned int ctrlreg) 1179 { 1180 const struct rcsi2_cphy_line_order *info = NULL; 1181 1182 for (unsigned int i = 0; i < ARRAY_SIZE(rcsi2_cphy_line_orders); i++) { 1183 if (rcsi2_cphy_line_orders[i].order == order) { 1184 info = &rcsi2_cphy_line_orders[i]; 1185 break; 1186 } 1187 } 1188 1189 if (!info) 1190 return; 1191 1192 rcsi2_modify16(priv, cfgreg, info->cfg, 0x000f); 1193 rcsi2_modify16(priv, ctrlreg, info->ctrl29, 0x0100); 1194 } 1195 1196 static int rcsi2_wait_phy_start_v4h(struct rcar_csi2 *priv, u32 match) 1197 { 1198 unsigned int timeout; 1199 u32 status; 1200 1201 for (timeout = 0; timeout <= 10; timeout++) { 1202 status = rcsi2_read(priv, V4H_ST_PHYST_REG); 1203 if ((status & match) == match) 1204 return 0; 1205 1206 usleep_range(1000, 2000); 1207 } 1208 1209 return -ETIMEDOUT; 1210 } 1211 1212 static int rcsi2_c_phy_setting_v4h(struct rcar_csi2 *priv, int msps) 1213 { 1214 const struct rcsi2_cphy_setting *conf; 1215 1216 for (conf = cphy_setting_table_r8a779g0; conf->msps != 0; conf++) { 1217 if (conf->msps > msps) 1218 break; 1219 } 1220 1221 if (!conf->msps) { 1222 dev_err(priv->dev, "Unsupported PHY speed for msps setting (%u Msps)", msps); 1223 return -ERANGE; 1224 } 1225 1226 /* C-PHY specific */ 1227 rcsi2_write16(priv, V4H_CORE_DIG_RW_COMMON_REG(7), 0x0155); 1228 rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(7), 0x0068); 1229 rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(8), 0x0010); 1230 1231 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_LP_0_REG, 0x463c); 1232 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_LP_0_REG, 0x463c); 1233 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_LP_0_REG, 0x463c); 1234 1235 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(0), 0x00d5); 1236 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(0), 0x00d5); 1237 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(0), 0x00d5); 1238 1239 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(1), 0x0013); 1240 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(1), 0x0013); 1241 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(1), 0x0013); 1242 1243 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(5), 0x0013); 1244 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(5), 0x0013); 1245 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(5), 0x0013); 1246 1247 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(6), 0x000a); 1248 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(6), 0x000a); 1249 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(6), 0x000a); 1250 1251 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(2), conf->rx2); 1252 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(2), conf->rx2); 1253 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(2), conf->rx2); 1254 1255 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_REG(2), 0x0001); 1256 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_REG(2), 0); 1257 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_REG(2), 0x0001); 1258 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_REG(2), 0x0001); 1259 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_REG(2), 0); 1260 1261 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO0_REG(0), conf->trio0); 1262 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO1_REG(0), conf->trio0); 1263 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO2_REG(0), conf->trio0); 1264 1265 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO0_REG(2), conf->trio2); 1266 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO1_REG(2), conf->trio2); 1267 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO2_REG(2), conf->trio2); 1268 1269 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO0_REG(1), conf->trio1); 1270 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO1_REG(1), conf->trio1); 1271 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO2_REG(1), conf->trio1); 1272 1273 /* Configure data line order. */ 1274 rsci2_set_line_order(priv, priv->line_orders[0], 1275 V4H_CORE_DIG_CLANE_0_RW_CFG_0_REG, 1276 V4H_CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_REG(9)); 1277 rsci2_set_line_order(priv, priv->line_orders[1], 1278 V4H_CORE_DIG_CLANE_1_RW_CFG_0_REG, 1279 V4H_CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_REG(9)); 1280 rsci2_set_line_order(priv, priv->line_orders[2], 1281 V4H_CORE_DIG_CLANE_2_RW_CFG_0_REG, 1282 V4H_CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_REG(9)); 1283 1284 /* TODO: This registers is not documented. */ 1285 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_TX_6_REG, 0x5000); 1286 1287 /* Leave Shutdown mode */ 1288 rcsi2_write(priv, V4H_DPHY_RSTZ_REG, BIT(0)); 1289 rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, BIT(0)); 1290 1291 /* Wait for calibration */ 1292 if (rcsi2_wait_phy_start_v4h(priv, V4H_ST_PHYST_ST_PHY_READY)) { 1293 dev_err(priv->dev, "PHY calibration failed\n"); 1294 return -ETIMEDOUT; 1295 } 1296 1297 /* C-PHY setting - analog programing*/ 1298 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_REG(9), conf->lane29); 1299 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_REG(7), conf->lane27); 1300 1301 return 0; 1302 } 1303 1304 static int rcsi2_start_receiver_v4h(struct rcar_csi2 *priv, 1305 struct v4l2_subdev_state *state) 1306 { 1307 const struct rcar_csi2_format *format; 1308 const struct v4l2_mbus_framefmt *fmt; 1309 unsigned int lanes; 1310 int msps; 1311 int ret; 1312 1313 /* Use the format on the sink pad to compute the receiver config. */ 1314 fmt = v4l2_subdev_state_get_format(state, RCAR_CSI2_SINK); 1315 format = rcsi2_code_to_fmt(fmt->code); 1316 if (!format) 1317 return -EINVAL; 1318 1319 ret = rcsi2_get_active_lanes(priv, &lanes); 1320 if (ret) 1321 return ret; 1322 1323 msps = rcsi2_calc_mbps(priv, format->bpp, lanes); 1324 if (msps < 0) 1325 return msps; 1326 1327 /* Reset LINK and PHY*/ 1328 rcsi2_write(priv, V4H_CSI2_RESETN_REG, 0); 1329 rcsi2_write(priv, V4H_DPHY_RSTZ_REG, 0); 1330 rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, 0); 1331 1332 /* PHY static setting */ 1333 rcsi2_write(priv, V4H_PHY_EN_REG, V4H_PHY_EN_ENABLE_CLK); 1334 rcsi2_write(priv, V4H_FLDC_REG, 0); 1335 rcsi2_write(priv, V4H_FLDD_REG, 0); 1336 rcsi2_write(priv, V4H_IDIC_REG, 0); 1337 rcsi2_write(priv, V4H_PHY_MODE_REG, V4H_PHY_MODE_CPHY); 1338 rcsi2_write(priv, V4H_N_LANES_REG, lanes - 1); 1339 1340 /* Reset CSI2 */ 1341 rcsi2_write(priv, V4H_CSI2_RESETN_REG, BIT(0)); 1342 1343 /* Registers static setting through APB */ 1344 /* Common setting */ 1345 rcsi2_write16(priv, V4H_CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_REG(0), 0x1bfd); 1346 rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_STARTUP_1_1_REG, 0x0233); 1347 rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(6), 0x0027); 1348 rcsi2_write16(priv, V4H_PPI_CALIBCTRL_RW_COMMON_BG_0_REG, 0x01f4); 1349 rcsi2_write16(priv, V4H_PPI_RW_TERMCAL_CFG_0_REG, 0x0013); 1350 rcsi2_write16(priv, V4H_PPI_RW_OFFSETCAL_CFG_0_REG, 0x0003); 1351 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_TIMEBASE_REG, 0x004f); 1352 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_NREF_REG, 0x0320); 1353 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_NREF_RANGE_REG, 0x000f); 1354 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_TWAIT_CONFIG_REG, 0xfe18); 1355 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_VT_CONFIG_REG, 0x0c3c); 1356 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_COARSE_CFG_REG, 0x0105); 1357 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(6), 0x1000); 1358 rcsi2_write16(priv, V4H_PPI_RW_COMMON_CFG_REG, 0x0003); 1359 1360 /* C-PHY settings */ 1361 ret = rcsi2_c_phy_setting_v4h(priv, msps); 1362 if (ret) 1363 return ret; 1364 1365 rcsi2_wait_phy_start_v4h(priv, V4H_ST_PHYST_ST_STOPSTATE_0 | 1366 V4H_ST_PHYST_ST_STOPSTATE_1 | 1367 V4H_ST_PHYST_ST_STOPSTATE_2); 1368 1369 return 0; 1370 } 1371 1372 static int rcsi2_d_phy_setting_v4m(struct rcar_csi2 *priv, int data_rate) 1373 { 1374 unsigned int timeout; 1375 int ret; 1376 1377 static const struct phtw_value step1[] = { 1378 { .data = 0x00, .code = 0x00 }, 1379 { .data = 0x00, .code = 0x1e }, 1380 }; 1381 1382 /* Shutdown and reset PHY. */ 1383 rcsi2_write(priv, V4H_DPHY_RSTZ_REG, BIT(0)); 1384 rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, BIT(0)); 1385 1386 /* Start internal calibration (POR). */ 1387 ret = rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1)); 1388 if (ret) 1389 return ret; 1390 1391 /* Wait for POR to complete. */ 1392 for (timeout = 10; timeout > 0; timeout--) { 1393 if ((rcsi2_read(priv, V4M_PHTR_REG) & 0xf0000) == 0x70000) 1394 break; 1395 usleep_range(1000, 2000); 1396 } 1397 1398 if (!timeout) { 1399 dev_err(priv->dev, "D-PHY calibration failed\n"); 1400 return -ETIMEDOUT; 1401 } 1402 1403 return 0; 1404 } 1405 1406 static int rcsi2_set_osc_freq(struct rcar_csi2 *priv, unsigned int mbps) 1407 { 1408 const struct rcsi2_mbps_info *info; 1409 struct phtw_value steps[] = { 1410 { .data = 0x00, .code = 0x00 }, 1411 { .code = 0xe2 }, /* Data filled in below. */ 1412 { .code = 0xe3 }, /* Data filled in below. */ 1413 { .data = 0x01, .code = 0xe4 }, 1414 }; 1415 1416 info = rcsi2_mbps_to_info(priv, priv->info->hsfreqrange, mbps); 1417 if (!info) 1418 return -ERANGE; 1419 1420 /* Fill in data for command. */ 1421 steps[1].data = (info->osc_freq & 0x00ff) >> 0; 1422 steps[2].data = (info->osc_freq & 0x0f00) >> 8; 1423 1424 return rcsi2_phtw_write_array(priv, steps, ARRAY_SIZE(steps)); 1425 } 1426 1427 static int rcsi2_init_common_v4m(struct rcar_csi2 *priv, unsigned int mbps) 1428 { 1429 int ret; 1430 1431 static const struct phtw_value step1[] = { 1432 { .data = 0x00, .code = 0x00 }, 1433 { .data = 0x3c, .code = 0x08 }, 1434 }; 1435 1436 static const struct phtw_value step2[] = { 1437 { .data = 0x00, .code = 0x00 }, 1438 { .data = 0x80, .code = 0xe0 }, 1439 { .data = 0x31, .code = 0xe1 }, 1440 { .data = 0x06, .code = 0x00 }, 1441 { .data = 0x11, .code = 0x11 }, 1442 { .data = 0x08, .code = 0x00 }, 1443 { .data = 0x11, .code = 0x11 }, 1444 { .data = 0x0a, .code = 0x00 }, 1445 { .data = 0x11, .code = 0x11 }, 1446 { .data = 0x0c, .code = 0x00 }, 1447 { .data = 0x11, .code = 0x11 }, 1448 { .data = 0x01, .code = 0x00 }, 1449 { .data = 0x31, .code = 0xaa }, 1450 { .data = 0x05, .code = 0x00 }, 1451 { .data = 0x05, .code = 0x09 }, 1452 { .data = 0x07, .code = 0x00 }, 1453 { .data = 0x05, .code = 0x09 }, 1454 { .data = 0x09, .code = 0x00 }, 1455 { .data = 0x05, .code = 0x09 }, 1456 { .data = 0x0b, .code = 0x00 }, 1457 { .data = 0x05, .code = 0x09 }, 1458 }; 1459 1460 static const struct phtw_value step3[] = { 1461 { .data = 0x01, .code = 0x00 }, 1462 { .data = 0x06, .code = 0xab }, 1463 }; 1464 1465 if (priv->info->hsfreqrange) { 1466 ret = rcsi2_set_phypll(priv, mbps); 1467 if (ret) 1468 return ret; 1469 1470 ret = rcsi2_set_osc_freq(priv, mbps); 1471 if (ret) 1472 return ret; 1473 } 1474 1475 if (mbps <= 1500) { 1476 ret = rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1)); 1477 if (ret) 1478 return ret; 1479 } 1480 1481 if (priv->info->csi0clkfreqrange) 1482 rcsi2_write(priv, V4M_CSI0CLKFCPR_REG, 1483 CSI0CLKFREQRANGE(priv->info->csi0clkfreqrange)); 1484 1485 rcsi2_write(priv, V4H_PHY_EN_REG, V4H_PHY_EN_ENABLE_CLK | 1486 V4H_PHY_EN_ENABLE_0 | V4H_PHY_EN_ENABLE_1 | 1487 V4H_PHY_EN_ENABLE_2 | V4H_PHY_EN_ENABLE_3); 1488 1489 if (mbps > 1500) { 1490 ret = rcsi2_phtw_write_array(priv, step2, ARRAY_SIZE(step2)); 1491 if (ret) 1492 return ret; 1493 } 1494 1495 return rcsi2_phtw_write_array(priv, step3, ARRAY_SIZE(step3)); 1496 } 1497 1498 static int rcsi2_start_receiver_v4m(struct rcar_csi2 *priv, 1499 struct v4l2_subdev_state *state) 1500 { 1501 const struct rcar_csi2_format *format; 1502 const struct v4l2_mbus_framefmt *fmt; 1503 unsigned int lanes; 1504 int mbps; 1505 int ret; 1506 1507 /* Calculate parameters */ 1508 fmt = v4l2_subdev_state_get_format(state, RCAR_CSI2_SINK); 1509 format = rcsi2_code_to_fmt(fmt->code); 1510 if (!format) 1511 return -EINVAL; 1512 1513 ret = rcsi2_get_active_lanes(priv, &lanes); 1514 if (ret) 1515 return ret; 1516 1517 mbps = rcsi2_calc_mbps(priv, format->bpp, lanes); 1518 if (mbps < 0) 1519 return mbps; 1520 1521 /* Reset LINK and PHY */ 1522 rcsi2_write(priv, V4H_CSI2_RESETN_REG, 0); 1523 rcsi2_write(priv, V4H_DPHY_RSTZ_REG, 0); 1524 rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, 0); 1525 rcsi2_write(priv, V4M_PHTC_REG, PHTC_TESTCLR); 1526 1527 /* PHY static setting */ 1528 rcsi2_write(priv, V4H_PHY_EN_REG, V4H_PHY_EN_ENABLE_CLK); 1529 rcsi2_write(priv, V4H_FLDC_REG, 0); 1530 rcsi2_write(priv, V4H_FLDD_REG, 0); 1531 rcsi2_write(priv, V4H_IDIC_REG, 0); 1532 rcsi2_write(priv, V4H_PHY_MODE_REG, V4H_PHY_MODE_DPHY); 1533 rcsi2_write(priv, V4H_N_LANES_REG, lanes - 1); 1534 1535 rcsi2_write(priv, V4M_FRXM_REG, 1536 V4M_FRXM_FORCERXMODE_0 | V4M_FRXM_FORCERXMODE_1 | 1537 V4M_FRXM_FORCERXMODE_2 | V4M_FRXM_FORCERXMODE_3); 1538 rcsi2_write(priv, V4M_OVR1_REG, 1539 V4M_OVR1_FORCERXMODE_0 | V4M_OVR1_FORCERXMODE_1 | 1540 V4M_OVR1_FORCERXMODE_2 | V4M_OVR1_FORCERXMODE_3); 1541 1542 /* Reset CSI2 */ 1543 rcsi2_write(priv, V4M_PHTC_REG, 0); 1544 rcsi2_write(priv, V4H_CSI2_RESETN_REG, BIT(0)); 1545 1546 /* Common settings */ 1547 ret = rcsi2_init_common_v4m(priv, mbps); 1548 if (ret) 1549 return ret; 1550 1551 /* D-PHY settings */ 1552 ret = rcsi2_d_phy_setting_v4m(priv, mbps); 1553 if (ret) 1554 return ret; 1555 1556 rcsi2_wait_phy_start_v4h(priv, V4H_ST_PHYST_ST_STOPSTATE_0 | 1557 V4H_ST_PHYST_ST_STOPSTATE_1 | 1558 V4H_ST_PHYST_ST_STOPSTATE_2 | 1559 V4H_ST_PHYST_ST_STOPSTATE_3); 1560 1561 rcsi2_write(priv, V4M_FRXM_REG, 0); 1562 1563 return 0; 1564 } 1565 1566 static int rcsi2_start(struct rcar_csi2 *priv, struct v4l2_subdev_state *state) 1567 { 1568 int ret; 1569 1570 ret = rcsi2_exit_standby(priv); 1571 if (ret < 0) 1572 return ret; 1573 1574 ret = priv->info->start_receiver(priv, state); 1575 if (ret) { 1576 rcsi2_enter_standby(priv); 1577 return ret; 1578 } 1579 1580 ret = v4l2_subdev_enable_streams(priv->remote, priv->remote_pad, 1581 BIT_ULL(0)); 1582 if (ret) { 1583 rcsi2_enter_standby(priv); 1584 return ret; 1585 } 1586 1587 return 0; 1588 } 1589 1590 static void rcsi2_stop(struct rcar_csi2 *priv) 1591 { 1592 rcsi2_enter_standby(priv); 1593 v4l2_subdev_disable_streams(priv->remote, priv->remote_pad, BIT_ULL(0)); 1594 } 1595 1596 static int rcsi2_enable_streams(struct v4l2_subdev *sd, 1597 struct v4l2_subdev_state *state, u32 source_pad, 1598 u64 source_streams_mask) 1599 { 1600 struct rcar_csi2 *priv = sd_to_csi2(sd); 1601 int ret = 0; 1602 1603 if (source_streams_mask != 1) 1604 return -EINVAL; 1605 1606 if (!priv->remote) 1607 return -ENODEV; 1608 1609 if (priv->stream_count == 0) { 1610 ret = rcsi2_start(priv, state); 1611 if (ret) 1612 return ret; 1613 } 1614 1615 priv->stream_count += 1; 1616 1617 return ret; 1618 } 1619 1620 static int rcsi2_disable_streams(struct v4l2_subdev *sd, 1621 struct v4l2_subdev_state *state, 1622 u32 source_pad, u64 source_streams_mask) 1623 { 1624 struct rcar_csi2 *priv = sd_to_csi2(sd); 1625 int ret = 0; 1626 1627 if (source_streams_mask != 1) 1628 return -EINVAL; 1629 1630 if (!priv->remote) 1631 return -ENODEV; 1632 1633 if (priv->stream_count == 1) 1634 rcsi2_stop(priv); 1635 1636 priv->stream_count -= 1; 1637 1638 return ret; 1639 } 1640 1641 static int rcsi2_set_pad_format(struct v4l2_subdev *sd, 1642 struct v4l2_subdev_state *state, 1643 struct v4l2_subdev_format *format) 1644 { 1645 struct rcar_csi2 *priv = sd_to_csi2(sd); 1646 unsigned int num_pads = rcsi2_num_pads(priv); 1647 1648 if (format->pad > RCAR_CSI2_SINK) 1649 return v4l2_subdev_get_fmt(sd, state, format); 1650 1651 if (!rcsi2_code_to_fmt(format->format.code)) 1652 format->format.code = rcar_csi2_formats[0].code; 1653 1654 *v4l2_subdev_state_get_format(state, format->pad) = format->format; 1655 1656 /* Propagate the format to the source pads. */ 1657 for (unsigned int i = RCAR_CSI2_SOURCE_VC0; i < num_pads; i++) 1658 *v4l2_subdev_state_get_format(state, i) = format->format; 1659 1660 return 0; 1661 } 1662 1663 static const struct v4l2_subdev_pad_ops rcar_csi2_pad_ops = { 1664 .enable_streams = rcsi2_enable_streams, 1665 .disable_streams = rcsi2_disable_streams, 1666 1667 .set_fmt = rcsi2_set_pad_format, 1668 .get_fmt = v4l2_subdev_get_fmt, 1669 }; 1670 1671 static const struct v4l2_subdev_ops rcar_csi2_subdev_ops = { 1672 .pad = &rcar_csi2_pad_ops, 1673 }; 1674 1675 static int rcsi2_init_state(struct v4l2_subdev *sd, 1676 struct v4l2_subdev_state *state) 1677 { 1678 struct rcar_csi2 *priv = sd_to_csi2(sd); 1679 unsigned int num_pads = rcsi2_num_pads(priv); 1680 1681 static const struct v4l2_mbus_framefmt rcar_csi2_default_fmt = { 1682 .width = 1920, 1683 .height = 1080, 1684 .code = MEDIA_BUS_FMT_RGB888_1X24, 1685 .colorspace = V4L2_COLORSPACE_SRGB, 1686 .field = V4L2_FIELD_NONE, 1687 .ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT, 1688 .quantization = V4L2_QUANTIZATION_DEFAULT, 1689 .xfer_func = V4L2_XFER_FUNC_DEFAULT, 1690 }; 1691 1692 for (unsigned int i = RCAR_CSI2_SINK; i < num_pads; i++) 1693 *v4l2_subdev_state_get_format(state, i) = rcar_csi2_default_fmt; 1694 1695 return 0; 1696 } 1697 1698 static const struct v4l2_subdev_internal_ops rcar_csi2_internal_ops = { 1699 .init_state = rcsi2_init_state, 1700 }; 1701 1702 static irqreturn_t rcsi2_irq(int irq, void *data) 1703 { 1704 struct rcar_csi2 *priv = data; 1705 u32 status, err_status; 1706 1707 status = rcsi2_read(priv, INTSTATE_REG); 1708 err_status = rcsi2_read(priv, INTERRSTATE_REG); 1709 1710 if (!status) 1711 return IRQ_HANDLED; 1712 1713 rcsi2_write(priv, INTSTATE_REG, status); 1714 1715 if (!err_status) 1716 return IRQ_HANDLED; 1717 1718 rcsi2_write(priv, INTERRSTATE_REG, err_status); 1719 1720 dev_info(priv->dev, "Transfer error, restarting CSI-2 receiver\n"); 1721 1722 return IRQ_WAKE_THREAD; 1723 } 1724 1725 static irqreturn_t rcsi2_irq_thread(int irq, void *data) 1726 { 1727 struct v4l2_subdev_state *state; 1728 struct rcar_csi2 *priv = data; 1729 1730 state = v4l2_subdev_lock_and_get_active_state(&priv->subdev); 1731 1732 rcsi2_stop(priv); 1733 usleep_range(1000, 2000); 1734 if (rcsi2_start(priv, state)) 1735 dev_warn(priv->dev, "Failed to restart CSI-2 receiver\n"); 1736 1737 v4l2_subdev_unlock_state(state); 1738 1739 return IRQ_HANDLED; 1740 } 1741 1742 /* ----------------------------------------------------------------------------- 1743 * Async handling and registration of subdevices and links. 1744 */ 1745 1746 static int rcsi2_notify_bound(struct v4l2_async_notifier *notifier, 1747 struct v4l2_subdev *subdev, 1748 struct v4l2_async_connection *asc) 1749 { 1750 struct rcar_csi2 *priv = notifier_to_csi2(notifier); 1751 int pad; 1752 1753 pad = media_entity_get_fwnode_pad(&subdev->entity, asc->match.fwnode, 1754 MEDIA_PAD_FL_SOURCE); 1755 if (pad < 0) { 1756 dev_err(priv->dev, "Failed to find pad for %s\n", subdev->name); 1757 return pad; 1758 } 1759 1760 priv->remote = subdev; 1761 priv->remote_pad = pad; 1762 1763 dev_dbg(priv->dev, "Bound %s pad: %d\n", subdev->name, pad); 1764 1765 return media_create_pad_link(&subdev->entity, pad, 1766 &priv->subdev.entity, 0, 1767 MEDIA_LNK_FL_ENABLED | 1768 MEDIA_LNK_FL_IMMUTABLE); 1769 } 1770 1771 static void rcsi2_notify_unbind(struct v4l2_async_notifier *notifier, 1772 struct v4l2_subdev *subdev, 1773 struct v4l2_async_connection *asc) 1774 { 1775 struct rcar_csi2 *priv = notifier_to_csi2(notifier); 1776 1777 priv->remote = NULL; 1778 1779 dev_dbg(priv->dev, "Unbind %s\n", subdev->name); 1780 } 1781 1782 static const struct v4l2_async_notifier_operations rcar_csi2_notify_ops = { 1783 .bound = rcsi2_notify_bound, 1784 .unbind = rcsi2_notify_unbind, 1785 }; 1786 1787 static int rcsi2_parse_v4l2(struct rcar_csi2 *priv, 1788 struct v4l2_fwnode_endpoint *vep) 1789 { 1790 unsigned int i; 1791 1792 /* Only port 0 endpoint 0 is valid. */ 1793 if (vep->base.port || vep->base.id) 1794 return -ENOTCONN; 1795 1796 priv->lanes = vep->bus.mipi_csi2.num_data_lanes; 1797 1798 switch (vep->bus_type) { 1799 case V4L2_MBUS_CSI2_DPHY: 1800 if (!priv->info->support_dphy) { 1801 dev_err(priv->dev, "D-PHY not supported\n"); 1802 return -EINVAL; 1803 } 1804 1805 if (priv->lanes != 1 && priv->lanes != 2 && priv->lanes != 4) { 1806 dev_err(priv->dev, 1807 "Unsupported number of data-lanes for D-PHY: %u\n", 1808 priv->lanes); 1809 return -EINVAL; 1810 } 1811 1812 priv->cphy = false; 1813 break; 1814 case V4L2_MBUS_CSI2_CPHY: 1815 if (!priv->info->support_cphy) { 1816 dev_err(priv->dev, "C-PHY not supported\n"); 1817 return -EINVAL; 1818 } 1819 1820 if (priv->lanes != 3) { 1821 dev_err(priv->dev, 1822 "Unsupported number of data-lanes for C-PHY: %u\n", 1823 priv->lanes); 1824 return -EINVAL; 1825 } 1826 1827 priv->cphy = true; 1828 break; 1829 default: 1830 dev_err(priv->dev, "Unsupported bus: %u\n", vep->bus_type); 1831 return -EINVAL; 1832 } 1833 1834 for (i = 0; i < ARRAY_SIZE(priv->lane_swap); i++) { 1835 priv->lane_swap[i] = i < priv->lanes ? 1836 vep->bus.mipi_csi2.data_lanes[i] : i; 1837 1838 /* Check for valid lane number. */ 1839 if (priv->lane_swap[i] < 1 || priv->lane_swap[i] > 4) { 1840 dev_err(priv->dev, "data-lanes must be in 1-4 range\n"); 1841 return -EINVAL; 1842 } 1843 } 1844 1845 for (i = 0; i < ARRAY_SIZE(priv->line_orders); i++) 1846 priv->line_orders[i] = vep->bus.mipi_csi2.line_orders[i]; 1847 1848 return 0; 1849 } 1850 1851 static int rcsi2_parse_dt(struct rcar_csi2 *priv) 1852 { 1853 struct v4l2_async_connection *asc; 1854 struct fwnode_handle *fwnode; 1855 struct fwnode_handle *ep; 1856 struct v4l2_fwnode_endpoint v4l2_ep = { 1857 .bus_type = V4L2_MBUS_UNKNOWN, 1858 }; 1859 int ret; 1860 1861 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(priv->dev), 0, 0, 0); 1862 if (!ep) { 1863 dev_err(priv->dev, "Not connected to subdevice\n"); 1864 return -EINVAL; 1865 } 1866 1867 ret = v4l2_fwnode_endpoint_parse(ep, &v4l2_ep); 1868 if (ret) { 1869 dev_err(priv->dev, "Could not parse v4l2 endpoint\n"); 1870 fwnode_handle_put(ep); 1871 return -EINVAL; 1872 } 1873 1874 ret = rcsi2_parse_v4l2(priv, &v4l2_ep); 1875 if (ret) { 1876 fwnode_handle_put(ep); 1877 return ret; 1878 } 1879 1880 fwnode = fwnode_graph_get_remote_endpoint(ep); 1881 fwnode_handle_put(ep); 1882 1883 dev_dbg(priv->dev, "Found '%pOF'\n", to_of_node(fwnode)); 1884 1885 v4l2_async_subdev_nf_init(&priv->notifier, &priv->subdev); 1886 priv->notifier.ops = &rcar_csi2_notify_ops; 1887 1888 asc = v4l2_async_nf_add_fwnode(&priv->notifier, fwnode, 1889 struct v4l2_async_connection); 1890 fwnode_handle_put(fwnode); 1891 if (IS_ERR(asc)) 1892 return PTR_ERR(asc); 1893 1894 ret = v4l2_async_nf_register(&priv->notifier); 1895 if (ret) 1896 v4l2_async_nf_cleanup(&priv->notifier); 1897 1898 return ret; 1899 } 1900 1901 /* ----------------------------------------------------------------------------- 1902 * PHTW initialization sequences. 1903 * 1904 * NOTE: Magic values are from the datasheet and lack documentation. 1905 */ 1906 1907 static int rcsi2_phtw_write_mbps(struct rcar_csi2 *priv, unsigned int mbps, 1908 const struct rcsi2_mbps_info *values, u8 code) 1909 { 1910 const struct rcsi2_mbps_info *info; 1911 1912 info = rcsi2_mbps_to_info(priv, values, mbps); 1913 if (!info) 1914 return -ERANGE; 1915 1916 return rcsi2_phtw_write(priv, info->reg, code); 1917 } 1918 1919 static int __rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, 1920 unsigned int mbps) 1921 { 1922 static const struct phtw_value step1[] = { 1923 { .data = 0xcc, .code = 0xe2 }, 1924 { .data = 0x01, .code = 0xe3 }, 1925 { .data = 0x11, .code = 0xe4 }, 1926 { .data = 0x01, .code = 0xe5 }, 1927 { .data = 0x10, .code = 0x04 }, 1928 }; 1929 1930 static const struct phtw_value step2[] = { 1931 { .data = 0x38, .code = 0x08 }, 1932 { .data = 0x01, .code = 0x00 }, 1933 { .data = 0x4b, .code = 0xac }, 1934 { .data = 0x03, .code = 0x00 }, 1935 { .data = 0x80, .code = 0x07 }, 1936 }; 1937 1938 int ret; 1939 1940 ret = rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1)); 1941 if (ret) 1942 return ret; 1943 1944 if (mbps != 0 && mbps <= 250) { 1945 ret = rcsi2_phtw_write(priv, 0x39, 0x05); 1946 if (ret) 1947 return ret; 1948 1949 ret = rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_h3_v3h_m3n, 1950 0xf1); 1951 if (ret) 1952 return ret; 1953 } 1954 1955 return rcsi2_phtw_write_array(priv, step2, ARRAY_SIZE(step2)); 1956 } 1957 1958 static int rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, unsigned int mbps) 1959 { 1960 return __rcsi2_init_phtw_h3_v3h_m3n(priv, mbps); 1961 } 1962 1963 static int rcsi2_init_phtw_h3es2(struct rcar_csi2 *priv, unsigned int mbps) 1964 { 1965 return __rcsi2_init_phtw_h3_v3h_m3n(priv, 0); 1966 } 1967 1968 static int rcsi2_init_phtw_v3m_e3(struct rcar_csi2 *priv, unsigned int mbps) 1969 { 1970 return rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3m_e3, 0x44); 1971 } 1972 1973 static int rcsi2_phy_post_init_v3m_e3(struct rcar_csi2 *priv) 1974 { 1975 static const struct phtw_value step1[] = { 1976 { .data = 0xee, .code = 0x34 }, 1977 { .data = 0xee, .code = 0x44 }, 1978 { .data = 0xee, .code = 0x54 }, 1979 { .data = 0xee, .code = 0x84 }, 1980 { .data = 0xee, .code = 0x94 }, 1981 }; 1982 1983 return rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1)); 1984 } 1985 1986 static int rcsi2_init_phtw_v3u(struct rcar_csi2 *priv, 1987 unsigned int mbps) 1988 { 1989 /* In case of 1500Mbps or less */ 1990 static const struct phtw_value step1[] = { 1991 { .data = 0xcc, .code = 0xe2 }, 1992 }; 1993 1994 static const struct phtw_value step2[] = { 1995 { .data = 0x01, .code = 0xe3 }, 1996 { .data = 0x11, .code = 0xe4 }, 1997 { .data = 0x01, .code = 0xe5 }, 1998 }; 1999 2000 /* In case of 1500Mbps or less */ 2001 static const struct phtw_value step3[] = { 2002 { .data = 0x38, .code = 0x08 }, 2003 }; 2004 2005 static const struct phtw_value step4[] = { 2006 { .data = 0x01, .code = 0x00 }, 2007 { .data = 0x4b, .code = 0xac }, 2008 { .data = 0x03, .code = 0x00 }, 2009 { .data = 0x80, .code = 0x07 }, 2010 }; 2011 2012 int ret; 2013 2014 if (mbps != 0 && mbps <= 1500) 2015 ret = rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1)); 2016 else 2017 ret = rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3u, 0xe2); 2018 if (ret) 2019 return ret; 2020 2021 ret = rcsi2_phtw_write_array(priv, step2, ARRAY_SIZE(step2)); 2022 if (ret) 2023 return ret; 2024 2025 if (mbps != 0 && mbps <= 1500) { 2026 ret = rcsi2_phtw_write_array(priv, step3, ARRAY_SIZE(step3)); 2027 if (ret) 2028 return ret; 2029 } 2030 2031 ret = rcsi2_phtw_write_array(priv, step4, ARRAY_SIZE(step4)); 2032 if (ret) 2033 return ret; 2034 2035 return ret; 2036 } 2037 2038 /* ----------------------------------------------------------------------------- 2039 * Platform Device Driver. 2040 */ 2041 2042 static int rcsi2_link_setup(struct media_entity *entity, 2043 const struct media_pad *local, 2044 const struct media_pad *remote, u32 flags) 2045 { 2046 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity); 2047 struct rcar_csi2 *priv = sd_to_csi2(sd); 2048 struct video_device *vdev; 2049 int channel, vc; 2050 u32 id; 2051 2052 if (!is_media_entity_v4l2_video_device(remote->entity)) { 2053 dev_err(priv->dev, "Remote is not a video device\n"); 2054 return -EINVAL; 2055 } 2056 2057 vdev = media_entity_to_video_device(remote->entity); 2058 2059 if (of_property_read_u32(vdev->dev_parent->of_node, "renesas,id", &id)) { 2060 dev_err(priv->dev, "No renesas,id, can't configure routing\n"); 2061 return -EINVAL; 2062 } 2063 2064 channel = id % 4; 2065 2066 if (flags & MEDIA_LNK_FL_ENABLED) { 2067 if (media_pad_remote_pad_first(local)) { 2068 dev_dbg(priv->dev, 2069 "Each VC can only be routed to one output channel\n"); 2070 return -EINVAL; 2071 } 2072 2073 vc = local->index - 1; 2074 2075 dev_dbg(priv->dev, "Route VC%d to VIN%u on output channel %d\n", 2076 vc, id, channel); 2077 } else { 2078 vc = -1; 2079 } 2080 2081 priv->channel_vc[channel] = vc; 2082 2083 return 0; 2084 } 2085 2086 static const struct media_entity_operations rcar_csi2_entity_ops = { 2087 .link_setup = rcsi2_link_setup, 2088 .link_validate = v4l2_subdev_link_validate, 2089 }; 2090 2091 static int rcsi2_probe_resources(struct rcar_csi2 *priv, 2092 struct platform_device *pdev) 2093 { 2094 int irq, ret; 2095 2096 priv->base = devm_platform_ioremap_resource(pdev, 0); 2097 if (IS_ERR(priv->base)) 2098 return PTR_ERR(priv->base); 2099 2100 irq = platform_get_irq(pdev, 0); 2101 if (irq < 0) 2102 return irq; 2103 2104 ret = devm_request_threaded_irq(&pdev->dev, irq, rcsi2_irq, 2105 rcsi2_irq_thread, IRQF_SHARED, 2106 KBUILD_MODNAME, priv); 2107 if (ret) 2108 return ret; 2109 2110 priv->rstc = devm_reset_control_get(&pdev->dev, NULL); 2111 2112 return PTR_ERR_OR_ZERO(priv->rstc); 2113 } 2114 2115 static const struct rcsi2_register_layout rcsi2_registers_gen3 = { 2116 .phtw = PHTW_REG, 2117 .phypll = PHYPLL_REG, 2118 }; 2119 2120 static const struct rcar_csi2_info rcar_csi2_info_r8a7795 = { 2121 .regs = &rcsi2_registers_gen3, 2122 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n, 2123 .start_receiver = rcsi2_start_receiver_gen3, 2124 .enter_standby = rcsi2_enter_standby_gen3, 2125 .hsfreqrange = hsfreqrange_h3_v3h_m3n, 2126 .csi0clkfreqrange = 0x20, 2127 .num_channels = 4, 2128 .clear_ulps = true, 2129 .support_dphy = true, 2130 }; 2131 2132 static const struct rcar_csi2_info rcar_csi2_info_r8a7795es2 = { 2133 .regs = &rcsi2_registers_gen3, 2134 .init_phtw = rcsi2_init_phtw_h3es2, 2135 .start_receiver = rcsi2_start_receiver_gen3, 2136 .enter_standby = rcsi2_enter_standby_gen3, 2137 .hsfreqrange = hsfreqrange_h3_v3h_m3n, 2138 .csi0clkfreqrange = 0x20, 2139 .num_channels = 4, 2140 .clear_ulps = true, 2141 .support_dphy = true, 2142 }; 2143 2144 static const struct rcar_csi2_info rcar_csi2_info_r8a7796 = { 2145 .regs = &rcsi2_registers_gen3, 2146 .start_receiver = rcsi2_start_receiver_gen3, 2147 .enter_standby = rcsi2_enter_standby_gen3, 2148 .hsfreqrange = hsfreqrange_m3w, 2149 .num_channels = 4, 2150 .support_dphy = true, 2151 }; 2152 2153 static const struct rcar_csi2_info rcar_csi2_info_r8a77961 = { 2154 .regs = &rcsi2_registers_gen3, 2155 .start_receiver = rcsi2_start_receiver_gen3, 2156 .enter_standby = rcsi2_enter_standby_gen3, 2157 .hsfreqrange = hsfreqrange_m3w, 2158 .num_channels = 4, 2159 .support_dphy = true, 2160 }; 2161 2162 static const struct rcar_csi2_info rcar_csi2_info_r8a77965 = { 2163 .regs = &rcsi2_registers_gen3, 2164 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n, 2165 .start_receiver = rcsi2_start_receiver_gen3, 2166 .enter_standby = rcsi2_enter_standby_gen3, 2167 .hsfreqrange = hsfreqrange_h3_v3h_m3n, 2168 .csi0clkfreqrange = 0x20, 2169 .num_channels = 4, 2170 .clear_ulps = true, 2171 .support_dphy = true, 2172 }; 2173 2174 static const struct rcar_csi2_info rcar_csi2_info_r8a77970 = { 2175 .regs = &rcsi2_registers_gen3, 2176 .init_phtw = rcsi2_init_phtw_v3m_e3, 2177 .phy_post_init = rcsi2_phy_post_init_v3m_e3, 2178 .start_receiver = rcsi2_start_receiver_gen3, 2179 .enter_standby = rcsi2_enter_standby_gen3, 2180 .num_channels = 4, 2181 .support_dphy = true, 2182 }; 2183 2184 static const struct rcar_csi2_info rcar_csi2_info_r8a77980 = { 2185 .regs = &rcsi2_registers_gen3, 2186 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n, 2187 .start_receiver = rcsi2_start_receiver_gen3, 2188 .enter_standby = rcsi2_enter_standby_gen3, 2189 .hsfreqrange = hsfreqrange_h3_v3h_m3n, 2190 .csi0clkfreqrange = 0x20, 2191 .clear_ulps = true, 2192 .support_dphy = true, 2193 }; 2194 2195 static const struct rcar_csi2_info rcar_csi2_info_r8a77990 = { 2196 .regs = &rcsi2_registers_gen3, 2197 .init_phtw = rcsi2_init_phtw_v3m_e3, 2198 .phy_post_init = rcsi2_phy_post_init_v3m_e3, 2199 .start_receiver = rcsi2_start_receiver_gen3, 2200 .enter_standby = rcsi2_enter_standby_gen3, 2201 .num_channels = 2, 2202 .support_dphy = true, 2203 }; 2204 2205 static const struct rcar_csi2_info rcar_csi2_info_r8a779a0 = { 2206 .regs = &rcsi2_registers_gen3, 2207 .init_phtw = rcsi2_init_phtw_v3u, 2208 .start_receiver = rcsi2_start_receiver_gen3, 2209 .enter_standby = rcsi2_enter_standby_gen3, 2210 .hsfreqrange = hsfreqrange_v3u, 2211 .csi0clkfreqrange = 0x20, 2212 .clear_ulps = true, 2213 .use_isp = true, 2214 .support_dphy = true, 2215 }; 2216 2217 static const struct rcar_csi2_info rcar_csi2_info_r8a779g0 = { 2218 .regs = &rcsi2_registers_gen3, 2219 .start_receiver = rcsi2_start_receiver_v4h, 2220 .use_isp = true, 2221 .support_cphy = true, 2222 }; 2223 2224 static const struct rcsi2_register_layout rcsi2_registers_v4m = { 2225 .phtw = V4M_PHTW_REG, 2226 .phypll = V4M_PHYPLL_REG, 2227 }; 2228 2229 static const struct rcar_csi2_info rcar_csi2_info_r8a779h0 = { 2230 .regs = &rcsi2_registers_v4m, 2231 .start_receiver = rcsi2_start_receiver_v4m, 2232 .hsfreqrange = hsfreqrange_v4m, 2233 .csi0clkfreqrange = 0x0c, 2234 .use_isp = true, 2235 .support_dphy = true, 2236 }; 2237 2238 static const struct of_device_id rcar_csi2_of_table[] = { 2239 { 2240 .compatible = "renesas,r8a774a1-csi2", 2241 .data = &rcar_csi2_info_r8a7796, 2242 }, 2243 { 2244 .compatible = "renesas,r8a774b1-csi2", 2245 .data = &rcar_csi2_info_r8a77965, 2246 }, 2247 { 2248 .compatible = "renesas,r8a774c0-csi2", 2249 .data = &rcar_csi2_info_r8a77990, 2250 }, 2251 { 2252 .compatible = "renesas,r8a774e1-csi2", 2253 .data = &rcar_csi2_info_r8a7795, 2254 }, 2255 { 2256 .compatible = "renesas,r8a7795-csi2", 2257 .data = &rcar_csi2_info_r8a7795, 2258 }, 2259 { 2260 .compatible = "renesas,r8a7796-csi2", 2261 .data = &rcar_csi2_info_r8a7796, 2262 }, 2263 { 2264 .compatible = "renesas,r8a77961-csi2", 2265 .data = &rcar_csi2_info_r8a77961, 2266 }, 2267 { 2268 .compatible = "renesas,r8a77965-csi2", 2269 .data = &rcar_csi2_info_r8a77965, 2270 }, 2271 { 2272 .compatible = "renesas,r8a77970-csi2", 2273 .data = &rcar_csi2_info_r8a77970, 2274 }, 2275 { 2276 .compatible = "renesas,r8a77980-csi2", 2277 .data = &rcar_csi2_info_r8a77980, 2278 }, 2279 { 2280 .compatible = "renesas,r8a77990-csi2", 2281 .data = &rcar_csi2_info_r8a77990, 2282 }, 2283 { 2284 .compatible = "renesas,r8a779a0-csi2", 2285 .data = &rcar_csi2_info_r8a779a0, 2286 }, 2287 { 2288 .compatible = "renesas,r8a779g0-csi2", 2289 .data = &rcar_csi2_info_r8a779g0, 2290 }, 2291 { 2292 .compatible = "renesas,r8a779h0-csi2", 2293 .data = &rcar_csi2_info_r8a779h0, 2294 }, 2295 { /* sentinel */ }, 2296 }; 2297 MODULE_DEVICE_TABLE(of, rcar_csi2_of_table); 2298 2299 static const struct soc_device_attribute r8a7795[] = { 2300 { 2301 .soc_id = "r8a7795", .revision = "ES2.*", 2302 .data = &rcar_csi2_info_r8a7795es2, 2303 }, 2304 { /* sentinel */ } 2305 }; 2306 2307 static int rcsi2_probe(struct platform_device *pdev) 2308 { 2309 const struct soc_device_attribute *attr; 2310 struct rcar_csi2 *priv; 2311 unsigned int i, num_pads; 2312 int ret; 2313 2314 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 2315 if (!priv) 2316 return -ENOMEM; 2317 2318 priv->info = of_device_get_match_data(&pdev->dev); 2319 2320 /* 2321 * The different ES versions of r8a7795 (H3) behave differently but 2322 * share the same compatible string. 2323 */ 2324 attr = soc_device_match(r8a7795); 2325 if (attr) 2326 priv->info = attr->data; 2327 2328 priv->dev = &pdev->dev; 2329 2330 priv->stream_count = 0; 2331 2332 ret = rcsi2_probe_resources(priv, pdev); 2333 if (ret) { 2334 dev_err(priv->dev, "Failed to get resources\n"); 2335 return ret; 2336 } 2337 2338 platform_set_drvdata(pdev, priv); 2339 2340 ret = rcsi2_parse_dt(priv); 2341 if (ret) 2342 return ret; 2343 2344 priv->subdev.owner = THIS_MODULE; 2345 priv->subdev.dev = &pdev->dev; 2346 priv->subdev.internal_ops = &rcar_csi2_internal_ops; 2347 v4l2_subdev_init(&priv->subdev, &rcar_csi2_subdev_ops); 2348 v4l2_set_subdevdata(&priv->subdev, &pdev->dev); 2349 snprintf(priv->subdev.name, sizeof(priv->subdev.name), "%s %s", 2350 KBUILD_MODNAME, dev_name(&pdev->dev)); 2351 priv->subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE; 2352 2353 priv->subdev.entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER; 2354 priv->subdev.entity.ops = &rcar_csi2_entity_ops; 2355 2356 num_pads = rcsi2_num_pads(priv); 2357 2358 priv->pads[RCAR_CSI2_SINK].flags = MEDIA_PAD_FL_SINK; 2359 for (i = RCAR_CSI2_SOURCE_VC0; i < num_pads; i++) 2360 priv->pads[i].flags = MEDIA_PAD_FL_SOURCE; 2361 2362 ret = media_entity_pads_init(&priv->subdev.entity, num_pads, 2363 priv->pads); 2364 if (ret) 2365 goto error_async; 2366 2367 for (i = 0; i < ARRAY_SIZE(priv->channel_vc); i++) 2368 priv->channel_vc[i] = -1; 2369 2370 pm_runtime_enable(&pdev->dev); 2371 2372 ret = v4l2_subdev_init_finalize(&priv->subdev); 2373 if (ret) 2374 goto error_pm_runtime; 2375 2376 ret = v4l2_async_register_subdev(&priv->subdev); 2377 if (ret < 0) 2378 goto error_subdev; 2379 2380 dev_info(priv->dev, "%d lanes found\n", priv->lanes); 2381 2382 return 0; 2383 2384 error_subdev: 2385 v4l2_subdev_cleanup(&priv->subdev); 2386 error_pm_runtime: 2387 pm_runtime_disable(&pdev->dev); 2388 error_async: 2389 v4l2_async_nf_unregister(&priv->notifier); 2390 v4l2_async_nf_cleanup(&priv->notifier); 2391 2392 return ret; 2393 } 2394 2395 static void rcsi2_remove(struct platform_device *pdev) 2396 { 2397 struct rcar_csi2 *priv = platform_get_drvdata(pdev); 2398 2399 v4l2_async_nf_unregister(&priv->notifier); 2400 v4l2_async_nf_cleanup(&priv->notifier); 2401 v4l2_async_unregister_subdev(&priv->subdev); 2402 v4l2_subdev_cleanup(&priv->subdev); 2403 2404 pm_runtime_disable(&pdev->dev); 2405 } 2406 2407 static struct platform_driver rcar_csi2_pdrv = { 2408 .remove = rcsi2_remove, 2409 .probe = rcsi2_probe, 2410 .driver = { 2411 .name = "rcar-csi2", 2412 .suppress_bind_attrs = true, 2413 .of_match_table = rcar_csi2_of_table, 2414 }, 2415 }; 2416 2417 module_platform_driver(rcar_csi2_pdrv); 2418 2419 MODULE_AUTHOR("Niklas Söderlund <niklas.soderlund@ragnatech.se>"); 2420 MODULE_DESCRIPTION("Renesas R-Car MIPI CSI-2 receiver driver"); 2421 MODULE_LICENSE("GPL"); 2422