1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 static struct platform_inst_fw_cap inst_fw_cap_qcs8300[] = { 7 { 8 .cap_id = PROFILE, 9 .min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, 10 .max = V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH, 11 .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) | 12 BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH) | 13 BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) | 14 BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) | 15 BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH), 16 .value = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, 17 .hfi_id = HFI_PROP_PROFILE, 18 .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, 19 .set = iris_set_u32_enum, 20 }, 21 { 22 .cap_id = LEVEL, 23 .min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0, 24 .max = V4L2_MPEG_VIDEO_H264_LEVEL_6_2, 25 .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) | 26 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) | 27 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) | 28 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) | 29 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) | 30 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) | 31 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) | 32 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) | 33 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) | 34 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) | 35 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) | 36 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) | 37 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) | 38 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) | 39 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) | 40 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) | 41 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2) | 42 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_0) | 43 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_1) | 44 BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_2), 45 .value = V4L2_MPEG_VIDEO_H264_LEVEL_6_1, 46 .hfi_id = HFI_PROP_LEVEL, 47 .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, 48 .set = iris_set_u32_enum, 49 }, 50 { 51 .cap_id = INPUT_BUF_HOST_MAX_COUNT, 52 .min = DEFAULT_MAX_HOST_BUF_COUNT, 53 .max = DEFAULT_MAX_HOST_BURST_BUF_COUNT, 54 .step_or_mask = 1, 55 .value = DEFAULT_MAX_HOST_BUF_COUNT, 56 .hfi_id = HFI_PROP_BUFFER_HOST_MAX_COUNT, 57 .flags = CAP_FLAG_INPUT_PORT, 58 .set = iris_set_u32, 59 }, 60 { 61 .cap_id = STAGE, 62 .min = STAGE_1, 63 .max = STAGE_2, 64 .step_or_mask = 1, 65 .value = STAGE_2, 66 .hfi_id = HFI_PROP_STAGE, 67 .set = iris_set_stage, 68 }, 69 { 70 .cap_id = PIPE, 71 .min = PIPE_1, 72 .max = PIPE_2, 73 .step_or_mask = 1, 74 .value = PIPE_2, 75 .hfi_id = HFI_PROP_PIPE, 76 .set = iris_set_pipe, 77 }, 78 { 79 .cap_id = POC, 80 .min = 0, 81 .max = 2, 82 .step_or_mask = 1, 83 .value = 1, 84 .hfi_id = HFI_PROP_PIC_ORDER_CNT_TYPE, 85 }, 86 { 87 .cap_id = CODED_FRAMES, 88 .min = CODED_FRAMES_PROGRESSIVE, 89 .max = CODED_FRAMES_PROGRESSIVE, 90 .step_or_mask = 0, 91 .value = CODED_FRAMES_PROGRESSIVE, 92 .hfi_id = HFI_PROP_CODED_FRAMES, 93 }, 94 { 95 .cap_id = BIT_DEPTH, 96 .min = BIT_DEPTH_8, 97 .max = BIT_DEPTH_8, 98 .step_or_mask = 1, 99 .value = BIT_DEPTH_8, 100 .hfi_id = HFI_PROP_LUMA_CHROMA_BIT_DEPTH, 101 }, 102 { 103 .cap_id = RAP_FRAME, 104 .min = 0, 105 .max = 1, 106 .step_or_mask = 1, 107 .value = 1, 108 .hfi_id = HFI_PROP_DEC_START_FROM_RAP_FRAME, 109 .flags = CAP_FLAG_INPUT_PORT, 110 .set = iris_set_u32, 111 }, 112 }; 113 114 static struct platform_inst_caps platform_inst_cap_qcs8300 = { 115 .min_frame_width = 96, 116 .max_frame_width = 4096, 117 .min_frame_height = 96, 118 .max_frame_height = 4096, 119 .max_mbpf = (4096 * 2176) / 256, 120 .mb_cycles_vpp = 200, 121 .mb_cycles_fw = 326389, 122 .mb_cycles_fw_vpp = 44156, 123 .num_comv = 0, 124 }; 125