133be1ddeSDikshita Agarwal /* SPDX-License-Identifier: GPL-2.0-only */ 233be1ddeSDikshita Agarwal /* 333be1ddeSDikshita Agarwal * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. 433be1ddeSDikshita Agarwal */ 533be1ddeSDikshita Agarwal 633be1ddeSDikshita Agarwal #ifndef __IRIS_CTRLS_H__ 733be1ddeSDikshita Agarwal #define __IRIS_CTRLS_H__ 833be1ddeSDikshita Agarwal 933be1ddeSDikshita Agarwal #include "iris_platform_common.h" 1033be1ddeSDikshita Agarwal 1133be1ddeSDikshita Agarwal struct iris_core; 1233be1ddeSDikshita Agarwal struct iris_inst; 1333be1ddeSDikshita Agarwal 1433be1ddeSDikshita Agarwal int iris_ctrls_init(struct iris_inst *inst); 1533be1ddeSDikshita Agarwal void iris_session_init_caps(struct iris_core *core); 16*3a19d7b9SVedang Nagar int iris_set_u32_enum(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id); 17*3a19d7b9SVedang Nagar int iris_set_stage(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id); 18*3a19d7b9SVedang Nagar int iris_set_pipe(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id); 19*3a19d7b9SVedang Nagar int iris_set_u32(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id); 20*3a19d7b9SVedang Nagar int iris_set_properties(struct iris_inst *inst, u32 plane); 2133be1ddeSDikshita Agarwal 2233be1ddeSDikshita Agarwal #endif 23