1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * camss-vfe-4-1.c 4 * 5 * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v4.1 6 * 7 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 8 * Copyright (C) 2015-2018 Linaro Ltd. 9 */ 10 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 15 #include "camss.h" 16 #include "camss-vfe.h" 17 #include "camss-vfe-gen1.h" 18 19 #define VFE_0_HW_VERSION 0x000 20 21 #define VFE_0_GLOBAL_RESET_CMD 0x00c 22 #define VFE_0_GLOBAL_RESET_CMD_CORE BIT(0) 23 #define VFE_0_GLOBAL_RESET_CMD_CAMIF BIT(1) 24 #define VFE_0_GLOBAL_RESET_CMD_BUS BIT(2) 25 #define VFE_0_GLOBAL_RESET_CMD_BUS_BDG BIT(3) 26 #define VFE_0_GLOBAL_RESET_CMD_REGISTER BIT(4) 27 #define VFE_0_GLOBAL_RESET_CMD_TIMER BIT(5) 28 #define VFE_0_GLOBAL_RESET_CMD_PM BIT(6) 29 #define VFE_0_GLOBAL_RESET_CMD_BUS_MISR BIT(7) 30 #define VFE_0_GLOBAL_RESET_CMD_TESTGEN BIT(8) 31 32 #define VFE_0_MODULE_CFG 0x018 33 #define VFE_0_MODULE_CFG_DEMUX BIT(2) 34 #define VFE_0_MODULE_CFG_CHROMA_UPSAMPLE BIT(3) 35 #define VFE_0_MODULE_CFG_SCALE_ENC BIT(23) 36 #define VFE_0_MODULE_CFG_CROP_ENC BIT(27) 37 38 #define VFE_0_CORE_CFG 0x01c 39 #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCBYCR 0x4 40 #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCRYCB 0x5 41 #define VFE_0_CORE_CFG_PIXEL_PATTERN_CBYCRY 0x6 42 #define VFE_0_CORE_CFG_PIXEL_PATTERN_CRYCBY 0x7 43 44 #define VFE_0_IRQ_CMD 0x024 45 #define VFE_0_IRQ_CMD_GLOBAL_CLEAR BIT(0) 46 47 #define VFE_0_IRQ_MASK_0 0x028 48 #define VFE_0_IRQ_MASK_0_CAMIF_SOF BIT(0) 49 #define VFE_0_IRQ_MASK_0_CAMIF_EOF BIT(1) 50 #define VFE_0_IRQ_MASK_0_RDIn_REG_UPDATE(n) BIT((n) + 5) 51 #define VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(n) \ 52 ((n) == VFE_LINE_PIX ? BIT(4) : VFE_0_IRQ_MASK_0_RDIn_REG_UPDATE(n)) 53 #define VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(n) BIT((n) + 8) 54 #define VFE_0_IRQ_MASK_0_IMAGE_COMPOSITE_DONE_n(n) BIT((n) + 25) 55 #define VFE_0_IRQ_MASK_0_RESET_ACK BIT(31) 56 #define VFE_0_IRQ_MASK_1 0x02c 57 #define VFE_0_IRQ_MASK_1_CAMIF_ERROR BIT(0) 58 #define VFE_0_IRQ_MASK_1_VIOLATION BIT(7) 59 #define VFE_0_IRQ_MASK_1_BUS_BDG_HALT_ACK BIT(8) 60 #define VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(n) BIT((n) + 9) 61 #define VFE_0_IRQ_MASK_1_RDIn_SOF(n) BIT((n) + 29) 62 63 #define VFE_0_IRQ_CLEAR_0 0x030 64 #define VFE_0_IRQ_CLEAR_1 0x034 65 66 #define VFE_0_IRQ_STATUS_0 0x038 67 #define VFE_0_IRQ_STATUS_0_CAMIF_SOF BIT(0) 68 #define VFE_0_IRQ_STATUS_0_RDIn_REG_UPDATE(n) BIT((n) + 5) 69 #define VFE_0_IRQ_STATUS_0_line_n_REG_UPDATE(n) \ 70 ((n) == VFE_LINE_PIX ? BIT(4) : VFE_0_IRQ_STATUS_0_RDIn_REG_UPDATE(n)) 71 #define VFE_0_IRQ_STATUS_0_IMAGE_MASTER_n_PING_PONG(n) BIT((n) + 8) 72 #define VFE_0_IRQ_STATUS_0_IMAGE_COMPOSITE_DONE_n(n) BIT((n) + 25) 73 #define VFE_0_IRQ_STATUS_0_RESET_ACK BIT(31) 74 #define VFE_0_IRQ_STATUS_1 0x03c 75 #define VFE_0_IRQ_STATUS_1_VIOLATION BIT(7) 76 #define VFE_0_IRQ_STATUS_1_BUS_BDG_HALT_ACK BIT(8) 77 #define VFE_0_IRQ_STATUS_1_RDIn_SOF(n) BIT((n) + 29) 78 79 #define VFE_0_IRQ_COMPOSITE_MASK_0 0x40 80 #define VFE_0_VIOLATION_STATUS 0x48 81 82 #define VFE_0_BUS_CMD 0x4c 83 #define VFE_0_BUS_CMD_Mx_RLD_CMD(x) BIT(x) 84 85 #define VFE_0_BUS_CFG 0x050 86 87 #define VFE_0_BUS_XBAR_CFG_x(x) (0x58 + 0x4 * ((x) / 2)) 88 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN BIT(1) 89 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA (0x3 << 4) 90 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT 8 91 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_LUMA 0 92 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 5 93 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 6 94 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 7 95 96 #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(n) (0x06c + 0x24 * (n)) 97 #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT 0 98 #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_FRM_BASED_SHIFT 1 99 #define VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(n) (0x070 + 0x24 * (n)) 100 #define VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(n) (0x074 + 0x24 * (n)) 101 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(n) (0x078 + 0x24 * (n)) 102 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_SHIFT 2 103 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK (0x1f << 2) 104 105 #define VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(n) (0x07c + 0x24 * (n)) 106 #define VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG_OFFSET_SHIFT 16 107 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(n) (0x080 + 0x24 * (n)) 108 #define VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(n) (0x084 + 0x24 * (n)) 109 #define VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(n) \ 110 (0x088 + 0x24 * (n)) 111 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN(n) \ 112 (0x08c + 0x24 * (n)) 113 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF 0xffffffff 114 115 #define VFE_0_BUS_PING_PONG_STATUS 0x268 116 117 #define VFE_0_BUS_BDG_CMD 0x2c0 118 #define VFE_0_BUS_BDG_CMD_HALT_REQ 1 119 120 #define VFE_0_BUS_BDG_QOS_CFG_0 0x2c4 121 #define VFE_0_BUS_BDG_QOS_CFG_0_CFG 0xaaa5aaa5 122 #define VFE_0_BUS_BDG_QOS_CFG_1 0x2c8 123 #define VFE_0_BUS_BDG_QOS_CFG_2 0x2cc 124 #define VFE_0_BUS_BDG_QOS_CFG_3 0x2d0 125 #define VFE_0_BUS_BDG_QOS_CFG_4 0x2d4 126 #define VFE_0_BUS_BDG_QOS_CFG_5 0x2d8 127 #define VFE_0_BUS_BDG_QOS_CFG_6 0x2dc 128 #define VFE_0_BUS_BDG_QOS_CFG_7 0x2e0 129 #define VFE_0_BUS_BDG_QOS_CFG_7_CFG 0x0001aaa5 130 131 #define VFE_0_RDI_CFG_x(x) (0x2e8 + (0x4 * (x))) 132 #define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_SHIFT 28 133 #define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_MASK (0xf << 28) 134 #define VFE_0_RDI_CFG_x_RDI_M0_SEL_SHIFT 4 135 #define VFE_0_RDI_CFG_x_RDI_M0_SEL_MASK (0xf << 4) 136 #define VFE_0_RDI_CFG_x_RDI_EN_BIT BIT(2) 137 #define VFE_0_RDI_CFG_x_MIPI_EN_BITS 0x3 138 #define VFE_0_RDI_CFG_x_RDI_Mr_FRAME_BASED_EN(r) BIT(16 + (r)) 139 140 #define VFE_0_CAMIF_CMD 0x2f4 141 #define VFE_0_CAMIF_CMD_DISABLE_FRAME_BOUNDARY 0 142 #define VFE_0_CAMIF_CMD_ENABLE_FRAME_BOUNDARY 1 143 #define VFE_0_CAMIF_CMD_NO_CHANGE 3 144 #define VFE_0_CAMIF_CMD_CLEAR_CAMIF_STATUS BIT(2) 145 #define VFE_0_CAMIF_CFG 0x2f8 146 #define VFE_0_CAMIF_CFG_VFE_OUTPUT_EN BIT(6) 147 #define VFE_0_CAMIF_FRAME_CFG 0x300 148 #define VFE_0_CAMIF_WINDOW_WIDTH_CFG 0x304 149 #define VFE_0_CAMIF_WINDOW_HEIGHT_CFG 0x308 150 #define VFE_0_CAMIF_SUBSAMPLE_CFG_0 0x30c 151 #define VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN 0x314 152 #define VFE_0_CAMIF_STATUS 0x31c 153 #define VFE_0_CAMIF_STATUS_HALT BIT(31) 154 155 #define VFE_0_REG_UPDATE 0x378 156 #define VFE_0_REG_UPDATE_RDIn(n) BIT(1 + (n)) 157 #define VFE_0_REG_UPDATE_line_n(n) \ 158 ((n) == VFE_LINE_PIX ? 1 : VFE_0_REG_UPDATE_RDIn(n)) 159 160 #define VFE_0_DEMUX_CFG 0x424 161 #define VFE_0_DEMUX_CFG_PERIOD 0x3 162 #define VFE_0_DEMUX_GAIN_0 0x428 163 #define VFE_0_DEMUX_GAIN_0_CH0_EVEN (0x80 << 0) 164 #define VFE_0_DEMUX_GAIN_0_CH0_ODD (0x80 << 16) 165 #define VFE_0_DEMUX_GAIN_1 0x42c 166 #define VFE_0_DEMUX_GAIN_1_CH1 (0x80 << 0) 167 #define VFE_0_DEMUX_GAIN_1_CH2 (0x80 << 16) 168 #define VFE_0_DEMUX_EVEN_CFG 0x438 169 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_YUYV 0x9cac 170 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_YVYU 0xac9c 171 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_UYVY 0xc9ca 172 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_VYUY 0xcac9 173 #define VFE_0_DEMUX_ODD_CFG 0x43c 174 #define VFE_0_DEMUX_ODD_CFG_PATTERN_YUYV 0x9cac 175 #define VFE_0_DEMUX_ODD_CFG_PATTERN_YVYU 0xac9c 176 #define VFE_0_DEMUX_ODD_CFG_PATTERN_UYVY 0xc9ca 177 #define VFE_0_DEMUX_ODD_CFG_PATTERN_VYUY 0xcac9 178 179 #define VFE_0_SCALE_ENC_Y_CFG 0x75c 180 #define VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE 0x760 181 #define VFE_0_SCALE_ENC_Y_H_PHASE 0x764 182 #define VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE 0x76c 183 #define VFE_0_SCALE_ENC_Y_V_PHASE 0x770 184 #define VFE_0_SCALE_ENC_CBCR_CFG 0x778 185 #define VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE 0x77c 186 #define VFE_0_SCALE_ENC_CBCR_H_PHASE 0x780 187 #define VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE 0x790 188 #define VFE_0_SCALE_ENC_CBCR_V_PHASE 0x794 189 190 #define VFE_0_CROP_ENC_Y_WIDTH 0x854 191 #define VFE_0_CROP_ENC_Y_HEIGHT 0x858 192 #define VFE_0_CROP_ENC_CBCR_WIDTH 0x85c 193 #define VFE_0_CROP_ENC_CBCR_HEIGHT 0x860 194 195 #define VFE_0_CLAMP_ENC_MAX_CFG 0x874 196 #define VFE_0_CLAMP_ENC_MAX_CFG_CH0 (0xff << 0) 197 #define VFE_0_CLAMP_ENC_MAX_CFG_CH1 (0xff << 8) 198 #define VFE_0_CLAMP_ENC_MAX_CFG_CH2 (0xff << 16) 199 #define VFE_0_CLAMP_ENC_MIN_CFG 0x878 200 #define VFE_0_CLAMP_ENC_MIN_CFG_CH0 (0x0 << 0) 201 #define VFE_0_CLAMP_ENC_MIN_CFG_CH1 (0x0 << 8) 202 #define VFE_0_CLAMP_ENC_MIN_CFG_CH2 (0x0 << 16) 203 204 #define VFE_0_CGC_OVERRIDE_1 0x974 205 #define VFE_0_CGC_OVERRIDE_1_IMAGE_Mx_CGC_OVERRIDE(x) BIT(x) 206 207 #define CAMIF_TIMEOUT_SLEEP_US 1000 208 #define CAMIF_TIMEOUT_ALL_US 1000000 209 210 #define MSM_VFE_VFE0_UB_SIZE 1023 211 #define MSM_VFE_VFE0_UB_SIZE_RDI (MSM_VFE_VFE0_UB_SIZE / 3) 212 213 static u16 vfe_get_ub_size(u8 vfe_id) 214 { 215 if (vfe_id == 0) 216 return MSM_VFE_VFE0_UB_SIZE_RDI; 217 218 return 0; 219 } 220 221 static inline void vfe_reg_clr(struct vfe_device *vfe, u32 reg, u32 clr_bits) 222 { 223 u32 bits = readl_relaxed(vfe->base + reg); 224 225 writel_relaxed(bits & ~clr_bits, vfe->base + reg); 226 } 227 228 static inline void vfe_reg_set(struct vfe_device *vfe, u32 reg, u32 set_bits) 229 { 230 u32 bits = readl_relaxed(vfe->base + reg); 231 232 writel_relaxed(bits | set_bits, vfe->base + reg); 233 } 234 235 static void vfe_global_reset(struct vfe_device *vfe) 236 { 237 u32 reset_bits = VFE_0_GLOBAL_RESET_CMD_TESTGEN | 238 VFE_0_GLOBAL_RESET_CMD_BUS_MISR | 239 VFE_0_GLOBAL_RESET_CMD_PM | 240 VFE_0_GLOBAL_RESET_CMD_TIMER | 241 VFE_0_GLOBAL_RESET_CMD_REGISTER | 242 VFE_0_GLOBAL_RESET_CMD_BUS_BDG | 243 VFE_0_GLOBAL_RESET_CMD_BUS | 244 VFE_0_GLOBAL_RESET_CMD_CAMIF | 245 VFE_0_GLOBAL_RESET_CMD_CORE; 246 247 writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD); 248 } 249 250 static void vfe_halt_request(struct vfe_device *vfe) 251 { 252 writel_relaxed(VFE_0_BUS_BDG_CMD_HALT_REQ, 253 vfe->base + VFE_0_BUS_BDG_CMD); 254 } 255 256 static void vfe_halt_clear(struct vfe_device *vfe) 257 { 258 writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD); 259 } 260 261 static void vfe_wm_enable(struct vfe_device *vfe, u8 wm, u8 enable) 262 { 263 if (enable) 264 vfe_reg_set(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), 265 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT); 266 else 267 vfe_reg_clr(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), 268 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT); 269 } 270 271 static void vfe_wm_frame_based(struct vfe_device *vfe, u8 wm, u8 enable) 272 { 273 if (enable) 274 vfe_reg_set(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), 275 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_FRM_BASED_SHIFT); 276 else 277 vfe_reg_clr(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), 278 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_FRM_BASED_SHIFT); 279 } 280 281 static void vfe_get_wm_sizes(struct v4l2_pix_format_mplane *pix, u8 plane, 282 u16 *width, u16 *height, u16 *bytesperline) 283 { 284 *width = pix->width; 285 *height = pix->height; 286 *bytesperline = pix->plane_fmt[0].bytesperline; 287 288 if (pix->pixelformat == V4L2_PIX_FMT_NV12 || 289 pix->pixelformat == V4L2_PIX_FMT_NV21) 290 if (plane == 1) 291 *height /= 2; 292 } 293 294 static void vfe_wm_line_based(struct vfe_device *vfe, u32 wm, 295 struct v4l2_pix_format_mplane *pix, 296 u8 plane, u32 enable) 297 { 298 u32 reg; 299 300 if (enable) { 301 u16 width = 0, height = 0, bytesperline = 0, wpl; 302 303 vfe_get_wm_sizes(pix, plane, &width, &height, &bytesperline); 304 305 wpl = vfe_word_per_line(pix->pixelformat, width); 306 307 reg = height - 1; 308 reg |= ((wpl + 1) / 2 - 1) << 16; 309 310 writel_relaxed(reg, vfe->base + 311 VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(wm)); 312 313 wpl = vfe_word_per_line(pix->pixelformat, bytesperline); 314 315 reg = 0x3; 316 reg |= (height - 1) << 4; 317 reg |= wpl << 16; 318 319 writel_relaxed(reg, vfe->base + 320 VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(wm)); 321 } else { 322 writel_relaxed(0, vfe->base + 323 VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(wm)); 324 writel_relaxed(0, vfe->base + 325 VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(wm)); 326 } 327 } 328 329 static void vfe_wm_set_framedrop_period(struct vfe_device *vfe, u8 wm, u8 per) 330 { 331 u32 reg; 332 333 reg = readl_relaxed(vfe->base + 334 VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); 335 336 reg &= ~(VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK); 337 338 reg |= (per << VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_SHIFT) 339 & VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK; 340 341 writel_relaxed(reg, 342 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); 343 } 344 345 static void vfe_wm_set_framedrop_pattern(struct vfe_device *vfe, u8 wm, 346 u32 pattern) 347 { 348 writel_relaxed(pattern, 349 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(wm)); 350 } 351 352 static void vfe_wm_set_ub_cfg(struct vfe_device *vfe, u8 wm, 353 u16 offset, u16 depth) 354 { 355 u32 reg; 356 357 reg = (offset << VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG_OFFSET_SHIFT) | 358 depth; 359 writel_relaxed(reg, vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(wm)); 360 } 361 362 static void vfe_bus_reload_wm(struct vfe_device *vfe, u8 wm) 363 { 364 wmb(); 365 writel_relaxed(VFE_0_BUS_CMD_Mx_RLD_CMD(wm), vfe->base + VFE_0_BUS_CMD); 366 wmb(); 367 } 368 369 static void vfe_wm_set_ping_addr(struct vfe_device *vfe, u8 wm, u32 addr) 370 { 371 writel_relaxed(addr, 372 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(wm)); 373 } 374 375 static void vfe_wm_set_pong_addr(struct vfe_device *vfe, u8 wm, u32 addr) 376 { 377 writel_relaxed(addr, 378 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(wm)); 379 } 380 381 static int vfe_wm_get_ping_pong_status(struct vfe_device *vfe, u8 wm) 382 { 383 u32 reg; 384 385 reg = readl_relaxed(vfe->base + VFE_0_BUS_PING_PONG_STATUS); 386 387 return (reg >> wm) & 0x1; 388 } 389 390 static void vfe_bus_enable_wr_if(struct vfe_device *vfe, u8 enable) 391 { 392 if (enable) 393 writel_relaxed(0x10000009, vfe->base + VFE_0_BUS_CFG); 394 else 395 writel_relaxed(0, vfe->base + VFE_0_BUS_CFG); 396 } 397 398 static void vfe_bus_connect_wm_to_rdi(struct vfe_device *vfe, u8 wm, 399 enum vfe_line_id id) 400 { 401 u32 reg; 402 403 reg = VFE_0_RDI_CFG_x_MIPI_EN_BITS; 404 reg |= VFE_0_RDI_CFG_x_RDI_Mr_FRAME_BASED_EN(id); 405 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), reg); 406 407 reg = VFE_0_RDI_CFG_x_RDI_EN_BIT; 408 reg |= ((3 * id) << VFE_0_RDI_CFG_x_RDI_STREAM_SEL_SHIFT) & 409 VFE_0_RDI_CFG_x_RDI_STREAM_SEL_MASK; 410 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(id), reg); 411 412 switch (id) { 413 case VFE_LINE_RDI0: 414 default: 415 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 << 416 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 417 break; 418 case VFE_LINE_RDI1: 419 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 << 420 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 421 break; 422 case VFE_LINE_RDI2: 423 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 << 424 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 425 break; 426 } 427 428 if (wm % 2 == 1) 429 reg <<= 16; 430 431 vfe_reg_set(vfe, VFE_0_BUS_XBAR_CFG_x(wm), reg); 432 } 433 434 static void vfe_wm_set_subsample(struct vfe_device *vfe, u8 wm) 435 { 436 writel_relaxed(VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF, 437 vfe->base + 438 VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN(wm)); 439 } 440 441 static void vfe_bus_disconnect_wm_from_rdi(struct vfe_device *vfe, u8 wm, 442 enum vfe_line_id id) 443 { 444 u32 reg; 445 446 reg = VFE_0_RDI_CFG_x_RDI_Mr_FRAME_BASED_EN(id); 447 vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(0), reg); 448 449 reg = VFE_0_RDI_CFG_x_RDI_EN_BIT; 450 vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(id), reg); 451 452 switch (id) { 453 case VFE_LINE_RDI0: 454 default: 455 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 << 456 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 457 break; 458 case VFE_LINE_RDI1: 459 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 << 460 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 461 break; 462 case VFE_LINE_RDI2: 463 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 << 464 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 465 break; 466 } 467 468 if (wm % 2 == 1) 469 reg <<= 16; 470 471 vfe_reg_clr(vfe, VFE_0_BUS_XBAR_CFG_x(wm), reg); 472 } 473 474 static void vfe_set_xbar_cfg(struct vfe_device *vfe, struct vfe_output *output, 475 u8 enable) 476 { 477 struct vfe_line *line = container_of(output, struct vfe_line, output); 478 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 479 u32 reg; 480 unsigned int i; 481 482 for (i = 0; i < output->wm_num; i++) { 483 if (i == 0) { 484 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_LUMA << 485 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 486 } else if (i == 1) { 487 reg = VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN; 488 if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV16) 489 reg |= VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA; 490 } else { 491 /* On current devices output->wm_num is always <= 2 */ 492 break; 493 } 494 495 if (output->wm_idx[i] % 2 == 1) 496 reg <<= 16; 497 498 if (enable) 499 vfe_reg_set(vfe, 500 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[i]), 501 reg); 502 else 503 vfe_reg_clr(vfe, 504 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[i]), 505 reg); 506 } 507 } 508 509 static void vfe_set_realign_cfg(struct vfe_device *vfe, struct vfe_line *line, 510 u8 enable) 511 { 512 /* empty */ 513 } 514 static void vfe_set_rdi_cid(struct vfe_device *vfe, enum vfe_line_id id, u8 cid) 515 { 516 vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(id), 517 VFE_0_RDI_CFG_x_RDI_M0_SEL_MASK); 518 519 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(id), 520 cid << VFE_0_RDI_CFG_x_RDI_M0_SEL_SHIFT); 521 } 522 523 static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id) 524 { 525 vfe->reg_update |= VFE_0_REG_UPDATE_line_n(line_id); 526 wmb(); 527 writel_relaxed(vfe->reg_update, vfe->base + VFE_0_REG_UPDATE); 528 wmb(); 529 } 530 531 static inline void vfe_reg_update_clear(struct vfe_device *vfe, 532 enum vfe_line_id line_id) 533 { 534 vfe->reg_update &= ~VFE_0_REG_UPDATE_line_n(line_id); 535 } 536 537 static void vfe_enable_irq_wm_line(struct vfe_device *vfe, u8 wm, 538 enum vfe_line_id line_id, u8 enable) 539 { 540 u32 irq_en0 = VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(wm) | 541 VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(line_id); 542 u32 irq_en1 = VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(wm) | 543 VFE_0_IRQ_MASK_1_RDIn_SOF(line_id); 544 545 if (enable) { 546 vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0); 547 vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1); 548 } else { 549 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_0, irq_en0); 550 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_1, irq_en1); 551 } 552 } 553 554 static void vfe_enable_irq_pix_line(struct vfe_device *vfe, u8 comp, 555 enum vfe_line_id line_id, u8 enable) 556 { 557 struct vfe_output *output = &vfe->line[line_id].output; 558 unsigned int i; 559 u32 irq_en0; 560 u32 irq_en1; 561 u32 comp_mask = 0; 562 563 irq_en0 = VFE_0_IRQ_MASK_0_CAMIF_SOF; 564 irq_en0 |= VFE_0_IRQ_MASK_0_CAMIF_EOF; 565 irq_en0 |= VFE_0_IRQ_MASK_0_IMAGE_COMPOSITE_DONE_n(comp); 566 irq_en0 |= VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(line_id); 567 irq_en1 = VFE_0_IRQ_MASK_1_CAMIF_ERROR; 568 for (i = 0; i < output->wm_num; i++) { 569 irq_en1 |= VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW( 570 output->wm_idx[i]); 571 comp_mask |= (1 << output->wm_idx[i]) << comp * 8; 572 } 573 574 if (enable) { 575 vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0); 576 vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1); 577 vfe_reg_set(vfe, VFE_0_IRQ_COMPOSITE_MASK_0, comp_mask); 578 } else { 579 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_0, irq_en0); 580 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_1, irq_en1); 581 vfe_reg_clr(vfe, VFE_0_IRQ_COMPOSITE_MASK_0, comp_mask); 582 } 583 } 584 585 static void vfe_enable_irq_common(struct vfe_device *vfe) 586 { 587 u32 irq_en0 = VFE_0_IRQ_MASK_0_RESET_ACK; 588 u32 irq_en1 = VFE_0_IRQ_MASK_1_VIOLATION | 589 VFE_0_IRQ_MASK_1_BUS_BDG_HALT_ACK; 590 591 vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0); 592 vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1); 593 } 594 595 static void vfe_set_demux_cfg(struct vfe_device *vfe, struct vfe_line *line) 596 { 597 u32 val, even_cfg, odd_cfg; 598 599 writel_relaxed(VFE_0_DEMUX_CFG_PERIOD, vfe->base + VFE_0_DEMUX_CFG); 600 601 val = VFE_0_DEMUX_GAIN_0_CH0_EVEN | VFE_0_DEMUX_GAIN_0_CH0_ODD; 602 writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_0); 603 604 val = VFE_0_DEMUX_GAIN_1_CH1 | VFE_0_DEMUX_GAIN_1_CH2; 605 writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_1); 606 607 switch (line->fmt[MSM_VFE_PAD_SINK].code) { 608 case MEDIA_BUS_FMT_YUYV8_1X16: 609 even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_YUYV; 610 odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_YUYV; 611 break; 612 case MEDIA_BUS_FMT_YVYU8_1X16: 613 even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_YVYU; 614 odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_YVYU; 615 break; 616 case MEDIA_BUS_FMT_UYVY8_1X16: 617 default: 618 even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_UYVY; 619 odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_UYVY; 620 break; 621 case MEDIA_BUS_FMT_VYUY8_1X16: 622 even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_VYUY; 623 odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_VYUY; 624 break; 625 } 626 627 writel_relaxed(even_cfg, vfe->base + VFE_0_DEMUX_EVEN_CFG); 628 writel_relaxed(odd_cfg, vfe->base + VFE_0_DEMUX_ODD_CFG); 629 } 630 631 static void vfe_set_scale_cfg(struct vfe_device *vfe, struct vfe_line *line) 632 { 633 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 634 u32 reg; 635 u16 input, output; 636 u8 interp_reso; 637 u32 phase_mult; 638 639 writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_Y_CFG); 640 641 input = line->fmt[MSM_VFE_PAD_SINK].width; 642 output = line->compose.width; 643 reg = (output << 16) | input; 644 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE); 645 646 interp_reso = vfe_calc_interp_reso(input, output); 647 phase_mult = input * (1 << (13 + interp_reso)) / output; 648 reg = (interp_reso << 20) | phase_mult; 649 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_PHASE); 650 651 input = line->fmt[MSM_VFE_PAD_SINK].height; 652 output = line->compose.height; 653 reg = (output << 16) | input; 654 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE); 655 656 interp_reso = vfe_calc_interp_reso(input, output); 657 phase_mult = input * (1 << (13 + interp_reso)) / output; 658 reg = (interp_reso << 20) | phase_mult; 659 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_PHASE); 660 661 writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_CBCR_CFG); 662 663 input = line->fmt[MSM_VFE_PAD_SINK].width; 664 output = line->compose.width / 2; 665 reg = (output << 16) | input; 666 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE); 667 668 interp_reso = vfe_calc_interp_reso(input, output); 669 phase_mult = input * (1 << (13 + interp_reso)) / output; 670 reg = (interp_reso << 20) | phase_mult; 671 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_PHASE); 672 673 input = line->fmt[MSM_VFE_PAD_SINK].height; 674 output = line->compose.height; 675 if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV21) 676 output = line->compose.height / 2; 677 reg = (output << 16) | input; 678 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE); 679 680 interp_reso = vfe_calc_interp_reso(input, output); 681 phase_mult = input * (1 << (13 + interp_reso)) / output; 682 reg = (interp_reso << 20) | phase_mult; 683 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_PHASE); 684 } 685 686 static void vfe_set_crop_cfg(struct vfe_device *vfe, struct vfe_line *line) 687 { 688 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 689 u32 reg; 690 u16 first, last; 691 692 first = line->crop.left; 693 last = line->crop.left + line->crop.width - 1; 694 reg = (first << 16) | last; 695 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_WIDTH); 696 697 first = line->crop.top; 698 last = line->crop.top + line->crop.height - 1; 699 reg = (first << 16) | last; 700 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_HEIGHT); 701 702 first = line->crop.left / 2; 703 last = line->crop.left / 2 + line->crop.width / 2 - 1; 704 reg = (first << 16) | last; 705 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_WIDTH); 706 707 first = line->crop.top; 708 last = line->crop.top + line->crop.height - 1; 709 if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV21) { 710 first = line->crop.top / 2; 711 last = line->crop.top / 2 + line->crop.height / 2 - 1; 712 } 713 reg = (first << 16) | last; 714 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_HEIGHT); 715 } 716 717 static void vfe_set_clamp_cfg(struct vfe_device *vfe) 718 { 719 u32 val = VFE_0_CLAMP_ENC_MAX_CFG_CH0 | 720 VFE_0_CLAMP_ENC_MAX_CFG_CH1 | 721 VFE_0_CLAMP_ENC_MAX_CFG_CH2; 722 723 writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MAX_CFG); 724 725 val = VFE_0_CLAMP_ENC_MIN_CFG_CH0 | 726 VFE_0_CLAMP_ENC_MIN_CFG_CH1 | 727 VFE_0_CLAMP_ENC_MIN_CFG_CH2; 728 729 writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MIN_CFG); 730 } 731 732 static void vfe_set_qos(struct vfe_device *vfe) 733 { 734 u32 val = VFE_0_BUS_BDG_QOS_CFG_0_CFG; 735 u32 val7 = VFE_0_BUS_BDG_QOS_CFG_7_CFG; 736 737 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_0); 738 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_1); 739 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_2); 740 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_3); 741 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_4); 742 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_5); 743 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_6); 744 writel_relaxed(val7, vfe->base + VFE_0_BUS_BDG_QOS_CFG_7); 745 } 746 747 static void vfe_set_ds(struct vfe_device *vfe) 748 { 749 /* empty */ 750 } 751 752 static void vfe_set_cgc_override(struct vfe_device *vfe, u8 wm, u8 enable) 753 { 754 u32 val = VFE_0_CGC_OVERRIDE_1_IMAGE_Mx_CGC_OVERRIDE(wm); 755 756 if (enable) 757 vfe_reg_set(vfe, VFE_0_CGC_OVERRIDE_1, val); 758 else 759 vfe_reg_clr(vfe, VFE_0_CGC_OVERRIDE_1, val); 760 761 wmb(); 762 } 763 764 static void vfe_set_camif_cfg(struct vfe_device *vfe, struct vfe_line *line) 765 { 766 u32 val; 767 768 switch (line->fmt[MSM_VFE_PAD_SINK].code) { 769 case MEDIA_BUS_FMT_YUYV8_1X16: 770 val = VFE_0_CORE_CFG_PIXEL_PATTERN_YCBYCR; 771 break; 772 case MEDIA_BUS_FMT_YVYU8_1X16: 773 val = VFE_0_CORE_CFG_PIXEL_PATTERN_YCRYCB; 774 break; 775 case MEDIA_BUS_FMT_UYVY8_1X16: 776 default: 777 val = VFE_0_CORE_CFG_PIXEL_PATTERN_CBYCRY; 778 break; 779 case MEDIA_BUS_FMT_VYUY8_1X16: 780 val = VFE_0_CORE_CFG_PIXEL_PATTERN_CRYCBY; 781 break; 782 } 783 784 writel_relaxed(val, vfe->base + VFE_0_CORE_CFG); 785 786 val = line->fmt[MSM_VFE_PAD_SINK].width * 2; 787 val |= line->fmt[MSM_VFE_PAD_SINK].height << 16; 788 writel_relaxed(val, vfe->base + VFE_0_CAMIF_FRAME_CFG); 789 790 val = line->fmt[MSM_VFE_PAD_SINK].width * 2 - 1; 791 writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_WIDTH_CFG); 792 793 val = line->fmt[MSM_VFE_PAD_SINK].height - 1; 794 writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_HEIGHT_CFG); 795 796 val = 0xffffffff; 797 writel_relaxed(val, vfe->base + VFE_0_CAMIF_SUBSAMPLE_CFG_0); 798 799 val = 0xffffffff; 800 writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN); 801 802 val = VFE_0_RDI_CFG_x_MIPI_EN_BITS; 803 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), val); 804 805 val = VFE_0_CAMIF_CFG_VFE_OUTPUT_EN; 806 writel_relaxed(val, vfe->base + VFE_0_CAMIF_CFG); 807 } 808 809 static void vfe_set_camif_cmd(struct vfe_device *vfe, u8 enable) 810 { 811 u32 cmd; 812 813 cmd = VFE_0_CAMIF_CMD_CLEAR_CAMIF_STATUS | VFE_0_CAMIF_CMD_NO_CHANGE; 814 writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); 815 wmb(); 816 817 if (enable) 818 cmd = VFE_0_CAMIF_CMD_ENABLE_FRAME_BOUNDARY; 819 else 820 cmd = VFE_0_CAMIF_CMD_DISABLE_FRAME_BOUNDARY; 821 822 writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); 823 } 824 825 static void vfe_set_module_cfg(struct vfe_device *vfe, u8 enable) 826 { 827 u32 val = VFE_0_MODULE_CFG_DEMUX | 828 VFE_0_MODULE_CFG_CHROMA_UPSAMPLE | 829 VFE_0_MODULE_CFG_SCALE_ENC | 830 VFE_0_MODULE_CFG_CROP_ENC; 831 832 if (enable) 833 writel_relaxed(val, vfe->base + VFE_0_MODULE_CFG); 834 else 835 writel_relaxed(0x0, vfe->base + VFE_0_MODULE_CFG); 836 } 837 838 static int vfe_camif_wait_for_stop(struct vfe_device *vfe, struct device *dev) 839 { 840 u32 val; 841 int ret; 842 843 ret = readl_poll_timeout(vfe->base + VFE_0_CAMIF_STATUS, 844 val, 845 (val & VFE_0_CAMIF_STATUS_HALT), 846 CAMIF_TIMEOUT_SLEEP_US, 847 CAMIF_TIMEOUT_ALL_US); 848 if (ret < 0) 849 dev_err(dev, "%s: camif stop timeout\n", __func__); 850 851 return ret; 852 } 853 854 static void vfe_isr_read(struct vfe_device *vfe, u32 *value0, u32 *value1) 855 { 856 *value0 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_0); 857 *value1 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_1); 858 859 writel_relaxed(*value0, vfe->base + VFE_0_IRQ_CLEAR_0); 860 writel_relaxed(*value1, vfe->base + VFE_0_IRQ_CLEAR_1); 861 862 wmb(); 863 writel_relaxed(VFE_0_IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_0_IRQ_CMD); 864 } 865 866 static void vfe_violation_read(struct vfe_device *vfe) 867 { 868 u32 violation = readl_relaxed(vfe->base + VFE_0_VIOLATION_STATUS); 869 870 pr_err_ratelimited("VFE: violation = 0x%08x\n", violation); 871 } 872 873 /* 874 * vfe_isr - VFE module interrupt handler 875 * @irq: Interrupt line 876 * @dev: VFE device 877 * 878 * Return IRQ_HANDLED on success 879 */ 880 static irqreturn_t vfe_isr(int irq, void *dev) 881 { 882 struct vfe_device *vfe = dev; 883 u32 value0, value1; 884 int i, j; 885 886 vfe->res->hw_ops->isr_read(vfe, &value0, &value1); 887 888 dev_dbg(vfe->camss->dev, "VFE: status0 = 0x%08x, status1 = 0x%08x\n", 889 value0, value1); 890 891 if (value0 & VFE_0_IRQ_STATUS_0_RESET_ACK) 892 vfe->isr_ops.reset_ack(vfe); 893 894 if (value1 & VFE_0_IRQ_STATUS_1_VIOLATION) 895 vfe->res->hw_ops->violation_read(vfe); 896 897 if (value1 & VFE_0_IRQ_STATUS_1_BUS_BDG_HALT_ACK) 898 vfe->isr_ops.halt_ack(vfe); 899 900 for (i = VFE_LINE_RDI0; i <= VFE_LINE_PIX; i++) 901 if (value0 & VFE_0_IRQ_STATUS_0_line_n_REG_UPDATE(i)) 902 vfe->isr_ops.reg_update(vfe, i); 903 904 if (value0 & VFE_0_IRQ_STATUS_0_CAMIF_SOF) 905 vfe->isr_ops.sof(vfe, VFE_LINE_PIX); 906 907 for (i = VFE_LINE_RDI0; i <= VFE_LINE_RDI2; i++) 908 if (value1 & VFE_0_IRQ_STATUS_1_RDIn_SOF(i)) 909 vfe->isr_ops.sof(vfe, i); 910 911 for (i = 0; i < MSM_VFE_COMPOSITE_IRQ_NUM; i++) 912 if (value0 & VFE_0_IRQ_STATUS_0_IMAGE_COMPOSITE_DONE_n(i)) { 913 vfe->isr_ops.comp_done(vfe, i); 914 for (j = 0; j < ARRAY_SIZE(vfe->wm_output_map); j++) 915 if (vfe->wm_output_map[j] == VFE_LINE_PIX) 916 value0 &= ~VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(j); 917 } 918 919 for (i = 0; i < MSM_VFE_IMAGE_MASTERS_NUM; i++) 920 if (value0 & VFE_0_IRQ_STATUS_0_IMAGE_MASTER_n_PING_PONG(i)) 921 vfe->isr_ops.wm_done(vfe, i); 922 923 return IRQ_HANDLED; 924 } 925 926 /* 927 * vfe_pm_domain_off - Disable power domains specific to this VFE. 928 * @vfe: VFE Device 929 */ 930 static void vfe_4_1_pm_domain_off(struct vfe_device *vfe) 931 { 932 if (!vfe->res->has_pd) 933 return; 934 935 vfe_pm_domain_off(vfe); 936 } 937 938 /* 939 * vfe_pm_domain_on - Enable power domains specific to this VFE. 940 * @vfe: VFE Device 941 */ 942 static int vfe_4_1_pm_domain_on(struct vfe_device *vfe) 943 { 944 if (!vfe->res->has_pd) 945 return 0; 946 947 return vfe_pm_domain_on(vfe); 948 } 949 950 static const struct vfe_hw_ops_gen1 vfe_ops_gen1_4_1 = { 951 .bus_connect_wm_to_rdi = vfe_bus_connect_wm_to_rdi, 952 .bus_disconnect_wm_from_rdi = vfe_bus_disconnect_wm_from_rdi, 953 .bus_enable_wr_if = vfe_bus_enable_wr_if, 954 .bus_reload_wm = vfe_bus_reload_wm, 955 .camif_wait_for_stop = vfe_camif_wait_for_stop, 956 .enable_irq_common = vfe_enable_irq_common, 957 .enable_irq_pix_line = vfe_enable_irq_pix_line, 958 .enable_irq_wm_line = vfe_enable_irq_wm_line, 959 .get_ub_size = vfe_get_ub_size, 960 .halt_clear = vfe_halt_clear, 961 .halt_request = vfe_halt_request, 962 .set_camif_cfg = vfe_set_camif_cfg, 963 .set_camif_cmd = vfe_set_camif_cmd, 964 .set_cgc_override = vfe_set_cgc_override, 965 .set_clamp_cfg = vfe_set_clamp_cfg, 966 .set_crop_cfg = vfe_set_crop_cfg, 967 .set_demux_cfg = vfe_set_demux_cfg, 968 .set_ds = vfe_set_ds, 969 .set_module_cfg = vfe_set_module_cfg, 970 .set_qos = vfe_set_qos, 971 .set_rdi_cid = vfe_set_rdi_cid, 972 .set_realign_cfg = vfe_set_realign_cfg, 973 .set_scale_cfg = vfe_set_scale_cfg, 974 .set_xbar_cfg = vfe_set_xbar_cfg, 975 .wm_enable = vfe_wm_enable, 976 .wm_frame_based = vfe_wm_frame_based, 977 .wm_get_ping_pong_status = vfe_wm_get_ping_pong_status, 978 .wm_line_based = vfe_wm_line_based, 979 .wm_set_framedrop_pattern = vfe_wm_set_framedrop_pattern, 980 .wm_set_framedrop_period = vfe_wm_set_framedrop_period, 981 .wm_set_ping_addr = vfe_wm_set_ping_addr, 982 .wm_set_pong_addr = vfe_wm_set_pong_addr, 983 .wm_set_subsample = vfe_wm_set_subsample, 984 .wm_set_ub_cfg = vfe_wm_set_ub_cfg, 985 }; 986 987 static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe) 988 { 989 vfe->isr_ops = vfe_isr_ops_gen1; 990 vfe->ops_gen1 = &vfe_ops_gen1_4_1; 991 vfe->video_ops = vfe_video_ops_gen1; 992 } 993 994 const struct vfe_hw_ops vfe_ops_4_1 = { 995 .global_reset = vfe_global_reset, 996 .hw_version = vfe_hw_version, 997 .isr_read = vfe_isr_read, 998 .isr = vfe_isr, 999 .pm_domain_off = vfe_4_1_pm_domain_off, 1000 .pm_domain_on = vfe_4_1_pm_domain_on, 1001 .reg_update_clear = vfe_reg_update_clear, 1002 .reg_update = vfe_reg_update, 1003 .subdev_init = vfe_subdev_init, 1004 .vfe_disable = vfe_gen1_disable, 1005 .vfe_enable = vfe_gen1_enable, 1006 .vfe_halt = vfe_gen1_halt, 1007 .violation_read = vfe_violation_read, 1008 }; 1009