1*c942fddfSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */
202b20b0bSMauro Carvalho Chehab /*
302b20b0bSMauro Carvalho Chehab * Driver for the Conexant CX25821 PCIe bridge
402b20b0bSMauro Carvalho Chehab *
502b20b0bSMauro Carvalho Chehab * Copyright (C) 2009 Conexant Systems Inc.
602b20b0bSMauro Carvalho Chehab * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
702b20b0bSMauro Carvalho Chehab * Based on Steven Toth <stoth@linuxtv.org> cx23885 driver
802b20b0bSMauro Carvalho Chehab */
902b20b0bSMauro Carvalho Chehab
1002b20b0bSMauro Carvalho Chehab #ifndef CX25821_H_
1102b20b0bSMauro Carvalho Chehab #define CX25821_H_
1202b20b0bSMauro Carvalho Chehab
1302b20b0bSMauro Carvalho Chehab #include <linux/pci.h>
1402b20b0bSMauro Carvalho Chehab #include <linux/i2c.h>
1502b20b0bSMauro Carvalho Chehab #include <linux/interrupt.h>
1602b20b0bSMauro Carvalho Chehab #include <linux/delay.h>
1702b20b0bSMauro Carvalho Chehab #include <linux/sched.h>
1802b20b0bSMauro Carvalho Chehab #include <linux/kdev_t.h>
1902b20b0bSMauro Carvalho Chehab
2002b20b0bSMauro Carvalho Chehab #include <media/v4l2-common.h>
2102b20b0bSMauro Carvalho Chehab #include <media/v4l2-device.h>
22f8d7ee70SHans Verkuil #include <media/v4l2-ctrls.h>
232d700715SJunghak Sung #include <media/videobuf2-v4l2.h>
24b671ae6bSHans Verkuil #include <media/videobuf2-dma-sg.h>
2502b20b0bSMauro Carvalho Chehab
2602b20b0bSMauro Carvalho Chehab #include "cx25821-reg.h"
2702b20b0bSMauro Carvalho Chehab #include "cx25821-medusa-reg.h"
2802b20b0bSMauro Carvalho Chehab #include "cx25821-sram.h"
2902b20b0bSMauro Carvalho Chehab #include "cx25821-audio.h"
3002b20b0bSMauro Carvalho Chehab
3102b20b0bSMauro Carvalho Chehab #include <linux/mutex.h>
3202b20b0bSMauro Carvalho Chehab
3302b20b0bSMauro Carvalho Chehab #define UNSET (-1U)
3402b20b0bSMauro Carvalho Chehab #define NO_SYNC_LINE (-1U)
3502b20b0bSMauro Carvalho Chehab
3602b20b0bSMauro Carvalho Chehab #define CX25821_MAXBOARDS 2
3702b20b0bSMauro Carvalho Chehab
3802b20b0bSMauro Carvalho Chehab #define LINE_SIZE_D1 1440
3902b20b0bSMauro Carvalho Chehab
406d8c2ba1SPalash Bandyopadhyay /* Number of decoders and encoders */
4102b20b0bSMauro Carvalho Chehab #define MAX_DECODERS 8
4202b20b0bSMauro Carvalho Chehab #define MAX_ENCODERS 2
4302b20b0bSMauro Carvalho Chehab #define QUAD_DECODERS 4
4402b20b0bSMauro Carvalho Chehab #define MAX_CAMERAS 16
4502b20b0bSMauro Carvalho Chehab
4602b20b0bSMauro Carvalho Chehab /* Max number of inputs by card */
4702b20b0bSMauro Carvalho Chehab #define MAX_CX25821_INPUT 8
4802b20b0bSMauro Carvalho Chehab #define RESOURCE_VIDEO0 1
4902b20b0bSMauro Carvalho Chehab #define RESOURCE_VIDEO1 2
5002b20b0bSMauro Carvalho Chehab #define RESOURCE_VIDEO2 4
5102b20b0bSMauro Carvalho Chehab #define RESOURCE_VIDEO3 8
5202b20b0bSMauro Carvalho Chehab #define RESOURCE_VIDEO4 16
5302b20b0bSMauro Carvalho Chehab #define RESOURCE_VIDEO5 32
5402b20b0bSMauro Carvalho Chehab #define RESOURCE_VIDEO6 64
5502b20b0bSMauro Carvalho Chehab #define RESOURCE_VIDEO7 128
5602b20b0bSMauro Carvalho Chehab #define RESOURCE_VIDEO8 256
5702b20b0bSMauro Carvalho Chehab #define RESOURCE_VIDEO9 512
5802b20b0bSMauro Carvalho Chehab #define RESOURCE_VIDEO10 1024
5902b20b0bSMauro Carvalho Chehab #define RESOURCE_VIDEO11 2048
6002b20b0bSMauro Carvalho Chehab
6102b20b0bSMauro Carvalho Chehab #define BUFFER_TIMEOUT (HZ) /* 0.5 seconds */
6202b20b0bSMauro Carvalho Chehab
6302b20b0bSMauro Carvalho Chehab #define UNKNOWN_BOARD 0
6402b20b0bSMauro Carvalho Chehab #define CX25821_BOARD 1
6502b20b0bSMauro Carvalho Chehab
6602b20b0bSMauro Carvalho Chehab /* Currently supported by the driver */
6702b20b0bSMauro Carvalho Chehab #define CX25821_NORMS (\
6802b20b0bSMauro Carvalho Chehab V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_M_KR | \
6902b20b0bSMauro Carvalho Chehab V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_I | \
7002b20b0bSMauro Carvalho Chehab V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_H | \
7102b20b0bSMauro Carvalho Chehab V4L2_STD_PAL_Nc)
7202b20b0bSMauro Carvalho Chehab
7302b20b0bSMauro Carvalho Chehab #define CX25821_BOARD_CONEXANT_ATHENA10 1
7402b20b0bSMauro Carvalho Chehab #define MAX_VID_CHANNEL_NUM 12
75b6f21dc3SHans Verkuil
76b6f21dc3SHans Verkuil /*
77b6f21dc3SHans Verkuil * Maximum capture-only channels. This can go away once video/audio output
78b6f21dc3SHans Verkuil * is fully supported in this driver.
79b6f21dc3SHans Verkuil */
80b6f21dc3SHans Verkuil #define MAX_VID_CAP_CHANNEL_NUM 10
81b6f21dc3SHans Verkuil
8202b20b0bSMauro Carvalho Chehab #define VID_CHANNEL_NUM 8
8302b20b0bSMauro Carvalho Chehab
8402b20b0bSMauro Carvalho Chehab struct cx25821_fmt {
8502b20b0bSMauro Carvalho Chehab u32 fourcc; /* v4l2 format id */
8602b20b0bSMauro Carvalho Chehab int depth;
8702b20b0bSMauro Carvalho Chehab int flags;
8802b20b0bSMauro Carvalho Chehab u32 cxformat;
8902b20b0bSMauro Carvalho Chehab };
9002b20b0bSMauro Carvalho Chehab
9102b20b0bSMauro Carvalho Chehab struct cx25821_tvnorm {
9202b20b0bSMauro Carvalho Chehab char *name;
9302b20b0bSMauro Carvalho Chehab v4l2_std_id id;
9402b20b0bSMauro Carvalho Chehab u32 cxiformat;
9502b20b0bSMauro Carvalho Chehab u32 cxoformat;
9602b20b0bSMauro Carvalho Chehab };
9702b20b0bSMauro Carvalho Chehab
9802b20b0bSMauro Carvalho Chehab enum cx25821_src_sel_type {
9902b20b0bSMauro Carvalho Chehab CX25821_SRC_SEL_EXT_656_VIDEO = 0,
10002b20b0bSMauro Carvalho Chehab CX25821_SRC_SEL_PARALLEL_MPEG_VIDEO
10102b20b0bSMauro Carvalho Chehab };
10202b20b0bSMauro Carvalho Chehab
1035ede94c7SHans Verkuil struct cx25821_riscmem {
1045ede94c7SHans Verkuil unsigned int size;
1055ede94c7SHans Verkuil __le32 *cpu;
1065ede94c7SHans Verkuil __le32 *jmp;
1075ede94c7SHans Verkuil dma_addr_t dma;
1085ede94c7SHans Verkuil };
1095ede94c7SHans Verkuil
11002b20b0bSMauro Carvalho Chehab /* buffer for one video frame */
11102b20b0bSMauro Carvalho Chehab struct cx25821_buffer {
11202b20b0bSMauro Carvalho Chehab /* common v4l buffer stuff -- must be first */
1132d700715SJunghak Sung struct vb2_v4l2_buffer vb;
114b671ae6bSHans Verkuil struct list_head queue;
11502b20b0bSMauro Carvalho Chehab
11602b20b0bSMauro Carvalho Chehab /* cx25821 specific */
11702b20b0bSMauro Carvalho Chehab unsigned int bpl;
1185ede94c7SHans Verkuil struct cx25821_riscmem risc;
11995c232a2SHans Verkuil const struct cx25821_fmt *fmt;
12002b20b0bSMauro Carvalho Chehab };
12102b20b0bSMauro Carvalho Chehab
1227ae70c8bSLeonid V. Fedorenchik enum port {
12302b20b0bSMauro Carvalho Chehab CX25821_UNDEFINED = 0,
12402b20b0bSMauro Carvalho Chehab CX25821_RAW,
12502b20b0bSMauro Carvalho Chehab CX25821_264
1267ae70c8bSLeonid V. Fedorenchik };
12702b20b0bSMauro Carvalho Chehab
12802b20b0bSMauro Carvalho Chehab struct cx25821_board {
129c854d888SEzequiel García const char *name;
1307ae70c8bSLeonid V. Fedorenchik enum port porta;
1317ae70c8bSLeonid V. Fedorenchik enum port portb;
1327ae70c8bSLeonid V. Fedorenchik enum port portc;
13302b20b0bSMauro Carvalho Chehab
13402b20b0bSMauro Carvalho Chehab u32 clk_freq;
13502b20b0bSMauro Carvalho Chehab };
13602b20b0bSMauro Carvalho Chehab
13702b20b0bSMauro Carvalho Chehab struct cx25821_i2c {
13802b20b0bSMauro Carvalho Chehab struct cx25821_dev *dev;
13902b20b0bSMauro Carvalho Chehab
14002b20b0bSMauro Carvalho Chehab int nr;
14102b20b0bSMauro Carvalho Chehab
14202b20b0bSMauro Carvalho Chehab /* i2c i/o */
14302b20b0bSMauro Carvalho Chehab struct i2c_adapter i2c_adap;
14402b20b0bSMauro Carvalho Chehab struct i2c_client i2c_client;
14502b20b0bSMauro Carvalho Chehab u32 i2c_rc;
14602b20b0bSMauro Carvalho Chehab
14716790554SMauro Carvalho Chehab /* cx25821 registers used for raw address */
14802b20b0bSMauro Carvalho Chehab u32 i2c_period;
14902b20b0bSMauro Carvalho Chehab u32 reg_ctrl;
15002b20b0bSMauro Carvalho Chehab u32 reg_stat;
15102b20b0bSMauro Carvalho Chehab u32 reg_addr;
15202b20b0bSMauro Carvalho Chehab u32 reg_rdata;
15302b20b0bSMauro Carvalho Chehab u32 reg_wdata;
15402b20b0bSMauro Carvalho Chehab };
15502b20b0bSMauro Carvalho Chehab
15602b20b0bSMauro Carvalho Chehab struct cx25821_dmaqueue {
15702b20b0bSMauro Carvalho Chehab struct list_head active;
15802b20b0bSMauro Carvalho Chehab u32 count;
15902b20b0bSMauro Carvalho Chehab };
16002b20b0bSMauro Carvalho Chehab
161f8d7ee70SHans Verkuil struct cx25821_dev;
162f8d7ee70SHans Verkuil
1637087d31bSHans Verkuil struct cx25821_channel;
1647087d31bSHans Verkuil
1657087d31bSHans Verkuil struct cx25821_video_out_data {
1667087d31bSHans Verkuil struct cx25821_channel *chan;
1677087d31bSHans Verkuil int _line_size;
1687087d31bSHans Verkuil int _prog_cnt;
1697087d31bSHans Verkuil int _pixel_format;
1707087d31bSHans Verkuil int _is_first_frame;
1717087d31bSHans Verkuil int _is_running;
1727087d31bSHans Verkuil int _file_status;
1737087d31bSHans Verkuil int _lines_count;
1747087d31bSHans Verkuil int _frame_count;
1757087d31bSHans Verkuil unsigned int _risc_size;
1767087d31bSHans Verkuil
1777087d31bSHans Verkuil __le32 *_dma_virt_start_addr;
1787087d31bSHans Verkuil __le32 *_dma_virt_addr;
1797087d31bSHans Verkuil dma_addr_t _dma_phys_addr;
1807087d31bSHans Verkuil dma_addr_t _dma_phys_start_addr;
1817087d31bSHans Verkuil
1827087d31bSHans Verkuil unsigned int _data_buf_size;
1837087d31bSHans Verkuil __le32 *_data_buf_virt_addr;
1847087d31bSHans Verkuil dma_addr_t _data_buf_phys_addr;
1857087d31bSHans Verkuil
1867087d31bSHans Verkuil u32 upstream_riscbuf_size;
1877087d31bSHans Verkuil u32 upstream_databuf_size;
1887087d31bSHans Verkuil int is_60hz;
1897087d31bSHans Verkuil int _frame_index;
190ea3f7ac6SHans Verkuil int cur_frame_index;
191ea3f7ac6SHans Verkuil int curpos;
192ea3f7ac6SHans Verkuil wait_queue_head_t waitq;
1937087d31bSHans Verkuil };
1947087d31bSHans Verkuil
1956d8c2ba1SPalash Bandyopadhyay struct cx25821_channel {
196f8d7ee70SHans Verkuil unsigned id;
197f8d7ee70SHans Verkuil struct cx25821_dev *dev;
1986d8c2ba1SPalash Bandyopadhyay
199f8d7ee70SHans Verkuil struct v4l2_ctrl_handler hdl;
2006d8c2ba1SPalash Bandyopadhyay
201467870caSHans Verkuil struct video_device vdev;
2022efe2cc4SHans Verkuil struct cx25821_dmaqueue dma_vidq;
203b671ae6bSHans Verkuil struct vb2_queue vidq;
2046d8c2ba1SPalash Bandyopadhyay
205bfef0d35SHans Verkuil const struct sram_channel *sram_channels;
2066d8c2ba1SPalash Bandyopadhyay
2072efe2cc4SHans Verkuil const struct cx25821_fmt *fmt;
208b671ae6bSHans Verkuil unsigned field;
2092efe2cc4SHans Verkuil unsigned int width, height;
2106d8c2ba1SPalash Bandyopadhyay int pixel_formats;
2116d8c2ba1SPalash Bandyopadhyay int use_cif_resolution;
2126d8c2ba1SPalash Bandyopadhyay int cif_width;
2137087d31bSHans Verkuil
2147087d31bSHans Verkuil /* video output data for the video output channel */
2157087d31bSHans Verkuil struct cx25821_video_out_data *out;
2166d8c2ba1SPalash Bandyopadhyay };
2176d8c2ba1SPalash Bandyopadhyay
218a8f35ce3SHans Verkuil struct snd_card;
219a8f35ce3SHans Verkuil
22002b20b0bSMauro Carvalho Chehab struct cx25821_dev {
22102b20b0bSMauro Carvalho Chehab struct v4l2_device v4l2_dev;
22202b20b0bSMauro Carvalho Chehab
22302b20b0bSMauro Carvalho Chehab /* pci stuff */
22402b20b0bSMauro Carvalho Chehab struct pci_dev *pci;
22502b20b0bSMauro Carvalho Chehab unsigned char pci_rev, pci_lat;
22602b20b0bSMauro Carvalho Chehab int pci_bus, pci_slot;
22702b20b0bSMauro Carvalho Chehab u32 base_io_addr;
22802b20b0bSMauro Carvalho Chehab u32 __iomem *lmmio;
22902b20b0bSMauro Carvalho Chehab u8 __iomem *bmmio;
23002b20b0bSMauro Carvalho Chehab int pci_irqmask;
23102b20b0bSMauro Carvalho Chehab int hwrevision;
232a8f35ce3SHans Verkuil /* used by cx25821-alsa */
233a8f35ce3SHans Verkuil struct snd_card *card;
23402b20b0bSMauro Carvalho Chehab
23502b20b0bSMauro Carvalho Chehab u32 clk_freq;
23602b20b0bSMauro Carvalho Chehab
23702b20b0bSMauro Carvalho Chehab /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
23802b20b0bSMauro Carvalho Chehab struct cx25821_i2c i2c_bus[3];
23902b20b0bSMauro Carvalho Chehab
24002b20b0bSMauro Carvalho Chehab int nr;
24102b20b0bSMauro Carvalho Chehab struct mutex lock;
24202b20b0bSMauro Carvalho Chehab
2436d8c2ba1SPalash Bandyopadhyay struct cx25821_channel channels[MAX_VID_CHANNEL_NUM];
2446d8c2ba1SPalash Bandyopadhyay
24502b20b0bSMauro Carvalho Chehab /* board details */
24602b20b0bSMauro Carvalho Chehab unsigned int board;
24702b20b0bSMauro Carvalho Chehab char name[32];
24802b20b0bSMauro Carvalho Chehab
24902b20b0bSMauro Carvalho Chehab /* Analog video */
25002b20b0bSMauro Carvalho Chehab unsigned int input;
25102b20b0bSMauro Carvalho Chehab v4l2_std_id tvnorm;
25202b20b0bSMauro Carvalho Chehab unsigned short _max_num_decoders;
25302b20b0bSMauro Carvalho Chehab
25402b20b0bSMauro Carvalho Chehab /* Analog Audio Upstream */
25502b20b0bSMauro Carvalho Chehab int _audio_is_running;
25602b20b0bSMauro Carvalho Chehab int _audiopixel_format;
25702b20b0bSMauro Carvalho Chehab int _is_first_audio_frame;
25802b20b0bSMauro Carvalho Chehab int _audiofile_status;
25902b20b0bSMauro Carvalho Chehab int _audio_lines_count;
26002b20b0bSMauro Carvalho Chehab int _audioframe_count;
2616100c579SLeonid V. Fedorenchik int _audio_upstream_channel;
2626d8c2ba1SPalash Bandyopadhyay int _last_index_irq; /* The last interrupt index processed. */
26302b20b0bSMauro Carvalho Chehab
26402b20b0bSMauro Carvalho Chehab __le32 *_risc_audio_jmp_addr;
26502b20b0bSMauro Carvalho Chehab __le32 *_risc_virt_start_addr;
26602b20b0bSMauro Carvalho Chehab __le32 *_risc_virt_addr;
26702b20b0bSMauro Carvalho Chehab dma_addr_t _risc_phys_addr;
26802b20b0bSMauro Carvalho Chehab dma_addr_t _risc_phys_start_addr;
26902b20b0bSMauro Carvalho Chehab
27002b20b0bSMauro Carvalho Chehab unsigned int _audiorisc_size;
27102b20b0bSMauro Carvalho Chehab unsigned int _audiodata_buf_size;
27202b20b0bSMauro Carvalho Chehab __le32 *_audiodata_buf_virt_addr;
27302b20b0bSMauro Carvalho Chehab dma_addr_t _audiodata_buf_phys_addr;
27402b20b0bSMauro Carvalho Chehab char *_audiofilename;
2757087d31bSHans Verkuil u32 audio_upstream_riscbuf_size;
2767087d31bSHans Verkuil u32 audio_upstream_databuf_size;
2777087d31bSHans Verkuil int _audioframe_index;
2787087d31bSHans Verkuil struct work_struct _audio_work_entry;
2797087d31bSHans Verkuil char *input_audiofilename;
28002b20b0bSMauro Carvalho Chehab
28102b20b0bSMauro Carvalho Chehab /* V4l */
28202b20b0bSMauro Carvalho Chehab spinlock_t slock;
28302b20b0bSMauro Carvalho Chehab
28402b20b0bSMauro Carvalho Chehab /* Video Upstream */
2857087d31bSHans Verkuil struct cx25821_video_out_data vid_out_data[2];
28602b20b0bSMauro Carvalho Chehab };
28702b20b0bSMauro Carvalho Chehab
get_cx25821(struct v4l2_device * v4l2_dev)28802b20b0bSMauro Carvalho Chehab static inline struct cx25821_dev *get_cx25821(struct v4l2_device *v4l2_dev)
28902b20b0bSMauro Carvalho Chehab {
29002b20b0bSMauro Carvalho Chehab return container_of(v4l2_dev, struct cx25821_dev, v4l2_dev);
29102b20b0bSMauro Carvalho Chehab }
29202b20b0bSMauro Carvalho Chehab
29302b20b0bSMauro Carvalho Chehab extern struct cx25821_board cx25821_boards[];
29402b20b0bSMauro Carvalho Chehab
29502b20b0bSMauro Carvalho Chehab #define SRAM_CH00 0 /* Video A */
29602b20b0bSMauro Carvalho Chehab #define SRAM_CH01 1 /* Video B */
29702b20b0bSMauro Carvalho Chehab #define SRAM_CH02 2 /* Video C */
29802b20b0bSMauro Carvalho Chehab #define SRAM_CH03 3 /* Video D */
29902b20b0bSMauro Carvalho Chehab #define SRAM_CH04 4 /* Video E */
30002b20b0bSMauro Carvalho Chehab #define SRAM_CH05 5 /* Video F */
30102b20b0bSMauro Carvalho Chehab #define SRAM_CH06 6 /* Video G */
30202b20b0bSMauro Carvalho Chehab #define SRAM_CH07 7 /* Video H */
30302b20b0bSMauro Carvalho Chehab
30402b20b0bSMauro Carvalho Chehab #define SRAM_CH08 8 /* Audio A */
30502b20b0bSMauro Carvalho Chehab #define SRAM_CH09 9 /* Video Upstream I */
30602b20b0bSMauro Carvalho Chehab #define SRAM_CH10 10 /* Video Upstream J */
30702b20b0bSMauro Carvalho Chehab #define SRAM_CH11 11 /* Audio Upstream AUD_CHANNEL_B */
30802b20b0bSMauro Carvalho Chehab
30902b20b0bSMauro Carvalho Chehab #define VID_UPSTREAM_SRAM_CHANNEL_I SRAM_CH09
31002b20b0bSMauro Carvalho Chehab #define VID_UPSTREAM_SRAM_CHANNEL_J SRAM_CH10
31102b20b0bSMauro Carvalho Chehab #define AUDIO_UPSTREAM_SRAM_CHANNEL_B SRAM_CH11
31202b20b0bSMauro Carvalho Chehab
31302b20b0bSMauro Carvalho Chehab struct sram_channel {
31402b20b0bSMauro Carvalho Chehab char *name;
31502b20b0bSMauro Carvalho Chehab u32 i;
31602b20b0bSMauro Carvalho Chehab u32 cmds_start;
31702b20b0bSMauro Carvalho Chehab u32 ctrl_start;
31802b20b0bSMauro Carvalho Chehab u32 cdt;
31902b20b0bSMauro Carvalho Chehab u32 fifo_start;
32002b20b0bSMauro Carvalho Chehab u32 fifo_size;
32102b20b0bSMauro Carvalho Chehab u32 ptr1_reg;
32202b20b0bSMauro Carvalho Chehab u32 ptr2_reg;
32302b20b0bSMauro Carvalho Chehab u32 cnt1_reg;
32402b20b0bSMauro Carvalho Chehab u32 cnt2_reg;
32502b20b0bSMauro Carvalho Chehab u32 int_msk;
32602b20b0bSMauro Carvalho Chehab u32 int_stat;
32702b20b0bSMauro Carvalho Chehab u32 int_mstat;
32802b20b0bSMauro Carvalho Chehab u32 dma_ctl;
32902b20b0bSMauro Carvalho Chehab u32 gpcnt_ctl;
33002b20b0bSMauro Carvalho Chehab u32 gpcnt;
33102b20b0bSMauro Carvalho Chehab u32 aud_length;
33202b20b0bSMauro Carvalho Chehab u32 aud_cfg;
33302b20b0bSMauro Carvalho Chehab u32 fld_aud_fifo_en;
33402b20b0bSMauro Carvalho Chehab u32 fld_aud_risc_en;
33502b20b0bSMauro Carvalho Chehab
3366d8c2ba1SPalash Bandyopadhyay /* For Upstream Video */
33702b20b0bSMauro Carvalho Chehab u32 vid_fmt_ctl;
33802b20b0bSMauro Carvalho Chehab u32 vid_active_ctl1;
33902b20b0bSMauro Carvalho Chehab u32 vid_active_ctl2;
34002b20b0bSMauro Carvalho Chehab u32 vid_cdt_size;
34102b20b0bSMauro Carvalho Chehab
34202b20b0bSMauro Carvalho Chehab u32 vip_ctl;
34302b20b0bSMauro Carvalho Chehab u32 pix_frmt;
34402b20b0bSMauro Carvalho Chehab u32 jumponly;
34502b20b0bSMauro Carvalho Chehab u32 irq_bit;
34602b20b0bSMauro Carvalho Chehab };
347bfef0d35SHans Verkuil
348bfef0d35SHans Verkuil extern const struct sram_channel cx25821_sram_channels[];
34902b20b0bSMauro Carvalho Chehab
35002b20b0bSMauro Carvalho Chehab #define cx_read(reg) readl(dev->lmmio + ((reg)>>2))
35102b20b0bSMauro Carvalho Chehab #define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2))
35202b20b0bSMauro Carvalho Chehab
35302b20b0bSMauro Carvalho Chehab #define cx_andor(reg, mask, value) \
35402b20b0bSMauro Carvalho Chehab writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
35502b20b0bSMauro Carvalho Chehab ((value) & (mask)), dev->lmmio+((reg)>>2))
35602b20b0bSMauro Carvalho Chehab
35702b20b0bSMauro Carvalho Chehab #define cx_set(reg, bit) cx_andor((reg), (bit), (bit))
35802b20b0bSMauro Carvalho Chehab #define cx_clear(reg, bit) cx_andor((reg), (bit), 0)
35902b20b0bSMauro Carvalho Chehab
36002b20b0bSMauro Carvalho Chehab #define Set_GPIO_Bit(Bit) (1 << Bit)
36102b20b0bSMauro Carvalho Chehab #define Clear_GPIO_Bit(Bit) (~(1 << Bit))
36202b20b0bSMauro Carvalho Chehab
36336d89f7dSJoe Perches #define CX25821_ERR(fmt, args...) \
36436d89f7dSJoe Perches pr_err("(%d): " fmt, dev->board, ##args)
36536d89f7dSJoe Perches #define CX25821_WARN(fmt, args...) \
36636d89f7dSJoe Perches pr_warn("(%d): " fmt, dev->board, ##args)
36736d89f7dSJoe Perches #define CX25821_INFO(fmt, args...) \
36836d89f7dSJoe Perches pr_info("(%d): " fmt, dev->board, ##args)
36902b20b0bSMauro Carvalho Chehab
37002b20b0bSMauro Carvalho Chehab extern int cx25821_i2c_register(struct cx25821_i2c *bus);
37102b20b0bSMauro Carvalho Chehab extern int cx25821_i2c_read(struct cx25821_i2c *bus, u16 reg_addr, int *value);
37202b20b0bSMauro Carvalho Chehab extern int cx25821_i2c_write(struct cx25821_i2c *bus, u16 reg_addr, int value);
37302b20b0bSMauro Carvalho Chehab extern int cx25821_i2c_unregister(struct cx25821_i2c *bus);
37402b20b0bSMauro Carvalho Chehab extern void cx25821_gpio_init(struct cx25821_dev *dev);
37502b20b0bSMauro Carvalho Chehab extern void cx25821_set_gpiopin_direction(struct cx25821_dev *dev,
3761a9fc855SMauro Carvalho Chehab int pin_number, int pin_logic_value);
37702b20b0bSMauro Carvalho Chehab
37802b20b0bSMauro Carvalho Chehab extern int medusa_video_init(struct cx25821_dev *dev);
37902b20b0bSMauro Carvalho Chehab extern int medusa_set_videostandard(struct cx25821_dev *dev);
3801a9fc855SMauro Carvalho Chehab extern void medusa_set_resolution(struct cx25821_dev *dev, int width,
3811a9fc855SMauro Carvalho Chehab int decoder_select);
3821a9fc855SMauro Carvalho Chehab extern int medusa_set_brightness(struct cx25821_dev *dev, int brightness,
3831a9fc855SMauro Carvalho Chehab int decoder);
3841a9fc855SMauro Carvalho Chehab extern int medusa_set_contrast(struct cx25821_dev *dev, int contrast,
3851a9fc855SMauro Carvalho Chehab int decoder);
38602b20b0bSMauro Carvalho Chehab extern int medusa_set_hue(struct cx25821_dev *dev, int hue, int decoder);
3871a9fc855SMauro Carvalho Chehab extern int medusa_set_saturation(struct cx25821_dev *dev, int saturation,
3881a9fc855SMauro Carvalho Chehab int decoder);
38902b20b0bSMauro Carvalho Chehab
3901a9fc855SMauro Carvalho Chehab extern int cx25821_sram_channel_setup(struct cx25821_dev *dev,
391bfef0d35SHans Verkuil const struct sram_channel *ch, unsigned int bpl,
3921a9fc855SMauro Carvalho Chehab u32 risc);
39302b20b0bSMauro Carvalho Chehab
3945ede94c7SHans Verkuil extern int cx25821_riscmem_alloc(struct pci_dev *pci,
3955ede94c7SHans Verkuil struct cx25821_riscmem *risc,
3965ede94c7SHans Verkuil unsigned int size);
3975ede94c7SHans Verkuil extern int cx25821_risc_buffer(struct pci_dev *pci, struct cx25821_riscmem *risc,
39802b20b0bSMauro Carvalho Chehab struct scatterlist *sglist,
39902b20b0bSMauro Carvalho Chehab unsigned int top_offset,
40002b20b0bSMauro Carvalho Chehab unsigned int bottom_offset,
40102b20b0bSMauro Carvalho Chehab unsigned int bpl,
4021a9fc855SMauro Carvalho Chehab unsigned int padding, unsigned int lines);
40302b20b0bSMauro Carvalho Chehab extern int cx25821_risc_databuffer_audio(struct pci_dev *pci,
4045ede94c7SHans Verkuil struct cx25821_riscmem *risc,
40502b20b0bSMauro Carvalho Chehab struct scatterlist *sglist,
40602b20b0bSMauro Carvalho Chehab unsigned int bpl,
4071a9fc855SMauro Carvalho Chehab unsigned int lines, unsigned int lpi);
408b671ae6bSHans Verkuil extern void cx25821_free_buffer(struct cx25821_dev *dev,
4091a9fc855SMauro Carvalho Chehab struct cx25821_buffer *buf);
4101a9fc855SMauro Carvalho Chehab extern void cx25821_sram_channel_dump(struct cx25821_dev *dev,
411bfef0d35SHans Verkuil const struct sram_channel *ch);
4121a9fc855SMauro Carvalho Chehab extern void cx25821_sram_channel_dump_audio(struct cx25821_dev *dev,
413bfef0d35SHans Verkuil const struct sram_channel *ch);
41402b20b0bSMauro Carvalho Chehab
41502b20b0bSMauro Carvalho Chehab extern struct cx25821_dev *cx25821_dev_get(struct pci_dev *pci);
4161a9fc855SMauro Carvalho Chehab extern void cx25821_print_irqbits(char *name, char *tag, char **strings,
4171a9fc855SMauro Carvalho Chehab int len, u32 bits, u32 mask);
41802b20b0bSMauro Carvalho Chehab extern void cx25821_dev_unregister(struct cx25821_dev *dev);
41902b20b0bSMauro Carvalho Chehab extern int cx25821_sram_channel_setup_audio(struct cx25821_dev *dev,
420bfef0d35SHans Verkuil const struct sram_channel *ch,
42102b20b0bSMauro Carvalho Chehab unsigned int bpl, u32 risc);
42202b20b0bSMauro Carvalho Chehab
4231a9fc855SMauro Carvalho Chehab extern void cx25821_set_pixel_format(struct cx25821_dev *dev, int channel,
4241a9fc855SMauro Carvalho Chehab u32 format);
42595c232a2SHans Verkuil
42602b20b0bSMauro Carvalho Chehab #endif
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