1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 NXP TDA10048HN DVB OFDM demodulator driver 4 5 Copyright (C) 2009 Steven Toth <stoth@kernellabs.com> 6 7 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <linux/module.h> 13 #include <linux/string.h> 14 #include <linux/slab.h> 15 #include <linux/delay.h> 16 #include <linux/math64.h> 17 #include <asm/div64.h> 18 #include <media/dvb_frontend.h> 19 #include <linux/int_log.h> 20 #include "tda10048.h" 21 22 #define TDA10048_DEFAULT_FIRMWARE "dvb-fe-tda10048-1.0.fw" 23 #define TDA10048_DEFAULT_FIRMWARE_SIZE 24878 24 25 /* Register name definitions */ 26 #define TDA10048_IDENTITY 0x00 27 #define TDA10048_VERSION 0x01 28 #define TDA10048_DSP_CODE_CPT 0x0C 29 #define TDA10048_DSP_CODE_IN 0x0E 30 #define TDA10048_IN_CONF1 0x10 31 #define TDA10048_IN_CONF2 0x11 32 #define TDA10048_IN_CONF3 0x12 33 #define TDA10048_OUT_CONF1 0x14 34 #define TDA10048_OUT_CONF2 0x15 35 #define TDA10048_OUT_CONF3 0x16 36 #define TDA10048_AUTO 0x18 37 #define TDA10048_SYNC_STATUS 0x1A 38 #define TDA10048_CONF_C4_1 0x1E 39 #define TDA10048_CONF_C4_2 0x1F 40 #define TDA10048_CODE_IN_RAM 0x20 41 #define TDA10048_CHANNEL_INFO1_R 0x22 42 #define TDA10048_CHANNEL_INFO2_R 0x23 43 #define TDA10048_CHANNEL_INFO1 0x24 44 #define TDA10048_CHANNEL_INFO2 0x25 45 #define TDA10048_TIME_ERROR_R 0x26 46 #define TDA10048_TIME_ERROR 0x27 47 #define TDA10048_FREQ_ERROR_LSB_R 0x28 48 #define TDA10048_FREQ_ERROR_MSB_R 0x29 49 #define TDA10048_FREQ_ERROR_LSB 0x2A 50 #define TDA10048_FREQ_ERROR_MSB 0x2B 51 #define TDA10048_IT_SEL 0x30 52 #define TDA10048_IT_STAT 0x32 53 #define TDA10048_DSP_AD_LSB 0x3C 54 #define TDA10048_DSP_AD_MSB 0x3D 55 #define TDA10048_DSP_REG_LSB 0x3E 56 #define TDA10048_DSP_REG_MSB 0x3F 57 #define TDA10048_CONF_TRISTATE1 0x44 58 #define TDA10048_CONF_TRISTATE2 0x45 59 #define TDA10048_CONF_POLARITY 0x46 60 #define TDA10048_GPIO_SP_DS0 0x48 61 #define TDA10048_GPIO_SP_DS1 0x49 62 #define TDA10048_GPIO_SP_DS2 0x4A 63 #define TDA10048_GPIO_SP_DS3 0x4B 64 #define TDA10048_GPIO_OUT_SEL 0x4C 65 #define TDA10048_GPIO_SELECT 0x4D 66 #define TDA10048_IC_MODE 0x4E 67 #define TDA10048_CONF_XO 0x50 68 #define TDA10048_CONF_PLL1 0x51 69 #define TDA10048_CONF_PLL2 0x52 70 #define TDA10048_CONF_PLL3 0x53 71 #define TDA10048_CONF_ADC 0x54 72 #define TDA10048_CONF_ADC_2 0x55 73 #define TDA10048_CONF_C1_1 0x60 74 #define TDA10048_CONF_C1_3 0x62 75 #define TDA10048_AGC_CONF 0x70 76 #define TDA10048_AGC_THRESHOLD_LSB 0x72 77 #define TDA10048_AGC_THRESHOLD_MSB 0x73 78 #define TDA10048_AGC_RENORM 0x74 79 #define TDA10048_AGC_GAINS 0x76 80 #define TDA10048_AGC_TUN_MIN 0x78 81 #define TDA10048_AGC_TUN_MAX 0x79 82 #define TDA10048_AGC_IF_MIN 0x7A 83 #define TDA10048_AGC_IF_MAX 0x7B 84 #define TDA10048_AGC_TUN_LEVEL 0x7E 85 #define TDA10048_AGC_IF_LEVEL 0x7F 86 #define TDA10048_DIG_AGC_LEVEL 0x81 87 #define TDA10048_FREQ_PHY2_LSB 0x86 88 #define TDA10048_FREQ_PHY2_MSB 0x87 89 #define TDA10048_TIME_INVWREF_LSB 0x88 90 #define TDA10048_TIME_INVWREF_MSB 0x89 91 #define TDA10048_TIME_WREF_LSB 0x8A 92 #define TDA10048_TIME_WREF_MID1 0x8B 93 #define TDA10048_TIME_WREF_MID2 0x8C 94 #define TDA10048_TIME_WREF_MSB 0x8D 95 #define TDA10048_NP_OUT 0xA2 96 #define TDA10048_CELL_ID_LSB 0xA4 97 #define TDA10048_CELL_ID_MSB 0xA5 98 #define TDA10048_EXTTPS_ODD 0xAA 99 #define TDA10048_EXTTPS_EVEN 0xAB 100 #define TDA10048_TPS_LENGTH 0xAC 101 #define TDA10048_FREE_REG_1 0xB2 102 #define TDA10048_FREE_REG_2 0xB3 103 #define TDA10048_CONF_C3_1 0xC0 104 #define TDA10048_CVBER_CTRL 0xC2 105 #define TDA10048_CBER_NMAX_LSB 0xC4 106 #define TDA10048_CBER_NMAX_MSB 0xC5 107 #define TDA10048_CBER_LSB 0xC6 108 #define TDA10048_CBER_MSB 0xC7 109 #define TDA10048_VBER_LSB 0xC8 110 #define TDA10048_VBER_MID 0xC9 111 #define TDA10048_VBER_MSB 0xCA 112 #define TDA10048_CVBER_LUT 0xCC 113 #define TDA10048_UNCOR_CTRL 0xCD 114 #define TDA10048_UNCOR_CPT_LSB 0xCE 115 #define TDA10048_UNCOR_CPT_MSB 0xCF 116 #define TDA10048_SOFT_IT_C3 0xD6 117 #define TDA10048_CONF_TS2 0xE0 118 #define TDA10048_CONF_TS1 0xE1 119 120 static unsigned int debug; 121 122 #define dprintk(level, fmt, arg...)\ 123 do { if (debug >= level)\ 124 printk(KERN_DEBUG "tda10048: " fmt, ## arg);\ 125 } while (0) 126 127 struct tda10048_state { 128 129 struct i2c_adapter *i2c; 130 131 /* We'll cache and update the attach config settings */ 132 struct tda10048_config config; 133 struct dvb_frontend frontend; 134 135 int fwloaded; 136 137 u32 freq_if_hz; 138 u32 xtal_hz; 139 u32 pll_mfactor; 140 u32 pll_nfactor; 141 u32 pll_pfactor; 142 u32 sample_freq; 143 144 u32 bandwidth; 145 }; 146 147 static struct init_tab { 148 u8 reg; 149 u16 data; 150 } init_tab[] = { 151 { TDA10048_CONF_PLL1, 0x08 }, 152 { TDA10048_CONF_ADC_2, 0x00 }, 153 { TDA10048_CONF_C4_1, 0x00 }, 154 { TDA10048_CONF_PLL1, 0x0f }, 155 { TDA10048_CONF_PLL2, 0x0a }, 156 { TDA10048_CONF_PLL3, 0x43 }, 157 { TDA10048_FREQ_PHY2_LSB, 0x02 }, 158 { TDA10048_FREQ_PHY2_MSB, 0x0a }, 159 { TDA10048_TIME_WREF_LSB, 0xbd }, 160 { TDA10048_TIME_WREF_MID1, 0xe4 }, 161 { TDA10048_TIME_WREF_MID2, 0xa8 }, 162 { TDA10048_TIME_WREF_MSB, 0x02 }, 163 { TDA10048_TIME_INVWREF_LSB, 0x04 }, 164 { TDA10048_TIME_INVWREF_MSB, 0x06 }, 165 { TDA10048_CONF_C4_1, 0x00 }, 166 { TDA10048_CONF_C1_1, 0xa8 }, 167 { TDA10048_AGC_CONF, 0x16 }, 168 { TDA10048_CONF_C1_3, 0x0b }, 169 { TDA10048_AGC_TUN_MIN, 0x00 }, 170 { TDA10048_AGC_TUN_MAX, 0xff }, 171 { TDA10048_AGC_IF_MIN, 0x00 }, 172 { TDA10048_AGC_IF_MAX, 0xff }, 173 { TDA10048_AGC_THRESHOLD_MSB, 0x00 }, 174 { TDA10048_AGC_THRESHOLD_LSB, 0x70 }, 175 { TDA10048_CVBER_CTRL, 0x38 }, 176 { TDA10048_AGC_GAINS, 0x12 }, 177 { TDA10048_CONF_XO, 0x00 }, 178 { TDA10048_CONF_TS1, 0x07 }, 179 { TDA10048_IC_MODE, 0x00 }, 180 { TDA10048_CONF_TS2, 0xc0 }, 181 { TDA10048_CONF_TRISTATE1, 0x21 }, 182 { TDA10048_CONF_TRISTATE2, 0x00 }, 183 { TDA10048_CONF_POLARITY, 0x00 }, 184 { TDA10048_CONF_C4_2, 0x04 }, 185 { TDA10048_CONF_ADC, 0x60 }, 186 { TDA10048_CONF_ADC_2, 0x10 }, 187 { TDA10048_CONF_ADC, 0x60 }, 188 { TDA10048_CONF_ADC_2, 0x00 }, 189 { TDA10048_CONF_C1_1, 0xa8 }, 190 { TDA10048_UNCOR_CTRL, 0x00 }, 191 { TDA10048_CONF_C4_2, 0x04 }, 192 }; 193 194 static struct pll_tab { 195 u32 clk_freq_khz; 196 u32 if_freq_khz; 197 } pll_tab[] = { 198 { TDA10048_CLK_4000, TDA10048_IF_36130 }, 199 { TDA10048_CLK_16000, TDA10048_IF_3300 }, 200 { TDA10048_CLK_16000, TDA10048_IF_3500 }, 201 { TDA10048_CLK_16000, TDA10048_IF_3800 }, 202 { TDA10048_CLK_16000, TDA10048_IF_4000 }, 203 { TDA10048_CLK_16000, TDA10048_IF_4300 }, 204 { TDA10048_CLK_16000, TDA10048_IF_4500 }, 205 { TDA10048_CLK_16000, TDA10048_IF_5000 }, 206 { TDA10048_CLK_16000, TDA10048_IF_36130 }, 207 }; 208 209 static int tda10048_writereg(struct tda10048_state *state, u8 reg, u8 data) 210 { 211 struct tda10048_config *config = &state->config; 212 int ret; 213 u8 buf[] = { reg, data }; 214 struct i2c_msg msg = { 215 .addr = config->demod_address, 216 .flags = 0, .buf = buf, .len = 2 }; 217 218 dprintk(2, "%s(reg = 0x%02x, data = 0x%02x)\n", __func__, reg, data); 219 220 ret = i2c_transfer(state->i2c, &msg, 1); 221 222 if (ret != 1) 223 printk("%s: writereg error (ret == %i)\n", __func__, ret); 224 225 return (ret != 1) ? -1 : 0; 226 } 227 228 static u8 tda10048_readreg(struct tda10048_state *state, u8 reg) 229 { 230 struct tda10048_config *config = &state->config; 231 int ret; 232 u8 b0[] = { reg }; 233 u8 b1[] = { 0 }; 234 struct i2c_msg msg[] = { 235 { .addr = config->demod_address, 236 .flags = 0, .buf = b0, .len = 1 }, 237 { .addr = config->demod_address, 238 .flags = I2C_M_RD, .buf = b1, .len = 1 } }; 239 240 dprintk(2, "%s(reg = 0x%02x)\n", __func__, reg); 241 242 ret = i2c_transfer(state->i2c, msg, 2); 243 244 if (ret != 2) 245 printk(KERN_ERR "%s: readreg error (ret == %i)\n", 246 __func__, ret); 247 248 return b1[0]; 249 } 250 251 static int tda10048_writeregbulk(struct tda10048_state *state, u8 reg, 252 const u8 *data, u16 len) 253 { 254 struct tda10048_config *config = &state->config; 255 int ret = -EREMOTEIO; 256 struct i2c_msg msg; 257 u8 *buf; 258 259 dprintk(2, "%s(%d, ?, len = %d)\n", __func__, reg, len); 260 261 buf = kmalloc(len + 1, GFP_KERNEL); 262 if (buf == NULL) { 263 ret = -ENOMEM; 264 goto error; 265 } 266 267 *buf = reg; 268 memcpy(buf + 1, data, len); 269 270 msg.addr = config->demod_address; 271 msg.flags = 0; 272 msg.buf = buf; 273 msg.len = len + 1; 274 275 dprintk(2, "%s(): write len = %d\n", 276 __func__, msg.len); 277 278 ret = i2c_transfer(state->i2c, &msg, 1); 279 if (ret != 1) { 280 printk(KERN_ERR "%s(): writereg error err %i\n", 281 __func__, ret); 282 ret = -EREMOTEIO; 283 } 284 285 error: 286 kfree(buf); 287 288 return ret; 289 } 290 291 static int tda10048_set_phy2(struct dvb_frontend *fe, u32 sample_freq_hz, 292 u32 if_hz) 293 { 294 struct tda10048_state *state = fe->demodulator_priv; 295 u64 t; 296 297 dprintk(1, "%s()\n", __func__); 298 299 if (sample_freq_hz == 0) 300 return -EINVAL; 301 302 if (if_hz < (sample_freq_hz / 2)) { 303 /* PHY2 = (if2/fs) * 2^15 */ 304 t = if_hz; 305 t *= 10; 306 t *= 32768; 307 do_div(t, sample_freq_hz); 308 t += 5; 309 do_div(t, 10); 310 } else { 311 /* PHY2 = ((IF1-fs)/fs) * 2^15 */ 312 t = sample_freq_hz - if_hz; 313 t *= 10; 314 t *= 32768; 315 do_div(t, sample_freq_hz); 316 t += 5; 317 do_div(t, 10); 318 t = ~t + 1; 319 } 320 321 tda10048_writereg(state, TDA10048_FREQ_PHY2_LSB, (u8)t); 322 tda10048_writereg(state, TDA10048_FREQ_PHY2_MSB, (u8)(t >> 8)); 323 324 return 0; 325 } 326 327 static int tda10048_set_wref(struct dvb_frontend *fe, u32 sample_freq_hz, 328 u32 bw) 329 { 330 struct tda10048_state *state = fe->demodulator_priv; 331 u64 t; 332 u32 z; 333 334 dprintk(1, "%s()\n", __func__); 335 336 if (sample_freq_hz == 0) 337 return -EINVAL; 338 339 /* WREF = (B / (7 * fs)) * 2^31 */ 340 t = bw * 10; 341 /* avoid warning: this decimal constant is unsigned only in ISO C90 */ 342 /* t *= 2147483648 on 32bit platforms */ 343 t *= (2048 * 1024); 344 t *= 1024; 345 346 /* 347 * Sample frequency is typically 55 MHz, with a theoretical maximum of 348 * 69 MHz. With a 32 bit z we have enough accuracy for up to 613 MHz. 349 */ 350 z = 7 * sample_freq_hz; 351 do_div(t, z); 352 t += 5; 353 do_div(t, 10); 354 355 tda10048_writereg(state, TDA10048_TIME_WREF_LSB, (u8)t); 356 tda10048_writereg(state, TDA10048_TIME_WREF_MID1, (u8)(t >> 8)); 357 tda10048_writereg(state, TDA10048_TIME_WREF_MID2, (u8)(t >> 16)); 358 tda10048_writereg(state, TDA10048_TIME_WREF_MSB, (u8)(t >> 24)); 359 360 return 0; 361 } 362 363 static int tda10048_set_invwref(struct dvb_frontend *fe, u32 sample_freq_hz, 364 u32 bw) 365 { 366 struct tda10048_state *state = fe->demodulator_priv; 367 u64 t; 368 369 dprintk(1, "%s()\n", __func__); 370 371 if (sample_freq_hz == 0) 372 return -EINVAL; 373 374 /* INVWREF = ((7 * fs) / B) * 2^5 */ 375 t = sample_freq_hz; 376 t *= 7; 377 t *= 32; 378 t *= 10; 379 do_div(t, bw); 380 t += 5; 381 do_div(t, 10); 382 383 tda10048_writereg(state, TDA10048_TIME_INVWREF_LSB, (u8)t); 384 tda10048_writereg(state, TDA10048_TIME_INVWREF_MSB, (u8)(t >> 8)); 385 386 return 0; 387 } 388 389 static int tda10048_set_bandwidth(struct dvb_frontend *fe, 390 u32 bw) 391 { 392 struct tda10048_state *state = fe->demodulator_priv; 393 dprintk(1, "%s(bw=%d)\n", __func__, bw); 394 395 /* Bandwidth setting may need to be adjusted */ 396 switch (bw) { 397 case 6000000: 398 case 7000000: 399 case 8000000: 400 tda10048_set_wref(fe, state->sample_freq, bw); 401 tda10048_set_invwref(fe, state->sample_freq, bw); 402 break; 403 default: 404 printk(KERN_ERR "%s() invalid bandwidth\n", __func__); 405 return -EINVAL; 406 } 407 408 state->bandwidth = bw; 409 410 return 0; 411 } 412 413 static int tda10048_set_if(struct dvb_frontend *fe, u32 bw) 414 { 415 struct tda10048_state *state = fe->demodulator_priv; 416 struct tda10048_config *config = &state->config; 417 int i; 418 u32 if_freq_khz; 419 u64 sample_freq; 420 421 dprintk(1, "%s(bw = %d)\n", __func__, bw); 422 423 /* based on target bandwidth and clk we calculate pll factors */ 424 switch (bw) { 425 case 6000000: 426 if_freq_khz = config->dtv6_if_freq_khz; 427 break; 428 case 7000000: 429 if_freq_khz = config->dtv7_if_freq_khz; 430 break; 431 case 8000000: 432 if_freq_khz = config->dtv8_if_freq_khz; 433 break; 434 default: 435 printk(KERN_ERR "%s() no default\n", __func__); 436 return -EINVAL; 437 } 438 439 for (i = 0; i < ARRAY_SIZE(pll_tab); i++) { 440 if ((pll_tab[i].clk_freq_khz == config->clk_freq_khz) && 441 (pll_tab[i].if_freq_khz == if_freq_khz)) { 442 443 state->freq_if_hz = pll_tab[i].if_freq_khz * 1000; 444 state->xtal_hz = pll_tab[i].clk_freq_khz * 1000; 445 break; 446 } 447 } 448 if (i == ARRAY_SIZE(pll_tab)) { 449 printk(KERN_ERR "%s() Incorrect attach settings\n", 450 __func__); 451 return -EINVAL; 452 } 453 454 dprintk(1, "- freq_if_hz = %d\n", state->freq_if_hz); 455 dprintk(1, "- xtal_hz = %d\n", state->xtal_hz); 456 dprintk(1, "- pll_mfactor = %d\n", state->pll_mfactor); 457 dprintk(1, "- pll_nfactor = %d\n", state->pll_nfactor); 458 dprintk(1, "- pll_pfactor = %d\n", state->pll_pfactor); 459 460 /* Calculate the sample frequency */ 461 sample_freq = state->xtal_hz; 462 sample_freq *= state->pll_mfactor + 45; 463 do_div(sample_freq, state->pll_nfactor + 1); 464 do_div(sample_freq, state->pll_pfactor + 4); 465 state->sample_freq = sample_freq; 466 dprintk(1, "- sample_freq = %d\n", state->sample_freq); 467 468 /* Update the I/F */ 469 tda10048_set_phy2(fe, state->sample_freq, state->freq_if_hz); 470 471 return 0; 472 } 473 474 static int tda10048_firmware_upload(struct dvb_frontend *fe) 475 { 476 struct tda10048_state *state = fe->demodulator_priv; 477 struct tda10048_config *config = &state->config; 478 const struct firmware *fw; 479 int ret; 480 int pos = 0; 481 int cnt; 482 u8 wlen = config->fwbulkwritelen; 483 484 if ((wlen != TDA10048_BULKWRITE_200) && (wlen != TDA10048_BULKWRITE_50)) 485 wlen = TDA10048_BULKWRITE_200; 486 487 /* request the firmware, this will block and timeout */ 488 printk(KERN_INFO "%s: waiting for firmware upload (%s)...\n", 489 __func__, 490 TDA10048_DEFAULT_FIRMWARE); 491 492 ret = request_firmware(&fw, TDA10048_DEFAULT_FIRMWARE, 493 state->i2c->dev.parent); 494 if (ret) { 495 printk(KERN_ERR "%s: Upload failed. (file not found?)\n", 496 __func__); 497 return -EIO; 498 } else { 499 printk(KERN_INFO "%s: firmware read %zu bytes.\n", 500 __func__, 501 fw->size); 502 ret = 0; 503 } 504 505 if (fw->size != TDA10048_DEFAULT_FIRMWARE_SIZE) { 506 printk(KERN_ERR "%s: firmware incorrect size\n", __func__); 507 ret = -EIO; 508 } else { 509 printk(KERN_INFO "%s: firmware uploading\n", __func__); 510 511 /* Soft reset */ 512 tda10048_writereg(state, TDA10048_CONF_TRISTATE1, 513 tda10048_readreg(state, TDA10048_CONF_TRISTATE1) 514 & 0xfe); 515 tda10048_writereg(state, TDA10048_CONF_TRISTATE1, 516 tda10048_readreg(state, TDA10048_CONF_TRISTATE1) 517 | 0x01); 518 519 /* Put the demod into host download mode */ 520 tda10048_writereg(state, TDA10048_CONF_C4_1, 521 tda10048_readreg(state, TDA10048_CONF_C4_1) & 0xf9); 522 523 /* Boot the DSP */ 524 tda10048_writereg(state, TDA10048_CONF_C4_1, 525 tda10048_readreg(state, TDA10048_CONF_C4_1) | 0x08); 526 527 /* Prepare for download */ 528 tda10048_writereg(state, TDA10048_DSP_CODE_CPT, 0); 529 530 /* Download the firmware payload */ 531 while (pos < fw->size) { 532 533 if ((fw->size - pos) > wlen) 534 cnt = wlen; 535 else 536 cnt = fw->size - pos; 537 538 tda10048_writeregbulk(state, TDA10048_DSP_CODE_IN, 539 &fw->data[pos], cnt); 540 541 pos += cnt; 542 } 543 544 ret = -EIO; 545 /* Wait up to 250ms for the DSP to boot */ 546 for (cnt = 0; cnt < 250 ; cnt += 10) { 547 548 msleep(10); 549 550 if (tda10048_readreg(state, TDA10048_SYNC_STATUS) 551 & 0x40) { 552 ret = 0; 553 break; 554 } 555 } 556 } 557 558 release_firmware(fw); 559 560 if (ret == 0) { 561 printk(KERN_INFO "%s: firmware uploaded\n", __func__); 562 state->fwloaded = 1; 563 } else 564 printk(KERN_ERR "%s: firmware upload failed\n", __func__); 565 566 return ret; 567 } 568 569 static int tda10048_set_inversion(struct dvb_frontend *fe, int inversion) 570 { 571 struct tda10048_state *state = fe->demodulator_priv; 572 573 dprintk(1, "%s(%d)\n", __func__, inversion); 574 575 if (inversion == TDA10048_INVERSION_ON) 576 tda10048_writereg(state, TDA10048_CONF_C1_1, 577 tda10048_readreg(state, TDA10048_CONF_C1_1) | 0x20); 578 else 579 tda10048_writereg(state, TDA10048_CONF_C1_1, 580 tda10048_readreg(state, TDA10048_CONF_C1_1) & 0xdf); 581 582 return 0; 583 } 584 585 /* Retrieve the demod settings */ 586 static int tda10048_get_tps(struct tda10048_state *state, 587 struct dtv_frontend_properties *p) 588 { 589 u8 val; 590 591 /* Make sure the TPS regs are valid */ 592 if (!(tda10048_readreg(state, TDA10048_AUTO) & 0x01)) 593 return -EAGAIN; 594 595 val = tda10048_readreg(state, TDA10048_OUT_CONF2); 596 switch ((val & 0x60) >> 5) { 597 case 0: 598 p->modulation = QPSK; 599 break; 600 case 1: 601 p->modulation = QAM_16; 602 break; 603 case 2: 604 p->modulation = QAM_64; 605 break; 606 } 607 switch ((val & 0x18) >> 3) { 608 case 0: 609 p->hierarchy = HIERARCHY_NONE; 610 break; 611 case 1: 612 p->hierarchy = HIERARCHY_1; 613 break; 614 case 2: 615 p->hierarchy = HIERARCHY_2; 616 break; 617 case 3: 618 p->hierarchy = HIERARCHY_4; 619 break; 620 } 621 switch (val & 0x07) { 622 case 0: 623 p->code_rate_HP = FEC_1_2; 624 break; 625 case 1: 626 p->code_rate_HP = FEC_2_3; 627 break; 628 case 2: 629 p->code_rate_HP = FEC_3_4; 630 break; 631 case 3: 632 p->code_rate_HP = FEC_5_6; 633 break; 634 case 4: 635 p->code_rate_HP = FEC_7_8; 636 break; 637 } 638 639 val = tda10048_readreg(state, TDA10048_OUT_CONF3); 640 switch (val & 0x07) { 641 case 0: 642 p->code_rate_LP = FEC_1_2; 643 break; 644 case 1: 645 p->code_rate_LP = FEC_2_3; 646 break; 647 case 2: 648 p->code_rate_LP = FEC_3_4; 649 break; 650 case 3: 651 p->code_rate_LP = FEC_5_6; 652 break; 653 case 4: 654 p->code_rate_LP = FEC_7_8; 655 break; 656 } 657 658 val = tda10048_readreg(state, TDA10048_OUT_CONF1); 659 switch ((val & 0x0c) >> 2) { 660 case 0: 661 p->guard_interval = GUARD_INTERVAL_1_32; 662 break; 663 case 1: 664 p->guard_interval = GUARD_INTERVAL_1_16; 665 break; 666 case 2: 667 p->guard_interval = GUARD_INTERVAL_1_8; 668 break; 669 case 3: 670 p->guard_interval = GUARD_INTERVAL_1_4; 671 break; 672 } 673 switch (val & 0x03) { 674 case 0: 675 p->transmission_mode = TRANSMISSION_MODE_2K; 676 break; 677 case 1: 678 p->transmission_mode = TRANSMISSION_MODE_8K; 679 break; 680 } 681 682 return 0; 683 } 684 685 static int tda10048_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 686 { 687 struct tda10048_state *state = fe->demodulator_priv; 688 struct tda10048_config *config = &state->config; 689 dprintk(1, "%s(%d)\n", __func__, enable); 690 691 if (config->disable_gate_access) 692 return 0; 693 694 if (enable) 695 return tda10048_writereg(state, TDA10048_CONF_C4_1, 696 tda10048_readreg(state, TDA10048_CONF_C4_1) | 0x02); 697 else 698 return tda10048_writereg(state, TDA10048_CONF_C4_1, 699 tda10048_readreg(state, TDA10048_CONF_C4_1) & 0xfd); 700 } 701 702 static int tda10048_output_mode(struct dvb_frontend *fe, int serial) 703 { 704 struct tda10048_state *state = fe->demodulator_priv; 705 dprintk(1, "%s(%d)\n", __func__, serial); 706 707 /* Ensure pins are out of tri-state */ 708 tda10048_writereg(state, TDA10048_CONF_TRISTATE1, 0x21); 709 tda10048_writereg(state, TDA10048_CONF_TRISTATE2, 0x00); 710 711 if (serial) { 712 tda10048_writereg(state, TDA10048_IC_MODE, 0x80 | 0x20); 713 tda10048_writereg(state, TDA10048_CONF_TS2, 0xc0); 714 } else { 715 tda10048_writereg(state, TDA10048_IC_MODE, 0x00); 716 tda10048_writereg(state, TDA10048_CONF_TS2, 0x01); 717 } 718 719 return 0; 720 } 721 722 /* Talk to the demod, set the FEC, GUARD, QAM settings etc */ 723 /* TODO: Support manual tuning with specific params */ 724 static int tda10048_set_frontend(struct dvb_frontend *fe) 725 { 726 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 727 struct tda10048_state *state = fe->demodulator_priv; 728 729 dprintk(1, "%s(frequency=%d)\n", __func__, p->frequency); 730 731 /* Update the I/F pll's if the bandwidth changes */ 732 if (p->bandwidth_hz != state->bandwidth) { 733 tda10048_set_if(fe, p->bandwidth_hz); 734 tda10048_set_bandwidth(fe, p->bandwidth_hz); 735 } 736 737 if (fe->ops.tuner_ops.set_params) { 738 739 if (fe->ops.i2c_gate_ctrl) 740 fe->ops.i2c_gate_ctrl(fe, 1); 741 742 fe->ops.tuner_ops.set_params(fe); 743 744 if (fe->ops.i2c_gate_ctrl) 745 fe->ops.i2c_gate_ctrl(fe, 0); 746 } 747 748 /* Enable demod TPS auto detection and begin acquisition */ 749 tda10048_writereg(state, TDA10048_AUTO, 0x57); 750 /* trigger cber and vber acquisition */ 751 tda10048_writereg(state, TDA10048_CVBER_CTRL, 0x3B); 752 753 return 0; 754 } 755 756 /* Establish sane defaults and load firmware. */ 757 static int tda10048_init(struct dvb_frontend *fe) 758 { 759 struct tda10048_state *state = fe->demodulator_priv; 760 struct tda10048_config *config = &state->config; 761 int ret = 0, i; 762 763 dprintk(1, "%s()\n", __func__); 764 765 /* PLL */ 766 init_tab[4].data = (u8)(state->pll_mfactor); 767 init_tab[5].data = (u8)(state->pll_nfactor) | 0x40; 768 769 /* Apply register defaults */ 770 for (i = 0; i < ARRAY_SIZE(init_tab); i++) 771 tda10048_writereg(state, init_tab[i].reg, init_tab[i].data); 772 773 if (state->fwloaded == 0) 774 ret = tda10048_firmware_upload(fe); 775 776 /* Set either serial or parallel */ 777 tda10048_output_mode(fe, config->output_mode); 778 779 /* Set inversion */ 780 tda10048_set_inversion(fe, config->inversion); 781 782 /* Establish default RF values */ 783 tda10048_set_if(fe, 8000000); 784 tda10048_set_bandwidth(fe, 8000000); 785 786 /* Ensure we leave the gate closed */ 787 tda10048_i2c_gate_ctrl(fe, 0); 788 789 return ret; 790 } 791 792 static int tda10048_read_status(struct dvb_frontend *fe, enum fe_status *status) 793 { 794 struct tda10048_state *state = fe->demodulator_priv; 795 u8 reg; 796 797 *status = 0; 798 799 reg = tda10048_readreg(state, TDA10048_SYNC_STATUS); 800 801 dprintk(1, "%s() status =0x%02x\n", __func__, reg); 802 803 if (reg & 0x02) 804 *status |= FE_HAS_CARRIER; 805 806 if (reg & 0x04) 807 *status |= FE_HAS_SIGNAL; 808 809 if (reg & 0x08) { 810 *status |= FE_HAS_LOCK; 811 *status |= FE_HAS_VITERBI; 812 *status |= FE_HAS_SYNC; 813 } 814 815 return 0; 816 } 817 818 static int tda10048_read_ber(struct dvb_frontend *fe, u32 *ber) 819 { 820 struct tda10048_state *state = fe->demodulator_priv; 821 static u32 cber_current; 822 u32 cber_nmax; 823 u64 cber_tmp; 824 825 dprintk(1, "%s()\n", __func__); 826 827 /* update cber on interrupt */ 828 if (tda10048_readreg(state, TDA10048_SOFT_IT_C3) & 0x01) { 829 cber_tmp = tda10048_readreg(state, TDA10048_CBER_MSB) << 8 | 830 tda10048_readreg(state, TDA10048_CBER_LSB); 831 cber_nmax = tda10048_readreg(state, TDA10048_CBER_NMAX_MSB) << 8 | 832 tda10048_readreg(state, TDA10048_CBER_NMAX_LSB); 833 cber_tmp *= 100000000; 834 cber_tmp *= 2; 835 cber_tmp = div_u64(cber_tmp, (cber_nmax * 32) + 1); 836 cber_current = (u32)cber_tmp; 837 /* retrigger cber acquisition */ 838 tda10048_writereg(state, TDA10048_CVBER_CTRL, 0x39); 839 } 840 /* actual cber is (*ber)/1e8 */ 841 *ber = cber_current; 842 843 return 0; 844 } 845 846 static int tda10048_read_signal_strength(struct dvb_frontend *fe, 847 u16 *signal_strength) 848 { 849 struct tda10048_state *state = fe->demodulator_priv; 850 u8 v; 851 852 dprintk(1, "%s()\n", __func__); 853 854 *signal_strength = 65535; 855 856 v = tda10048_readreg(state, TDA10048_NP_OUT); 857 if (v > 0) 858 *signal_strength -= (v << 8) | v; 859 860 return 0; 861 } 862 863 /* SNR lookup table */ 864 static struct snr_tab { 865 u8 val; 866 u8 data; 867 } snr_tab[] = { 868 { 0, 0 }, 869 { 1, 246 }, 870 { 2, 215 }, 871 { 3, 198 }, 872 { 4, 185 }, 873 { 5, 176 }, 874 { 6, 168 }, 875 { 7, 161 }, 876 { 8, 155 }, 877 { 9, 150 }, 878 { 10, 146 }, 879 { 11, 141 }, 880 { 12, 138 }, 881 { 13, 134 }, 882 { 14, 131 }, 883 { 15, 128 }, 884 { 16, 125 }, 885 { 17, 122 }, 886 { 18, 120 }, 887 { 19, 118 }, 888 { 20, 115 }, 889 { 21, 113 }, 890 { 22, 111 }, 891 { 23, 109 }, 892 { 24, 107 }, 893 { 25, 106 }, 894 { 26, 104 }, 895 { 27, 102 }, 896 { 28, 101 }, 897 { 29, 99 }, 898 { 30, 98 }, 899 { 31, 96 }, 900 { 32, 95 }, 901 { 33, 94 }, 902 { 34, 92 }, 903 { 35, 91 }, 904 { 36, 90 }, 905 { 37, 89 }, 906 { 38, 88 }, 907 { 39, 86 }, 908 { 40, 85 }, 909 { 41, 84 }, 910 { 42, 83 }, 911 { 43, 82 }, 912 { 44, 81 }, 913 { 45, 80 }, 914 { 46, 79 }, 915 { 47, 78 }, 916 { 48, 77 }, 917 { 49, 76 }, 918 { 50, 76 }, 919 { 51, 75 }, 920 { 52, 74 }, 921 { 53, 73 }, 922 { 54, 72 }, 923 { 56, 71 }, 924 { 57, 70 }, 925 { 58, 69 }, 926 { 60, 68 }, 927 { 61, 67 }, 928 { 63, 66 }, 929 { 64, 65 }, 930 { 66, 64 }, 931 { 67, 63 }, 932 { 68, 62 }, 933 { 69, 62 }, 934 { 70, 61 }, 935 { 72, 60 }, 936 { 74, 59 }, 937 { 75, 58 }, 938 { 77, 57 }, 939 { 79, 56 }, 940 { 81, 55 }, 941 { 83, 54 }, 942 { 85, 53 }, 943 { 87, 52 }, 944 { 89, 51 }, 945 { 91, 50 }, 946 { 93, 49 }, 947 { 95, 48 }, 948 { 97, 47 }, 949 { 100, 46 }, 950 { 102, 45 }, 951 { 104, 44 }, 952 { 107, 43 }, 953 { 109, 42 }, 954 { 112, 41 }, 955 { 114, 40 }, 956 { 117, 39 }, 957 { 120, 38 }, 958 { 123, 37 }, 959 { 125, 36 }, 960 { 128, 35 }, 961 { 131, 34 }, 962 { 134, 33 }, 963 { 138, 32 }, 964 { 141, 31 }, 965 { 144, 30 }, 966 { 147, 29 }, 967 { 151, 28 }, 968 { 154, 27 }, 969 { 158, 26 }, 970 { 162, 25 }, 971 { 165, 24 }, 972 { 169, 23 }, 973 { 173, 22 }, 974 { 177, 21 }, 975 { 181, 20 }, 976 { 186, 19 }, 977 { 190, 18 }, 978 { 194, 17 }, 979 { 199, 16 }, 980 { 204, 15 }, 981 { 208, 14 }, 982 { 213, 13 }, 983 { 218, 12 }, 984 { 223, 11 }, 985 { 229, 10 }, 986 { 234, 9 }, 987 { 239, 8 }, 988 { 245, 7 }, 989 { 251, 6 }, 990 { 255, 5 }, 991 }; 992 993 static int tda10048_read_snr(struct dvb_frontend *fe, u16 *snr) 994 { 995 struct tda10048_state *state = fe->demodulator_priv; 996 u8 v; 997 int i, ret = -EINVAL; 998 999 dprintk(1, "%s()\n", __func__); 1000 1001 v = tda10048_readreg(state, TDA10048_NP_OUT); 1002 for (i = 0; i < ARRAY_SIZE(snr_tab); i++) { 1003 if (v <= snr_tab[i].val) { 1004 *snr = snr_tab[i].data; 1005 ret = 0; 1006 break; 1007 } 1008 } 1009 1010 return ret; 1011 } 1012 1013 static int tda10048_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 1014 { 1015 struct tda10048_state *state = fe->demodulator_priv; 1016 1017 dprintk(1, "%s()\n", __func__); 1018 1019 *ucblocks = tda10048_readreg(state, TDA10048_UNCOR_CPT_MSB) << 8 | 1020 tda10048_readreg(state, TDA10048_UNCOR_CPT_LSB); 1021 /* clear the uncorrected TS packets counter when saturated */ 1022 if (*ucblocks == 0xFFFF) 1023 tda10048_writereg(state, TDA10048_UNCOR_CTRL, 0x80); 1024 1025 return 0; 1026 } 1027 1028 static int tda10048_get_frontend(struct dvb_frontend *fe, 1029 struct dtv_frontend_properties *p) 1030 { 1031 struct tda10048_state *state = fe->demodulator_priv; 1032 1033 dprintk(1, "%s()\n", __func__); 1034 1035 p->inversion = tda10048_readreg(state, TDA10048_CONF_C1_1) 1036 & 0x20 ? INVERSION_ON : INVERSION_OFF; 1037 1038 return tda10048_get_tps(state, p); 1039 } 1040 1041 static int tda10048_get_tune_settings(struct dvb_frontend *fe, 1042 struct dvb_frontend_tune_settings *tune) 1043 { 1044 tune->min_delay_ms = 1000; 1045 return 0; 1046 } 1047 1048 static void tda10048_release(struct dvb_frontend *fe) 1049 { 1050 struct tda10048_state *state = fe->demodulator_priv; 1051 dprintk(1, "%s()\n", __func__); 1052 kfree(state); 1053 } 1054 1055 static void tda10048_establish_defaults(struct dvb_frontend *fe) 1056 { 1057 struct tda10048_state *state = fe->demodulator_priv; 1058 struct tda10048_config *config = &state->config; 1059 1060 /* Validate/default the config */ 1061 if (config->dtv6_if_freq_khz == 0) { 1062 config->dtv6_if_freq_khz = TDA10048_IF_4300; 1063 printk(KERN_WARNING "%s() tda10048_config.dtv6_if_freq_khz is not set (defaulting to %d)\n", 1064 __func__, 1065 config->dtv6_if_freq_khz); 1066 } 1067 1068 if (config->dtv7_if_freq_khz == 0) { 1069 config->dtv7_if_freq_khz = TDA10048_IF_4300; 1070 printk(KERN_WARNING "%s() tda10048_config.dtv7_if_freq_khz is not set (defaulting to %d)\n", 1071 __func__, 1072 config->dtv7_if_freq_khz); 1073 } 1074 1075 if (config->dtv8_if_freq_khz == 0) { 1076 config->dtv8_if_freq_khz = TDA10048_IF_4300; 1077 printk(KERN_WARNING "%s() tda10048_config.dtv8_if_freq_khz is not set (defaulting to %d)\n", 1078 __func__, 1079 config->dtv8_if_freq_khz); 1080 } 1081 1082 if (config->clk_freq_khz == 0) { 1083 config->clk_freq_khz = TDA10048_CLK_16000; 1084 printk(KERN_WARNING "%s() tda10048_config.clk_freq_khz is not set (defaulting to %d)\n", 1085 __func__, 1086 config->clk_freq_khz); 1087 } 1088 } 1089 1090 static const struct dvb_frontend_ops tda10048_ops; 1091 1092 struct dvb_frontend *tda10048_attach(const struct tda10048_config *config, 1093 struct i2c_adapter *i2c) 1094 { 1095 struct tda10048_state *state = NULL; 1096 1097 dprintk(1, "%s()\n", __func__); 1098 1099 /* allocate memory for the internal state */ 1100 state = kzalloc(sizeof(struct tda10048_state), GFP_KERNEL); 1101 if (state == NULL) 1102 goto error; 1103 1104 /* setup the state and clone the config */ 1105 memcpy(&state->config, config, sizeof(*config)); 1106 state->i2c = i2c; 1107 state->fwloaded = config->no_firmware; 1108 state->bandwidth = 8000000; 1109 1110 /* check if the demod is present */ 1111 if (tda10048_readreg(state, TDA10048_IDENTITY) != 0x048) 1112 goto error; 1113 1114 /* create dvb_frontend */ 1115 memcpy(&state->frontend.ops, &tda10048_ops, 1116 sizeof(struct dvb_frontend_ops)); 1117 state->frontend.demodulator_priv = state; 1118 1119 /* set pll */ 1120 if (config->set_pll) { 1121 state->pll_mfactor = config->pll_m; 1122 state->pll_nfactor = config->pll_n; 1123 state->pll_pfactor = config->pll_p; 1124 } else { 1125 state->pll_mfactor = 10; 1126 state->pll_nfactor = 3; 1127 state->pll_pfactor = 0; 1128 } 1129 1130 /* Establish any defaults the user didn't pass */ 1131 tda10048_establish_defaults(&state->frontend); 1132 1133 /* Set the xtal and freq defaults */ 1134 if (tda10048_set_if(&state->frontend, 8000000) != 0) 1135 goto error; 1136 1137 /* Default bandwidth */ 1138 if (tda10048_set_bandwidth(&state->frontend, 8000000) != 0) 1139 goto error; 1140 1141 /* Leave the gate closed */ 1142 tda10048_i2c_gate_ctrl(&state->frontend, 0); 1143 1144 return &state->frontend; 1145 1146 error: 1147 kfree(state); 1148 return NULL; 1149 } 1150 EXPORT_SYMBOL_GPL(tda10048_attach); 1151 1152 static const struct dvb_frontend_ops tda10048_ops = { 1153 .delsys = { SYS_DVBT }, 1154 .info = { 1155 .name = "NXP TDA10048HN DVB-T", 1156 .frequency_min_hz = 177 * MHz, 1157 .frequency_max_hz = 858 * MHz, 1158 .frequency_stepsize_hz = 166666, 1159 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 1160 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 1161 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | 1162 FE_CAN_HIERARCHY_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | 1163 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER 1164 }, 1165 1166 .release = tda10048_release, 1167 .init = tda10048_init, 1168 .i2c_gate_ctrl = tda10048_i2c_gate_ctrl, 1169 .set_frontend = tda10048_set_frontend, 1170 .get_frontend = tda10048_get_frontend, 1171 .get_tune_settings = tda10048_get_tune_settings, 1172 .read_status = tda10048_read_status, 1173 .read_ber = tda10048_read_ber, 1174 .read_signal_strength = tda10048_read_signal_strength, 1175 .read_snr = tda10048_read_snr, 1176 .read_ucblocks = tda10048_read_ucblocks, 1177 }; 1178 1179 module_param(debug, int, 0644); 1180 MODULE_PARM_DESC(debug, "Enable verbose debug messages"); 1181 1182 MODULE_DESCRIPTION("NXP TDA10048HN DVB-T Demodulator driver"); 1183 MODULE_AUTHOR("Steven Toth"); 1184 MODULE_LICENSE("GPL"); 1185