1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 243dd07f7SRalph Metzler #define AUD_COMM_EXEC__A 0x1000000 343dd07f7SRalph Metzler #define AUD_COMM_EXEC_STOP 0x0 443dd07f7SRalph Metzler #define FEC_COMM_EXEC__A 0x1C00000 543dd07f7SRalph Metzler #define FEC_COMM_EXEC_STOP 0x0 643dd07f7SRalph Metzler #define FEC_COMM_EXEC_ACTIVE 0x1 743dd07f7SRalph Metzler #define FEC_DI_COMM_EXEC__A 0x1C20000 843dd07f7SRalph Metzler #define FEC_DI_COMM_EXEC_STOP 0x0 943dd07f7SRalph Metzler #define FEC_DI_INPUT_CTL__A 0x1C20016 1043dd07f7SRalph Metzler #define FEC_RS_COMM_EXEC__A 0x1C30000 1143dd07f7SRalph Metzler #define FEC_RS_COMM_EXEC_STOP 0x0 1243dd07f7SRalph Metzler #define FEC_RS_MEASUREMENT_PERIOD__A 0x1C30012 1343dd07f7SRalph Metzler #define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C30013 148f3741e0SMauro Carvalho Chehab #define FEC_RS_NR_BIT_ERRORS__A 0x1C30014 1543dd07f7SRalph Metzler #define FEC_OC_MODE__A 0x1C40011 1643dd07f7SRalph Metzler #define FEC_OC_MODE_PARITY__M 0x1 1743dd07f7SRalph Metzler #define FEC_OC_DTO_MODE__A 0x1C40014 1843dd07f7SRalph Metzler #define FEC_OC_DTO_MODE_DYNAMIC__M 0x1 1943dd07f7SRalph Metzler #define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4 2043dd07f7SRalph Metzler #define FEC_OC_DTO_PERIOD__A 0x1C40015 2143dd07f7SRalph Metzler #define FEC_OC_DTO_BURST_LEN__A 0x1C40018 2243dd07f7SRalph Metzler #define FEC_OC_FCT_MODE__A 0x1C4001A 2343dd07f7SRalph Metzler #define FEC_OC_FCT_MODE__PRE 0x0 2443dd07f7SRalph Metzler #define FEC_OC_FCT_MODE_RAT_ENA__M 0x1 2543dd07f7SRalph Metzler #define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2 2643dd07f7SRalph Metzler #define FEC_OC_TMD_MODE__A 0x1C4001E 2743dd07f7SRalph Metzler #define FEC_OC_TMD_COUNT__A 0x1C4001F 2843dd07f7SRalph Metzler #define FEC_OC_TMD_HI_MARGIN__A 0x1C40020 2943dd07f7SRalph Metzler #define FEC_OC_TMD_LO_MARGIN__A 0x1C40021 3043dd07f7SRalph Metzler #define FEC_OC_TMD_INT_UPD_RATE__A 0x1C40023 3143dd07f7SRalph Metzler #define FEC_OC_AVR_PARM_A__A 0x1C40026 3243dd07f7SRalph Metzler #define FEC_OC_AVR_PARM_B__A 0x1C40027 3343dd07f7SRalph Metzler #define FEC_OC_RCN_GAIN__A 0x1C4002E 3443dd07f7SRalph Metzler #define FEC_OC_RCN_CTL_RATE_LO__A 0x1C40030 3543dd07f7SRalph Metzler #define FEC_OC_RCN_CTL_STEP_LO__A 0x1C40032 3643dd07f7SRalph Metzler #define FEC_OC_RCN_CTL_STEP_HI__A 0x1C40033 3743dd07f7SRalph Metzler #define FEC_OC_SNC_MODE__A 0x1C40040 3843dd07f7SRalph Metzler #define FEC_OC_SNC_MODE_SHUTDOWN__M 0x10 3943dd07f7SRalph Metzler #define FEC_OC_SNC_LWM__A 0x1C40041 4043dd07f7SRalph Metzler #define FEC_OC_SNC_HWM__A 0x1C40042 4143dd07f7SRalph Metzler #define FEC_OC_SNC_UNLOCK__A 0x1C40043 4243dd07f7SRalph Metzler #define FEC_OC_SNC_FAIL_PERIOD__A 0x1C40046 4343dd07f7SRalph Metzler #define FEC_OC_IPR_MODE__A 0x1C40048 4443dd07f7SRalph Metzler #define FEC_OC_IPR_MODE_SERIAL__M 0x1 4543dd07f7SRalph Metzler #define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x4 4643dd07f7SRalph Metzler #define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x10 4743dd07f7SRalph Metzler #define FEC_OC_IPR_INVERT__A 0x1C40049 4843dd07f7SRalph Metzler #define FEC_OC_IPR_INVERT_MD0__M 0x1 4943dd07f7SRalph Metzler #define FEC_OC_IPR_INVERT_MD1__M 0x2 5043dd07f7SRalph Metzler #define FEC_OC_IPR_INVERT_MD2__M 0x4 5143dd07f7SRalph Metzler #define FEC_OC_IPR_INVERT_MD3__M 0x8 5243dd07f7SRalph Metzler #define FEC_OC_IPR_INVERT_MD4__M 0x10 5343dd07f7SRalph Metzler #define FEC_OC_IPR_INVERT_MD5__M 0x20 5443dd07f7SRalph Metzler #define FEC_OC_IPR_INVERT_MD6__M 0x40 5543dd07f7SRalph Metzler #define FEC_OC_IPR_INVERT_MD7__M 0x80 5643dd07f7SRalph Metzler #define FEC_OC_IPR_INVERT_MERR__M 0x100 5743dd07f7SRalph Metzler #define FEC_OC_IPR_INVERT_MSTRT__M 0x200 5843dd07f7SRalph Metzler #define FEC_OC_IPR_INVERT_MVAL__M 0x400 5943dd07f7SRalph Metzler #define FEC_OC_IPR_INVERT_MCLK__M 0x800 6043dd07f7SRalph Metzler #define FEC_OC_OCR_INVERT__A 0x1C40052 6143dd07f7SRalph Metzler #define IQM_COMM_EXEC__A 0x1800000 6243dd07f7SRalph Metzler #define IQM_COMM_EXEC_B_STOP 0x0 6343dd07f7SRalph Metzler #define IQM_COMM_EXEC_B_ACTIVE 0x1 6443dd07f7SRalph Metzler #define IQM_FS_RATE_OFS_LO__A 0x1820010 6543dd07f7SRalph Metzler #define IQM_FS_ADJ_SEL__A 0x1820014 6643dd07f7SRalph Metzler #define IQM_FS_ADJ_SEL_B_OFF 0x0 6743dd07f7SRalph Metzler #define IQM_FS_ADJ_SEL_B_QAM 0x1 6843dd07f7SRalph Metzler #define IQM_FS_ADJ_SEL_B_VSB 0x2 6943dd07f7SRalph Metzler #define IQM_FD_RATESEL__A 0x1830010 7043dd07f7SRalph Metzler #define IQM_RC_RATE_OFS_LO__A 0x1840010 7143dd07f7SRalph Metzler #define IQM_RC_RATE_OFS_LO__W 16 7243dd07f7SRalph Metzler #define IQM_RC_RATE_OFS_LO__M 0xFFFF 7343dd07f7SRalph Metzler #define IQM_RC_RATE_OFS_HI__M 0xFF 7443dd07f7SRalph Metzler #define IQM_RC_ADJ_SEL__A 0x1840014 7543dd07f7SRalph Metzler #define IQM_RC_ADJ_SEL_B_OFF 0x0 7643dd07f7SRalph Metzler #define IQM_RC_ADJ_SEL_B_QAM 0x1 7743dd07f7SRalph Metzler #define IQM_RC_ADJ_SEL_B_VSB 0x2 7843dd07f7SRalph Metzler #define IQM_RC_STRETCH__A 0x1840016 7943dd07f7SRalph Metzler #define IQM_CF_COMM_INT_MSK__A 0x1860006 8043dd07f7SRalph Metzler #define IQM_CF_SYMMETRIC__A 0x1860010 8143dd07f7SRalph Metzler #define IQM_CF_MIDTAP__A 0x1860011 8243dd07f7SRalph Metzler #define IQM_CF_MIDTAP_RE__B 0 8343dd07f7SRalph Metzler #define IQM_CF_MIDTAP_IM__B 1 8443dd07f7SRalph Metzler #define IQM_CF_OUT_ENA__A 0x1860012 8543dd07f7SRalph Metzler #define IQM_CF_OUT_ENA_QAM__B 1 8643dd07f7SRalph Metzler #define IQM_CF_OUT_ENA_OFDM__M 0x4 8743dd07f7SRalph Metzler #define IQM_CF_ADJ_SEL__A 0x1860013 8843dd07f7SRalph Metzler #define IQM_CF_SCALE__A 0x1860014 8943dd07f7SRalph Metzler #define IQM_CF_SCALE_SH__A 0x1860015 9043dd07f7SRalph Metzler #define IQM_CF_SCALE_SH__PRE 0x0 9143dd07f7SRalph Metzler #define IQM_CF_POW_MEAS_LEN__A 0x1860017 9243dd07f7SRalph Metzler #define IQM_CF_DS_ENA__A 0x1860019 9343dd07f7SRalph Metzler #define IQM_CF_TAP_RE0__A 0x1860020 9443dd07f7SRalph Metzler #define IQM_CF_TAP_IM0__A 0x1860040 9543dd07f7SRalph Metzler #define IQM_CF_CLP_VAL__A 0x1860060 9643dd07f7SRalph Metzler #define IQM_CF_DATATH__A 0x1860061 9743dd07f7SRalph Metzler #define IQM_CF_PKDTH__A 0x1860062 9843dd07f7SRalph Metzler #define IQM_CF_WND_LEN__A 0x1860063 9943dd07f7SRalph Metzler #define IQM_CF_DET_LCT__A 0x1860064 10043dd07f7SRalph Metzler #define IQM_CF_BYPASSDET__A 0x1860067 10143dd07f7SRalph Metzler #define IQM_AF_COMM_EXEC__A 0x1870000 10243dd07f7SRalph Metzler #define IQM_AF_COMM_EXEC_ACTIVE 0x1 10343dd07f7SRalph Metzler #define IQM_AF_CLKNEG__A 0x1870012 10443dd07f7SRalph Metzler #define IQM_AF_CLKNEG_CLKNEGDATA__M 0x2 10543dd07f7SRalph Metzler #define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x0 10643dd07f7SRalph Metzler #define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2 10743dd07f7SRalph Metzler #define IQM_AF_START_LOCK__A 0x187001B 10843dd07f7SRalph Metzler #define IQM_AF_PHASE0__A 0x187001C 10943dd07f7SRalph Metzler #define IQM_AF_PHASE1__A 0x187001D 11043dd07f7SRalph Metzler #define IQM_AF_PHASE2__A 0x187001E 11143dd07f7SRalph Metzler #define IQM_AF_CLP_LEN__A 0x1870023 11243dd07f7SRalph Metzler #define IQM_AF_CLP_TH__A 0x1870024 11343dd07f7SRalph Metzler #define IQM_AF_SNS_LEN__A 0x1870026 11443dd07f7SRalph Metzler #define IQM_AF_AGC_IF__A 0x1870028 11543dd07f7SRalph Metzler #define IQM_AF_AGC_RF__A 0x1870029 11643dd07f7SRalph Metzler #define IQM_AF_PDREF__A 0x187002B 11743dd07f7SRalph Metzler #define IQM_AF_PDREF__M 0x1F 11843dd07f7SRalph Metzler #define IQM_AF_STDBY__A 0x187002C 11943dd07f7SRalph Metzler #define IQM_AF_STDBY_STDBY_ADC_STANDBY 0x2 12043dd07f7SRalph Metzler #define IQM_AF_STDBY_STDBY_AMP_STANDBY 0x4 12143dd07f7SRalph Metzler #define IQM_AF_STDBY_STDBY_PD_STANDBY 0x8 12243dd07f7SRalph Metzler #define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 0x10 12343dd07f7SRalph Metzler #define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY 0x20 12443dd07f7SRalph Metzler #define IQM_AF_AMUX__A 0x187002D 12543dd07f7SRalph Metzler #define IQM_AF_AMUX_SIGNAL2ADC 0x1 12643dd07f7SRalph Metzler #define IQM_AF_UPD_SEL__A 0x187002F 12743dd07f7SRalph Metzler #define IQM_AF_INC_LCT__A 0x1870034 12843dd07f7SRalph Metzler #define IQM_AF_INC_BYPASS__A 0x1870036 12943dd07f7SRalph Metzler #define OFDM_CP_COMM_EXEC__A 0x2800000 13043dd07f7SRalph Metzler #define OFDM_CP_COMM_EXEC_STOP 0x0 13143dd07f7SRalph Metzler #define OFDM_EC_SB_PRIOR__A 0x3410013 13243dd07f7SRalph Metzler #define OFDM_EC_SB_PRIOR_HI 0x0 13343dd07f7SRalph Metzler #define OFDM_EC_SB_PRIOR_LO 0x1 1348f3741e0SMauro Carvalho Chehab #define OFDM_EC_VD_ERR_BIT_CNT__A 0x3420017 1358f3741e0SMauro Carvalho Chehab #define OFDM_EC_VD_IN_BIT_CNT__A 0x3420018 13643dd07f7SRalph Metzler #define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054 13743dd07f7SRalph Metzler #define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3 13843dd07f7SRalph Metzler #define OFDM_EQ_TOP_TD_TPS_CONST_64QAM 0x2 13943dd07f7SRalph Metzler #define OFDM_EQ_TOP_TD_TPS_CODE_HP__A 0x3010056 14043dd07f7SRalph Metzler #define OFDM_EQ_TOP_TD_TPS_CODE_HP__M 0x7 14143dd07f7SRalph Metzler #define OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8 0x4 14243dd07f7SRalph Metzler #define OFDM_EQ_TOP_TD_SQR_ERR_I__A 0x301005E 14343dd07f7SRalph Metzler #define OFDM_EQ_TOP_TD_SQR_ERR_Q__A 0x301005F 14443dd07f7SRalph Metzler #define OFDM_EQ_TOP_TD_SQR_ERR_EXP__A 0x3010060 14543dd07f7SRalph Metzler #define OFDM_EQ_TOP_TD_REQ_SMB_CNT__A 0x3010061 14643dd07f7SRalph Metzler #define OFDM_EQ_TOP_TD_TPS_PWR_OFS__A 0x3010062 14743dd07f7SRalph Metzler #define OFDM_LC_COMM_EXEC__A 0x3800000 14843dd07f7SRalph Metzler #define OFDM_LC_COMM_EXEC_STOP 0x0 14943dd07f7SRalph Metzler #define OFDM_SC_COMM_EXEC__A 0x3C00000 15043dd07f7SRalph Metzler #define OFDM_SC_COMM_EXEC_STOP 0x0 15143dd07f7SRalph Metzler #define OFDM_SC_COMM_STATE__A 0x3C00001 15243dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_PARAM0__A 0x3C20040 15343dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_PARAM1__A 0x3C20041 15443dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_CMD_ADDR__A 0x3C20042 15543dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_CMD__A 0x3C20043 15643dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_CMD_NULL 0x0 15743dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_CMD_PROC_START 0x1 15843dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 15943dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4 16043dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_CMD_GET_OP_PARAM 0x5 16143dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_CMD_USER_IO 0x6 16243dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_CMD_SET_TIMER 0x7 16343dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8 16443dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 16543dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_LOCKTRACK_MIN 0x1 16643dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_OP_PARAM__A 0x3C20048 16743dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3 16843dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 16943dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 17043dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_OP_PARAM_GUARD_32 0x0 17143dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_OP_PARAM_GUARD_16 0x4 17243dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_OP_PARAM_GUARD_8 0x8 17343dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_OP_PARAM_GUARD_4 0xC 17443dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 17543dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 17643dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 17743dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_OP_PARAM_HIER_NO 0x0 17843dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_OP_PARAM_HIER_A1 0x40 17943dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_OP_PARAM_HIER_A2 0x80 18043dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 18143dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 18243dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 18343dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 18443dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 18543dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 18643dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 18743dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 18843dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_OP_AUTO_MODE__M 0x1 18943dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_OP_AUTO_GUARD__M 0x2 19043dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_OP_AUTO_CONST__M 0x4 19143dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_OP_AUTO_HIER__M 0x8 19243dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_OP_AUTO_RATE__M 0x10 19343dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_LOCK__A 0x3C2004B 19443dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_LOCK_DEMOD__M 0x1 19543dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_LOCK_FEC__M 0x2 19643dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_LOCK_MPEG__M 0x4 19743dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_LOCK_NODVBT__M 0x8 19843dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_BE_OPT_DELAY__A 0x3C2004D 19943dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x3C2004E 20043dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_ECHO_THRES__A 0x3C2004F 20143dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_ECHO_THRES_8K__B 0 20243dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_ECHO_THRES_8K__M 0xFF 20343dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_ECHO_THRES_2K__B 8 20443dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_ECHO_THRES_2K__M 0xFF00 20543dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_CONFIG__A 0x3C20050 20643dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M 0x800 20743dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_FR_THRES_8K__A 0x3C2007D 20843dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x3C200E0 20943dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x3C200E1 21043dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x3C200E3 21143dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x3C200E4 21243dd07f7SRalph Metzler #define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A 0x3C200F8 21343dd07f7SRalph Metzler #define QAM_COMM_EXEC__A 0x1400000 21443dd07f7SRalph Metzler #define QAM_COMM_EXEC_STOP 0x0 21543dd07f7SRalph Metzler #define QAM_COMM_EXEC_ACTIVE 0x1 21643dd07f7SRalph Metzler #define QAM_TOP_ANNEX_A 0x0 21743dd07f7SRalph Metzler #define QAM_TOP_ANNEX_C 0x2 21843dd07f7SRalph Metzler #define QAM_SL_ERR_POWER__A 0x1430017 21943dd07f7SRalph Metzler #define QAM_DQ_QUAL_FUN0__A 0x1440018 22043dd07f7SRalph Metzler #define QAM_DQ_QUAL_FUN1__A 0x1440019 22143dd07f7SRalph Metzler #define QAM_DQ_QUAL_FUN2__A 0x144001A 22243dd07f7SRalph Metzler #define QAM_DQ_QUAL_FUN3__A 0x144001B 22343dd07f7SRalph Metzler #define QAM_DQ_QUAL_FUN4__A 0x144001C 22443dd07f7SRalph Metzler #define QAM_DQ_QUAL_FUN5__A 0x144001D 22543dd07f7SRalph Metzler #define QAM_LC_MODE__A 0x1450010 22643dd07f7SRalph Metzler #define QAM_LC_QUAL_TAB0__A 0x1450018 22743dd07f7SRalph Metzler #define QAM_LC_QUAL_TAB1__A 0x1450019 22843dd07f7SRalph Metzler #define QAM_LC_QUAL_TAB2__A 0x145001A 22943dd07f7SRalph Metzler #define QAM_LC_QUAL_TAB3__A 0x145001B 23043dd07f7SRalph Metzler #define QAM_LC_QUAL_TAB4__A 0x145001C 23143dd07f7SRalph Metzler #define QAM_LC_QUAL_TAB5__A 0x145001D 23243dd07f7SRalph Metzler #define QAM_LC_QUAL_TAB6__A 0x145001E 23343dd07f7SRalph Metzler #define QAM_LC_QUAL_TAB8__A 0x145001F 23443dd07f7SRalph Metzler #define QAM_LC_QUAL_TAB9__A 0x1450020 23543dd07f7SRalph Metzler #define QAM_LC_QUAL_TAB10__A 0x1450021 23643dd07f7SRalph Metzler #define QAM_LC_QUAL_TAB12__A 0x1450022 23743dd07f7SRalph Metzler #define QAM_LC_QUAL_TAB15__A 0x1450023 23843dd07f7SRalph Metzler #define QAM_LC_QUAL_TAB16__A 0x1450024 23943dd07f7SRalph Metzler #define QAM_LC_QUAL_TAB20__A 0x1450025 24043dd07f7SRalph Metzler #define QAM_LC_QUAL_TAB25__A 0x1450026 24143dd07f7SRalph Metzler #define QAM_LC_LPF_FACTORP__A 0x1450028 24243dd07f7SRalph Metzler #define QAM_LC_LPF_FACTORI__A 0x1450029 24343dd07f7SRalph Metzler #define QAM_LC_RATE_LIMIT__A 0x145002A 24443dd07f7SRalph Metzler #define QAM_LC_SYMBOL_FREQ__A 0x145002B 24543dd07f7SRalph Metzler #define QAM_SY_TIMEOUT__A 0x1470011 24643dd07f7SRalph Metzler #define QAM_SY_TIMEOUT__PRE 0x3A98 24743dd07f7SRalph Metzler #define QAM_SY_SYNC_LWM__A 0x1470012 24843dd07f7SRalph Metzler #define QAM_SY_SYNC_AWM__A 0x1470013 24943dd07f7SRalph Metzler #define QAM_SY_SYNC_HWM__A 0x1470014 25043dd07f7SRalph Metzler #define QAM_SY_SP_INV__A 0x1470017 25143dd07f7SRalph Metzler #define QAM_SY_SP_INV_SPECTRUM_INV_DIS 0x0 25243dd07f7SRalph Metzler #define SCU_COMM_EXEC__A 0x800000 25343dd07f7SRalph Metzler #define SCU_COMM_EXEC_STOP 0x0 25443dd07f7SRalph Metzler #define SCU_COMM_EXEC_ACTIVE 0x1 25543dd07f7SRalph Metzler #define SCU_COMM_EXEC_HOLD 0x2 25643dd07f7SRalph Metzler #define SCU_RAM_DRIVER_DEBUG__A 0x831EBF 25743dd07f7SRalph Metzler #define SCU_RAM_QAM_FSM_STEP_PERIOD__A 0x831EC4 25843dd07f7SRalph Metzler #define SCU_RAM_GPIO__A 0x831EC7 25943dd07f7SRalph Metzler #define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0 26043dd07f7SRalph Metzler #define SCU_RAM_AGC_CLP_CTRL_MODE__A 0x831EC8 26143dd07f7SRalph Metzler #define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A 0x831ECB 26243dd07f7SRalph Metzler #define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A 0x831F05 26343dd07f7SRalph Metzler #define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A 0x831F15 26443dd07f7SRalph Metzler #define SCU_RAM_AGC_KI_CYCLEN__A 0x831F17 26543dd07f7SRalph Metzler #define SCU_RAM_AGC_SNS_CYCLEN__A 0x831F18 26643dd07f7SRalph Metzler #define SCU_RAM_AGC_RF_SNS_DEV_MAX__A 0x831F19 26743dd07f7SRalph Metzler #define SCU_RAM_AGC_RF_SNS_DEV_MIN__A 0x831F1A 26843dd07f7SRalph Metzler #define SCU_RAM_AGC_RF_MAX__A 0x831F1B 26943dd07f7SRalph Metzler #define SCU_RAM_AGC_CONFIG__A 0x831F24 27043dd07f7SRalph Metzler #define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M 0x1 27143dd07f7SRalph Metzler #define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M 0x2 27243dd07f7SRalph Metzler #define SCU_RAM_AGC_CONFIG_INV_IF_POL__M 0x100 27343dd07f7SRalph Metzler #define SCU_RAM_AGC_CONFIG_INV_RF_POL__M 0x200 27443dd07f7SRalph Metzler #define SCU_RAM_AGC_KI__A 0x831F25 27543dd07f7SRalph Metzler #define SCU_RAM_AGC_KI_RF__B 4 27643dd07f7SRalph Metzler #define SCU_RAM_AGC_KI_RF__M 0xF0 27743dd07f7SRalph Metzler #define SCU_RAM_AGC_KI_IF__B 8 27843dd07f7SRalph Metzler #define SCU_RAM_AGC_KI_IF__M 0xF00 27943dd07f7SRalph Metzler #define SCU_RAM_AGC_KI_RED__A 0x831F26 28043dd07f7SRalph Metzler #define SCU_RAM_AGC_KI_RED_RAGC_RED__B 2 28143dd07f7SRalph Metzler #define SCU_RAM_AGC_KI_RED_RAGC_RED__M 0xC 28243dd07f7SRalph Metzler #define SCU_RAM_AGC_KI_RED_IAGC_RED__B 4 28343dd07f7SRalph Metzler #define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x30 28443dd07f7SRalph Metzler #define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831F27 28543dd07f7SRalph Metzler #define SCU_RAM_AGC_KI_MINGAIN__A 0x831F28 28643dd07f7SRalph Metzler #define SCU_RAM_AGC_KI_MAXGAIN__A 0x831F29 28743dd07f7SRalph Metzler #define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A 0x831F2A 28843dd07f7SRalph Metzler #define SCU_RAM_AGC_KI_MIN__A 0x831F2B 28943dd07f7SRalph Metzler #define SCU_RAM_AGC_KI_MAX__A 0x831F2C 29043dd07f7SRalph Metzler #define SCU_RAM_AGC_CLP_SUM__A 0x831F2D 29143dd07f7SRalph Metzler #define SCU_RAM_AGC_CLP_SUM_MIN__A 0x831F2E 29243dd07f7SRalph Metzler #define SCU_RAM_AGC_CLP_SUM_MAX__A 0x831F2F 29343dd07f7SRalph Metzler #define SCU_RAM_AGC_CLP_CYCLEN__A 0x831F30 29443dd07f7SRalph Metzler #define SCU_RAM_AGC_CLP_CYCCNT__A 0x831F31 29543dd07f7SRalph Metzler #define SCU_RAM_AGC_CLP_DIR_TO__A 0x831F32 29643dd07f7SRalph Metzler #define SCU_RAM_AGC_CLP_DIR_WD__A 0x831F33 29743dd07f7SRalph Metzler #define SCU_RAM_AGC_CLP_DIR_STP__A 0x831F34 29843dd07f7SRalph Metzler #define SCU_RAM_AGC_SNS_SUM__A 0x831F35 29943dd07f7SRalph Metzler #define SCU_RAM_AGC_SNS_SUM_MIN__A 0x831F36 30043dd07f7SRalph Metzler #define SCU_RAM_AGC_SNS_SUM_MAX__A 0x831F37 30143dd07f7SRalph Metzler #define SCU_RAM_AGC_SNS_CYCCNT__A 0x831F38 30243dd07f7SRalph Metzler #define SCU_RAM_AGC_SNS_DIR_TO__A 0x831F39 30343dd07f7SRalph Metzler #define SCU_RAM_AGC_SNS_DIR_WD__A 0x831F3A 30443dd07f7SRalph Metzler #define SCU_RAM_AGC_SNS_DIR_STP__A 0x831F3B 30543dd07f7SRalph Metzler #define SCU_RAM_AGC_INGAIN_TGT__A 0x831F3D 30643dd07f7SRalph Metzler #define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831F3E 30743dd07f7SRalph Metzler #define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831F3F 30843dd07f7SRalph Metzler #define SCU_RAM_AGC_IF_IACCU_HI__A 0x831F40 30943dd07f7SRalph Metzler #define SCU_RAM_AGC_IF_IACCU_LO__A 0x831F41 31043dd07f7SRalph Metzler #define SCU_RAM_AGC_IF_IACCU_HI_TGT__A 0x831F42 31143dd07f7SRalph Metzler #define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A 0x831F43 31243dd07f7SRalph Metzler #define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44 31343dd07f7SRalph Metzler #define SCU_RAM_AGC_RF_IACCU_HI__A 0x831F45 31443dd07f7SRalph Metzler #define SCU_RAM_AGC_RF_IACCU_LO__A 0x831F46 31543dd07f7SRalph Metzler #define SCU_RAM_AGC_RF_IACCU_HI_CO__A 0x831F47 31643dd07f7SRalph Metzler #define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84 31743dd07f7SRalph Metzler #define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85 31843dd07f7SRalph Metzler #define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86 31943dd07f7SRalph Metzler #define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87 32043dd07f7SRalph Metzler #define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88 32143dd07f7SRalph Metzler #define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89 32243dd07f7SRalph Metzler #define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A 32343dd07f7SRalph Metzler #define SCU_RAM_QAM_FSM_RTH__A 0x831F8E 32443dd07f7SRalph Metzler #define SCU_RAM_QAM_FSM_FTH__A 0x831F8F 32543dd07f7SRalph Metzler #define SCU_RAM_QAM_FSM_PTH__A 0x831F90 32643dd07f7SRalph Metzler #define SCU_RAM_QAM_FSM_MTH__A 0x831F91 32743dd07f7SRalph Metzler #define SCU_RAM_QAM_FSM_CTH__A 0x831F92 32843dd07f7SRalph Metzler #define SCU_RAM_QAM_FSM_QTH__A 0x831F93 32943dd07f7SRalph Metzler #define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94 33043dd07f7SRalph Metzler #define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95 33143dd07f7SRalph Metzler #define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96 33243dd07f7SRalph Metzler #define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97 33343dd07f7SRalph Metzler #define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99 33443dd07f7SRalph Metzler #define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A 33543dd07f7SRalph Metzler #define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B 33643dd07f7SRalph Metzler #define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C 33743dd07f7SRalph Metzler #define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D 33843dd07f7SRalph Metzler #define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E 33943dd07f7SRalph Metzler #define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F 34043dd07f7SRalph Metzler #define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0 34143dd07f7SRalph Metzler #define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1 34243dd07f7SRalph Metzler #define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2 34343dd07f7SRalph Metzler #define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3 34443dd07f7SRalph Metzler #define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4 34543dd07f7SRalph Metzler #define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5 34643dd07f7SRalph Metzler #define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6 34743dd07f7SRalph Metzler #define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7 34843dd07f7SRalph Metzler #define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8 34943dd07f7SRalph Metzler #define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9 35043dd07f7SRalph Metzler #define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA 35143dd07f7SRalph Metzler #define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB 35243dd07f7SRalph Metzler #define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC 35343dd07f7SRalph Metzler #define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD 35443dd07f7SRalph Metzler #define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE 35543dd07f7SRalph Metzler #define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF 35643dd07f7SRalph Metzler #define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0 35743dd07f7SRalph Metzler #define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1 35843dd07f7SRalph Metzler #define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2 35943dd07f7SRalph Metzler #define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED 0x4000 36043dd07f7SRalph Metzler #define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED 0x8000 36143dd07f7SRalph Metzler #define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK 0xC000 36243dd07f7SRalph Metzler #define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831FEA 36343dd07f7SRalph Metzler #define SCU_RAM_DRIVER_VER_HI__A 0x831FEB 36443dd07f7SRalph Metzler #define SCU_RAM_DRIVER_VER_LO__A 0x831FEC 36543dd07f7SRalph Metzler #define SCU_RAM_PARAM_15__A 0x831FED 36643dd07f7SRalph Metzler #define SCU_RAM_PARAM_0__A 0x831FFC 36743dd07f7SRalph Metzler #define SCU_RAM_COMMAND__A 0x831FFD 36843dd07f7SRalph Metzler #define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1 36943dd07f7SRalph Metzler #define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x2 37043dd07f7SRalph Metzler #define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM 0x3 37143dd07f7SRalph Metzler #define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4 37243dd07f7SRalph Metzler #define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK 0x5 37343dd07f7SRalph Metzler #define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9 37443dd07f7SRalph Metzler #define SCU_RAM_COMMAND_STANDARD_QAM 0x200 37543dd07f7SRalph Metzler #define SCU_RAM_COMMAND_STANDARD_OFDM 0x400 37643dd07f7SRalph Metzler #define SIO_TOP_COMM_KEY__A 0x41000F 37743dd07f7SRalph Metzler #define SIO_TOP_COMM_KEY_KEY 0xFABA 37843dd07f7SRalph Metzler #define SIO_TOP_JTAGID_LO__A 0x410012 37943dd07f7SRalph Metzler #define SIO_HI_RA_RAM_RES__A 0x420031 38043dd07f7SRalph Metzler #define SIO_HI_RA_RAM_CMD__A 0x420032 38143dd07f7SRalph Metzler #define SIO_HI_RA_RAM_CMD_RESET 0x2 38243dd07f7SRalph Metzler #define SIO_HI_RA_RAM_CMD_CONFIG 0x3 38343dd07f7SRalph Metzler #define SIO_HI_RA_RAM_CMD_BRDCTRL 0x7 38443dd07f7SRalph Metzler #define SIO_HI_RA_RAM_PAR_1__A 0x420033 38543dd07f7SRalph Metzler #define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945 38643dd07f7SRalph Metzler #define SIO_HI_RA_RAM_PAR_2__A 0x420034 38743dd07f7SRalph Metzler #define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F 38843dd07f7SRalph Metzler #define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0 38943dd07f7SRalph Metzler #define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4 39043dd07f7SRalph Metzler #define SIO_HI_RA_RAM_PAR_3__A 0x420035 39143dd07f7SRalph Metzler #define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F 39243dd07f7SRalph Metzler #define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7 39343dd07f7SRalph Metzler #define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0 39443dd07f7SRalph Metzler #define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8 39543dd07f7SRalph Metzler #define SIO_HI_RA_RAM_PAR_4__A 0x420036 39643dd07f7SRalph Metzler #define SIO_HI_RA_RAM_PAR_5__A 0x420037 39743dd07f7SRalph Metzler #define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1 39843dd07f7SRalph Metzler #define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8 39943dd07f7SRalph Metzler #define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8 40043dd07f7SRalph Metzler #define SIO_HI_RA_RAM_PAR_6__A 0x420038 40143dd07f7SRalph Metzler #define SIO_CC_PLL_LOCK__A 0x450012 40243dd07f7SRalph Metzler #define SIO_CC_PWD_MODE__A 0x450015 40343dd07f7SRalph Metzler #define SIO_CC_PWD_MODE_LEVEL_NONE 0x0 40443dd07f7SRalph Metzler #define SIO_CC_PWD_MODE_LEVEL_OFDM 0x1 40543dd07f7SRalph Metzler #define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x2 40643dd07f7SRalph Metzler #define SIO_CC_PWD_MODE_LEVEL_PLL 0x3 40743dd07f7SRalph Metzler #define SIO_CC_PWD_MODE_LEVEL_OSC 0x4 40843dd07f7SRalph Metzler #define SIO_CC_SOFT_RST__A 0x450016 40943dd07f7SRalph Metzler #define SIO_CC_SOFT_RST_OFDM__M 0x1 41043dd07f7SRalph Metzler #define SIO_CC_SOFT_RST_SYS__M 0x2 41143dd07f7SRalph Metzler #define SIO_CC_SOFT_RST_OSC__M 0x4 41243dd07f7SRalph Metzler #define SIO_CC_UPDATE__A 0x450017 41343dd07f7SRalph Metzler #define SIO_CC_UPDATE_KEY 0xFABA 41443dd07f7SRalph Metzler #define SIO_OFDM_SH_OFDM_RING_ENABLE__A 0x470010 41543dd07f7SRalph Metzler #define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF 0x0 41643dd07f7SRalph Metzler #define SIO_OFDM_SH_OFDM_RING_ENABLE_ON 0x1 41743dd07f7SRalph Metzler #define SIO_OFDM_SH_OFDM_RING_STATUS__A 0x470012 41843dd07f7SRalph Metzler #define SIO_OFDM_SH_OFDM_RING_STATUS_DOWN 0x0 41943dd07f7SRalph Metzler #define SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED 0x1 42043dd07f7SRalph Metzler #define SIO_BL_COMM_EXEC__A 0x480000 42143dd07f7SRalph Metzler #define SIO_BL_COMM_EXEC_ACTIVE 0x1 42243dd07f7SRalph Metzler #define SIO_BL_STATUS__A 0x480010 42343dd07f7SRalph Metzler #define SIO_BL_MODE__A 0x480011 42443dd07f7SRalph Metzler #define SIO_BL_MODE_DIRECT 0x0 42543dd07f7SRalph Metzler #define SIO_BL_MODE_CHAIN 0x1 42643dd07f7SRalph Metzler #define SIO_BL_ENABLE__A 0x480012 42743dd07f7SRalph Metzler #define SIO_BL_ENABLE_ON 0x1 42843dd07f7SRalph Metzler #define SIO_BL_TGT_HDR__A 0x480014 42943dd07f7SRalph Metzler #define SIO_BL_TGT_ADDR__A 0x480015 43043dd07f7SRalph Metzler #define SIO_BL_SRC_ADDR__A 0x480016 43143dd07f7SRalph Metzler #define SIO_BL_SRC_LEN__A 0x480017 43243dd07f7SRalph Metzler #define SIO_BL_CHAIN_ADDR__A 0x480018 43343dd07f7SRalph Metzler #define SIO_BL_CHAIN_LEN__A 0x480019 43443dd07f7SRalph Metzler #define SIO_PDR_MON_CFG__A 0x7F0010 43543dd07f7SRalph Metzler #define SIO_PDR_UIO_IN_HI__A 0x7F0015 43643dd07f7SRalph Metzler #define SIO_PDR_UIO_OUT_LO__A 0x7F0016 43743dd07f7SRalph Metzler #define SIO_PDR_OHW_CFG__A 0x7F001F 43843dd07f7SRalph Metzler #define SIO_PDR_OHW_CFG_FREF_SEL__M 0x3 43914053443SAntti Palosaari #define SIO_PDR_GPIO_CFG__A 0x7F0021 44043dd07f7SRalph Metzler #define SIO_PDR_MSTRT_CFG__A 0x7F0025 44143dd07f7SRalph Metzler #define SIO_PDR_MERR_CFG__A 0x7F0026 44243dd07f7SRalph Metzler #define SIO_PDR_MCLK_CFG__A 0x7F0028 44343dd07f7SRalph Metzler #define SIO_PDR_MCLK_CFG_DRIVE__B 3 44443dd07f7SRalph Metzler #define SIO_PDR_MVAL_CFG__A 0x7F0029 44543dd07f7SRalph Metzler #define SIO_PDR_MD0_CFG__A 0x7F002A 44643dd07f7SRalph Metzler #define SIO_PDR_MD0_CFG_DRIVE__B 3 44743dd07f7SRalph Metzler #define SIO_PDR_MD1_CFG__A 0x7F002B 44843dd07f7SRalph Metzler #define SIO_PDR_MD2_CFG__A 0x7F002C 44943dd07f7SRalph Metzler #define SIO_PDR_MD3_CFG__A 0x7F002D 45043dd07f7SRalph Metzler #define SIO_PDR_MD4_CFG__A 0x7F002F 45143dd07f7SRalph Metzler #define SIO_PDR_MD5_CFG__A 0x7F0030 45243dd07f7SRalph Metzler #define SIO_PDR_MD6_CFG__A 0x7F0031 45343dd07f7SRalph Metzler #define SIO_PDR_MD7_CFG__A 0x7F0032 45414053443SAntti Palosaari #define SIO_PDR_SMA_RX_CFG__A 0x7F0037 45543dd07f7SRalph Metzler #define SIO_PDR_SMA_TX_CFG__A 0x7F0038 456