1 /* 2 Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. 3 All rights reserved. 4 5 Redistribution and use in source and binary forms, with or without 6 modification, are permitted provided that the following conditions are met: 7 8 * Redistributions of source code must retain the above copyright notice, 9 this list of conditions and the following disclaimer. 10 * Redistributions in binary form must reproduce the above copyright notice, 11 this list of conditions and the following disclaimer in the documentation 12 and/or other materials provided with the distribution. 13 * Neither the name of Trident Microsystems nor Hauppauge Computer Works 14 nor the names of its contributors may be used to endorse or promote 15 products derived from this software without specific prior written 16 permission. 17 18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /** 32 * \file $Id: drxj.h,v 1.132 2009/12/22 12:13:48 danielg Exp $ 33 * 34 * \brief DRXJ specific header file 35 * 36 * \author Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen 37 */ 38 39 #ifndef __DRXJ_H__ 40 #define __DRXJ_H__ 41 /*------------------------------------------------------------------------- 42 INCLUDES 43 -------------------------------------------------------------------------*/ 44 45 #include "drx_driver.h" 46 #include "drx_dap_fasi.h" 47 48 #ifdef __cplusplus 49 extern "C" { 50 #endif 51 52 /* Check DRX-J specific dap condition */ 53 /* Multi master mode and short addr format only will not work. 54 RMW, CRC reset, broadcast and switching back to single master mode 55 cannot be done with short addr only in multi master mode. */ 56 #if ((DRXDAP_SINGLE_MASTER == 0) && (DRXDAPFASI_LONG_ADDR_ALLOWED == 0)) 57 #error "Multi master mode and short addressing only is an illegal combination" 58 *; /* Generate a fatal compiler error to make sure it stops here, 59 this is necesarry because not all compilers stop after a #error. */ 60 #endif 61 62 /*------------------------------------------------------------------------- 63 TYPEDEFS 64 -------------------------------------------------------------------------*/ 65 /*============================================================================*/ 66 /*============================================================================*/ 67 /*== code support ============================================================*/ 68 /*============================================================================*/ 69 /*============================================================================*/ 70 71 /*============================================================================*/ 72 /*============================================================================*/ 73 /*== SCU cmd if =============================================================*/ 74 /*============================================================================*/ 75 /*============================================================================*/ 76 77 typedef struct { 78 u16 command; 79 /**< Command number */ 80 u16 parameterLen; 81 /**< Data length in byte */ 82 u16 resultLen; 83 /**< result length in byte */ 84 u16 *parameter; 85 /**< General purpous param */ 86 u16 *result; 87 /**< General purpous param */ 88 } DRXJSCUCmd_t, *pDRXJSCUCmd_t; 89 90 /*============================================================================*/ 91 /*============================================================================*/ 92 /*== CTRL CFG related data structures ========================================*/ 93 /*============================================================================*/ 94 /*============================================================================*/ 95 96 /* extra intermediate lock state for VSB,QAM,NTSC */ 97 #define DRXJ_DEMOD_LOCK (DRX_LOCK_STATE_1) 98 99 /* OOB lock states */ 100 #define DRXJ_OOB_AGC_LOCK (DRX_LOCK_STATE_1) /* analog gain control lock */ 101 #define DRXJ_OOB_SYNC_LOCK (DRX_LOCK_STATE_2) /* digital gain control lock */ 102 103 /* Intermediate powermodes for DRXJ */ 104 #define DRXJ_POWER_DOWN_MAIN_PATH DRX_POWER_MODE_8 105 #define DRXJ_POWER_DOWN_CORE DRX_POWER_MODE_9 106 #define DRXJ_POWER_DOWN_PLL DRX_POWER_MODE_10 107 108 /* supstition for GPIO FNC mux */ 109 #define APP_O (0x0000) 110 111 /*#define DRX_CTRL_BASE (0x0000)*/ 112 113 #define DRXJ_CTRL_CFG_BASE (0x1000) 114 typedef enum { 115 DRXJ_CFG_AGC_RF = DRXJ_CTRL_CFG_BASE, 116 DRXJ_CFG_AGC_IF, 117 DRXJ_CFG_AGC_INTERNAL, 118 DRXJ_CFG_PRE_SAW, 119 DRXJ_CFG_AFE_GAIN, 120 DRXJ_CFG_SYMBOL_CLK_OFFSET, 121 DRXJ_CFG_ACCUM_CR_RS_CW_ERR, 122 DRXJ_CFG_FEC_MERS_SEQ_COUNT, 123 DRXJ_CFG_OOB_MISC, 124 DRXJ_CFG_SMART_ANT, 125 DRXJ_CFG_OOB_PRE_SAW, 126 DRXJ_CFG_VSB_MISC, 127 DRXJ_CFG_RESET_PACKET_ERR, 128 129 /* ATV (FM) */ 130 DRXJ_CFG_ATV_OUTPUT, /* also for FM (SIF control) but not likely */ 131 DRXJ_CFG_ATV_MISC, 132 DRXJ_CFG_ATV_EQU_COEF, 133 DRXJ_CFG_ATV_AGC_STATUS, /* also for FM ( IF,RF, audioAGC ) */ 134 135 DRXJ_CFG_MPEG_OUTPUT_MISC, 136 DRXJ_CFG_HW_CFG, 137 DRXJ_CFG_OOB_LO_POW, 138 139 DRXJ_CFG_MAX /* dummy, never to be used */ 140 } DRXJCfgType_t, *pDRXJCfgType_t; 141 142 /** 143 * /struct DRXJCfgSmartAntIO_t 144 * smart antenna i/o. 145 */ 146 typedef enum DRXJCfgSmartAntIO_t { 147 DRXJ_SMT_ANT_OUTPUT = 0, 148 DRXJ_SMT_ANT_INPUT 149 } DRXJCfgSmartAntIO_t, *pDRXJCfgSmartAntIO_t; 150 151 /** 152 * /struct DRXJCfgSmartAnt_t 153 * Set smart antenna. 154 */ 155 typedef struct { 156 DRXJCfgSmartAntIO_t io; 157 u16 ctrlData; 158 } DRXJCfgSmartAnt_t, *pDRXJCfgSmartAnt_t; 159 160 /** 161 * /struct DRXJAGCSTATUS_t 162 * AGC status information from the DRXJ-IQM-AF. 163 */ 164 typedef struct { 165 u16 IFAGC; 166 u16 RFAGC; 167 u16 DigitalAGC; 168 } DRXJAgcStatus_t, *pDRXJAgcStatus_t; 169 170 /* DRXJ_CFG_AGC_RF, DRXJ_CFG_AGC_IF */ 171 172 /** 173 * /struct DRXJAgcCtrlMode_t 174 * Available AGCs modes in the DRXJ. 175 */ 176 typedef enum { 177 DRX_AGC_CTRL_AUTO = 0, 178 DRX_AGC_CTRL_USER, 179 DRX_AGC_CTRL_OFF 180 } DRXJAgcCtrlMode_t, *pDRXJAgcCtrlMode_t; 181 182 /** 183 * /struct DRXJCfgAgc_t 184 * Generic interface for all AGCs present on the DRXJ. 185 */ 186 typedef struct { 187 enum drx_standard standard; /* standard for which these settings apply */ 188 DRXJAgcCtrlMode_t ctrlMode; /* off, user, auto */ 189 u16 outputLevel; /* range dependent on AGC */ 190 u16 minOutputLevel; /* range dependent on AGC */ 191 u16 maxOutputLevel; /* range dependent on AGC */ 192 u16 speed; /* range dependent on AGC */ 193 u16 top; /* rf-agc take over point */ 194 u16 cutOffCurrent; /* rf-agc is accelerated if output current 195 is below cut-off current */ 196 } DRXJCfgAgc_t, *pDRXJCfgAgc_t; 197 198 /* DRXJ_CFG_PRE_SAW */ 199 200 /** 201 * /struct DRXJCfgPreSaw_t 202 * Interface to configure pre SAW sense. 203 */ 204 typedef struct { 205 enum drx_standard standard; /* standard to which these settings apply */ 206 u16 reference; /* pre SAW reference value, range 0 .. 31 */ 207 bool usePreSaw; /* true algorithms must use pre SAW sense */ 208 } DRXJCfgPreSaw_t, *pDRXJCfgPreSaw_t; 209 210 /* DRXJ_CFG_AFE_GAIN */ 211 212 /** 213 * /struct DRXJCfgAfeGain_t 214 * Interface to configure gain of AFE (LNA + PGA). 215 */ 216 typedef struct { 217 enum drx_standard standard; /* standard to which these settings apply */ 218 u16 gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */ 219 } DRXJCfgAfeGain_t, *pDRXJCfgAfeGain_t; 220 221 /** 222 * /struct DRXJRSErrors_t 223 * Available failure information in DRXJ_FEC_RS. 224 * 225 * Container for errors that are received in the most recently finished measurment period 226 * 227 */ 228 typedef struct { 229 u16 nrBitErrors; 230 /**< no of pre RS bit errors */ 231 u16 nrSymbolErrors; 232 /**< no of pre RS symbol errors */ 233 u16 nrPacketErrors; 234 /**< no of pre RS packet errors */ 235 u16 nrFailures; 236 /**< no of post RS failures to decode */ 237 u16 nrSncParFailCount; 238 /**< no of post RS bit erros */ 239 } DRXJRSErrors_t, *pDRXJRSErrors_t; 240 241 /** 242 * /struct DRXJCfgVSBMisc_t 243 * symbol error rate 244 */ 245 typedef struct { 246 u32 symbError; 247 /**< symbol error rate sps */ 248 } DRXJCfgVSBMisc_t, *pDRXJCfgVSBMisc_t; 249 250 /** 251 * /enum DRXJMpegOutputClockRate_t 252 * Mpeg output clock rate. 253 * 254 */ 255 typedef enum { 256 DRXJ_MPEG_START_WIDTH_1CLKCYC, 257 DRXJ_MPEG_START_WIDTH_8CLKCYC 258 } DRXJMpegStartWidth_t, *pDRXJMpegStartWidth_t; 259 260 /** 261 * /enum DRXJMpegOutputClockRate_t 262 * Mpeg output clock rate. 263 * 264 */ 265 typedef enum { 266 DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO, 267 DRXJ_MPEGOUTPUT_CLOCK_RATE_75973K, 268 DRXJ_MPEGOUTPUT_CLOCK_RATE_50625K, 269 DRXJ_MPEGOUTPUT_CLOCK_RATE_37968K, 270 DRXJ_MPEGOUTPUT_CLOCK_RATE_30375K, 271 DRXJ_MPEGOUTPUT_CLOCK_RATE_25313K, 272 DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K 273 } DRXJMpegOutputClockRate_t, *pDRXJMpegOutputClockRate_t; 274 275 /** 276 * /struct DRXJCfgMisc_t 277 * Change TEI bit of MPEG output 278 * reverse MPEG output bit order 279 * set MPEG output clock rate 280 */ 281 typedef struct { 282 bool disableTEIHandling; /**< if true pass (not change) TEI bit */ 283 bool bitReverseMpegOutout; /**< if true, parallel: msb on MD0; serial: lsb out first */ 284 DRXJMpegOutputClockRate_t mpegOutputClockRate; 285 /**< set MPEG output clock rate that overwirtes the derived one from symbol rate */ 286 DRXJMpegStartWidth_t mpegStartWidth; /**< set MPEG output start width */ 287 } DRXJCfgMpegOutputMisc_t, *pDRXJCfgMpegOutputMisc_t; 288 289 /** 290 * /enum DRXJXtalFreq_t 291 * Supported external crystal reference frequency. 292 */ 293 typedef enum { 294 DRXJ_XTAL_FREQ_RSVD, 295 DRXJ_XTAL_FREQ_27MHZ, 296 DRXJ_XTAL_FREQ_20P25MHZ, 297 DRXJ_XTAL_FREQ_4MHZ 298 } DRXJXtalFreq_t, *pDRXJXtalFreq_t; 299 300 /** 301 * /enum DRXJXtalFreq_t 302 * Supported external crystal reference frequency. 303 */ 304 typedef enum { 305 DRXJ_I2C_SPEED_400KBPS, 306 DRXJ_I2C_SPEED_100KBPS 307 } DRXJI2CSpeed_t, *pDRXJI2CSpeed_t; 308 309 /** 310 * /struct DRXJCfgHwCfg_t 311 * Get hw configuration, such as crystal reference frequency, I2C speed, etc... 312 */ 313 typedef struct { 314 DRXJXtalFreq_t xtalFreq; 315 /**< crystal reference frequency */ 316 DRXJI2CSpeed_t i2cSpeed; 317 /**< 100 or 400 kbps */ 318 } DRXJCfgHwCfg_t, *pDRXJCfgHwCfg_t; 319 320 /* 321 * DRXJ_CFG_ATV_MISC 322 */ 323 typedef struct { 324 s16 peakFilter; /* -8 .. 15 */ 325 u16 noiseFilter; /* 0 .. 15 */ 326 } DRXJCfgAtvMisc_t, *pDRXJCfgAtvMisc_t; 327 328 /* 329 * DRXJCfgOOBMisc_t 330 */ 331 #define DRXJ_OOB_STATE_RESET 0x0 332 #define DRXJ_OOB_STATE_AGN_HUNT 0x1 333 #define DRXJ_OOB_STATE_DGN_HUNT 0x2 334 #define DRXJ_OOB_STATE_AGC_HUNT 0x3 335 #define DRXJ_OOB_STATE_FRQ_HUNT 0x4 336 #define DRXJ_OOB_STATE_PHA_HUNT 0x8 337 #define DRXJ_OOB_STATE_TIM_HUNT 0x10 338 #define DRXJ_OOB_STATE_EQU_HUNT 0x20 339 #define DRXJ_OOB_STATE_EQT_HUNT 0x30 340 #define DRXJ_OOB_STATE_SYNC 0x40 341 342 typedef struct { 343 DRXJAgcStatus_t agc; 344 bool eqLock; 345 bool symTimingLock; 346 bool phaseLock; 347 bool freqLock; 348 bool digGainLock; 349 bool anaGainLock; 350 u8 state; 351 } DRXJCfgOOBMisc_t, *pDRXJCfgOOBMisc_t; 352 353 /* 354 * Index of in array of coef 355 */ 356 typedef enum { 357 DRXJ_OOB_LO_POW_MINUS0DB = 0, 358 DRXJ_OOB_LO_POW_MINUS5DB, 359 DRXJ_OOB_LO_POW_MINUS10DB, 360 DRXJ_OOB_LO_POW_MINUS15DB, 361 DRXJ_OOB_LO_POW_MAX 362 } DRXJCfgOobLoPower_t, *pDRXJCfgOobLoPower_t; 363 364 /* 365 * DRXJ_CFG_ATV_EQU_COEF 366 */ 367 typedef struct { 368 s16 coef0; /* -256 .. 255 */ 369 s16 coef1; /* -256 .. 255 */ 370 s16 coef2; /* -256 .. 255 */ 371 s16 coef3; /* -256 .. 255 */ 372 } DRXJCfgAtvEquCoef_t, *pDRXJCfgAtvEquCoef_t; 373 374 /* 375 * Index of in array of coef 376 */ 377 typedef enum { 378 DRXJ_COEF_IDX_MN = 0, 379 DRXJ_COEF_IDX_FM, 380 DRXJ_COEF_IDX_L, 381 DRXJ_COEF_IDX_LP, 382 DRXJ_COEF_IDX_BG, 383 DRXJ_COEF_IDX_DK, 384 DRXJ_COEF_IDX_I, 385 DRXJ_COEF_IDX_MAX 386 } DRXJCoefArrayIndex_t, *pDRXJCoefArrayIndex_t; 387 388 /* 389 * DRXJ_CFG_ATV_OUTPUT 390 */ 391 392 /** 393 * /enum DRXJAttenuation_t 394 * Attenuation setting for SIF AGC. 395 * 396 */ 397 typedef enum { 398 DRXJ_SIF_ATTENUATION_0DB, 399 DRXJ_SIF_ATTENUATION_3DB, 400 DRXJ_SIF_ATTENUATION_6DB, 401 DRXJ_SIF_ATTENUATION_9DB 402 } DRXJSIFAttenuation_t, *pDRXJSIFAttenuation_t; 403 404 /** 405 * /struct DRXJCfgAtvOutput_t 406 * SIF attenuation setting. 407 * 408 */ 409 typedef struct { 410 bool enableCVBSOutput; /* true= enabled */ 411 bool enableSIFOutput; /* true= enabled */ 412 DRXJSIFAttenuation_t sifAttenuation; 413 } DRXJCfgAtvOutput_t, *pDRXJCfgAtvOutput_t; 414 415 /* 416 DRXJ_CFG_ATV_AGC_STATUS (get only) 417 */ 418 /* TODO : AFE interface not yet finished, subject to change */ 419 typedef struct { 420 u16 rfAgcGain; /* 0 .. 877 uA */ 421 u16 ifAgcGain; /* 0 .. 877 uA */ 422 s16 videoAgcGain; /* -75 .. 1972 in 0.1 dB steps */ 423 s16 audioAgcGain; /* -4 .. 1020 in 0.1 dB steps */ 424 u16 rfAgcLoopGain; /* 0 .. 7 */ 425 u16 ifAgcLoopGain; /* 0 .. 7 */ 426 u16 videoAgcLoopGain; /* 0 .. 7 */ 427 } DRXJCfgAtvAgcStatus_t, *pDRXJCfgAtvAgcStatus_t; 428 429 /*============================================================================*/ 430 /*============================================================================*/ 431 /*== CTRL related data structures ============================================*/ 432 /*============================================================================*/ 433 /*============================================================================*/ 434 435 /* NONE */ 436 437 /*============================================================================*/ 438 /*============================================================================*/ 439 440 /*========================================*/ 441 /** 442 * /struct DRXJData_t 443 * DRXJ specific attributes. 444 * 445 * Global data container for DRXJ specific data. 446 * 447 */ 448 typedef struct { 449 /* device capabilties (determined during DRX_Open()) */ 450 bool hasLNA; /**< true if LNA (aka PGA) present */ 451 bool hasOOB; /**< true if OOB supported */ 452 bool hasNTSC; /**< true if NTSC supported */ 453 bool hasBTSC; /**< true if BTSC supported */ 454 bool hasSMATX; /**< true if mat_tx is available */ 455 bool hasSMARX; /**< true if mat_rx is available */ 456 bool hasGPIO; /**< true if GPIO is available */ 457 bool hasIRQN; /**< true if IRQN is available */ 458 /* A1/A2/A... */ 459 u8 mfx; /**< metal fix */ 460 461 /* tuner settings */ 462 bool mirrorFreqSpectOOB;/**< tuner inversion (true = tuner mirrors the signal */ 463 464 /* standard/channel settings */ 465 enum drx_standard standard; /**< current standard information */ 466 enum drx_modulation constellation; 467 /**< current constellation */ 468 s32 frequency; /**< center signal frequency in KHz */ 469 enum drx_bandwidth currBandwidth; 470 /**< current channel bandwidth */ 471 enum drx_mirror mirror; /**< current channel mirror */ 472 473 /* signal quality information */ 474 u32 fecBitsDesired; /**< BER accounting period */ 475 u16 fecVdPlen; /**< no of trellis symbols: VD SER measurement period */ 476 u16 qamVdPrescale; /**< Viterbi Measurement Prescale */ 477 u16 qamVdPeriod; /**< Viterbi Measurement period */ 478 u16 fecRsPlen; /**< defines RS BER measurement period */ 479 u16 fecRsPrescale; /**< ReedSolomon Measurement Prescale */ 480 u16 fecRsPeriod; /**< ReedSolomon Measurement period */ 481 bool resetPktErrAcc; /**< Set a flag to reset accumulated packet error */ 482 u16 pktErrAccStart; /**< Set a flag to reset accumulated packet error */ 483 484 /* HI configuration */ 485 u16 HICfgTimingDiv; /**< HI Configure() parameter 2 */ 486 u16 HICfgBridgeDelay; /**< HI Configure() parameter 3 */ 487 u16 HICfgWakeUpKey; /**< HI Configure() parameter 4 */ 488 u16 HICfgCtrl; /**< HI Configure() parameter 5 */ 489 u16 HICfgTransmit; /**< HI Configure() parameter 6 */ 490 491 /* UIO configuartion */ 492 DRXUIOMode_t uioSmaRxMode;/**< current mode of SmaRx pin */ 493 DRXUIOMode_t uioSmaTxMode;/**< current mode of SmaTx pin */ 494 DRXUIOMode_t uioGPIOMode; /**< current mode of ASEL pin */ 495 DRXUIOMode_t uioIRQNMode; /**< current mode of IRQN pin */ 496 497 /* IQM fs frequecy shift and inversion */ 498 u32 iqmFsRateOfs; /**< frequency shifter setting after setchannel */ 499 bool posImage; /**< Ture: positive image */ 500 /* IQM RC frequecy shift */ 501 u32 iqmRcRateOfs; /**< frequency shifter setting after setchannel */ 502 503 /* ATV configuartion */ 504 u32 atvCfgChangedFlags; /**< flag: flags cfg changes */ 505 s16 atvTopEqu0[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU0__A */ 506 s16 atvTopEqu1[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU1__A */ 507 s16 atvTopEqu2[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU2__A */ 508 s16 atvTopEqu3[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU3__A */ 509 bool phaseCorrectionBypass;/**< flag: true=bypass */ 510 s16 atvTopVidPeak; /**< shadow of ATV_TOP_VID_PEAK__A */ 511 u16 atvTopNoiseTh; /**< shadow of ATV_TOP_NOISE_TH__A */ 512 bool enableCVBSOutput; /**< flag CVBS ouput enable */ 513 bool enableSIFOutput; /**< flag SIF ouput enable */ 514 DRXJSIFAttenuation_t sifAttenuation; 515 /**< current SIF att setting */ 516 /* Agc configuration for QAM and VSB */ 517 DRXJCfgAgc_t qamRfAgcCfg; /**< qam RF AGC config */ 518 DRXJCfgAgc_t qamIfAgcCfg; /**< qam IF AGC config */ 519 DRXJCfgAgc_t vsbRfAgcCfg; /**< vsb RF AGC config */ 520 DRXJCfgAgc_t vsbIfAgcCfg; /**< vsb IF AGC config */ 521 522 /* PGA gain configuration for QAM and VSB */ 523 u16 qamPgaCfg; /**< qam PGA config */ 524 u16 vsbPgaCfg; /**< vsb PGA config */ 525 526 /* Pre SAW configuration for QAM and VSB */ 527 DRXJCfgPreSaw_t qamPreSawCfg; 528 /**< qam pre SAW config */ 529 DRXJCfgPreSaw_t vsbPreSawCfg; 530 /**< qam pre SAW config */ 531 532 /* Version information */ 533 char vText[2][12]; /**< allocated text versions */ 534 DRXVersion_t vVersion[2]; /**< allocated versions structs */ 535 DRXVersionList_t vListElements[2]; 536 /**< allocated version list */ 537 538 /* smart antenna configuration */ 539 bool smartAntInverted; 540 541 /* Tracking filter setting for OOB */ 542 u16 oobTrkFilterCfg[8]; 543 bool oobPowerOn; 544 545 /* MPEG static bitrate setting */ 546 u32 mpegTsStaticBitrate; /**< bitrate static MPEG output */ 547 bool disableTEIhandling; /**< MPEG TS TEI handling */ 548 bool bitReverseMpegOutout;/**< MPEG output bit order */ 549 DRXJMpegOutputClockRate_t mpegOutputClockRate; 550 /**< MPEG output clock rate */ 551 DRXJMpegStartWidth_t mpegStartWidth; 552 /**< MPEG Start width */ 553 554 /* Pre SAW & Agc configuration for ATV */ 555 DRXJCfgPreSaw_t atvPreSawCfg; 556 /**< atv pre SAW config */ 557 DRXJCfgAgc_t atvRfAgcCfg; /**< atv RF AGC config */ 558 DRXJCfgAgc_t atvIfAgcCfg; /**< atv IF AGC config */ 559 u16 atvPgaCfg; /**< atv pga config */ 560 561 u32 currSymbolRate; 562 563 /* pin-safe mode */ 564 bool pdrSafeMode; /**< PDR safe mode activated */ 565 u16 pdrSafeRestoreValGpio; 566 u16 pdrSafeRestoreValVSync; 567 u16 pdrSafeRestoreValSmaRx; 568 u16 pdrSafeRestoreValSmaTx; 569 570 /* OOB pre-saw value */ 571 u16 oobPreSaw; 572 DRXJCfgOobLoPower_t oobLoPow; 573 574 DRXAudData_t audData; 575 /**< audio storage */ 576 577 } DRXJData_t, *pDRXJData_t; 578 579 /*------------------------------------------------------------------------- 580 Access MACROS 581 -------------------------------------------------------------------------*/ 582 /** 583 * \brief Compilable references to attributes 584 * \param d pointer to demod instance 585 * 586 * Used as main reference to an attribute field. 587 * Can be used by both macro implementation and function implementation. 588 * These macros are defined to avoid duplication of code in macro and function 589 * definitions that handle access of demod common or extended attributes. 590 * 591 */ 592 593 #define DRXJ_ATTR_BTSC_DETECT(d) \ 594 (((pDRXJData_t)(d)->myExtAttr)->audData.btscDetect) 595 596 /** 597 * \brief Actual access macros 598 * \param d pointer to demod instance 599 * \param x value to set or to get 600 * 601 * SET macros must be used to set the value of an attribute. 602 * GET macros must be used to retrieve the value of an attribute. 603 * Depending on the value of DRX_USE_ACCESS_FUNCTIONS the macro's will be 604 * substituted by "direct-access-inline-code" or a function call. 605 * 606 */ 607 #define DRXJ_GET_BTSC_DETECT(d, x) \ 608 do { \ 609 (x) = DRXJ_ATTR_BTSC_DETECT((d); \ 610 } while (0) 611 612 #define DRXJ_SET_BTSC_DETECT(d, x) \ 613 do { \ 614 DRXJ_ATTR_BTSC_DETECT(d) = (x); \ 615 } while (0) 616 617 /*------------------------------------------------------------------------- 618 DEFINES 619 -------------------------------------------------------------------------*/ 620 621 /** 622 * \def DRXJ_NTSC_CARRIER_FREQ_OFFSET 623 * \brief Offset from picture carrier to centre frequency in kHz, in RF domain 624 * 625 * For NTSC standard. 626 * NTSC channels are listed by their picture carrier frequency (Fpc). 627 * The function DRX_CTRL_SET_CHANNEL requires the centre frequency as input. 628 * In case the tuner module is not used the DRX-J requires that the tuner is 629 * tuned to the centre frequency of the channel: 630 * 631 * Fcentre = Fpc + DRXJ_NTSC_CARRIER_FREQ_OFFSET 632 * 633 */ 634 #define DRXJ_NTSC_CARRIER_FREQ_OFFSET ((s32)(1750)) 635 636 /** 637 * \def DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET 638 * \brief Offset from picture carrier to centre frequency in kHz, in RF domain 639 * 640 * For PAL/SECAM - BG standard. This define is needed in case the tuner module 641 * is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). 642 * The DRX-J requires that the tuner is tuned to: 643 * Fpc + DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET 644 * 645 * In case the tuner module is used the drxdriver takes care of this. 646 * In case the tuner module is NOT used the application programmer must take 647 * care of this. 648 * 649 */ 650 #define DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET ((s32)(2375)) 651 652 /** 653 * \def DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET 654 * \brief Offset from picture carrier to centre frequency in kHz, in RF domain 655 * 656 * For PAL/SECAM - DK, I, L standards. This define is needed in case the tuner module 657 * is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). 658 * The DRX-J requires that the tuner is tuned to: 659 * Fpc + DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET 660 * 661 * In case the tuner module is used the drxdriver takes care of this. 662 * In case the tuner module is NOT used the application programmer must take 663 * care of this. 664 * 665 */ 666 #define DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET ((s32)(2775)) 667 668 /** 669 * \def DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET 670 * \brief Offset from picture carrier to centre frequency in kHz, in RF domain 671 * 672 * For PAL/SECAM - LP standard. This define is needed in case the tuner module 673 * is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc). 674 * The DRX-J requires that the tuner is tuned to: 675 * Fpc + DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET 676 * 677 * In case the tuner module is used the drxdriver takes care of this. 678 * In case the tuner module is NOT used the application programmer must take 679 * care of this. 680 */ 681 #define DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET ((s32)(-3255)) 682 683 /** 684 * \def DRXJ_FM_CARRIER_FREQ_OFFSET 685 * \brief Offset from sound carrier to centre frequency in kHz, in RF domain 686 * 687 * For FM standard. 688 * FM channels are listed by their sound carrier frequency (Fsc). 689 * The function DRX_CTRL_SET_CHANNEL requires the Ffm frequency (see below) as 690 * input. 691 * In case the tuner module is not used the DRX-J requires that the tuner is 692 * tuned to the Ffm frequency of the channel. 693 * 694 * Ffm = Fsc + DRXJ_FM_CARRIER_FREQ_OFFSET 695 * 696 */ 697 #define DRXJ_FM_CARRIER_FREQ_OFFSET ((s32)(-3000)) 698 699 /* Revision types -------------------------------------------------------*/ 700 701 #define DRXJ_TYPE_ID (0x3946000DUL) 702 703 /* Macros ---------------------------------------------------------------*/ 704 705 /* Convert OOB lock status to string */ 706 #define DRXJ_STR_OOB_LOCKSTATUS(x) ( \ 707 (x == DRX_NEVER_LOCK) ? "Never" : \ 708 (x == DRX_NOT_LOCKED) ? "No" : \ 709 (x == DRX_LOCKED) ? "Locked" : \ 710 (x == DRX_LOCK_STATE_1) ? "AGC lock" : \ 711 (x == DRX_LOCK_STATE_2) ? "sync lock" : \ 712 "(Invalid)") 713 714 /*------------------------------------------------------------------------- 715 ENUM 716 -------------------------------------------------------------------------*/ 717 718 /*------------------------------------------------------------------------- 719 STRUCTS 720 -------------------------------------------------------------------------*/ 721 722 /*------------------------------------------------------------------------- 723 Exported FUNCTIONS 724 -------------------------------------------------------------------------*/ 725 726 extern int DRXJ_Open(pDRXDemodInstance_t demod); 727 extern int DRXJ_Close(pDRXDemodInstance_t demod); 728 extern int DRXJ_Ctrl(pDRXDemodInstance_t demod, 729 u32 ctrl, void *ctrlData); 730 731 /*------------------------------------------------------------------------- 732 Exported GLOBAL VARIABLES 733 -------------------------------------------------------------------------*/ 734 extern DRXAccessFunc_t drxDapDRXJFunct_g; 735 extern DRXDemodFunc_t DRXJFunctions_g; 736 extern DRXJData_t DRXJData_g; 737 extern struct i2c_device_addr DRXJDefaultAddr_g; 738 extern DRXCommonAttr_t DRXJDefaultCommAttr_g; 739 extern DRXDemodInstance_t DRXJDefaultDemod_g; 740 741 /*------------------------------------------------------------------------- 742 THE END 743 -------------------------------------------------------------------------*/ 744 #ifdef __cplusplus 745 } 746 #endif 747 #endif /* __DRXJ_H__ */ 748