xref: /linux/drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.h (revision 762f99f4f3cb41a775b5157dd761217beba65873)
129c8d9ebSAdit Ranadive /*
229c8d9ebSAdit Ranadive  * Copyright (c) 2012-2016 VMware, Inc.  All rights reserved.
329c8d9ebSAdit Ranadive  *
429c8d9ebSAdit Ranadive  * This program is free software; you can redistribute it and/or
529c8d9ebSAdit Ranadive  * modify it under the terms of EITHER the GNU General Public License
629c8d9ebSAdit Ranadive  * version 2 as published by the Free Software Foundation or the BSD
729c8d9ebSAdit Ranadive  * 2-Clause License. This program is distributed in the hope that it
829c8d9ebSAdit Ranadive  * will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
929c8d9ebSAdit Ranadive  * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
1029c8d9ebSAdit Ranadive  * See the GNU General Public License version 2 for more details at
1129c8d9ebSAdit Ranadive  * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
1229c8d9ebSAdit Ranadive  *
1329c8d9ebSAdit Ranadive  * You should have received a copy of the GNU General Public License
1429c8d9ebSAdit Ranadive  * along with this program available in the file COPYING in the main
1529c8d9ebSAdit Ranadive  * directory of this source tree.
1629c8d9ebSAdit Ranadive  *
1729c8d9ebSAdit Ranadive  * The BSD 2-Clause License
1829c8d9ebSAdit Ranadive  *
1929c8d9ebSAdit Ranadive  *     Redistribution and use in source and binary forms, with or
2029c8d9ebSAdit Ranadive  *     without modification, are permitted provided that the following
2129c8d9ebSAdit Ranadive  *     conditions are met:
2229c8d9ebSAdit Ranadive  *
2329c8d9ebSAdit Ranadive  *      - Redistributions of source code must retain the above
2429c8d9ebSAdit Ranadive  *        copyright notice, this list of conditions and the following
2529c8d9ebSAdit Ranadive  *        disclaimer.
2629c8d9ebSAdit Ranadive  *
2729c8d9ebSAdit Ranadive  *      - Redistributions in binary form must reproduce the above
2829c8d9ebSAdit Ranadive  *        copyright notice, this list of conditions and the following
2929c8d9ebSAdit Ranadive  *        disclaimer in the documentation and/or other materials
3029c8d9ebSAdit Ranadive  *        provided with the distribution.
3129c8d9ebSAdit Ranadive  *
3229c8d9ebSAdit Ranadive  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
3329c8d9ebSAdit Ranadive  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
3429c8d9ebSAdit Ranadive  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
3529c8d9ebSAdit Ranadive  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
3629c8d9ebSAdit Ranadive  * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
3729c8d9ebSAdit Ranadive  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
3829c8d9ebSAdit Ranadive  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
3929c8d9ebSAdit Ranadive  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
4029c8d9ebSAdit Ranadive  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
4129c8d9ebSAdit Ranadive  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
4229c8d9ebSAdit Ranadive  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
4329c8d9ebSAdit Ranadive  * OF THE POSSIBILITY OF SUCH DAMAGE.
4429c8d9ebSAdit Ranadive  */
4529c8d9ebSAdit Ranadive 
4629c8d9ebSAdit Ranadive #ifndef __PVRDMA_VERBS_H__
4729c8d9ebSAdit Ranadive #define __PVRDMA_VERBS_H__
4829c8d9ebSAdit Ranadive 
4929c8d9ebSAdit Ranadive #include <linux/types.h>
5029c8d9ebSAdit Ranadive 
5129c8d9ebSAdit Ranadive union pvrdma_gid {
5229c8d9ebSAdit Ranadive 	u8	raw[16];
5329c8d9ebSAdit Ranadive 	struct {
5429c8d9ebSAdit Ranadive 		__be64	subnet_prefix;
5529c8d9ebSAdit Ranadive 		__be64	interface_id;
5629c8d9ebSAdit Ranadive 	} global;
5729c8d9ebSAdit Ranadive };
5829c8d9ebSAdit Ranadive 
5929c8d9ebSAdit Ranadive enum pvrdma_link_layer {
6029c8d9ebSAdit Ranadive 	PVRDMA_LINK_LAYER_UNSPECIFIED,
6129c8d9ebSAdit Ranadive 	PVRDMA_LINK_LAYER_INFINIBAND,
6229c8d9ebSAdit Ranadive 	PVRDMA_LINK_LAYER_ETHERNET,
6329c8d9ebSAdit Ranadive };
6429c8d9ebSAdit Ranadive 
6529c8d9ebSAdit Ranadive enum pvrdma_mtu {
6629c8d9ebSAdit Ranadive 	PVRDMA_MTU_256  = 1,
6729c8d9ebSAdit Ranadive 	PVRDMA_MTU_512  = 2,
6829c8d9ebSAdit Ranadive 	PVRDMA_MTU_1024 = 3,
6929c8d9ebSAdit Ranadive 	PVRDMA_MTU_2048 = 4,
7029c8d9ebSAdit Ranadive 	PVRDMA_MTU_4096 = 5,
7129c8d9ebSAdit Ranadive };
7229c8d9ebSAdit Ranadive 
7329c8d9ebSAdit Ranadive enum pvrdma_port_state {
7429c8d9ebSAdit Ranadive 	PVRDMA_PORT_NOP			= 0,
7529c8d9ebSAdit Ranadive 	PVRDMA_PORT_DOWN		= 1,
7629c8d9ebSAdit Ranadive 	PVRDMA_PORT_INIT		= 2,
7729c8d9ebSAdit Ranadive 	PVRDMA_PORT_ARMED		= 3,
7829c8d9ebSAdit Ranadive 	PVRDMA_PORT_ACTIVE		= 4,
7929c8d9ebSAdit Ranadive 	PVRDMA_PORT_ACTIVE_DEFER	= 5,
8029c8d9ebSAdit Ranadive };
8129c8d9ebSAdit Ranadive 
8229c8d9ebSAdit Ranadive enum pvrdma_port_cap_flags {
8329c8d9ebSAdit Ranadive 	PVRDMA_PORT_SM				= 1 <<  1,
8429c8d9ebSAdit Ranadive 	PVRDMA_PORT_NOTICE_SUP			= 1 <<  2,
8529c8d9ebSAdit Ranadive 	PVRDMA_PORT_TRAP_SUP			= 1 <<  3,
8629c8d9ebSAdit Ranadive 	PVRDMA_PORT_OPT_IPD_SUP			= 1 <<  4,
8729c8d9ebSAdit Ranadive 	PVRDMA_PORT_AUTO_MIGR_SUP		= 1 <<  5,
8829c8d9ebSAdit Ranadive 	PVRDMA_PORT_SL_MAP_SUP			= 1 <<  6,
8929c8d9ebSAdit Ranadive 	PVRDMA_PORT_MKEY_NVRAM			= 1 <<  7,
9029c8d9ebSAdit Ranadive 	PVRDMA_PORT_PKEY_NVRAM			= 1 <<  8,
9129c8d9ebSAdit Ranadive 	PVRDMA_PORT_LED_INFO_SUP		= 1 <<  9,
9229c8d9ebSAdit Ranadive 	PVRDMA_PORT_SM_DISABLED			= 1 << 10,
9329c8d9ebSAdit Ranadive 	PVRDMA_PORT_SYS_IMAGE_GUID_SUP		= 1 << 11,
9429c8d9ebSAdit Ranadive 	PVRDMA_PORT_PKEY_SW_EXT_PORT_TRAP_SUP	= 1 << 12,
9529c8d9ebSAdit Ranadive 	PVRDMA_PORT_EXTENDED_SPEEDS_SUP		= 1 << 14,
9629c8d9ebSAdit Ranadive 	PVRDMA_PORT_CM_SUP			= 1 << 16,
9729c8d9ebSAdit Ranadive 	PVRDMA_PORT_SNMP_TUNNEL_SUP		= 1 << 17,
9829c8d9ebSAdit Ranadive 	PVRDMA_PORT_REINIT_SUP			= 1 << 18,
9929c8d9ebSAdit Ranadive 	PVRDMA_PORT_DEVICE_MGMT_SUP		= 1 << 19,
10029c8d9ebSAdit Ranadive 	PVRDMA_PORT_VENDOR_CLASS_SUP		= 1 << 20,
10129c8d9ebSAdit Ranadive 	PVRDMA_PORT_DR_NOTICE_SUP		= 1 << 21,
10229c8d9ebSAdit Ranadive 	PVRDMA_PORT_CAP_MASK_NOTICE_SUP		= 1 << 22,
10329c8d9ebSAdit Ranadive 	PVRDMA_PORT_BOOT_MGMT_SUP		= 1 << 23,
10429c8d9ebSAdit Ranadive 	PVRDMA_PORT_LINK_LATENCY_SUP		= 1 << 24,
10529c8d9ebSAdit Ranadive 	PVRDMA_PORT_CLIENT_REG_SUP		= 1 << 25,
10629c8d9ebSAdit Ranadive 	PVRDMA_PORT_IP_BASED_GIDS		= 1 << 26,
10729c8d9ebSAdit Ranadive 	PVRDMA_PORT_CAP_FLAGS_MAX		= PVRDMA_PORT_IP_BASED_GIDS,
10829c8d9ebSAdit Ranadive };
10929c8d9ebSAdit Ranadive 
11029c8d9ebSAdit Ranadive enum pvrdma_port_width {
11129c8d9ebSAdit Ranadive 	PVRDMA_WIDTH_1X		= 1,
11229c8d9ebSAdit Ranadive 	PVRDMA_WIDTH_4X		= 2,
11329c8d9ebSAdit Ranadive 	PVRDMA_WIDTH_8X		= 4,
11429c8d9ebSAdit Ranadive 	PVRDMA_WIDTH_12X	= 8,
11529c8d9ebSAdit Ranadive };
11629c8d9ebSAdit Ranadive 
11729c8d9ebSAdit Ranadive enum pvrdma_port_speed {
11829c8d9ebSAdit Ranadive 	PVRDMA_SPEED_SDR	= 1,
11929c8d9ebSAdit Ranadive 	PVRDMA_SPEED_DDR	= 2,
12029c8d9ebSAdit Ranadive 	PVRDMA_SPEED_QDR	= 4,
12129c8d9ebSAdit Ranadive 	PVRDMA_SPEED_FDR10	= 8,
12229c8d9ebSAdit Ranadive 	PVRDMA_SPEED_FDR	= 16,
12329c8d9ebSAdit Ranadive 	PVRDMA_SPEED_EDR	= 32,
12429c8d9ebSAdit Ranadive };
12529c8d9ebSAdit Ranadive 
12629c8d9ebSAdit Ranadive struct pvrdma_port_attr {
12729c8d9ebSAdit Ranadive 	enum pvrdma_port_state	state;
12829c8d9ebSAdit Ranadive 	enum pvrdma_mtu		max_mtu;
12929c8d9ebSAdit Ranadive 	enum pvrdma_mtu		active_mtu;
13029c8d9ebSAdit Ranadive 	u32			gid_tbl_len;
13129c8d9ebSAdit Ranadive 	u32			port_cap_flags;
13229c8d9ebSAdit Ranadive 	u32			max_msg_sz;
13329c8d9ebSAdit Ranadive 	u32			bad_pkey_cntr;
13429c8d9ebSAdit Ranadive 	u32			qkey_viol_cntr;
13529c8d9ebSAdit Ranadive 	u16			pkey_tbl_len;
13629c8d9ebSAdit Ranadive 	u16			lid;
13729c8d9ebSAdit Ranadive 	u16			sm_lid;
13829c8d9ebSAdit Ranadive 	u8			lmc;
13929c8d9ebSAdit Ranadive 	u8			max_vl_num;
14029c8d9ebSAdit Ranadive 	u8			sm_sl;
14129c8d9ebSAdit Ranadive 	u8			subnet_timeout;
14229c8d9ebSAdit Ranadive 	u8			init_type_reply;
14329c8d9ebSAdit Ranadive 	u8			active_width;
14400469c97SAdit Ranadive 	u8			active_speed;
14529c8d9ebSAdit Ranadive 	u8			phys_state;
14629c8d9ebSAdit Ranadive 	u8			reserved[2];
14729c8d9ebSAdit Ranadive };
14829c8d9ebSAdit Ranadive 
14929c8d9ebSAdit Ranadive struct pvrdma_global_route {
15029c8d9ebSAdit Ranadive 	union pvrdma_gid	dgid;
15129c8d9ebSAdit Ranadive 	u32			flow_label;
15229c8d9ebSAdit Ranadive 	u8			sgid_index;
15329c8d9ebSAdit Ranadive 	u8			hop_limit;
15429c8d9ebSAdit Ranadive 	u8			traffic_class;
15529c8d9ebSAdit Ranadive 	u8			reserved;
15629c8d9ebSAdit Ranadive };
15729c8d9ebSAdit Ranadive 
15829c8d9ebSAdit Ranadive struct pvrdma_grh {
15929c8d9ebSAdit Ranadive 	__be32			version_tclass_flow;
16029c8d9ebSAdit Ranadive 	__be16			paylen;
16129c8d9ebSAdit Ranadive 	u8			next_hdr;
16229c8d9ebSAdit Ranadive 	u8			hop_limit;
16329c8d9ebSAdit Ranadive 	union pvrdma_gid	sgid;
16429c8d9ebSAdit Ranadive 	union pvrdma_gid	dgid;
16529c8d9ebSAdit Ranadive };
16629c8d9ebSAdit Ranadive 
16729c8d9ebSAdit Ranadive enum pvrdma_ah_flags {
16829c8d9ebSAdit Ranadive 	PVRDMA_AH_GRH = 1,
16929c8d9ebSAdit Ranadive };
17029c8d9ebSAdit Ranadive 
17129c8d9ebSAdit Ranadive enum pvrdma_rate {
17229c8d9ebSAdit Ranadive 	PVRDMA_RATE_PORT_CURRENT	= 0,
17329c8d9ebSAdit Ranadive 	PVRDMA_RATE_2_5_GBPS		= 2,
17429c8d9ebSAdit Ranadive 	PVRDMA_RATE_5_GBPS		= 5,
17529c8d9ebSAdit Ranadive 	PVRDMA_RATE_10_GBPS		= 3,
17629c8d9ebSAdit Ranadive 	PVRDMA_RATE_20_GBPS		= 6,
17729c8d9ebSAdit Ranadive 	PVRDMA_RATE_30_GBPS		= 4,
17829c8d9ebSAdit Ranadive 	PVRDMA_RATE_40_GBPS		= 7,
17929c8d9ebSAdit Ranadive 	PVRDMA_RATE_60_GBPS		= 8,
18029c8d9ebSAdit Ranadive 	PVRDMA_RATE_80_GBPS		= 9,
18129c8d9ebSAdit Ranadive 	PVRDMA_RATE_120_GBPS		= 10,
18229c8d9ebSAdit Ranadive 	PVRDMA_RATE_14_GBPS		= 11,
18329c8d9ebSAdit Ranadive 	PVRDMA_RATE_56_GBPS		= 12,
18429c8d9ebSAdit Ranadive 	PVRDMA_RATE_112_GBPS		= 13,
18529c8d9ebSAdit Ranadive 	PVRDMA_RATE_168_GBPS		= 14,
18629c8d9ebSAdit Ranadive 	PVRDMA_RATE_25_GBPS		= 15,
18729c8d9ebSAdit Ranadive 	PVRDMA_RATE_100_GBPS		= 16,
18829c8d9ebSAdit Ranadive 	PVRDMA_RATE_200_GBPS		= 17,
18929c8d9ebSAdit Ranadive 	PVRDMA_RATE_300_GBPS		= 18,
19029c8d9ebSAdit Ranadive };
19129c8d9ebSAdit Ranadive 
19229c8d9ebSAdit Ranadive struct pvrdma_ah_attr {
19329c8d9ebSAdit Ranadive 	struct pvrdma_global_route	grh;
19429c8d9ebSAdit Ranadive 	u16				dlid;
19529c8d9ebSAdit Ranadive 	u16				vlan_id;
19629c8d9ebSAdit Ranadive 	u8				sl;
19729c8d9ebSAdit Ranadive 	u8				src_path_bits;
19829c8d9ebSAdit Ranadive 	u8				static_rate;
19929c8d9ebSAdit Ranadive 	u8				ah_flags;
20029c8d9ebSAdit Ranadive 	u8				port_num;
20129c8d9ebSAdit Ranadive 	u8				dmac[6];
20229c8d9ebSAdit Ranadive 	u8				reserved;
20329c8d9ebSAdit Ranadive };
20429c8d9ebSAdit Ranadive 
20529c8d9ebSAdit Ranadive enum pvrdma_cq_notify_flags {
20629c8d9ebSAdit Ranadive 	PVRDMA_CQ_SOLICITED		= 1 << 0,
20729c8d9ebSAdit Ranadive 	PVRDMA_CQ_NEXT_COMP		= 1 << 1,
20829c8d9ebSAdit Ranadive 	PVRDMA_CQ_SOLICITED_MASK	= PVRDMA_CQ_SOLICITED |
20929c8d9ebSAdit Ranadive 					  PVRDMA_CQ_NEXT_COMP,
21029c8d9ebSAdit Ranadive 	PVRDMA_CQ_REPORT_MISSED_EVENTS	= 1 << 2,
21129c8d9ebSAdit Ranadive };
21229c8d9ebSAdit Ranadive 
21329c8d9ebSAdit Ranadive struct pvrdma_qp_cap {
21429c8d9ebSAdit Ranadive 	u32	max_send_wr;
21529c8d9ebSAdit Ranadive 	u32	max_recv_wr;
21629c8d9ebSAdit Ranadive 	u32	max_send_sge;
21729c8d9ebSAdit Ranadive 	u32	max_recv_sge;
21829c8d9ebSAdit Ranadive 	u32	max_inline_data;
21929c8d9ebSAdit Ranadive 	u32	reserved;
22029c8d9ebSAdit Ranadive };
22129c8d9ebSAdit Ranadive 
22229c8d9ebSAdit Ranadive enum pvrdma_sig_type {
22329c8d9ebSAdit Ranadive 	PVRDMA_SIGNAL_ALL_WR,
22429c8d9ebSAdit Ranadive 	PVRDMA_SIGNAL_REQ_WR,
22529c8d9ebSAdit Ranadive };
22629c8d9ebSAdit Ranadive 
22729c8d9ebSAdit Ranadive enum pvrdma_qp_type {
22829c8d9ebSAdit Ranadive 	PVRDMA_QPT_SMI,
22929c8d9ebSAdit Ranadive 	PVRDMA_QPT_GSI,
23029c8d9ebSAdit Ranadive 	PVRDMA_QPT_RC,
23129c8d9ebSAdit Ranadive 	PVRDMA_QPT_UC,
23229c8d9ebSAdit Ranadive 	PVRDMA_QPT_UD,
23329c8d9ebSAdit Ranadive 	PVRDMA_QPT_RAW_IPV6,
23429c8d9ebSAdit Ranadive 	PVRDMA_QPT_RAW_ETHERTYPE,
23529c8d9ebSAdit Ranadive 	PVRDMA_QPT_RAW_PACKET = 8,
23629c8d9ebSAdit Ranadive 	PVRDMA_QPT_XRC_INI = 9,
23729c8d9ebSAdit Ranadive 	PVRDMA_QPT_XRC_TGT,
23829c8d9ebSAdit Ranadive 	PVRDMA_QPT_MAX,
23929c8d9ebSAdit Ranadive };
24029c8d9ebSAdit Ranadive 
24129c8d9ebSAdit Ranadive enum pvrdma_qp_create_flags {
24229c8d9ebSAdit Ranadive 	PVRDMA_QP_CREATE_IPOPVRDMA_UD_LSO		= 1 << 0,
24329c8d9ebSAdit Ranadive 	PVRDMA_QP_CREATE_BLOCK_MULTICAST_LOOPBACK	= 1 << 1,
24429c8d9ebSAdit Ranadive };
24529c8d9ebSAdit Ranadive 
24629c8d9ebSAdit Ranadive enum pvrdma_qp_attr_mask {
24729c8d9ebSAdit Ranadive 	PVRDMA_QP_STATE			= 1 << 0,
24829c8d9ebSAdit Ranadive 	PVRDMA_QP_CUR_STATE		= 1 << 1,
24929c8d9ebSAdit Ranadive 	PVRDMA_QP_EN_SQD_ASYNC_NOTIFY	= 1 << 2,
25029c8d9ebSAdit Ranadive 	PVRDMA_QP_ACCESS_FLAGS		= 1 << 3,
25129c8d9ebSAdit Ranadive 	PVRDMA_QP_PKEY_INDEX		= 1 << 4,
25229c8d9ebSAdit Ranadive 	PVRDMA_QP_PORT			= 1 << 5,
25329c8d9ebSAdit Ranadive 	PVRDMA_QP_QKEY			= 1 << 6,
25429c8d9ebSAdit Ranadive 	PVRDMA_QP_AV			= 1 << 7,
25529c8d9ebSAdit Ranadive 	PVRDMA_QP_PATH_MTU		= 1 << 8,
25629c8d9ebSAdit Ranadive 	PVRDMA_QP_TIMEOUT		= 1 << 9,
25729c8d9ebSAdit Ranadive 	PVRDMA_QP_RETRY_CNT		= 1 << 10,
25829c8d9ebSAdit Ranadive 	PVRDMA_QP_RNR_RETRY		= 1 << 11,
25929c8d9ebSAdit Ranadive 	PVRDMA_QP_RQ_PSN		= 1 << 12,
26029c8d9ebSAdit Ranadive 	PVRDMA_QP_MAX_QP_RD_ATOMIC	= 1 << 13,
26129c8d9ebSAdit Ranadive 	PVRDMA_QP_ALT_PATH		= 1 << 14,
26229c8d9ebSAdit Ranadive 	PVRDMA_QP_MIN_RNR_TIMER		= 1 << 15,
26329c8d9ebSAdit Ranadive 	PVRDMA_QP_SQ_PSN		= 1 << 16,
26429c8d9ebSAdit Ranadive 	PVRDMA_QP_MAX_DEST_RD_ATOMIC	= 1 << 17,
26529c8d9ebSAdit Ranadive 	PVRDMA_QP_PATH_MIG_STATE	= 1 << 18,
26629c8d9ebSAdit Ranadive 	PVRDMA_QP_CAP			= 1 << 19,
26729c8d9ebSAdit Ranadive 	PVRDMA_QP_DEST_QPN		= 1 << 20,
26829c8d9ebSAdit Ranadive 	PVRDMA_QP_ATTR_MASK_MAX		= PVRDMA_QP_DEST_QPN,
26929c8d9ebSAdit Ranadive };
27029c8d9ebSAdit Ranadive 
27129c8d9ebSAdit Ranadive enum pvrdma_qp_state {
27229c8d9ebSAdit Ranadive 	PVRDMA_QPS_RESET,
27329c8d9ebSAdit Ranadive 	PVRDMA_QPS_INIT,
27429c8d9ebSAdit Ranadive 	PVRDMA_QPS_RTR,
27529c8d9ebSAdit Ranadive 	PVRDMA_QPS_RTS,
27629c8d9ebSAdit Ranadive 	PVRDMA_QPS_SQD,
27729c8d9ebSAdit Ranadive 	PVRDMA_QPS_SQE,
27829c8d9ebSAdit Ranadive 	PVRDMA_QPS_ERR,
27929c8d9ebSAdit Ranadive };
28029c8d9ebSAdit Ranadive 
28129c8d9ebSAdit Ranadive enum pvrdma_mig_state {
28229c8d9ebSAdit Ranadive 	PVRDMA_MIG_MIGRATED,
28329c8d9ebSAdit Ranadive 	PVRDMA_MIG_REARM,
28429c8d9ebSAdit Ranadive 	PVRDMA_MIG_ARMED,
28529c8d9ebSAdit Ranadive };
28629c8d9ebSAdit Ranadive 
28729c8d9ebSAdit Ranadive enum pvrdma_mw_type {
28829c8d9ebSAdit Ranadive 	PVRDMA_MW_TYPE_1 = 1,
28929c8d9ebSAdit Ranadive 	PVRDMA_MW_TYPE_2 = 2,
29029c8d9ebSAdit Ranadive };
29129c8d9ebSAdit Ranadive 
2928b10ba78SBryan Tan struct pvrdma_srq_attr {
2938b10ba78SBryan Tan 	u32			max_wr;
2948b10ba78SBryan Tan 	u32			max_sge;
2958b10ba78SBryan Tan 	u32			srq_limit;
2968b10ba78SBryan Tan 	u32			reserved;
2978b10ba78SBryan Tan };
2988b10ba78SBryan Tan 
29929c8d9ebSAdit Ranadive struct pvrdma_qp_attr {
30029c8d9ebSAdit Ranadive 	enum pvrdma_qp_state	qp_state;
30129c8d9ebSAdit Ranadive 	enum pvrdma_qp_state	cur_qp_state;
30229c8d9ebSAdit Ranadive 	enum pvrdma_mtu		path_mtu;
30329c8d9ebSAdit Ranadive 	enum pvrdma_mig_state	path_mig_state;
30429c8d9ebSAdit Ranadive 	u32			qkey;
30529c8d9ebSAdit Ranadive 	u32			rq_psn;
30629c8d9ebSAdit Ranadive 	u32			sq_psn;
30729c8d9ebSAdit Ranadive 	u32			dest_qp_num;
30829c8d9ebSAdit Ranadive 	u32			qp_access_flags;
30929c8d9ebSAdit Ranadive 	u16			pkey_index;
31029c8d9ebSAdit Ranadive 	u16			alt_pkey_index;
31129c8d9ebSAdit Ranadive 	u8			en_sqd_async_notify;
31229c8d9ebSAdit Ranadive 	u8			sq_draining;
31329c8d9ebSAdit Ranadive 	u8			max_rd_atomic;
31429c8d9ebSAdit Ranadive 	u8			max_dest_rd_atomic;
31529c8d9ebSAdit Ranadive 	u8			min_rnr_timer;
31629c8d9ebSAdit Ranadive 	u8			port_num;
31729c8d9ebSAdit Ranadive 	u8			timeout;
31829c8d9ebSAdit Ranadive 	u8			retry_cnt;
31929c8d9ebSAdit Ranadive 	u8			rnr_retry;
32029c8d9ebSAdit Ranadive 	u8			alt_port_num;
32129c8d9ebSAdit Ranadive 	u8			alt_timeout;
32229c8d9ebSAdit Ranadive 	u8			reserved[5];
32329c8d9ebSAdit Ranadive 	struct pvrdma_qp_cap	cap;
32429c8d9ebSAdit Ranadive 	struct pvrdma_ah_attr	ah_attr;
32529c8d9ebSAdit Ranadive 	struct pvrdma_ah_attr	alt_ah_attr;
32629c8d9ebSAdit Ranadive };
32729c8d9ebSAdit Ranadive 
32829c8d9ebSAdit Ranadive enum pvrdma_send_flags {
32929c8d9ebSAdit Ranadive 	PVRDMA_SEND_FENCE	= 1 << 0,
33029c8d9ebSAdit Ranadive 	PVRDMA_SEND_SIGNALED	= 1 << 1,
33129c8d9ebSAdit Ranadive 	PVRDMA_SEND_SOLICITED	= 1 << 2,
33229c8d9ebSAdit Ranadive 	PVRDMA_SEND_INLINE	= 1 << 3,
33329c8d9ebSAdit Ranadive 	PVRDMA_SEND_IP_CSUM	= 1 << 4,
33429c8d9ebSAdit Ranadive 	PVRDMA_SEND_FLAGS_MAX	= PVRDMA_SEND_IP_CSUM,
33529c8d9ebSAdit Ranadive };
33629c8d9ebSAdit Ranadive 
33729c8d9ebSAdit Ranadive enum pvrdma_access_flags {
33829c8d9ebSAdit Ranadive 	PVRDMA_ACCESS_LOCAL_WRITE	= 1 << 0,
33929c8d9ebSAdit Ranadive 	PVRDMA_ACCESS_REMOTE_WRITE	= 1 << 1,
34029c8d9ebSAdit Ranadive 	PVRDMA_ACCESS_REMOTE_READ	= 1 << 2,
34129c8d9ebSAdit Ranadive 	PVRDMA_ACCESS_REMOTE_ATOMIC	= 1 << 3,
34229c8d9ebSAdit Ranadive 	PVRDMA_ACCESS_MW_BIND		= 1 << 4,
34329c8d9ebSAdit Ranadive 	PVRDMA_ZERO_BASED		= 1 << 5,
34429c8d9ebSAdit Ranadive 	PVRDMA_ACCESS_ON_DEMAND		= 1 << 6,
34529c8d9ebSAdit Ranadive 	PVRDMA_ACCESS_FLAGS_MAX		= PVRDMA_ACCESS_ON_DEMAND,
34629c8d9ebSAdit Ranadive };
34729c8d9ebSAdit Ranadive 
34829c8d9ebSAdit Ranadive int pvrdma_query_device(struct ib_device *ibdev,
34929c8d9ebSAdit Ranadive 			struct ib_device_attr *props,
35029c8d9ebSAdit Ranadive 			struct ib_udata *udata);
3511fb7f897SMark Bloch int pvrdma_query_port(struct ib_device *ibdev, u32 port,
35229c8d9ebSAdit Ranadive 		      struct ib_port_attr *props);
3531fb7f897SMark Bloch int pvrdma_query_gid(struct ib_device *ibdev, u32 port,
35429c8d9ebSAdit Ranadive 		     int index, union ib_gid *gid);
3551fb7f897SMark Bloch int pvrdma_query_pkey(struct ib_device *ibdev, u32 port,
35629c8d9ebSAdit Ranadive 		      u16 index, u16 *pkey);
35729c8d9ebSAdit Ranadive enum rdma_link_layer pvrdma_port_link_layer(struct ib_device *ibdev,
3581fb7f897SMark Bloch 					    u32 port);
35929c8d9ebSAdit Ranadive int pvrdma_modify_device(struct ib_device *ibdev, int mask,
36029c8d9ebSAdit Ranadive 			 struct ib_device_modify *props);
3611fb7f897SMark Bloch int pvrdma_modify_port(struct ib_device *ibdev, u32 port,
36229c8d9ebSAdit Ranadive 		       int mask, struct ib_port_modify *props);
36329c8d9ebSAdit Ranadive int pvrdma_mmap(struct ib_ucontext *context, struct vm_area_struct *vma);
364a2a074efSLeon Romanovsky int pvrdma_alloc_ucontext(struct ib_ucontext *uctx, struct ib_udata *udata);
365a2a074efSLeon Romanovsky void pvrdma_dealloc_ucontext(struct ib_ucontext *context);
366ff23dfa1SShamir Rabinovitch int pvrdma_alloc_pd(struct ib_pd *pd, struct ib_udata *udata);
36791a7c58fSLeon Romanovsky int pvrdma_dealloc_pd(struct ib_pd *ibpd, struct ib_udata *udata);
36829c8d9ebSAdit Ranadive struct ib_mr *pvrdma_get_dma_mr(struct ib_pd *pd, int acc);
36929c8d9ebSAdit Ranadive struct ib_mr *pvrdma_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
37029c8d9ebSAdit Ranadive 				 u64 virt_addr, int access_flags,
37129c8d9ebSAdit Ranadive 				 struct ib_udata *udata);
372c4367a26SShamir Rabinovitch int pvrdma_dereg_mr(struct ib_mr *mr, struct ib_udata *udata);
37329c8d9ebSAdit Ranadive struct ib_mr *pvrdma_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
37442a3b153SGal Pressman 			      u32 max_num_sg);
37529c8d9ebSAdit Ranadive int pvrdma_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg,
37629c8d9ebSAdit Ranadive 		     int sg_nents, unsigned int *sg_offset);
377e39afe3dSLeon Romanovsky int pvrdma_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
37829c8d9ebSAdit Ranadive 		     struct ib_udata *udata);
37943d781b9SLeon Romanovsky int pvrdma_destroy_cq(struct ib_cq *cq, struct ib_udata *udata);
38029c8d9ebSAdit Ranadive int pvrdma_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
38129c8d9ebSAdit Ranadive int pvrdma_req_notify_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags);
382fa5d010cSMaor Gottlieb int pvrdma_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr,
383d3456914SLeon Romanovsky 		     struct ib_udata *udata);
3849a9ebf8cSLeon Romanovsky int pvrdma_destroy_ah(struct ib_ah *ah, u32 flags);
3858b10ba78SBryan Tan 
38668e326deSLeon Romanovsky int pvrdma_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr,
3878b10ba78SBryan Tan 		      struct ib_udata *udata);
3888b10ba78SBryan Tan int pvrdma_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
3898b10ba78SBryan Tan 		      enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
3908b10ba78SBryan Tan int pvrdma_query_srq(struct ib_srq *srq, struct ib_srq_attr *srq_attr);
391119181d1SLeon Romanovsky int pvrdma_destroy_srq(struct ib_srq *srq, struct ib_udata *udata);
3928b10ba78SBryan Tan 
393*514aee66SLeon Romanovsky int pvrdma_create_qp(struct ib_qp *qp, struct ib_qp_init_attr *init_attr,
39429c8d9ebSAdit Ranadive 		     struct ib_udata *udata);
39529c8d9ebSAdit Ranadive int pvrdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
39629c8d9ebSAdit Ranadive 		     int attr_mask, struct ib_udata *udata);
39729c8d9ebSAdit Ranadive int pvrdma_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
39829c8d9ebSAdit Ranadive 		    int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr);
399c4367a26SShamir Rabinovitch int pvrdma_destroy_qp(struct ib_qp *qp, struct ib_udata *udata);
400d34ac5cdSBart Van Assche int pvrdma_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
401d34ac5cdSBart Van Assche 		     const struct ib_send_wr **bad_wr);
402d34ac5cdSBart Van Assche int pvrdma_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
403d34ac5cdSBart Van Assche 		     const struct ib_recv_wr **bad_wr);
40429c8d9ebSAdit Ranadive 
40529c8d9ebSAdit Ranadive #endif /* __PVRDMA_VERBS_H__ */
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