1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 #ifndef IRDMA_MAIN_H 4 #define IRDMA_MAIN_H 5 6 #include <linux/ip.h> 7 #include <linux/tcp.h> 8 #include <linux/if_vlan.h> 9 #include <net/addrconf.h> 10 #include <net/netevent.h> 11 #include <net/tcp.h> 12 #include <net/ip6_route.h> 13 #include <net/flow.h> 14 #include <net/secure_seq.h> 15 #include <linux/netdevice.h> 16 #include <linux/etherdevice.h> 17 #include <linux/inetdevice.h> 18 #include <linux/spinlock.h> 19 #include <linux/kernel.h> 20 #include <linux/delay.h> 21 #include <linux/pci.h> 22 #include <linux/dma-mapping.h> 23 #include <linux/workqueue.h> 24 #include <linux/slab.h> 25 #include <linux/io.h> 26 #include <linux/crc32c.h> 27 #include <linux/kthread.h> 28 #ifndef CONFIG_64BIT 29 #include <linux/io-64-nonatomic-lo-hi.h> 30 #endif 31 #include <linux/auxiliary_bus.h> 32 #include <linux/net/intel/iidc_rdma.h> 33 #include <linux/net/intel/iidc_rdma_ice.h> 34 #include <rdma/ib_smi.h> 35 #include <rdma/ib_verbs.h> 36 #include <rdma/ib_pack.h> 37 #include <rdma/rdma_cm.h> 38 #include <rdma/iw_cm.h> 39 #include <rdma/ib_user_verbs.h> 40 #include <rdma/ib_umem.h> 41 #include <rdma/ib_cache.h> 42 #include <rdma/uverbs_ioctl.h> 43 #include "osdep.h" 44 #include "defs.h" 45 #include "hmc.h" 46 #include "type.h" 47 #include "ws.h" 48 #include "protos.h" 49 #include "pble.h" 50 #include "cm.h" 51 #include <rdma/irdma-abi.h> 52 #include "verbs.h" 53 #include "user.h" 54 #include "puda.h" 55 56 extern struct auxiliary_driver i40iw_auxiliary_drv; 57 58 #define IRDMA_FW_VER_DEFAULT 2 59 #define IRDMA_HW_VER 2 60 61 #define IRDMA_ARP_ADD 1 62 #define IRDMA_ARP_DELETE 2 63 #define IRDMA_ARP_RESOLVE 3 64 65 #define IRDMA_MACIP_ADD 1 66 #define IRDMA_MACIP_DELETE 2 67 68 #define IW_CCQ_SIZE (IRDMA_CQP_SW_SQSIZE_2048 + 1) 69 #define IW_CEQ_SIZE 2048 70 #define IW_AEQ_SIZE 2048 71 72 #define RX_BUF_SIZE (1536 + 8) 73 #define IW_REG0_SIZE (4 * 1024) 74 #define IW_TX_TIMEOUT (6 * HZ) 75 #define IW_FIRST_QPN 1 76 77 #define IW_SW_CONTEXT_ALIGN 1024 78 79 #define MAX_DPC_ITERATIONS 128 80 81 #define IRDMA_EVENT_TIMEOUT_MS 5000 82 #define IRDMA_VCHNL_EVENT_TIMEOUT 100000 83 #define IRDMA_RST_TIMEOUT_HZ 4 84 85 #define IRDMA_NO_QSET 0xffff 86 87 #define IW_CFG_FPM_QP_COUNT 32768 88 #define IRDMA_MAX_PAGES_PER_FMR 262144 89 #define IRDMA_MIN_PAGES_PER_FMR 1 90 #define IRDMA_CQP_COMPL_RQ_WQE_FLUSHED 2 91 #define IRDMA_CQP_COMPL_SQ_WQE_FLUSHED 3 92 93 #define IRDMA_Q_TYPE_PE_AEQ 0x80 94 #define IRDMA_Q_INVALID_IDX 0xffff 95 #define IRDMA_REM_ENDPOINT_TRK_QPID 3 96 97 #define IRDMA_DRV_OPT_ENA_MPA_VER_0 0x00000001 98 #define IRDMA_DRV_OPT_DISABLE_MPA_CRC 0x00000002 99 #define IRDMA_DRV_OPT_DISABLE_FIRST_WRITE 0x00000004 100 #define IRDMA_DRV_OPT_DISABLE_INTF 0x00000008 101 #define IRDMA_DRV_OPT_ENA_MSI 0x00000010 102 #define IRDMA_DRV_OPT_DUAL_LOGICAL_PORT 0x00000020 103 #define IRDMA_DRV_OPT_NO_INLINE_DATA 0x00000080 104 #define IRDMA_DRV_OPT_DISABLE_INT_MOD 0x00000100 105 #define IRDMA_DRV_OPT_DISABLE_VIRT_WQ 0x00000200 106 #define IRDMA_DRV_OPT_ENA_PAU 0x00000400 107 #define IRDMA_DRV_OPT_MCAST_LOGPORT_MAP 0x00000800 108 109 #define IW_HMC_OBJ_TYPE_NUM ARRAY_SIZE(iw_hmc_obj_types) 110 #define IRDMA_ROCE_CWND_DEFAULT 0x400 111 #define IRDMA_ROCE_ACKCREDS_DEFAULT 0x1E 112 113 #define IRDMA_FLUSH_SQ BIT(0) 114 #define IRDMA_FLUSH_RQ BIT(1) 115 #define IRDMA_REFLUSH BIT(2) 116 #define IRDMA_FLUSH_WAIT BIT(3) 117 118 #define IRDMA_IRQ_NAME_STR_LEN (64) 119 120 #define IRDMA_NUM_AEQ_MSIX 1 121 #define IRDMA_MIN_MSIX 2 122 123 enum init_completion_state { 124 INVALID_STATE = 0, 125 INITIAL_STATE, 126 CQP_CREATED, 127 HMC_OBJS_CREATED, 128 HW_RSRC_INITIALIZED, 129 CCQ_CREATED, 130 CEQ0_CREATED, /* Last state of probe */ 131 ILQ_CREATED, 132 IEQ_CREATED, 133 CEQS_CREATED, 134 PBLE_CHUNK_MEM, 135 AEQ_CREATED, 136 IP_ADDR_REGISTERED, /* Last state of open */ 137 }; 138 139 struct irdma_rsrc_limits { 140 u32 qplimit; 141 u32 mrlimit; 142 u32 cqlimit; 143 }; 144 145 struct irdma_cqp_err_info { 146 u16 maj; 147 u16 min; 148 const char *desc; 149 }; 150 151 struct irdma_cqp_compl_info { 152 u32 op_ret_val; 153 u16 maj_err_code; 154 u16 min_err_code; 155 bool error; 156 u8 op_code; 157 }; 158 159 struct irdma_cqp_request { 160 struct cqp_cmds_info info; 161 wait_queue_head_t waitq; 162 struct list_head list; 163 refcount_t refcnt; 164 void (*callback_fcn)(struct irdma_cqp_request *cqp_request); 165 void *param; 166 struct irdma_cqp_compl_info compl_info; 167 bool request_done; /* READ/WRITE_ONCE macros operate on it */ 168 bool waiting:1; 169 bool dynamic:1; 170 }; 171 172 struct irdma_cqp { 173 struct irdma_sc_cqp sc_cqp; 174 spinlock_t req_lock; /* protect CQP request list */ 175 spinlock_t compl_lock; /* protect CQP completion processing */ 176 wait_queue_head_t waitq; 177 wait_queue_head_t remove_wq; 178 struct irdma_dma_mem sq; 179 struct irdma_dma_mem host_ctx; 180 u64 *scratch_array; 181 struct irdma_cqp_request *cqp_requests; 182 struct list_head cqp_avail_reqs; 183 struct list_head cqp_pending_reqs; 184 }; 185 186 struct irdma_ccq { 187 struct irdma_sc_cq sc_cq; 188 struct irdma_dma_mem mem_cq; 189 struct irdma_dma_mem shadow_area; 190 }; 191 192 struct irdma_ceq { 193 struct irdma_sc_ceq sc_ceq; 194 struct irdma_dma_mem mem; 195 u32 irq; 196 u32 msix_idx; 197 struct irdma_pci_f *rf; 198 struct tasklet_struct dpc_tasklet; 199 spinlock_t ce_lock; /* sync cq destroy with cq completion event notification */ 200 }; 201 202 struct irdma_aeq { 203 struct irdma_sc_aeq sc_aeq; 204 struct irdma_dma_mem mem; 205 struct irdma_pble_alloc palloc; 206 bool virtual_map; 207 }; 208 209 struct irdma_arp_entry { 210 u32 ip_addr[4]; 211 u8 mac_addr[ETH_ALEN]; 212 }; 213 214 struct irdma_msix_vector { 215 u32 idx; 216 u32 irq; 217 u32 cpu_affinity; 218 u32 ceq_id; 219 cpumask_t mask; 220 char name[IRDMA_IRQ_NAME_STR_LEN]; 221 }; 222 223 struct irdma_mc_table_info { 224 u32 mgn; 225 u32 dest_ip[4]; 226 bool lan_fwd:1; 227 bool ipv4_valid:1; 228 }; 229 230 struct mc_table_list { 231 struct list_head list; 232 struct irdma_mc_table_info mc_info; 233 struct irdma_mcast_grp_info mc_grp_ctx; 234 }; 235 236 struct irdma_qv_info { 237 u32 v_idx; /* msix_vector */ 238 u16 ceq_idx; 239 u16 aeq_idx; 240 u8 itr_idx; 241 }; 242 243 struct irdma_qvlist_info { 244 u32 num_vectors; 245 struct irdma_qv_info qv_info[] __counted_by(num_vectors); 246 }; 247 248 struct irdma_gen_ops { 249 void (*request_reset)(struct irdma_pci_f *rf); 250 int (*register_qset)(struct irdma_sc_vsi *vsi, 251 struct irdma_ws_node *tc_node); 252 void (*unregister_qset)(struct irdma_sc_vsi *vsi, 253 struct irdma_ws_node *tc_node); 254 }; 255 256 struct irdma_pci_f { 257 bool reset:1; 258 bool rsrc_created:1; 259 bool msix_shared:1; 260 u8 rsrc_profile; 261 u8 *hmc_info_mem; 262 u8 *mem_rsrc; 263 u8 rdma_ver; 264 u8 rst_to; 265 u8 pf_id; 266 enum irdma_protocol_used protocol_used; 267 u32 sd_type; 268 u32 msix_count; 269 u32 max_mr; 270 u32 max_qp; 271 u32 max_cq; 272 u32 max_ah; 273 u32 next_ah; 274 u32 max_mcg; 275 u32 next_mcg; 276 u32 max_pd; 277 u32 next_qp; 278 u32 next_cq; 279 u32 next_pd; 280 u32 max_mr_size; 281 u32 max_cqe; 282 u32 mr_stagmask; 283 u32 used_pds; 284 u32 used_cqs; 285 u32 used_mrs; 286 u32 used_qps; 287 u32 arp_table_size; 288 u32 next_arp_index; 289 u32 ceqs_count; 290 u32 next_ws_node_id; 291 u32 max_ws_node_id; 292 u32 limits_sel; 293 unsigned long *allocated_ws_nodes; 294 unsigned long *allocated_qps; 295 unsigned long *allocated_cqs; 296 unsigned long *allocated_mrs; 297 unsigned long *allocated_pds; 298 unsigned long *allocated_mcgs; 299 unsigned long *allocated_ahs; 300 unsigned long *allocated_arps; 301 enum init_completion_state init_state; 302 struct irdma_sc_dev sc_dev; 303 struct pci_dev *pcidev; 304 void *cdev; 305 struct irdma_hw hw; 306 struct irdma_cqp cqp; 307 struct irdma_ccq ccq; 308 struct irdma_aeq aeq; 309 struct irdma_ceq *ceqlist; 310 struct irdma_hmc_pble_rsrc *pble_rsrc; 311 struct irdma_arp_entry *arp_table; 312 spinlock_t arp_lock; /*protect ARP table access*/ 313 spinlock_t rsrc_lock; /* protect HW resource array access */ 314 spinlock_t qptable_lock; /*protect QP table access*/ 315 spinlock_t cqtable_lock; /*protect CQ table access*/ 316 struct irdma_qp **qp_table; 317 struct irdma_cq **cq_table; 318 spinlock_t qh_list_lock; /* protect mc_qht_list */ 319 struct mc_table_list mc_qht_list; 320 struct irdma_msix_vector *iw_msixtbl; 321 struct irdma_qvlist_info *iw_qvlist; 322 struct tasklet_struct dpc_tasklet; 323 struct msix_entry *msix_entries; 324 struct irdma_dma_mem obj_mem; 325 struct irdma_dma_mem obj_next; 326 atomic_t vchnl_msgs; 327 wait_queue_head_t vchnl_waitq; 328 struct workqueue_struct *cqp_cmpl_wq; 329 struct work_struct cqp_cmpl_work; 330 struct irdma_sc_vsi default_vsi; 331 void *back_fcn; 332 struct irdma_gen_ops gen_ops; 333 struct irdma_device *iwdev; 334 }; 335 336 struct irdma_device { 337 struct ib_device ibdev; 338 struct irdma_pci_f *rf; 339 struct net_device *netdev; 340 struct workqueue_struct *cleanup_wq; 341 struct irdma_sc_vsi vsi; 342 struct irdma_cm_core cm_core; 343 DECLARE_HASHTABLE(ah_hash_tbl, 8); 344 struct mutex ah_tbl_lock; /* protect AH hash table access */ 345 u32 roce_cwnd; 346 u32 roce_ackcreds; 347 u32 vendor_id; 348 u32 vendor_part_id; 349 u32 push_mode; 350 u32 rcv_wnd; 351 u16 mac_ip_table_idx; 352 u16 vsi_num; 353 u8 rcv_wscale; 354 u8 iw_status; 355 bool roce_mode:1; 356 bool roce_dcqcn_en:1; 357 bool dcb_vlan_mode:1; 358 bool iw_ooo:1; 359 enum init_completion_state init_state; 360 361 wait_queue_head_t suspend_wq; 362 }; 363 364 static inline struct irdma_device *to_iwdev(struct ib_device *ibdev) 365 { 366 return container_of(ibdev, struct irdma_device, ibdev); 367 } 368 369 static inline struct irdma_ucontext *to_ucontext(struct ib_ucontext *ibucontext) 370 { 371 return container_of(ibucontext, struct irdma_ucontext, ibucontext); 372 } 373 374 static inline struct irdma_user_mmap_entry * 375 to_irdma_mmap_entry(struct rdma_user_mmap_entry *rdma_entry) 376 { 377 return container_of(rdma_entry, struct irdma_user_mmap_entry, 378 rdma_entry); 379 } 380 381 static inline struct irdma_pd *to_iwpd(struct ib_pd *ibpd) 382 { 383 return container_of(ibpd, struct irdma_pd, ibpd); 384 } 385 386 static inline struct irdma_ah *to_iwah(struct ib_ah *ibah) 387 { 388 return container_of(ibah, struct irdma_ah, ibah); 389 } 390 391 static inline struct irdma_mr *to_iwmr(struct ib_mr *ibmr) 392 { 393 return container_of(ibmr, struct irdma_mr, ibmr); 394 } 395 396 static inline struct irdma_mr *to_iwmw(struct ib_mw *ibmw) 397 { 398 return container_of(ibmw, struct irdma_mr, ibmw); 399 } 400 401 static inline struct irdma_cq *to_iwcq(struct ib_cq *ibcq) 402 { 403 return container_of(ibcq, struct irdma_cq, ibcq); 404 } 405 406 static inline struct irdma_qp *to_iwqp(struct ib_qp *ibqp) 407 { 408 return container_of(ibqp, struct irdma_qp, ibqp); 409 } 410 411 static inline struct irdma_pci_f *dev_to_rf(struct irdma_sc_dev *dev) 412 { 413 return container_of(dev, struct irdma_pci_f, sc_dev); 414 } 415 416 /** 417 * irdma_alloc_resource - allocate a resource 418 * @iwdev: device pointer 419 * @resource_array: resource bit array: 420 * @max_resources: maximum resource number 421 * @req_resources_num: Allocated resource number 422 * @next: next free id 423 **/ 424 static inline int irdma_alloc_rsrc(struct irdma_pci_f *rf, 425 unsigned long *rsrc_array, u32 max_rsrc, 426 u32 *req_rsrc_num, u32 *next) 427 { 428 u32 rsrc_num; 429 unsigned long flags; 430 431 spin_lock_irqsave(&rf->rsrc_lock, flags); 432 rsrc_num = find_next_zero_bit(rsrc_array, max_rsrc, *next); 433 if (rsrc_num >= max_rsrc) { 434 rsrc_num = find_first_zero_bit(rsrc_array, max_rsrc); 435 if (rsrc_num >= max_rsrc) { 436 spin_unlock_irqrestore(&rf->rsrc_lock, flags); 437 ibdev_dbg(&rf->iwdev->ibdev, 438 "ERR: resource [%d] allocation failed\n", 439 rsrc_num); 440 return -EOVERFLOW; 441 } 442 } 443 __set_bit(rsrc_num, rsrc_array); 444 *next = rsrc_num + 1; 445 if (*next == max_rsrc) 446 *next = 0; 447 *req_rsrc_num = rsrc_num; 448 spin_unlock_irqrestore(&rf->rsrc_lock, flags); 449 450 return 0; 451 } 452 453 /** 454 * irdma_free_resource - free a resource 455 * @iwdev: device pointer 456 * @resource_array: resource array for the resource_num 457 * @resource_num: resource number to free 458 **/ 459 static inline void irdma_free_rsrc(struct irdma_pci_f *rf, 460 unsigned long *rsrc_array, u32 rsrc_num) 461 { 462 unsigned long flags; 463 464 spin_lock_irqsave(&rf->rsrc_lock, flags); 465 __clear_bit(rsrc_num, rsrc_array); 466 spin_unlock_irqrestore(&rf->rsrc_lock, flags); 467 } 468 469 int irdma_ctrl_init_hw(struct irdma_pci_f *rf); 470 void irdma_ctrl_deinit_hw(struct irdma_pci_f *rf); 471 int irdma_rt_init_hw(struct irdma_device *iwdev, 472 struct irdma_l2params *l2params); 473 void irdma_rt_deinit_hw(struct irdma_device *iwdev); 474 void irdma_qp_add_ref(struct ib_qp *ibqp); 475 void irdma_qp_rem_ref(struct ib_qp *ibqp); 476 void irdma_free_lsmm_rsrc(struct irdma_qp *iwqp); 477 struct ib_qp *irdma_get_qp(struct ib_device *ibdev, int qpn); 478 void irdma_flush_wqes(struct irdma_qp *iwqp, u32 flush_mask); 479 void irdma_manage_arp_cache(struct irdma_pci_f *rf, 480 const unsigned char *mac_addr, 481 u32 *ip_addr, bool ipv4, u32 action); 482 struct irdma_apbvt_entry *irdma_add_apbvt(struct irdma_device *iwdev, u16 port); 483 void irdma_del_apbvt(struct irdma_device *iwdev, 484 struct irdma_apbvt_entry *entry); 485 struct irdma_cqp_request *irdma_alloc_and_get_cqp_request(struct irdma_cqp *cqp, 486 bool wait); 487 void irdma_free_cqp_request(struct irdma_cqp *cqp, 488 struct irdma_cqp_request *cqp_request); 489 void irdma_put_cqp_request(struct irdma_cqp *cqp, 490 struct irdma_cqp_request *cqp_request); 491 int irdma_alloc_local_mac_entry(struct irdma_pci_f *rf, u16 *mac_tbl_idx); 492 int irdma_add_local_mac_entry(struct irdma_pci_f *rf, const u8 *mac_addr, u16 idx); 493 void irdma_del_local_mac_entry(struct irdma_pci_f *rf, u16 idx); 494 495 u32 irdma_initialize_hw_rsrc(struct irdma_pci_f *rf); 496 void irdma_port_ibevent(struct irdma_device *iwdev); 497 void irdma_cm_disconn(struct irdma_qp *qp); 498 499 bool irdma_cqp_crit_err(struct irdma_sc_dev *dev, u8 cqp_cmd, 500 u16 maj_err_code, u16 min_err_code); 501 int irdma_handle_cqp_op(struct irdma_pci_f *rf, 502 struct irdma_cqp_request *cqp_request); 503 504 int irdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask, 505 struct ib_udata *udata); 506 int irdma_modify_qp_roce(struct ib_qp *ibqp, struct ib_qp_attr *attr, 507 int attr_mask, struct ib_udata *udata); 508 void irdma_cq_add_ref(struct ib_cq *ibcq); 509 void irdma_cq_rem_ref(struct ib_cq *ibcq); 510 void irdma_cq_wq_destroy(struct irdma_pci_f *rf, struct irdma_sc_cq *cq); 511 512 void irdma_cleanup_pending_cqp_op(struct irdma_pci_f *rf); 513 int irdma_hw_modify_qp(struct irdma_device *iwdev, struct irdma_qp *iwqp, 514 struct irdma_modify_qp_info *info, bool wait); 515 int irdma_qp_suspend_resume(struct irdma_sc_qp *qp, bool suspend); 516 int irdma_manage_qhash(struct irdma_device *iwdev, struct irdma_cm_info *cminfo, 517 enum irdma_quad_entry_type etype, 518 enum irdma_quad_hash_manage_type mtype, void *cmnode, 519 bool wait); 520 void irdma_receive_ilq(struct irdma_sc_vsi *vsi, struct irdma_puda_buf *rbuf); 521 void irdma_free_sqbuf(struct irdma_sc_vsi *vsi, void *bufp); 522 void irdma_free_qp_rsrc(struct irdma_qp *iwqp); 523 int irdma_setup_cm_core(struct irdma_device *iwdev, u8 ver); 524 void irdma_cleanup_cm_core(struct irdma_cm_core *cm_core); 525 void irdma_next_iw_state(struct irdma_qp *iwqp, u8 state, u8 del_hash, u8 term, 526 u8 term_len); 527 int irdma_send_syn(struct irdma_cm_node *cm_node, u32 sendack); 528 int irdma_send_reset(struct irdma_cm_node *cm_node); 529 struct irdma_cm_node *irdma_find_node(struct irdma_cm_core *cm_core, 530 u16 rem_port, u32 *rem_addr, u16 loc_port, 531 u32 *loc_addr, u16 vlan_id); 532 int irdma_hw_flush_wqes(struct irdma_pci_f *rf, struct irdma_sc_qp *qp, 533 struct irdma_qp_flush_info *info, bool wait); 534 void irdma_gen_ae(struct irdma_pci_f *rf, struct irdma_sc_qp *qp, 535 struct irdma_gen_ae_info *info, bool wait); 536 void irdma_copy_ip_ntohl(u32 *dst, __be32 *src); 537 void irdma_copy_ip_htonl(__be32 *dst, u32 *src); 538 u16 irdma_get_vlan_ipv4(u32 *addr); 539 void irdma_get_vlan_mac_ipv6(u32 *addr, u16 *vlan_id, u8 *mac); 540 struct ib_mr *irdma_reg_phys_mr(struct ib_pd *ib_pd, u64 addr, u64 size, 541 int acc, u64 *iova_start); 542 int irdma_upload_qp_context(struct irdma_qp *iwqp, bool freeze, bool raw); 543 void irdma_cqp_ce_handler(struct irdma_pci_f *rf, struct irdma_sc_cq *cq); 544 int irdma_ah_cqp_op(struct irdma_pci_f *rf, struct irdma_sc_ah *sc_ah, u8 cmd, 545 bool wait, 546 void (*callback_fcn)(struct irdma_cqp_request *cqp_request), 547 void *cb_param); 548 void irdma_gsi_ud_qp_ah_cb(struct irdma_cqp_request *cqp_request); 549 bool irdma_cq_empty(struct irdma_cq *iwcq); 550 int irdma_inetaddr_event(struct notifier_block *notifier, unsigned long event, 551 void *ptr); 552 int irdma_inet6addr_event(struct notifier_block *notifier, unsigned long event, 553 void *ptr); 554 int irdma_net_event(struct notifier_block *notifier, unsigned long event, 555 void *ptr); 556 int irdma_netdevice_event(struct notifier_block *notifier, unsigned long event, 557 void *ptr); 558 void irdma_add_ip(struct irdma_device *iwdev); 559 void cqp_compl_worker(struct work_struct *work); 560 #endif /* IRDMA_MAIN_H */ 561