1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* Copyright (c) 2015 - 2021 Intel Corporation */ 3 #include "main.h" 4 5 static struct irdma_rsrc_limits rsrc_limits_table[] = { 6 [0] = { 7 .qplimit = SZ_128, 8 }, 9 [1] = { 10 .qplimit = SZ_1K, 11 }, 12 [2] = { 13 .qplimit = SZ_2K, 14 }, 15 [3] = { 16 .qplimit = SZ_4K, 17 }, 18 [4] = { 19 .qplimit = SZ_16K, 20 }, 21 [5] = { 22 .qplimit = SZ_64K, 23 }, 24 [6] = { 25 .qplimit = SZ_128K, 26 }, 27 [7] = { 28 .qplimit = SZ_256K, 29 }, 30 }; 31 32 /* types of hmc objects */ 33 static enum irdma_hmc_rsrc_type iw_hmc_obj_types[] = { 34 IRDMA_HMC_IW_QP, 35 IRDMA_HMC_IW_CQ, 36 IRDMA_HMC_IW_HTE, 37 IRDMA_HMC_IW_ARP, 38 IRDMA_HMC_IW_APBVT_ENTRY, 39 IRDMA_HMC_IW_MR, 40 IRDMA_HMC_IW_XF, 41 IRDMA_HMC_IW_XFFL, 42 IRDMA_HMC_IW_Q1, 43 IRDMA_HMC_IW_Q1FL, 44 IRDMA_HMC_IW_PBLE, 45 IRDMA_HMC_IW_TIMER, 46 IRDMA_HMC_IW_FSIMC, 47 IRDMA_HMC_IW_FSIAV, 48 IRDMA_HMC_IW_RRF, 49 IRDMA_HMC_IW_RRFFL, 50 IRDMA_HMC_IW_HDR, 51 IRDMA_HMC_IW_MD, 52 IRDMA_HMC_IW_OOISC, 53 IRDMA_HMC_IW_OOISCFFL, 54 }; 55 56 /** 57 * irdma_iwarp_ce_handler - handle iwarp completions 58 * @iwcq: iwarp cq receiving event 59 */ 60 static void irdma_iwarp_ce_handler(struct irdma_sc_cq *iwcq) 61 { 62 struct irdma_cq *cq = iwcq->back_cq; 63 64 if (!cq->user_mode) 65 atomic_set(&cq->armed, 0); 66 if (cq->ibcq.comp_handler) 67 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context); 68 } 69 70 /** 71 * irdma_puda_ce_handler - handle puda completion events 72 * @rf: RDMA PCI function 73 * @cq: puda completion q for event 74 */ 75 static void irdma_puda_ce_handler(struct irdma_pci_f *rf, 76 struct irdma_sc_cq *cq) 77 { 78 struct irdma_sc_dev *dev = &rf->sc_dev; 79 u32 compl_error; 80 int status; 81 82 do { 83 status = irdma_puda_poll_cmpl(dev, cq, &compl_error); 84 if (status == -ENOENT) 85 break; 86 if (status) { 87 ibdev_dbg(to_ibdev(dev), "ERR: puda status = %d\n", status); 88 break; 89 } 90 if (compl_error) { 91 ibdev_dbg(to_ibdev(dev), "ERR: puda compl_err =0x%x\n", 92 compl_error); 93 break; 94 } 95 } while (1); 96 97 irdma_sc_ccq_arm(cq); 98 } 99 100 /** 101 * irdma_process_ceq - handle ceq for completions 102 * @rf: RDMA PCI function 103 * @ceq: ceq having cq for completion 104 */ 105 static void irdma_process_ceq(struct irdma_pci_f *rf, struct irdma_ceq *ceq) 106 { 107 struct irdma_sc_dev *dev = &rf->sc_dev; 108 struct irdma_sc_ceq *sc_ceq; 109 struct irdma_sc_cq *cq; 110 unsigned long flags; 111 112 sc_ceq = &ceq->sc_ceq; 113 do { 114 spin_lock_irqsave(&ceq->ce_lock, flags); 115 cq = irdma_sc_process_ceq(dev, sc_ceq); 116 if (!cq) { 117 spin_unlock_irqrestore(&ceq->ce_lock, flags); 118 break; 119 } 120 121 if (cq->cq_type == IRDMA_CQ_TYPE_IWARP) 122 irdma_iwarp_ce_handler(cq); 123 124 spin_unlock_irqrestore(&ceq->ce_lock, flags); 125 126 if (cq->cq_type == IRDMA_CQ_TYPE_CQP) 127 queue_work(rf->cqp_cmpl_wq, &rf->cqp_cmpl_work); 128 else if (cq->cq_type == IRDMA_CQ_TYPE_ILQ || 129 cq->cq_type == IRDMA_CQ_TYPE_IEQ) 130 irdma_puda_ce_handler(rf, cq); 131 } while (1); 132 } 133 134 static void irdma_set_flush_fields(struct irdma_sc_qp *qp, 135 struct irdma_aeqe_info *info) 136 { 137 qp->sq_flush_code = info->sq; 138 qp->rq_flush_code = info->rq; 139 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 140 141 switch (info->ae_id) { 142 case IRDMA_AE_AMP_BOUNDS_VIOLATION: 143 case IRDMA_AE_AMP_INVALID_STAG: 144 case IRDMA_AE_AMP_RIGHTS_VIOLATION: 145 case IRDMA_AE_AMP_UNALLOCATED_STAG: 146 case IRDMA_AE_AMP_BAD_PD: 147 case IRDMA_AE_AMP_BAD_QP: 148 case IRDMA_AE_AMP_BAD_STAG_KEY: 149 case IRDMA_AE_AMP_BAD_STAG_INDEX: 150 case IRDMA_AE_AMP_TO_WRAP: 151 case IRDMA_AE_PRIV_OPERATION_DENIED: 152 qp->flush_code = FLUSH_PROT_ERR; 153 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 154 break; 155 case IRDMA_AE_UDA_XMIT_BAD_PD: 156 case IRDMA_AE_WQE_UNEXPECTED_OPCODE: 157 qp->flush_code = FLUSH_LOC_QP_OP_ERR; 158 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 159 break; 160 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG: 161 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT: 162 case IRDMA_AE_UDA_L4LEN_INVALID: 163 case IRDMA_AE_DDP_UBE_INVALID_MO: 164 case IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER: 165 qp->flush_code = FLUSH_LOC_LEN_ERR; 166 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 167 break; 168 case IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS: 169 case IRDMA_AE_IB_REMOTE_ACCESS_ERROR: 170 qp->flush_code = FLUSH_REM_ACCESS_ERR; 171 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 172 break; 173 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL: 174 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR: 175 case IRDMA_AE_ROCE_RSP_LENGTH_ERROR: 176 case IRDMA_AE_IB_REMOTE_OP_ERROR: 177 qp->flush_code = FLUSH_REM_OP_ERR; 178 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 179 break; 180 case IRDMA_AE_LCE_QP_CATASTROPHIC: 181 qp->flush_code = FLUSH_FATAL_ERR; 182 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 183 break; 184 case IRDMA_AE_IB_RREQ_AND_Q1_FULL: 185 qp->flush_code = FLUSH_GENERAL_ERR; 186 break; 187 case IRDMA_AE_LLP_TOO_MANY_RETRIES: 188 qp->flush_code = FLUSH_RETRY_EXC_ERR; 189 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 190 break; 191 case IRDMA_AE_AMP_MWBIND_INVALID_RIGHTS: 192 case IRDMA_AE_AMP_MWBIND_BIND_DISABLED: 193 case IRDMA_AE_AMP_MWBIND_INVALID_BOUNDS: 194 case IRDMA_AE_AMP_MWBIND_VALID_STAG: 195 qp->flush_code = FLUSH_MW_BIND_ERR; 196 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; 197 break; 198 case IRDMA_AE_IB_INVALID_REQUEST: 199 qp->flush_code = FLUSH_REM_INV_REQ_ERR; 200 qp->event_type = IRDMA_QP_EVENT_REQ_ERR; 201 break; 202 default: 203 qp->flush_code = FLUSH_GENERAL_ERR; 204 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; 205 break; 206 } 207 } 208 209 /** 210 * irdma_process_aeq - handle aeq events 211 * @rf: RDMA PCI function 212 */ 213 static void irdma_process_aeq(struct irdma_pci_f *rf) 214 { 215 struct irdma_sc_dev *dev = &rf->sc_dev; 216 struct irdma_aeq *aeq = &rf->aeq; 217 struct irdma_sc_aeq *sc_aeq = &aeq->sc_aeq; 218 struct irdma_aeqe_info aeinfo; 219 struct irdma_aeqe_info *info = &aeinfo; 220 int ret; 221 struct irdma_qp *iwqp = NULL; 222 struct irdma_cq *iwcq = NULL; 223 struct irdma_sc_qp *qp = NULL; 224 struct irdma_qp_host_ctx_info *ctx_info = NULL; 225 struct irdma_device *iwdev = rf->iwdev; 226 unsigned long flags; 227 228 u32 aeqcnt = 0; 229 230 if (!sc_aeq->size) 231 return; 232 233 do { 234 memset(info, 0, sizeof(*info)); 235 ret = irdma_sc_get_next_aeqe(sc_aeq, info); 236 if (ret) 237 break; 238 239 aeqcnt++; 240 ibdev_dbg(&iwdev->ibdev, 241 "AEQ: ae_id = 0x%x bool qp=%d qp_id = %d tcp_state=%d iwarp_state=%d ae_src=%d\n", 242 info->ae_id, info->qp, info->qp_cq_id, info->tcp_state, 243 info->iwarp_state, info->ae_src); 244 245 if (info->qp) { 246 spin_lock_irqsave(&rf->qptable_lock, flags); 247 iwqp = rf->qp_table[info->qp_cq_id]; 248 if (!iwqp) { 249 spin_unlock_irqrestore(&rf->qptable_lock, 250 flags); 251 if (info->ae_id == IRDMA_AE_QP_SUSPEND_COMPLETE) { 252 atomic_dec(&iwdev->vsi.qp_suspend_reqs); 253 wake_up(&iwdev->suspend_wq); 254 continue; 255 } 256 ibdev_dbg(&iwdev->ibdev, "AEQ: qp_id %d is already freed\n", 257 info->qp_cq_id); 258 continue; 259 } 260 irdma_qp_add_ref(&iwqp->ibqp); 261 spin_unlock_irqrestore(&rf->qptable_lock, flags); 262 qp = &iwqp->sc_qp; 263 spin_lock_irqsave(&iwqp->lock, flags); 264 iwqp->hw_tcp_state = info->tcp_state; 265 iwqp->hw_iwarp_state = info->iwarp_state; 266 if (info->ae_id != IRDMA_AE_QP_SUSPEND_COMPLETE) 267 iwqp->last_aeq = info->ae_id; 268 spin_unlock_irqrestore(&iwqp->lock, flags); 269 ctx_info = &iwqp->ctx_info; 270 } else { 271 if (info->ae_id != IRDMA_AE_CQ_OPERATION_ERROR) 272 continue; 273 } 274 275 switch (info->ae_id) { 276 struct irdma_cm_node *cm_node; 277 case IRDMA_AE_LLP_CONNECTION_ESTABLISHED: 278 cm_node = iwqp->cm_node; 279 if (cm_node->accept_pend) { 280 atomic_dec(&cm_node->listener->pend_accepts_cnt); 281 cm_node->accept_pend = 0; 282 } 283 iwqp->rts_ae_rcvd = 1; 284 wake_up_interruptible(&iwqp->waitq); 285 break; 286 case IRDMA_AE_LLP_FIN_RECEIVED: 287 case IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE: 288 if (qp->term_flags) 289 break; 290 if (atomic_inc_return(&iwqp->close_timer_started) == 1) { 291 iwqp->hw_tcp_state = IRDMA_TCP_STATE_CLOSE_WAIT; 292 if (iwqp->hw_tcp_state == IRDMA_TCP_STATE_CLOSE_WAIT && 293 iwqp->ibqp_state == IB_QPS_RTS) { 294 irdma_next_iw_state(iwqp, 295 IRDMA_QP_STATE_CLOSING, 296 0, 0, 0); 297 irdma_cm_disconn(iwqp); 298 } 299 irdma_schedule_cm_timer(iwqp->cm_node, 300 (struct irdma_puda_buf *)iwqp, 301 IRDMA_TIMER_TYPE_CLOSE, 302 1, 0); 303 } 304 break; 305 case IRDMA_AE_LLP_CLOSE_COMPLETE: 306 if (qp->term_flags) 307 irdma_terminate_done(qp, 0); 308 else 309 irdma_cm_disconn(iwqp); 310 break; 311 case IRDMA_AE_BAD_CLOSE: 312 case IRDMA_AE_RESET_SENT: 313 irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, 1, 0, 314 0); 315 irdma_cm_disconn(iwqp); 316 break; 317 case IRDMA_AE_LLP_CONNECTION_RESET: 318 if (atomic_read(&iwqp->close_timer_started)) 319 break; 320 irdma_cm_disconn(iwqp); 321 break; 322 case IRDMA_AE_QP_SUSPEND_COMPLETE: 323 if (iwqp->iwdev->vsi.tc_change_pending) { 324 if (!atomic_dec_return(&qp->vsi->qp_suspend_reqs)) 325 wake_up(&iwqp->iwdev->suspend_wq); 326 } 327 if (iwqp->suspend_pending) { 328 iwqp->suspend_pending = false; 329 wake_up(&iwqp->iwdev->suspend_wq); 330 } 331 break; 332 case IRDMA_AE_TERMINATE_SENT: 333 irdma_terminate_send_fin(qp); 334 break; 335 case IRDMA_AE_LLP_TERMINATE_RECEIVED: 336 irdma_terminate_received(qp, info); 337 break; 338 case IRDMA_AE_CQ_OPERATION_ERROR: 339 ibdev_err(&iwdev->ibdev, 340 "Processing an iWARP related AE for CQ misc = 0x%04X\n", 341 info->ae_id); 342 343 spin_lock_irqsave(&rf->cqtable_lock, flags); 344 iwcq = rf->cq_table[info->qp_cq_id]; 345 if (!iwcq) { 346 spin_unlock_irqrestore(&rf->cqtable_lock, 347 flags); 348 ibdev_dbg(to_ibdev(dev), 349 "cq_id %d is already freed\n", info->qp_cq_id); 350 continue; 351 } 352 irdma_cq_add_ref(&iwcq->ibcq); 353 spin_unlock_irqrestore(&rf->cqtable_lock, flags); 354 355 if (iwcq->ibcq.event_handler) { 356 struct ib_event ibevent; 357 358 ibevent.device = iwcq->ibcq.device; 359 ibevent.event = IB_EVENT_CQ_ERR; 360 ibevent.element.cq = &iwcq->ibcq; 361 iwcq->ibcq.event_handler(&ibevent, 362 iwcq->ibcq.cq_context); 363 } 364 irdma_cq_rem_ref(&iwcq->ibcq); 365 break; 366 case IRDMA_AE_RESET_NOT_SENT: 367 case IRDMA_AE_LLP_DOUBT_REACHABILITY: 368 case IRDMA_AE_RESOURCE_EXHAUSTION: 369 break; 370 case IRDMA_AE_PRIV_OPERATION_DENIED: 371 case IRDMA_AE_STAG_ZERO_INVALID: 372 case IRDMA_AE_IB_RREQ_AND_Q1_FULL: 373 case IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION: 374 case IRDMA_AE_DDP_UBE_INVALID_MO: 375 case IRDMA_AE_DDP_UBE_INVALID_QN: 376 case IRDMA_AE_DDP_NO_L_BIT: 377 case IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION: 378 case IRDMA_AE_RDMAP_ROE_UNEXPECTED_OPCODE: 379 case IRDMA_AE_ROE_INVALID_RDMA_READ_REQUEST: 380 case IRDMA_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP: 381 case IRDMA_AE_INVALID_ARP_ENTRY: 382 case IRDMA_AE_INVALID_TCP_OPTION_RCVD: 383 case IRDMA_AE_STALE_ARP_ENTRY: 384 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR: 385 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL: 386 case IRDMA_AE_LLP_SYN_RECEIVED: 387 case IRDMA_AE_LLP_TOO_MANY_RETRIES: 388 case IRDMA_AE_LCE_QP_CATASTROPHIC: 389 case IRDMA_AE_LCE_FUNCTION_CATASTROPHIC: 390 case IRDMA_AE_LLP_TOO_MANY_RNRS: 391 case IRDMA_AE_LCE_CQ_CATASTROPHIC: 392 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG: 393 default: 394 ibdev_err(&iwdev->ibdev, "abnormal ae_id = 0x%x bool qp=%d qp_id = %d, ae_src=%d\n", 395 info->ae_id, info->qp, info->qp_cq_id, info->ae_src); 396 if (rdma_protocol_roce(&iwdev->ibdev, 1)) { 397 ctx_info->roce_info->err_rq_idx_valid = info->rq; 398 if (info->rq) { 399 ctx_info->roce_info->err_rq_idx = info->wqe_idx; 400 irdma_sc_qp_setctx_roce(&iwqp->sc_qp, iwqp->host_ctx.va, 401 ctx_info); 402 } 403 irdma_set_flush_fields(qp, info); 404 irdma_cm_disconn(iwqp); 405 break; 406 } 407 ctx_info->iwarp_info->err_rq_idx_valid = info->rq; 408 if (info->rq) { 409 ctx_info->iwarp_info->err_rq_idx = info->wqe_idx; 410 ctx_info->tcp_info_valid = false; 411 ctx_info->iwarp_info_valid = true; 412 irdma_sc_qp_setctx(&iwqp->sc_qp, iwqp->host_ctx.va, 413 ctx_info); 414 } 415 if (iwqp->hw_iwarp_state != IRDMA_QP_STATE_RTS && 416 iwqp->hw_iwarp_state != IRDMA_QP_STATE_TERMINATE) { 417 irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, 1, 0, 0); 418 irdma_cm_disconn(iwqp); 419 } else { 420 irdma_terminate_connection(qp, info); 421 } 422 break; 423 } 424 if (info->qp) 425 irdma_qp_rem_ref(&iwqp->ibqp); 426 } while (1); 427 428 if (aeqcnt) 429 irdma_sc_repost_aeq_entries(dev, aeqcnt); 430 } 431 432 /** 433 * irdma_ena_intr - set up device interrupts 434 * @dev: hardware control device structure 435 * @msix_id: id of the interrupt to be enabled 436 */ 437 static void irdma_ena_intr(struct irdma_sc_dev *dev, u32 msix_id) 438 { 439 dev->irq_ops->irdma_en_irq(dev, msix_id); 440 } 441 442 /** 443 * irdma_dpc - tasklet for aeq and ceq 0 444 * @t: tasklet_struct ptr 445 */ 446 static void irdma_dpc(struct tasklet_struct *t) 447 { 448 struct irdma_pci_f *rf = from_tasklet(rf, t, dpc_tasklet); 449 450 if (rf->msix_shared) 451 irdma_process_ceq(rf, rf->ceqlist); 452 irdma_process_aeq(rf); 453 irdma_ena_intr(&rf->sc_dev, rf->iw_msixtbl[0].idx); 454 } 455 456 /** 457 * irdma_ceq_dpc - dpc handler for CEQ 458 * @t: tasklet_struct ptr 459 */ 460 static void irdma_ceq_dpc(struct tasklet_struct *t) 461 { 462 struct irdma_ceq *iwceq = from_tasklet(iwceq, t, dpc_tasklet); 463 struct irdma_pci_f *rf = iwceq->rf; 464 465 irdma_process_ceq(rf, iwceq); 466 irdma_ena_intr(&rf->sc_dev, iwceq->msix_idx); 467 } 468 469 /** 470 * irdma_save_msix_info - copy msix vector information to iwarp device 471 * @rf: RDMA PCI function 472 * 473 * Allocate iwdev msix table and copy the msix info to the table 474 * Return 0 if successful, otherwise return error 475 */ 476 static int irdma_save_msix_info(struct irdma_pci_f *rf) 477 { 478 struct irdma_qvlist_info *iw_qvlist; 479 struct irdma_qv_info *iw_qvinfo; 480 struct msix_entry *pmsix; 481 u32 ceq_idx; 482 u32 i; 483 size_t size; 484 485 if (!rf->msix_count) 486 return -EINVAL; 487 488 size = sizeof(struct irdma_msix_vector) * rf->msix_count; 489 size += struct_size(iw_qvlist, qv_info, rf->msix_count); 490 rf->iw_msixtbl = kzalloc(size, GFP_KERNEL); 491 if (!rf->iw_msixtbl) 492 return -ENOMEM; 493 494 rf->iw_qvlist = (struct irdma_qvlist_info *) 495 (&rf->iw_msixtbl[rf->msix_count]); 496 iw_qvlist = rf->iw_qvlist; 497 iw_qvinfo = iw_qvlist->qv_info; 498 iw_qvlist->num_vectors = rf->msix_count; 499 if (rf->msix_count <= num_online_cpus()) 500 rf->msix_shared = true; 501 502 pmsix = rf->msix_entries; 503 for (i = 0, ceq_idx = 0; i < rf->msix_count; i++, iw_qvinfo++) { 504 rf->iw_msixtbl[i].idx = pmsix->entry; 505 rf->iw_msixtbl[i].irq = pmsix->vector; 506 rf->iw_msixtbl[i].cpu_affinity = ceq_idx; 507 if (!i) { 508 iw_qvinfo->aeq_idx = 0; 509 if (rf->msix_shared) 510 iw_qvinfo->ceq_idx = ceq_idx++; 511 else 512 iw_qvinfo->ceq_idx = IRDMA_Q_INVALID_IDX; 513 } else { 514 iw_qvinfo->aeq_idx = IRDMA_Q_INVALID_IDX; 515 iw_qvinfo->ceq_idx = ceq_idx++; 516 } 517 iw_qvinfo->itr_idx = 3; 518 iw_qvinfo->v_idx = rf->iw_msixtbl[i].idx; 519 pmsix++; 520 } 521 522 return 0; 523 } 524 525 /** 526 * irdma_irq_handler - interrupt handler for aeq and ceq0 527 * @irq: Interrupt request number 528 * @data: RDMA PCI function 529 */ 530 static irqreturn_t irdma_irq_handler(int irq, void *data) 531 { 532 struct irdma_pci_f *rf = data; 533 534 tasklet_schedule(&rf->dpc_tasklet); 535 536 return IRQ_HANDLED; 537 } 538 539 /** 540 * irdma_ceq_handler - interrupt handler for ceq 541 * @irq: interrupt request number 542 * @data: ceq pointer 543 */ 544 static irqreturn_t irdma_ceq_handler(int irq, void *data) 545 { 546 struct irdma_ceq *iwceq = data; 547 548 if (iwceq->irq != irq) 549 ibdev_err(to_ibdev(&iwceq->rf->sc_dev), "expected irq = %d received irq = %d\n", 550 iwceq->irq, irq); 551 tasklet_schedule(&iwceq->dpc_tasklet); 552 553 return IRQ_HANDLED; 554 } 555 556 /** 557 * irdma_destroy_irq - destroy device interrupts 558 * @rf: RDMA PCI function 559 * @msix_vec: msix vector to disable irq 560 * @dev_id: parameter to pass to free_irq (used during irq setup) 561 * 562 * The function is called when destroying aeq/ceq 563 */ 564 static void irdma_destroy_irq(struct irdma_pci_f *rf, 565 struct irdma_msix_vector *msix_vec, void *dev_id) 566 { 567 struct irdma_sc_dev *dev = &rf->sc_dev; 568 569 dev->irq_ops->irdma_dis_irq(dev, msix_vec->idx); 570 irq_update_affinity_hint(msix_vec->irq, NULL); 571 free_irq(msix_vec->irq, dev_id); 572 if (rf == dev_id) { 573 tasklet_kill(&rf->dpc_tasklet); 574 } else { 575 struct irdma_ceq *iwceq = (struct irdma_ceq *)dev_id; 576 577 tasklet_kill(&iwceq->dpc_tasklet); 578 } 579 } 580 581 /** 582 * irdma_destroy_cqp - destroy control qp 583 * @rf: RDMA PCI function 584 * 585 * Issue destroy cqp request and 586 * free the resources associated with the cqp 587 */ 588 static void irdma_destroy_cqp(struct irdma_pci_f *rf) 589 { 590 struct irdma_sc_dev *dev = &rf->sc_dev; 591 struct irdma_cqp *cqp = &rf->cqp; 592 int status = 0; 593 594 status = irdma_sc_cqp_destroy(dev->cqp); 595 if (status) 596 ibdev_dbg(to_ibdev(dev), "ERR: Destroy CQP failed %d\n", status); 597 598 irdma_cleanup_pending_cqp_op(rf); 599 dma_free_coherent(dev->hw->device, cqp->sq.size, cqp->sq.va, 600 cqp->sq.pa); 601 cqp->sq.va = NULL; 602 kfree(cqp->scratch_array); 603 cqp->scratch_array = NULL; 604 kfree(cqp->cqp_requests); 605 cqp->cqp_requests = NULL; 606 } 607 608 static void irdma_destroy_virt_aeq(struct irdma_pci_f *rf) 609 { 610 struct irdma_aeq *aeq = &rf->aeq; 611 u32 pg_cnt = DIV_ROUND_UP(aeq->mem.size, PAGE_SIZE); 612 dma_addr_t *pg_arr = (dma_addr_t *)aeq->palloc.level1.addr; 613 614 irdma_unmap_vm_page_list(&rf->hw, pg_arr, pg_cnt); 615 irdma_free_pble(rf->pble_rsrc, &aeq->palloc); 616 vfree(aeq->mem.va); 617 } 618 619 /** 620 * irdma_destroy_aeq - destroy aeq 621 * @rf: RDMA PCI function 622 * 623 * Issue a destroy aeq request and 624 * free the resources associated with the aeq 625 * The function is called during driver unload 626 */ 627 static void irdma_destroy_aeq(struct irdma_pci_f *rf) 628 { 629 struct irdma_sc_dev *dev = &rf->sc_dev; 630 struct irdma_aeq *aeq = &rf->aeq; 631 int status = -EBUSY; 632 633 if (!rf->msix_shared) { 634 rf->sc_dev.irq_ops->irdma_cfg_aeq(&rf->sc_dev, rf->iw_msixtbl->idx, false); 635 irdma_destroy_irq(rf, rf->iw_msixtbl, rf); 636 } 637 if (rf->reset) 638 goto exit; 639 640 aeq->sc_aeq.size = 0; 641 status = irdma_cqp_aeq_cmd(dev, &aeq->sc_aeq, IRDMA_OP_AEQ_DESTROY); 642 if (status) 643 ibdev_dbg(to_ibdev(dev), "ERR: Destroy AEQ failed %d\n", status); 644 645 exit: 646 if (aeq->virtual_map) { 647 irdma_destroy_virt_aeq(rf); 648 } else { 649 dma_free_coherent(dev->hw->device, aeq->mem.size, aeq->mem.va, 650 aeq->mem.pa); 651 aeq->mem.va = NULL; 652 } 653 } 654 655 /** 656 * irdma_destroy_ceq - destroy ceq 657 * @rf: RDMA PCI function 658 * @iwceq: ceq to be destroyed 659 * 660 * Issue a destroy ceq request and 661 * free the resources associated with the ceq 662 */ 663 static void irdma_destroy_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq) 664 { 665 struct irdma_sc_dev *dev = &rf->sc_dev; 666 int status; 667 668 if (rf->reset) 669 goto exit; 670 671 status = irdma_sc_ceq_destroy(&iwceq->sc_ceq, 0, 1); 672 if (status) { 673 ibdev_dbg(to_ibdev(dev), "ERR: CEQ destroy command failed %d\n", status); 674 goto exit; 675 } 676 677 status = irdma_sc_cceq_destroy_done(&iwceq->sc_ceq); 678 if (status) 679 ibdev_dbg(to_ibdev(dev), "ERR: CEQ destroy completion failed %d\n", 680 status); 681 exit: 682 dma_free_coherent(dev->hw->device, iwceq->mem.size, iwceq->mem.va, 683 iwceq->mem.pa); 684 iwceq->mem.va = NULL; 685 } 686 687 /** 688 * irdma_del_ceq_0 - destroy ceq 0 689 * @rf: RDMA PCI function 690 * 691 * Disable the ceq 0 interrupt and destroy the ceq 0 692 */ 693 static void irdma_del_ceq_0(struct irdma_pci_f *rf) 694 { 695 struct irdma_ceq *iwceq = rf->ceqlist; 696 struct irdma_msix_vector *msix_vec; 697 698 if (rf->msix_shared) { 699 msix_vec = &rf->iw_msixtbl[0]; 700 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, 701 msix_vec->ceq_id, 702 msix_vec->idx, false); 703 irdma_destroy_irq(rf, msix_vec, rf); 704 } else { 705 msix_vec = &rf->iw_msixtbl[1]; 706 irdma_destroy_irq(rf, msix_vec, iwceq); 707 } 708 709 irdma_destroy_ceq(rf, iwceq); 710 rf->sc_dev.ceq_valid = false; 711 rf->ceqs_count = 0; 712 } 713 714 /** 715 * irdma_del_ceqs - destroy all ceq's except CEQ 0 716 * @rf: RDMA PCI function 717 * 718 * Go through all of the device ceq's, except 0, and for each 719 * ceq disable the ceq interrupt and destroy the ceq 720 */ 721 static void irdma_del_ceqs(struct irdma_pci_f *rf) 722 { 723 struct irdma_ceq *iwceq = &rf->ceqlist[1]; 724 struct irdma_msix_vector *msix_vec; 725 u32 i = 0; 726 727 if (rf->msix_shared) 728 msix_vec = &rf->iw_msixtbl[1]; 729 else 730 msix_vec = &rf->iw_msixtbl[2]; 731 732 for (i = 1; i < rf->ceqs_count; i++, msix_vec++, iwceq++) { 733 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, msix_vec->ceq_id, 734 msix_vec->idx, false); 735 irdma_destroy_irq(rf, msix_vec, iwceq); 736 irdma_cqp_ceq_cmd(&rf->sc_dev, &iwceq->sc_ceq, 737 IRDMA_OP_CEQ_DESTROY); 738 dma_free_coherent(rf->sc_dev.hw->device, iwceq->mem.size, 739 iwceq->mem.va, iwceq->mem.pa); 740 iwceq->mem.va = NULL; 741 } 742 rf->ceqs_count = 1; 743 } 744 745 /** 746 * irdma_destroy_ccq - destroy control cq 747 * @rf: RDMA PCI function 748 * 749 * Issue destroy ccq request and 750 * free the resources associated with the ccq 751 */ 752 static void irdma_destroy_ccq(struct irdma_pci_f *rf) 753 { 754 struct irdma_sc_dev *dev = &rf->sc_dev; 755 struct irdma_ccq *ccq = &rf->ccq; 756 int status = 0; 757 758 if (rf->cqp_cmpl_wq) 759 destroy_workqueue(rf->cqp_cmpl_wq); 760 761 if (!rf->reset) 762 status = irdma_sc_ccq_destroy(dev->ccq, 0, true); 763 if (status) 764 ibdev_dbg(to_ibdev(dev), "ERR: CCQ destroy failed %d\n", status); 765 dma_free_coherent(dev->hw->device, ccq->mem_cq.size, ccq->mem_cq.va, 766 ccq->mem_cq.pa); 767 ccq->mem_cq.va = NULL; 768 } 769 770 /** 771 * irdma_close_hmc_objects_type - delete hmc objects of a given type 772 * @dev: iwarp device 773 * @obj_type: the hmc object type to be deleted 774 * @hmc_info: host memory info struct 775 * @privileged: permission to close HMC objects 776 * @reset: true if called before reset 777 */ 778 static void irdma_close_hmc_objects_type(struct irdma_sc_dev *dev, 779 enum irdma_hmc_rsrc_type obj_type, 780 struct irdma_hmc_info *hmc_info, 781 bool privileged, bool reset) 782 { 783 struct irdma_hmc_del_obj_info info = {}; 784 785 info.hmc_info = hmc_info; 786 info.rsrc_type = obj_type; 787 info.count = hmc_info->hmc_obj[obj_type].cnt; 788 info.privileged = privileged; 789 if (irdma_sc_del_hmc_obj(dev, &info, reset)) 790 ibdev_dbg(to_ibdev(dev), "ERR: del HMC obj of type %d failed\n", 791 obj_type); 792 } 793 794 /** 795 * irdma_del_hmc_objects - remove all device hmc objects 796 * @dev: iwarp device 797 * @hmc_info: hmc_info to free 798 * @privileged: permission to delete HMC objects 799 * @reset: true if called before reset 800 * @vers: hardware version 801 */ 802 static void irdma_del_hmc_objects(struct irdma_sc_dev *dev, 803 struct irdma_hmc_info *hmc_info, bool privileged, 804 bool reset, enum irdma_vers vers) 805 { 806 unsigned int i; 807 808 for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++) { 809 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) 810 irdma_close_hmc_objects_type(dev, iw_hmc_obj_types[i], 811 hmc_info, privileged, reset); 812 if (vers == IRDMA_GEN_1 && i == IRDMA_HMC_IW_TIMER) 813 break; 814 } 815 } 816 817 /** 818 * irdma_create_hmc_obj_type - create hmc object of a given type 819 * @dev: hardware control device structure 820 * @info: information for the hmc object to create 821 */ 822 static int irdma_create_hmc_obj_type(struct irdma_sc_dev *dev, 823 struct irdma_hmc_create_obj_info *info) 824 { 825 return irdma_sc_create_hmc_obj(dev, info); 826 } 827 828 /** 829 * irdma_create_hmc_objs - create all hmc objects for the device 830 * @rf: RDMA PCI function 831 * @privileged: permission to create HMC objects 832 * @vers: HW version 833 * 834 * Create the device hmc objects and allocate hmc pages 835 * Return 0 if successful, otherwise clean up and return error 836 */ 837 static int irdma_create_hmc_objs(struct irdma_pci_f *rf, bool privileged, 838 enum irdma_vers vers) 839 { 840 struct irdma_sc_dev *dev = &rf->sc_dev; 841 struct irdma_hmc_create_obj_info info = {}; 842 int i, status = 0; 843 844 info.hmc_info = dev->hmc_info; 845 info.privileged = privileged; 846 info.entry_type = rf->sd_type; 847 848 for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++) { 849 if (iw_hmc_obj_types[i] == IRDMA_HMC_IW_PBLE) 850 continue; 851 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) { 852 info.rsrc_type = iw_hmc_obj_types[i]; 853 info.count = dev->hmc_info->hmc_obj[info.rsrc_type].cnt; 854 info.add_sd_cnt = 0; 855 status = irdma_create_hmc_obj_type(dev, &info); 856 if (status) { 857 ibdev_dbg(to_ibdev(dev), 858 "ERR: create obj type %d status = %d\n", 859 iw_hmc_obj_types[i], status); 860 break; 861 } 862 } 863 if (vers == IRDMA_GEN_1 && i == IRDMA_HMC_IW_TIMER) 864 break; 865 } 866 867 if (!status) 868 return irdma_sc_static_hmc_pages_allocated(dev->cqp, 0, dev->hmc_fn_id, 869 true, true); 870 871 while (i) { 872 i--; 873 /* destroy the hmc objects of a given type */ 874 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) 875 irdma_close_hmc_objects_type(dev, iw_hmc_obj_types[i], 876 dev->hmc_info, privileged, 877 false); 878 } 879 880 return status; 881 } 882 883 /** 884 * irdma_obj_aligned_mem - get aligned memory from device allocated memory 885 * @rf: RDMA PCI function 886 * @memptr: points to the memory addresses 887 * @size: size of memory needed 888 * @mask: mask for the aligned memory 889 * 890 * Get aligned memory of the requested size and 891 * update the memptr to point to the new aligned memory 892 * Return 0 if successful, otherwise return no memory error 893 */ 894 static int irdma_obj_aligned_mem(struct irdma_pci_f *rf, 895 struct irdma_dma_mem *memptr, u32 size, 896 u32 mask) 897 { 898 unsigned long va, newva; 899 unsigned long extra; 900 901 va = (unsigned long)rf->obj_next.va; 902 newva = va; 903 if (mask) 904 newva = ALIGN(va, (unsigned long)mask + 1ULL); 905 extra = newva - va; 906 memptr->va = (u8 *)va + extra; 907 memptr->pa = rf->obj_next.pa + extra; 908 memptr->size = size; 909 if (((u8 *)memptr->va + size) > ((u8 *)rf->obj_mem.va + rf->obj_mem.size)) 910 return -ENOMEM; 911 912 rf->obj_next.va = (u8 *)memptr->va + size; 913 rf->obj_next.pa = memptr->pa + size; 914 915 return 0; 916 } 917 918 /** 919 * irdma_create_cqp - create control qp 920 * @rf: RDMA PCI function 921 * 922 * Return 0, if the cqp and all the resources associated with it 923 * are successfully created, otherwise return error 924 */ 925 static int irdma_create_cqp(struct irdma_pci_f *rf) 926 { 927 u32 sqsize = IRDMA_CQP_SW_SQSIZE_2048; 928 struct irdma_dma_mem mem; 929 struct irdma_sc_dev *dev = &rf->sc_dev; 930 struct irdma_cqp_init_info cqp_init_info = {}; 931 struct irdma_cqp *cqp = &rf->cqp; 932 u16 maj_err, min_err; 933 int i, status; 934 935 cqp->cqp_requests = kcalloc(sqsize, sizeof(*cqp->cqp_requests), GFP_KERNEL); 936 if (!cqp->cqp_requests) 937 return -ENOMEM; 938 939 cqp->scratch_array = kcalloc(sqsize, sizeof(*cqp->scratch_array), GFP_KERNEL); 940 if (!cqp->scratch_array) { 941 status = -ENOMEM; 942 goto err_scratch; 943 } 944 945 dev->cqp = &cqp->sc_cqp; 946 dev->cqp->dev = dev; 947 cqp->sq.size = ALIGN(sizeof(struct irdma_cqp_sq_wqe) * sqsize, 948 IRDMA_CQP_ALIGNMENT); 949 cqp->sq.va = dma_alloc_coherent(dev->hw->device, cqp->sq.size, 950 &cqp->sq.pa, GFP_KERNEL); 951 if (!cqp->sq.va) { 952 status = -ENOMEM; 953 goto err_sq; 954 } 955 956 status = irdma_obj_aligned_mem(rf, &mem, sizeof(struct irdma_cqp_ctx), 957 IRDMA_HOST_CTX_ALIGNMENT_M); 958 if (status) 959 goto err_ctx; 960 961 dev->cqp->host_ctx_pa = mem.pa; 962 dev->cqp->host_ctx = mem.va; 963 /* populate the cqp init info */ 964 cqp_init_info.dev = dev; 965 cqp_init_info.sq_size = sqsize; 966 cqp_init_info.sq = cqp->sq.va; 967 cqp_init_info.sq_pa = cqp->sq.pa; 968 cqp_init_info.host_ctx_pa = mem.pa; 969 cqp_init_info.host_ctx = mem.va; 970 cqp_init_info.hmc_profile = rf->rsrc_profile; 971 cqp_init_info.scratch_array = cqp->scratch_array; 972 cqp_init_info.protocol_used = rf->protocol_used; 973 974 switch (rf->rdma_ver) { 975 case IRDMA_GEN_1: 976 cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_1; 977 break; 978 case IRDMA_GEN_2: 979 cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_2; 980 break; 981 } 982 status = irdma_sc_cqp_init(dev->cqp, &cqp_init_info); 983 if (status) { 984 ibdev_dbg(to_ibdev(dev), "ERR: cqp init status %d\n", status); 985 goto err_ctx; 986 } 987 988 spin_lock_init(&cqp->req_lock); 989 spin_lock_init(&cqp->compl_lock); 990 991 status = irdma_sc_cqp_create(dev->cqp, &maj_err, &min_err); 992 if (status) { 993 ibdev_dbg(to_ibdev(dev), 994 "ERR: cqp create failed - status %d maj_err %d min_err %d\n", 995 status, maj_err, min_err); 996 goto err_ctx; 997 } 998 999 INIT_LIST_HEAD(&cqp->cqp_avail_reqs); 1000 INIT_LIST_HEAD(&cqp->cqp_pending_reqs); 1001 1002 /* init the waitqueue of the cqp_requests and add them to the list */ 1003 for (i = 0; i < sqsize; i++) { 1004 init_waitqueue_head(&cqp->cqp_requests[i].waitq); 1005 list_add_tail(&cqp->cqp_requests[i].list, &cqp->cqp_avail_reqs); 1006 } 1007 init_waitqueue_head(&cqp->remove_wq); 1008 return 0; 1009 1010 err_ctx: 1011 dma_free_coherent(dev->hw->device, cqp->sq.size, 1012 cqp->sq.va, cqp->sq.pa); 1013 cqp->sq.va = NULL; 1014 err_sq: 1015 kfree(cqp->scratch_array); 1016 cqp->scratch_array = NULL; 1017 err_scratch: 1018 kfree(cqp->cqp_requests); 1019 cqp->cqp_requests = NULL; 1020 1021 return status; 1022 } 1023 1024 /** 1025 * irdma_create_ccq - create control cq 1026 * @rf: RDMA PCI function 1027 * 1028 * Return 0, if the ccq and the resources associated with it 1029 * are successfully created, otherwise return error 1030 */ 1031 static int irdma_create_ccq(struct irdma_pci_f *rf) 1032 { 1033 struct irdma_sc_dev *dev = &rf->sc_dev; 1034 struct irdma_ccq_init_info info = {}; 1035 struct irdma_ccq *ccq = &rf->ccq; 1036 int status; 1037 1038 dev->ccq = &ccq->sc_cq; 1039 dev->ccq->dev = dev; 1040 info.dev = dev; 1041 ccq->shadow_area.size = sizeof(struct irdma_cq_shadow_area); 1042 ccq->mem_cq.size = ALIGN(sizeof(struct irdma_cqe) * IW_CCQ_SIZE, 1043 IRDMA_CQ0_ALIGNMENT); 1044 ccq->mem_cq.va = dma_alloc_coherent(dev->hw->device, ccq->mem_cq.size, 1045 &ccq->mem_cq.pa, GFP_KERNEL); 1046 if (!ccq->mem_cq.va) 1047 return -ENOMEM; 1048 1049 status = irdma_obj_aligned_mem(rf, &ccq->shadow_area, 1050 ccq->shadow_area.size, 1051 IRDMA_SHADOWAREA_M); 1052 if (status) 1053 goto exit; 1054 1055 ccq->sc_cq.back_cq = ccq; 1056 /* populate the ccq init info */ 1057 info.cq_base = ccq->mem_cq.va; 1058 info.cq_pa = ccq->mem_cq.pa; 1059 info.num_elem = IW_CCQ_SIZE; 1060 info.shadow_area = ccq->shadow_area.va; 1061 info.shadow_area_pa = ccq->shadow_area.pa; 1062 info.ceqe_mask = false; 1063 info.ceq_id_valid = true; 1064 info.shadow_read_threshold = 16; 1065 info.vsi = &rf->default_vsi; 1066 status = irdma_sc_ccq_init(dev->ccq, &info); 1067 if (!status) 1068 status = irdma_sc_ccq_create(dev->ccq, 0, true, true); 1069 exit: 1070 if (status) { 1071 dma_free_coherent(dev->hw->device, ccq->mem_cq.size, 1072 ccq->mem_cq.va, ccq->mem_cq.pa); 1073 ccq->mem_cq.va = NULL; 1074 } 1075 1076 return status; 1077 } 1078 1079 /** 1080 * irdma_alloc_set_mac - set up a mac address table entry 1081 * @iwdev: irdma device 1082 * 1083 * Allocate a mac ip entry and add it to the hw table Return 0 1084 * if successful, otherwise return error 1085 */ 1086 static int irdma_alloc_set_mac(struct irdma_device *iwdev) 1087 { 1088 int status; 1089 1090 status = irdma_alloc_local_mac_entry(iwdev->rf, 1091 &iwdev->mac_ip_table_idx); 1092 if (!status) { 1093 status = irdma_add_local_mac_entry(iwdev->rf, 1094 (const u8 *)iwdev->netdev->dev_addr, 1095 (u8)iwdev->mac_ip_table_idx); 1096 if (status) 1097 irdma_del_local_mac_entry(iwdev->rf, 1098 (u8)iwdev->mac_ip_table_idx); 1099 } 1100 return status; 1101 } 1102 1103 /** 1104 * irdma_cfg_ceq_vector - set up the msix interrupt vector for 1105 * ceq 1106 * @rf: RDMA PCI function 1107 * @iwceq: ceq associated with the vector 1108 * @ceq_id: the id number of the iwceq 1109 * @msix_vec: interrupt vector information 1110 * 1111 * Allocate interrupt resources and enable irq handling 1112 * Return 0 if successful, otherwise return error 1113 */ 1114 static int irdma_cfg_ceq_vector(struct irdma_pci_f *rf, struct irdma_ceq *iwceq, 1115 u32 ceq_id, struct irdma_msix_vector *msix_vec) 1116 { 1117 int status; 1118 1119 if (rf->msix_shared && !ceq_id) { 1120 snprintf(msix_vec->name, sizeof(msix_vec->name) - 1, 1121 "irdma-%s-AEQCEQ-0", dev_name(&rf->pcidev->dev)); 1122 tasklet_setup(&rf->dpc_tasklet, irdma_dpc); 1123 status = request_irq(msix_vec->irq, irdma_irq_handler, 0, 1124 msix_vec->name, rf); 1125 } else { 1126 snprintf(msix_vec->name, sizeof(msix_vec->name) - 1, 1127 "irdma-%s-CEQ-%d", 1128 dev_name(&rf->pcidev->dev), ceq_id); 1129 tasklet_setup(&iwceq->dpc_tasklet, irdma_ceq_dpc); 1130 1131 status = request_irq(msix_vec->irq, irdma_ceq_handler, 0, 1132 msix_vec->name, iwceq); 1133 } 1134 cpumask_clear(&msix_vec->mask); 1135 cpumask_set_cpu(msix_vec->cpu_affinity, &msix_vec->mask); 1136 irq_update_affinity_hint(msix_vec->irq, &msix_vec->mask); 1137 if (status) { 1138 ibdev_dbg(&rf->iwdev->ibdev, "ERR: ceq irq config fail\n"); 1139 return status; 1140 } 1141 1142 msix_vec->ceq_id = ceq_id; 1143 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, ceq_id, msix_vec->idx, true); 1144 1145 return 0; 1146 } 1147 1148 /** 1149 * irdma_cfg_aeq_vector - set up the msix vector for aeq 1150 * @rf: RDMA PCI function 1151 * 1152 * Allocate interrupt resources and enable irq handling 1153 * Return 0 if successful, otherwise return error 1154 */ 1155 static int irdma_cfg_aeq_vector(struct irdma_pci_f *rf) 1156 { 1157 struct irdma_msix_vector *msix_vec = rf->iw_msixtbl; 1158 u32 ret = 0; 1159 1160 if (!rf->msix_shared) { 1161 snprintf(msix_vec->name, sizeof(msix_vec->name) - 1, 1162 "irdma-%s-AEQ", dev_name(&rf->pcidev->dev)); 1163 tasklet_setup(&rf->dpc_tasklet, irdma_dpc); 1164 ret = request_irq(msix_vec->irq, irdma_irq_handler, 0, 1165 msix_vec->name, rf); 1166 } 1167 if (ret) { 1168 ibdev_dbg(&rf->iwdev->ibdev, "ERR: aeq irq config fail\n"); 1169 return -EINVAL; 1170 } 1171 1172 rf->sc_dev.irq_ops->irdma_cfg_aeq(&rf->sc_dev, msix_vec->idx, true); 1173 1174 return 0; 1175 } 1176 1177 /** 1178 * irdma_create_ceq - create completion event queue 1179 * @rf: RDMA PCI function 1180 * @iwceq: pointer to the ceq resources to be created 1181 * @ceq_id: the id number of the iwceq 1182 * @vsi: SC vsi struct 1183 * 1184 * Return 0, if the ceq and the resources associated with it 1185 * are successfully created, otherwise return error 1186 */ 1187 static int irdma_create_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq, 1188 u32 ceq_id, struct irdma_sc_vsi *vsi) 1189 { 1190 int status; 1191 struct irdma_ceq_init_info info = {}; 1192 struct irdma_sc_dev *dev = &rf->sc_dev; 1193 u32 ceq_size; 1194 1195 info.ceq_id = ceq_id; 1196 iwceq->rf = rf; 1197 ceq_size = min(rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt, 1198 dev->hw_attrs.max_hw_ceq_size); 1199 iwceq->mem.size = ALIGN(sizeof(struct irdma_ceqe) * ceq_size, 1200 IRDMA_CEQ_ALIGNMENT); 1201 iwceq->mem.va = dma_alloc_coherent(dev->hw->device, iwceq->mem.size, 1202 &iwceq->mem.pa, GFP_KERNEL); 1203 if (!iwceq->mem.va) 1204 return -ENOMEM; 1205 1206 info.ceq_id = ceq_id; 1207 info.ceqe_base = iwceq->mem.va; 1208 info.ceqe_pa = iwceq->mem.pa; 1209 info.elem_cnt = ceq_size; 1210 iwceq->sc_ceq.ceq_id = ceq_id; 1211 info.dev = dev; 1212 info.vsi = vsi; 1213 status = irdma_sc_ceq_init(&iwceq->sc_ceq, &info); 1214 if (!status) { 1215 if (dev->ceq_valid) 1216 status = irdma_cqp_ceq_cmd(&rf->sc_dev, &iwceq->sc_ceq, 1217 IRDMA_OP_CEQ_CREATE); 1218 else 1219 status = irdma_sc_cceq_create(&iwceq->sc_ceq, 0); 1220 } 1221 1222 if (status) { 1223 dma_free_coherent(dev->hw->device, iwceq->mem.size, 1224 iwceq->mem.va, iwceq->mem.pa); 1225 iwceq->mem.va = NULL; 1226 } 1227 1228 return status; 1229 } 1230 1231 /** 1232 * irdma_setup_ceq_0 - create CEQ 0 and it's interrupt resource 1233 * @rf: RDMA PCI function 1234 * 1235 * Allocate a list for all device completion event queues 1236 * Create the ceq 0 and configure it's msix interrupt vector 1237 * Return 0, if successfully set up, otherwise return error 1238 */ 1239 static int irdma_setup_ceq_0(struct irdma_pci_f *rf) 1240 { 1241 struct irdma_ceq *iwceq; 1242 struct irdma_msix_vector *msix_vec; 1243 u32 i; 1244 int status = 0; 1245 u32 num_ceqs; 1246 1247 num_ceqs = min(rf->msix_count, rf->sc_dev.hmc_fpm_misc.max_ceqs); 1248 rf->ceqlist = kcalloc(num_ceqs, sizeof(*rf->ceqlist), GFP_KERNEL); 1249 if (!rf->ceqlist) { 1250 status = -ENOMEM; 1251 goto exit; 1252 } 1253 1254 iwceq = &rf->ceqlist[0]; 1255 status = irdma_create_ceq(rf, iwceq, 0, &rf->default_vsi); 1256 if (status) { 1257 ibdev_dbg(&rf->iwdev->ibdev, "ERR: create ceq status = %d\n", 1258 status); 1259 goto exit; 1260 } 1261 1262 spin_lock_init(&iwceq->ce_lock); 1263 i = rf->msix_shared ? 0 : 1; 1264 msix_vec = &rf->iw_msixtbl[i]; 1265 iwceq->irq = msix_vec->irq; 1266 iwceq->msix_idx = msix_vec->idx; 1267 status = irdma_cfg_ceq_vector(rf, iwceq, 0, msix_vec); 1268 if (status) { 1269 irdma_destroy_ceq(rf, iwceq); 1270 goto exit; 1271 } 1272 1273 irdma_ena_intr(&rf->sc_dev, msix_vec->idx); 1274 rf->ceqs_count++; 1275 1276 exit: 1277 if (status && !rf->ceqs_count) { 1278 kfree(rf->ceqlist); 1279 rf->ceqlist = NULL; 1280 return status; 1281 } 1282 rf->sc_dev.ceq_valid = true; 1283 1284 return 0; 1285 } 1286 1287 /** 1288 * irdma_setup_ceqs - manage the device ceq's and their interrupt resources 1289 * @rf: RDMA PCI function 1290 * @vsi: VSI structure for this CEQ 1291 * 1292 * Allocate a list for all device completion event queues 1293 * Create the ceq's and configure their msix interrupt vectors 1294 * Return 0, if ceqs are successfully set up, otherwise return error 1295 */ 1296 static int irdma_setup_ceqs(struct irdma_pci_f *rf, struct irdma_sc_vsi *vsi) 1297 { 1298 u32 i; 1299 u32 ceq_id; 1300 struct irdma_ceq *iwceq; 1301 struct irdma_msix_vector *msix_vec; 1302 int status; 1303 u32 num_ceqs; 1304 1305 num_ceqs = min(rf->msix_count, rf->sc_dev.hmc_fpm_misc.max_ceqs); 1306 i = (rf->msix_shared) ? 1 : 2; 1307 for (ceq_id = 1; i < num_ceqs; i++, ceq_id++) { 1308 iwceq = &rf->ceqlist[ceq_id]; 1309 status = irdma_create_ceq(rf, iwceq, ceq_id, vsi); 1310 if (status) { 1311 ibdev_dbg(&rf->iwdev->ibdev, 1312 "ERR: create ceq status = %d\n", status); 1313 goto del_ceqs; 1314 } 1315 spin_lock_init(&iwceq->ce_lock); 1316 msix_vec = &rf->iw_msixtbl[i]; 1317 iwceq->irq = msix_vec->irq; 1318 iwceq->msix_idx = msix_vec->idx; 1319 status = irdma_cfg_ceq_vector(rf, iwceq, ceq_id, msix_vec); 1320 if (status) { 1321 irdma_destroy_ceq(rf, iwceq); 1322 goto del_ceqs; 1323 } 1324 irdma_ena_intr(&rf->sc_dev, msix_vec->idx); 1325 rf->ceqs_count++; 1326 } 1327 1328 return 0; 1329 1330 del_ceqs: 1331 irdma_del_ceqs(rf); 1332 1333 return status; 1334 } 1335 1336 static int irdma_create_virt_aeq(struct irdma_pci_f *rf, u32 size) 1337 { 1338 struct irdma_aeq *aeq = &rf->aeq; 1339 dma_addr_t *pg_arr; 1340 u32 pg_cnt; 1341 int status; 1342 1343 if (rf->rdma_ver < IRDMA_GEN_2) 1344 return -EOPNOTSUPP; 1345 1346 aeq->mem.size = sizeof(struct irdma_sc_aeqe) * size; 1347 aeq->mem.va = vzalloc(aeq->mem.size); 1348 1349 if (!aeq->mem.va) 1350 return -ENOMEM; 1351 1352 pg_cnt = DIV_ROUND_UP(aeq->mem.size, PAGE_SIZE); 1353 status = irdma_get_pble(rf->pble_rsrc, &aeq->palloc, pg_cnt, true); 1354 if (status) { 1355 vfree(aeq->mem.va); 1356 return status; 1357 } 1358 1359 pg_arr = (dma_addr_t *)aeq->palloc.level1.addr; 1360 status = irdma_map_vm_page_list(&rf->hw, aeq->mem.va, pg_arr, pg_cnt); 1361 if (status) { 1362 irdma_free_pble(rf->pble_rsrc, &aeq->palloc); 1363 vfree(aeq->mem.va); 1364 return status; 1365 } 1366 1367 return 0; 1368 } 1369 1370 /** 1371 * irdma_create_aeq - create async event queue 1372 * @rf: RDMA PCI function 1373 * 1374 * Return 0, if the aeq and the resources associated with it 1375 * are successfully created, otherwise return error 1376 */ 1377 static int irdma_create_aeq(struct irdma_pci_f *rf) 1378 { 1379 struct irdma_aeq_init_info info = {}; 1380 struct irdma_sc_dev *dev = &rf->sc_dev; 1381 struct irdma_aeq *aeq = &rf->aeq; 1382 struct irdma_hmc_info *hmc_info = rf->sc_dev.hmc_info; 1383 u32 aeq_size; 1384 u8 multiplier = (rf->protocol_used == IRDMA_IWARP_PROTOCOL_ONLY) ? 2 : 1; 1385 int status; 1386 1387 aeq_size = multiplier * hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt + 1388 hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt; 1389 aeq_size = min(aeq_size, dev->hw_attrs.max_hw_aeq_size); 1390 1391 aeq->mem.size = ALIGN(sizeof(struct irdma_sc_aeqe) * aeq_size, 1392 IRDMA_AEQ_ALIGNMENT); 1393 aeq->mem.va = dma_alloc_coherent(dev->hw->device, aeq->mem.size, 1394 &aeq->mem.pa, 1395 GFP_KERNEL | __GFP_NOWARN); 1396 if (aeq->mem.va) 1397 goto skip_virt_aeq; 1398 1399 /* physically mapped aeq failed. setup virtual aeq */ 1400 status = irdma_create_virt_aeq(rf, aeq_size); 1401 if (status) 1402 return status; 1403 1404 info.virtual_map = true; 1405 aeq->virtual_map = info.virtual_map; 1406 info.pbl_chunk_size = 1; 1407 info.first_pm_pbl_idx = aeq->palloc.level1.idx; 1408 1409 skip_virt_aeq: 1410 info.aeqe_base = aeq->mem.va; 1411 info.aeq_elem_pa = aeq->mem.pa; 1412 info.elem_cnt = aeq_size; 1413 info.dev = dev; 1414 info.msix_idx = rf->iw_msixtbl->idx; 1415 status = irdma_sc_aeq_init(&aeq->sc_aeq, &info); 1416 if (status) 1417 goto err; 1418 1419 status = irdma_cqp_aeq_cmd(dev, &aeq->sc_aeq, IRDMA_OP_AEQ_CREATE); 1420 if (status) 1421 goto err; 1422 1423 return 0; 1424 1425 err: 1426 if (aeq->virtual_map) { 1427 irdma_destroy_virt_aeq(rf); 1428 } else { 1429 dma_free_coherent(dev->hw->device, aeq->mem.size, aeq->mem.va, 1430 aeq->mem.pa); 1431 aeq->mem.va = NULL; 1432 } 1433 1434 return status; 1435 } 1436 1437 /** 1438 * irdma_setup_aeq - set up the device aeq 1439 * @rf: RDMA PCI function 1440 * 1441 * Create the aeq and configure its msix interrupt vector 1442 * Return 0 if successful, otherwise return error 1443 */ 1444 static int irdma_setup_aeq(struct irdma_pci_f *rf) 1445 { 1446 struct irdma_sc_dev *dev = &rf->sc_dev; 1447 int status; 1448 1449 status = irdma_create_aeq(rf); 1450 if (status) 1451 return status; 1452 1453 status = irdma_cfg_aeq_vector(rf); 1454 if (status) { 1455 irdma_destroy_aeq(rf); 1456 return status; 1457 } 1458 1459 if (!rf->msix_shared) 1460 irdma_ena_intr(dev, rf->iw_msixtbl[0].idx); 1461 1462 return 0; 1463 } 1464 1465 /** 1466 * irdma_initialize_ilq - create iwarp local queue for cm 1467 * @iwdev: irdma device 1468 * 1469 * Return 0 if successful, otherwise return error 1470 */ 1471 static int irdma_initialize_ilq(struct irdma_device *iwdev) 1472 { 1473 struct irdma_puda_rsrc_info info = {}; 1474 int status; 1475 1476 info.type = IRDMA_PUDA_RSRC_TYPE_ILQ; 1477 info.cq_id = 1; 1478 info.qp_id = 1; 1479 info.count = 1; 1480 info.pd_id = 1; 1481 info.abi_ver = IRDMA_ABI_VER; 1482 info.sq_size = min(iwdev->rf->max_qp / 2, (u32)32768); 1483 info.rq_size = info.sq_size; 1484 info.buf_size = 1024; 1485 info.tx_buf_cnt = 2 * info.sq_size; 1486 info.receive = irdma_receive_ilq; 1487 info.xmit_complete = irdma_free_sqbuf; 1488 status = irdma_puda_create_rsrc(&iwdev->vsi, &info); 1489 if (status) 1490 ibdev_dbg(&iwdev->ibdev, "ERR: ilq create fail\n"); 1491 1492 return status; 1493 } 1494 1495 /** 1496 * irdma_initialize_ieq - create iwarp exception queue 1497 * @iwdev: irdma device 1498 * 1499 * Return 0 if successful, otherwise return error 1500 */ 1501 static int irdma_initialize_ieq(struct irdma_device *iwdev) 1502 { 1503 struct irdma_puda_rsrc_info info = {}; 1504 int status; 1505 1506 info.type = IRDMA_PUDA_RSRC_TYPE_IEQ; 1507 info.cq_id = 2; 1508 info.qp_id = iwdev->vsi.exception_lan_q; 1509 info.count = 1; 1510 info.pd_id = 2; 1511 info.abi_ver = IRDMA_ABI_VER; 1512 info.sq_size = min(iwdev->rf->max_qp / 2, (u32)32768); 1513 info.rq_size = info.sq_size; 1514 info.buf_size = iwdev->vsi.mtu + IRDMA_IPV4_PAD; 1515 info.tx_buf_cnt = 4096; 1516 status = irdma_puda_create_rsrc(&iwdev->vsi, &info); 1517 if (status) 1518 ibdev_dbg(&iwdev->ibdev, "ERR: ieq create fail\n"); 1519 1520 return status; 1521 } 1522 1523 /** 1524 * irdma_reinitialize_ieq - destroy and re-create ieq 1525 * @vsi: VSI structure 1526 */ 1527 void irdma_reinitialize_ieq(struct irdma_sc_vsi *vsi) 1528 { 1529 struct irdma_device *iwdev = vsi->back_vsi; 1530 struct irdma_pci_f *rf = iwdev->rf; 1531 1532 irdma_puda_dele_rsrc(vsi, IRDMA_PUDA_RSRC_TYPE_IEQ, false); 1533 if (irdma_initialize_ieq(iwdev)) { 1534 iwdev->rf->reset = true; 1535 rf->gen_ops.request_reset(rf); 1536 } 1537 } 1538 1539 /** 1540 * irdma_hmc_setup - create hmc objects for the device 1541 * @rf: RDMA PCI function 1542 * 1543 * Set up the device private memory space for the number and size of 1544 * the hmc objects and create the objects 1545 * Return 0 if successful, otherwise return error 1546 */ 1547 static int irdma_hmc_setup(struct irdma_pci_f *rf) 1548 { 1549 int status; 1550 u32 qpcnt; 1551 1552 qpcnt = rsrc_limits_table[rf->limits_sel].qplimit; 1553 1554 rf->sd_type = IRDMA_SD_TYPE_DIRECT; 1555 status = irdma_cfg_fpm_val(&rf->sc_dev, qpcnt); 1556 if (status) 1557 return status; 1558 1559 status = irdma_create_hmc_objs(rf, true, rf->rdma_ver); 1560 1561 return status; 1562 } 1563 1564 /** 1565 * irdma_del_init_mem - deallocate memory resources 1566 * @rf: RDMA PCI function 1567 */ 1568 static void irdma_del_init_mem(struct irdma_pci_f *rf) 1569 { 1570 struct irdma_sc_dev *dev = &rf->sc_dev; 1571 1572 kfree(dev->hmc_info->sd_table.sd_entry); 1573 dev->hmc_info->sd_table.sd_entry = NULL; 1574 vfree(rf->mem_rsrc); 1575 rf->mem_rsrc = NULL; 1576 dma_free_coherent(rf->hw.device, rf->obj_mem.size, rf->obj_mem.va, 1577 rf->obj_mem.pa); 1578 rf->obj_mem.va = NULL; 1579 if (rf->rdma_ver != IRDMA_GEN_1) { 1580 bitmap_free(rf->allocated_ws_nodes); 1581 rf->allocated_ws_nodes = NULL; 1582 } 1583 kfree(rf->ceqlist); 1584 rf->ceqlist = NULL; 1585 kfree(rf->iw_msixtbl); 1586 rf->iw_msixtbl = NULL; 1587 kfree(rf->hmc_info_mem); 1588 rf->hmc_info_mem = NULL; 1589 } 1590 1591 /** 1592 * irdma_initialize_dev - initialize device 1593 * @rf: RDMA PCI function 1594 * 1595 * Allocate memory for the hmc objects and initialize iwdev 1596 * Return 0 if successful, otherwise clean up the resources 1597 * and return error 1598 */ 1599 static int irdma_initialize_dev(struct irdma_pci_f *rf) 1600 { 1601 int status; 1602 struct irdma_sc_dev *dev = &rf->sc_dev; 1603 struct irdma_device_init_info info = {}; 1604 struct irdma_dma_mem mem; 1605 u32 size; 1606 1607 size = sizeof(struct irdma_hmc_pble_rsrc) + 1608 sizeof(struct irdma_hmc_info) + 1609 (sizeof(struct irdma_hmc_obj_info) * IRDMA_HMC_IW_MAX); 1610 1611 rf->hmc_info_mem = kzalloc(size, GFP_KERNEL); 1612 if (!rf->hmc_info_mem) 1613 return -ENOMEM; 1614 1615 rf->pble_rsrc = (struct irdma_hmc_pble_rsrc *)rf->hmc_info_mem; 1616 dev->hmc_info = &rf->hw.hmc; 1617 dev->hmc_info->hmc_obj = (struct irdma_hmc_obj_info *) 1618 (rf->pble_rsrc + 1); 1619 1620 status = irdma_obj_aligned_mem(rf, &mem, IRDMA_QUERY_FPM_BUF_SIZE, 1621 IRDMA_FPM_QUERY_BUF_ALIGNMENT_M); 1622 if (status) 1623 goto error; 1624 1625 info.fpm_query_buf_pa = mem.pa; 1626 info.fpm_query_buf = mem.va; 1627 1628 status = irdma_obj_aligned_mem(rf, &mem, IRDMA_COMMIT_FPM_BUF_SIZE, 1629 IRDMA_FPM_COMMIT_BUF_ALIGNMENT_M); 1630 if (status) 1631 goto error; 1632 1633 info.fpm_commit_buf_pa = mem.pa; 1634 info.fpm_commit_buf = mem.va; 1635 1636 info.bar0 = rf->hw.hw_addr; 1637 info.hmc_fn_id = rf->pf_id; 1638 info.hw = &rf->hw; 1639 status = irdma_sc_dev_init(rf->rdma_ver, &rf->sc_dev, &info); 1640 if (status) 1641 goto error; 1642 1643 return status; 1644 error: 1645 kfree(rf->hmc_info_mem); 1646 rf->hmc_info_mem = NULL; 1647 1648 return status; 1649 } 1650 1651 /** 1652 * irdma_rt_deinit_hw - clean up the irdma device resources 1653 * @iwdev: irdma device 1654 * 1655 * remove the mac ip entry and ipv4/ipv6 addresses, destroy the 1656 * device queues and free the pble and the hmc objects 1657 */ 1658 void irdma_rt_deinit_hw(struct irdma_device *iwdev) 1659 { 1660 ibdev_dbg(&iwdev->ibdev, "INIT: state = %d\n", iwdev->init_state); 1661 1662 switch (iwdev->init_state) { 1663 case IP_ADDR_REGISTERED: 1664 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 1665 irdma_del_local_mac_entry(iwdev->rf, 1666 (u8)iwdev->mac_ip_table_idx); 1667 fallthrough; 1668 case AEQ_CREATED: 1669 case PBLE_CHUNK_MEM: 1670 case CEQS_CREATED: 1671 case IEQ_CREATED: 1672 if (!iwdev->roce_mode) 1673 irdma_puda_dele_rsrc(&iwdev->vsi, IRDMA_PUDA_RSRC_TYPE_IEQ, 1674 iwdev->rf->reset); 1675 fallthrough; 1676 case ILQ_CREATED: 1677 if (!iwdev->roce_mode) 1678 irdma_puda_dele_rsrc(&iwdev->vsi, 1679 IRDMA_PUDA_RSRC_TYPE_ILQ, 1680 iwdev->rf->reset); 1681 break; 1682 default: 1683 ibdev_warn(&iwdev->ibdev, "bad init_state = %d\n", iwdev->init_state); 1684 break; 1685 } 1686 1687 irdma_cleanup_cm_core(&iwdev->cm_core); 1688 if (iwdev->vsi.pestat) { 1689 irdma_vsi_stats_free(&iwdev->vsi); 1690 kfree(iwdev->vsi.pestat); 1691 } 1692 if (iwdev->cleanup_wq) 1693 destroy_workqueue(iwdev->cleanup_wq); 1694 } 1695 1696 static int irdma_setup_init_state(struct irdma_pci_f *rf) 1697 { 1698 int status; 1699 1700 status = irdma_save_msix_info(rf); 1701 if (status) 1702 return status; 1703 1704 rf->hw.device = &rf->pcidev->dev; 1705 rf->obj_mem.size = ALIGN(8192, IRDMA_HW_PAGE_SIZE); 1706 rf->obj_mem.va = dma_alloc_coherent(rf->hw.device, rf->obj_mem.size, 1707 &rf->obj_mem.pa, GFP_KERNEL); 1708 if (!rf->obj_mem.va) { 1709 status = -ENOMEM; 1710 goto clean_msixtbl; 1711 } 1712 1713 rf->obj_next = rf->obj_mem; 1714 status = irdma_initialize_dev(rf); 1715 if (status) 1716 goto clean_obj_mem; 1717 1718 return 0; 1719 1720 clean_obj_mem: 1721 dma_free_coherent(rf->hw.device, rf->obj_mem.size, rf->obj_mem.va, 1722 rf->obj_mem.pa); 1723 rf->obj_mem.va = NULL; 1724 clean_msixtbl: 1725 kfree(rf->iw_msixtbl); 1726 rf->iw_msixtbl = NULL; 1727 return status; 1728 } 1729 1730 /** 1731 * irdma_get_used_rsrc - determine resources used internally 1732 * @iwdev: irdma device 1733 * 1734 * Called at the end of open to get all internal allocations 1735 */ 1736 static void irdma_get_used_rsrc(struct irdma_device *iwdev) 1737 { 1738 iwdev->rf->used_pds = find_first_zero_bit(iwdev->rf->allocated_pds, 1739 iwdev->rf->max_pd); 1740 iwdev->rf->used_qps = find_first_zero_bit(iwdev->rf->allocated_qps, 1741 iwdev->rf->max_qp); 1742 iwdev->rf->used_cqs = find_first_zero_bit(iwdev->rf->allocated_cqs, 1743 iwdev->rf->max_cq); 1744 iwdev->rf->used_mrs = find_first_zero_bit(iwdev->rf->allocated_mrs, 1745 iwdev->rf->max_mr); 1746 } 1747 1748 void irdma_ctrl_deinit_hw(struct irdma_pci_f *rf) 1749 { 1750 enum init_completion_state state = rf->init_state; 1751 1752 rf->init_state = INVALID_STATE; 1753 if (rf->rsrc_created) { 1754 irdma_destroy_aeq(rf); 1755 irdma_destroy_pble_prm(rf->pble_rsrc); 1756 irdma_del_ceqs(rf); 1757 rf->rsrc_created = false; 1758 } 1759 switch (state) { 1760 case CEQ0_CREATED: 1761 irdma_del_ceq_0(rf); 1762 fallthrough; 1763 case CCQ_CREATED: 1764 irdma_destroy_ccq(rf); 1765 fallthrough; 1766 case HW_RSRC_INITIALIZED: 1767 case HMC_OBJS_CREATED: 1768 irdma_del_hmc_objects(&rf->sc_dev, rf->sc_dev.hmc_info, true, 1769 rf->reset, rf->rdma_ver); 1770 fallthrough; 1771 case CQP_CREATED: 1772 irdma_destroy_cqp(rf); 1773 fallthrough; 1774 case INITIAL_STATE: 1775 irdma_del_init_mem(rf); 1776 break; 1777 case INVALID_STATE: 1778 default: 1779 ibdev_warn(&rf->iwdev->ibdev, "bad init_state = %d\n", rf->init_state); 1780 break; 1781 } 1782 } 1783 1784 /** 1785 * irdma_rt_init_hw - Initializes runtime portion of HW 1786 * @iwdev: irdma device 1787 * @l2params: qos, tc, mtu info from netdev driver 1788 * 1789 * Create device queues ILQ, IEQ, CEQs and PBLEs. Setup irdma 1790 * device resource objects. 1791 */ 1792 int irdma_rt_init_hw(struct irdma_device *iwdev, 1793 struct irdma_l2params *l2params) 1794 { 1795 struct irdma_pci_f *rf = iwdev->rf; 1796 struct irdma_sc_dev *dev = &rf->sc_dev; 1797 struct irdma_vsi_init_info vsi_info = {}; 1798 struct irdma_vsi_stats_info stats_info = {}; 1799 int status; 1800 1801 vsi_info.dev = dev; 1802 vsi_info.back_vsi = iwdev; 1803 vsi_info.params = l2params; 1804 vsi_info.pf_data_vsi_num = iwdev->vsi_num; 1805 vsi_info.register_qset = rf->gen_ops.register_qset; 1806 vsi_info.unregister_qset = rf->gen_ops.unregister_qset; 1807 vsi_info.exception_lan_q = 2; 1808 irdma_sc_vsi_init(&iwdev->vsi, &vsi_info); 1809 1810 status = irdma_setup_cm_core(iwdev, rf->rdma_ver); 1811 if (status) 1812 return status; 1813 1814 stats_info.pestat = kzalloc(sizeof(*stats_info.pestat), GFP_KERNEL); 1815 if (!stats_info.pestat) { 1816 irdma_cleanup_cm_core(&iwdev->cm_core); 1817 return -ENOMEM; 1818 } 1819 stats_info.fcn_id = dev->hmc_fn_id; 1820 status = irdma_vsi_stats_init(&iwdev->vsi, &stats_info); 1821 if (status) { 1822 irdma_cleanup_cm_core(&iwdev->cm_core); 1823 kfree(stats_info.pestat); 1824 return status; 1825 } 1826 1827 do { 1828 if (!iwdev->roce_mode) { 1829 status = irdma_initialize_ilq(iwdev); 1830 if (status) 1831 break; 1832 iwdev->init_state = ILQ_CREATED; 1833 status = irdma_initialize_ieq(iwdev); 1834 if (status) 1835 break; 1836 iwdev->init_state = IEQ_CREATED; 1837 } 1838 if (!rf->rsrc_created) { 1839 status = irdma_setup_ceqs(rf, &iwdev->vsi); 1840 if (status) 1841 break; 1842 1843 iwdev->init_state = CEQS_CREATED; 1844 1845 status = irdma_hmc_init_pble(&rf->sc_dev, 1846 rf->pble_rsrc); 1847 if (status) { 1848 irdma_del_ceqs(rf); 1849 break; 1850 } 1851 1852 iwdev->init_state = PBLE_CHUNK_MEM; 1853 1854 status = irdma_setup_aeq(rf); 1855 if (status) { 1856 irdma_destroy_pble_prm(rf->pble_rsrc); 1857 irdma_del_ceqs(rf); 1858 break; 1859 } 1860 iwdev->init_state = AEQ_CREATED; 1861 rf->rsrc_created = true; 1862 } 1863 1864 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 1865 irdma_alloc_set_mac(iwdev); 1866 irdma_add_ip(iwdev); 1867 iwdev->init_state = IP_ADDR_REGISTERED; 1868 1869 /* handles asynch cleanup tasks - disconnect CM , free qp, 1870 * free cq bufs 1871 */ 1872 iwdev->cleanup_wq = alloc_workqueue("irdma-cleanup-wq", 1873 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); 1874 if (!iwdev->cleanup_wq) 1875 return -ENOMEM; 1876 irdma_get_used_rsrc(iwdev); 1877 init_waitqueue_head(&iwdev->suspend_wq); 1878 1879 return 0; 1880 } while (0); 1881 1882 dev_err(&rf->pcidev->dev, "HW runtime init FAIL status = %d last cmpl = %d\n", 1883 status, iwdev->init_state); 1884 irdma_rt_deinit_hw(iwdev); 1885 1886 return status; 1887 } 1888 1889 /** 1890 * irdma_ctrl_init_hw - Initializes control portion of HW 1891 * @rf: RDMA PCI function 1892 * 1893 * Create admin queues, HMC obejcts and RF resource objects 1894 */ 1895 int irdma_ctrl_init_hw(struct irdma_pci_f *rf) 1896 { 1897 struct irdma_sc_dev *dev = &rf->sc_dev; 1898 int status; 1899 do { 1900 status = irdma_setup_init_state(rf); 1901 if (status) 1902 break; 1903 rf->init_state = INITIAL_STATE; 1904 1905 status = irdma_create_cqp(rf); 1906 if (status) 1907 break; 1908 rf->init_state = CQP_CREATED; 1909 1910 status = irdma_hmc_setup(rf); 1911 if (status) 1912 break; 1913 rf->init_state = HMC_OBJS_CREATED; 1914 1915 status = irdma_initialize_hw_rsrc(rf); 1916 if (status) 1917 break; 1918 rf->init_state = HW_RSRC_INITIALIZED; 1919 1920 status = irdma_create_ccq(rf); 1921 if (status) 1922 break; 1923 rf->init_state = CCQ_CREATED; 1924 1925 dev->feature_info[IRDMA_FEATURE_FW_INFO] = IRDMA_FW_VER_DEFAULT; 1926 if (rf->rdma_ver != IRDMA_GEN_1) { 1927 status = irdma_get_rdma_features(dev); 1928 if (status) 1929 break; 1930 } 1931 1932 status = irdma_setup_ceq_0(rf); 1933 if (status) 1934 break; 1935 rf->init_state = CEQ0_CREATED; 1936 /* Handles processing of CQP completions */ 1937 rf->cqp_cmpl_wq = 1938 alloc_ordered_workqueue("cqp_cmpl_wq", WQ_HIGHPRI); 1939 if (!rf->cqp_cmpl_wq) { 1940 status = -ENOMEM; 1941 break; 1942 } 1943 INIT_WORK(&rf->cqp_cmpl_work, cqp_compl_worker); 1944 irdma_sc_ccq_arm(dev->ccq); 1945 return 0; 1946 } while (0); 1947 1948 dev_err(&rf->pcidev->dev, "IRDMA hardware initialization FAILED init_state=%d status=%d\n", 1949 rf->init_state, status); 1950 irdma_ctrl_deinit_hw(rf); 1951 return status; 1952 } 1953 1954 /** 1955 * irdma_set_hw_rsrc - set hw memory resources. 1956 * @rf: RDMA PCI function 1957 */ 1958 static void irdma_set_hw_rsrc(struct irdma_pci_f *rf) 1959 { 1960 rf->allocated_qps = (void *)(rf->mem_rsrc + 1961 (sizeof(struct irdma_arp_entry) * rf->arp_table_size)); 1962 rf->allocated_cqs = &rf->allocated_qps[BITS_TO_LONGS(rf->max_qp)]; 1963 rf->allocated_mrs = &rf->allocated_cqs[BITS_TO_LONGS(rf->max_cq)]; 1964 rf->allocated_pds = &rf->allocated_mrs[BITS_TO_LONGS(rf->max_mr)]; 1965 rf->allocated_ahs = &rf->allocated_pds[BITS_TO_LONGS(rf->max_pd)]; 1966 rf->allocated_mcgs = &rf->allocated_ahs[BITS_TO_LONGS(rf->max_ah)]; 1967 rf->allocated_arps = &rf->allocated_mcgs[BITS_TO_LONGS(rf->max_mcg)]; 1968 rf->qp_table = (struct irdma_qp **) 1969 (&rf->allocated_arps[BITS_TO_LONGS(rf->arp_table_size)]); 1970 rf->cq_table = (struct irdma_cq **)(&rf->qp_table[rf->max_qp]); 1971 1972 spin_lock_init(&rf->rsrc_lock); 1973 spin_lock_init(&rf->arp_lock); 1974 spin_lock_init(&rf->qptable_lock); 1975 spin_lock_init(&rf->cqtable_lock); 1976 spin_lock_init(&rf->qh_list_lock); 1977 } 1978 1979 /** 1980 * irdma_calc_mem_rsrc_size - calculate memory resources size. 1981 * @rf: RDMA PCI function 1982 */ 1983 static u32 irdma_calc_mem_rsrc_size(struct irdma_pci_f *rf) 1984 { 1985 u32 rsrc_size; 1986 1987 rsrc_size = sizeof(struct irdma_arp_entry) * rf->arp_table_size; 1988 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_qp); 1989 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_mr); 1990 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_cq); 1991 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_pd); 1992 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->arp_table_size); 1993 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_ah); 1994 rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_mcg); 1995 rsrc_size += sizeof(struct irdma_qp **) * rf->max_qp; 1996 rsrc_size += sizeof(struct irdma_cq **) * rf->max_cq; 1997 1998 return rsrc_size; 1999 } 2000 2001 /** 2002 * irdma_initialize_hw_rsrc - initialize hw resource tracking array 2003 * @rf: RDMA PCI function 2004 */ 2005 u32 irdma_initialize_hw_rsrc(struct irdma_pci_f *rf) 2006 { 2007 u32 rsrc_size; 2008 u32 mrdrvbits; 2009 u32 ret; 2010 2011 if (rf->rdma_ver != IRDMA_GEN_1) { 2012 rf->allocated_ws_nodes = bitmap_zalloc(IRDMA_MAX_WS_NODES, 2013 GFP_KERNEL); 2014 if (!rf->allocated_ws_nodes) 2015 return -ENOMEM; 2016 2017 set_bit(0, rf->allocated_ws_nodes); 2018 rf->max_ws_node_id = IRDMA_MAX_WS_NODES; 2019 } 2020 rf->max_cqe = rf->sc_dev.hw_attrs.uk_attrs.max_hw_cq_size; 2021 rf->max_qp = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt; 2022 rf->max_mr = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt; 2023 rf->max_cq = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt; 2024 rf->max_pd = rf->sc_dev.hw_attrs.max_hw_pds; 2025 rf->arp_table_size = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].cnt; 2026 rf->max_ah = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt; 2027 rf->max_mcg = rf->max_qp; 2028 2029 rsrc_size = irdma_calc_mem_rsrc_size(rf); 2030 rf->mem_rsrc = vzalloc(rsrc_size); 2031 if (!rf->mem_rsrc) { 2032 ret = -ENOMEM; 2033 goto mem_rsrc_vzalloc_fail; 2034 } 2035 2036 rf->arp_table = (struct irdma_arp_entry *)rf->mem_rsrc; 2037 2038 irdma_set_hw_rsrc(rf); 2039 2040 set_bit(0, rf->allocated_mrs); 2041 set_bit(0, rf->allocated_qps); 2042 set_bit(0, rf->allocated_cqs); 2043 set_bit(0, rf->allocated_pds); 2044 set_bit(0, rf->allocated_arps); 2045 set_bit(0, rf->allocated_ahs); 2046 set_bit(0, rf->allocated_mcgs); 2047 set_bit(2, rf->allocated_qps); /* qp 2 IEQ */ 2048 set_bit(1, rf->allocated_qps); /* qp 1 ILQ */ 2049 set_bit(1, rf->allocated_cqs); 2050 set_bit(1, rf->allocated_pds); 2051 set_bit(2, rf->allocated_cqs); 2052 set_bit(2, rf->allocated_pds); 2053 2054 INIT_LIST_HEAD(&rf->mc_qht_list.list); 2055 /* stag index mask has a minimum of 14 bits */ 2056 mrdrvbits = 24 - max(get_count_order(rf->max_mr), 14); 2057 rf->mr_stagmask = ~(((1 << mrdrvbits) - 1) << (32 - mrdrvbits)); 2058 2059 return 0; 2060 2061 mem_rsrc_vzalloc_fail: 2062 bitmap_free(rf->allocated_ws_nodes); 2063 rf->allocated_ws_nodes = NULL; 2064 2065 return ret; 2066 } 2067 2068 /** 2069 * irdma_cqp_ce_handler - handle cqp completions 2070 * @rf: RDMA PCI function 2071 * @cq: cq for cqp completions 2072 */ 2073 void irdma_cqp_ce_handler(struct irdma_pci_f *rf, struct irdma_sc_cq *cq) 2074 { 2075 struct irdma_cqp_request *cqp_request; 2076 struct irdma_sc_dev *dev = &rf->sc_dev; 2077 u32 cqe_count = 0; 2078 struct irdma_ccq_cqe_info info; 2079 unsigned long flags; 2080 int ret; 2081 2082 do { 2083 memset(&info, 0, sizeof(info)); 2084 spin_lock_irqsave(&rf->cqp.compl_lock, flags); 2085 ret = irdma_sc_ccq_get_cqe_info(cq, &info); 2086 spin_unlock_irqrestore(&rf->cqp.compl_lock, flags); 2087 if (ret) 2088 break; 2089 2090 cqp_request = (struct irdma_cqp_request *) 2091 (unsigned long)info.scratch; 2092 if (info.error && irdma_cqp_crit_err(dev, cqp_request->info.cqp_cmd, 2093 info.maj_err_code, 2094 info.min_err_code)) 2095 ibdev_err(&rf->iwdev->ibdev, "cqp opcode = 0x%x maj_err_code = 0x%x min_err_code = 0x%x\n", 2096 info.op_code, info.maj_err_code, info.min_err_code); 2097 if (cqp_request) { 2098 cqp_request->compl_info.maj_err_code = info.maj_err_code; 2099 cqp_request->compl_info.min_err_code = info.min_err_code; 2100 cqp_request->compl_info.op_ret_val = info.op_ret_val; 2101 cqp_request->compl_info.error = info.error; 2102 2103 if (cqp_request->waiting) { 2104 WRITE_ONCE(cqp_request->request_done, true); 2105 wake_up(&cqp_request->waitq); 2106 irdma_put_cqp_request(&rf->cqp, cqp_request); 2107 } else { 2108 if (cqp_request->callback_fcn) 2109 cqp_request->callback_fcn(cqp_request); 2110 irdma_put_cqp_request(&rf->cqp, cqp_request); 2111 } 2112 } 2113 2114 cqe_count++; 2115 } while (1); 2116 2117 if (cqe_count) { 2118 irdma_process_bh(dev); 2119 irdma_sc_ccq_arm(cq); 2120 } 2121 } 2122 2123 /** 2124 * cqp_compl_worker - Handle cqp completions 2125 * @work: Pointer to work structure 2126 */ 2127 void cqp_compl_worker(struct work_struct *work) 2128 { 2129 struct irdma_pci_f *rf = container_of(work, struct irdma_pci_f, 2130 cqp_cmpl_work); 2131 struct irdma_sc_cq *cq = &rf->ccq.sc_cq; 2132 2133 irdma_cqp_ce_handler(rf, cq); 2134 } 2135 2136 /** 2137 * irdma_lookup_apbvt_entry - lookup hash table for an existing apbvt entry corresponding to port 2138 * @cm_core: cm's core 2139 * @port: port to identify apbvt entry 2140 */ 2141 static struct irdma_apbvt_entry *irdma_lookup_apbvt_entry(struct irdma_cm_core *cm_core, 2142 u16 port) 2143 { 2144 struct irdma_apbvt_entry *entry; 2145 2146 hash_for_each_possible(cm_core->apbvt_hash_tbl, entry, hlist, port) { 2147 if (entry->port == port) { 2148 entry->use_cnt++; 2149 return entry; 2150 } 2151 } 2152 2153 return NULL; 2154 } 2155 2156 /** 2157 * irdma_next_iw_state - modify qp state 2158 * @iwqp: iwarp qp to modify 2159 * @state: next state for qp 2160 * @del_hash: del hash 2161 * @term: term message 2162 * @termlen: length of term message 2163 */ 2164 void irdma_next_iw_state(struct irdma_qp *iwqp, u8 state, u8 del_hash, u8 term, 2165 u8 termlen) 2166 { 2167 struct irdma_modify_qp_info info = {}; 2168 2169 info.next_iwarp_state = state; 2170 info.remove_hash_idx = del_hash; 2171 info.cq_num_valid = true; 2172 info.arp_cache_idx_valid = true; 2173 info.dont_send_term = true; 2174 info.dont_send_fin = true; 2175 info.termlen = termlen; 2176 2177 if (term & IRDMAQP_TERM_SEND_TERM_ONLY) 2178 info.dont_send_term = false; 2179 if (term & IRDMAQP_TERM_SEND_FIN_ONLY) 2180 info.dont_send_fin = false; 2181 if (iwqp->sc_qp.term_flags && state == IRDMA_QP_STATE_ERROR) 2182 info.reset_tcp_conn = true; 2183 iwqp->hw_iwarp_state = state; 2184 irdma_hw_modify_qp(iwqp->iwdev, iwqp, &info, 0); 2185 iwqp->iwarp_state = info.next_iwarp_state; 2186 } 2187 2188 /** 2189 * irdma_del_local_mac_entry - remove a mac entry from the hw 2190 * table 2191 * @rf: RDMA PCI function 2192 * @idx: the index of the mac ip address to delete 2193 */ 2194 void irdma_del_local_mac_entry(struct irdma_pci_f *rf, u16 idx) 2195 { 2196 struct irdma_cqp *iwcqp = &rf->cqp; 2197 struct irdma_cqp_request *cqp_request; 2198 struct cqp_cmds_info *cqp_info; 2199 2200 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); 2201 if (!cqp_request) 2202 return; 2203 2204 cqp_info = &cqp_request->info; 2205 cqp_info->cqp_cmd = IRDMA_OP_DELETE_LOCAL_MAC_ENTRY; 2206 cqp_info->post_sq = 1; 2207 cqp_info->in.u.del_local_mac_entry.cqp = &iwcqp->sc_cqp; 2208 cqp_info->in.u.del_local_mac_entry.scratch = (uintptr_t)cqp_request; 2209 cqp_info->in.u.del_local_mac_entry.entry_idx = idx; 2210 cqp_info->in.u.del_local_mac_entry.ignore_ref_count = 0; 2211 2212 irdma_handle_cqp_op(rf, cqp_request); 2213 irdma_put_cqp_request(iwcqp, cqp_request); 2214 } 2215 2216 /** 2217 * irdma_add_local_mac_entry - add a mac ip address entry to the 2218 * hw table 2219 * @rf: RDMA PCI function 2220 * @mac_addr: pointer to mac address 2221 * @idx: the index of the mac ip address to add 2222 */ 2223 int irdma_add_local_mac_entry(struct irdma_pci_f *rf, const u8 *mac_addr, u16 idx) 2224 { 2225 struct irdma_local_mac_entry_info *info; 2226 struct irdma_cqp *iwcqp = &rf->cqp; 2227 struct irdma_cqp_request *cqp_request; 2228 struct cqp_cmds_info *cqp_info; 2229 int status; 2230 2231 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); 2232 if (!cqp_request) 2233 return -ENOMEM; 2234 2235 cqp_info = &cqp_request->info; 2236 cqp_info->post_sq = 1; 2237 info = &cqp_info->in.u.add_local_mac_entry.info; 2238 ether_addr_copy(info->mac_addr, mac_addr); 2239 info->entry_idx = idx; 2240 cqp_info->in.u.add_local_mac_entry.scratch = (uintptr_t)cqp_request; 2241 cqp_info->cqp_cmd = IRDMA_OP_ADD_LOCAL_MAC_ENTRY; 2242 cqp_info->in.u.add_local_mac_entry.cqp = &iwcqp->sc_cqp; 2243 cqp_info->in.u.add_local_mac_entry.scratch = (uintptr_t)cqp_request; 2244 2245 status = irdma_handle_cqp_op(rf, cqp_request); 2246 irdma_put_cqp_request(iwcqp, cqp_request); 2247 2248 return status; 2249 } 2250 2251 /** 2252 * irdma_alloc_local_mac_entry - allocate a mac entry 2253 * @rf: RDMA PCI function 2254 * @mac_tbl_idx: the index of the new mac address 2255 * 2256 * Allocate a mac address entry and update the mac_tbl_idx 2257 * to hold the index of the newly created mac address 2258 * Return 0 if successful, otherwise return error 2259 */ 2260 int irdma_alloc_local_mac_entry(struct irdma_pci_f *rf, u16 *mac_tbl_idx) 2261 { 2262 struct irdma_cqp *iwcqp = &rf->cqp; 2263 struct irdma_cqp_request *cqp_request; 2264 struct cqp_cmds_info *cqp_info; 2265 int status = 0; 2266 2267 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); 2268 if (!cqp_request) 2269 return -ENOMEM; 2270 2271 cqp_info = &cqp_request->info; 2272 cqp_info->cqp_cmd = IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY; 2273 cqp_info->post_sq = 1; 2274 cqp_info->in.u.alloc_local_mac_entry.cqp = &iwcqp->sc_cqp; 2275 cqp_info->in.u.alloc_local_mac_entry.scratch = (uintptr_t)cqp_request; 2276 status = irdma_handle_cqp_op(rf, cqp_request); 2277 if (!status) 2278 *mac_tbl_idx = (u16)cqp_request->compl_info.op_ret_val; 2279 2280 irdma_put_cqp_request(iwcqp, cqp_request); 2281 2282 return status; 2283 } 2284 2285 /** 2286 * irdma_cqp_manage_apbvt_cmd - send cqp command manage apbvt 2287 * @iwdev: irdma device 2288 * @accel_local_port: port for apbvt 2289 * @add_port: add ordelete port 2290 */ 2291 static int irdma_cqp_manage_apbvt_cmd(struct irdma_device *iwdev, 2292 u16 accel_local_port, bool add_port) 2293 { 2294 struct irdma_apbvt_info *info; 2295 struct irdma_cqp_request *cqp_request; 2296 struct cqp_cmds_info *cqp_info; 2297 int status; 2298 2299 cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, add_port); 2300 if (!cqp_request) 2301 return -ENOMEM; 2302 2303 cqp_info = &cqp_request->info; 2304 info = &cqp_info->in.u.manage_apbvt_entry.info; 2305 memset(info, 0, sizeof(*info)); 2306 info->add = add_port; 2307 info->port = accel_local_port; 2308 cqp_info->cqp_cmd = IRDMA_OP_MANAGE_APBVT_ENTRY; 2309 cqp_info->post_sq = 1; 2310 cqp_info->in.u.manage_apbvt_entry.cqp = &iwdev->rf->cqp.sc_cqp; 2311 cqp_info->in.u.manage_apbvt_entry.scratch = (uintptr_t)cqp_request; 2312 ibdev_dbg(&iwdev->ibdev, "DEV: %s: port=0x%04x\n", 2313 (!add_port) ? "DELETE" : "ADD", accel_local_port); 2314 2315 status = irdma_handle_cqp_op(iwdev->rf, cqp_request); 2316 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request); 2317 2318 return status; 2319 } 2320 2321 /** 2322 * irdma_add_apbvt - add tcp port to HW apbvt table 2323 * @iwdev: irdma device 2324 * @port: port for apbvt 2325 */ 2326 struct irdma_apbvt_entry *irdma_add_apbvt(struct irdma_device *iwdev, u16 port) 2327 { 2328 struct irdma_cm_core *cm_core = &iwdev->cm_core; 2329 struct irdma_apbvt_entry *entry; 2330 unsigned long flags; 2331 2332 spin_lock_irqsave(&cm_core->apbvt_lock, flags); 2333 entry = irdma_lookup_apbvt_entry(cm_core, port); 2334 if (entry) { 2335 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2336 return entry; 2337 } 2338 2339 entry = kzalloc(sizeof(*entry), GFP_ATOMIC); 2340 if (!entry) { 2341 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2342 return NULL; 2343 } 2344 2345 entry->port = port; 2346 entry->use_cnt = 1; 2347 hash_add(cm_core->apbvt_hash_tbl, &entry->hlist, entry->port); 2348 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2349 2350 if (irdma_cqp_manage_apbvt_cmd(iwdev, port, true)) { 2351 kfree(entry); 2352 return NULL; 2353 } 2354 2355 return entry; 2356 } 2357 2358 /** 2359 * irdma_del_apbvt - delete tcp port from HW apbvt table 2360 * @iwdev: irdma device 2361 * @entry: apbvt entry object 2362 */ 2363 void irdma_del_apbvt(struct irdma_device *iwdev, 2364 struct irdma_apbvt_entry *entry) 2365 { 2366 struct irdma_cm_core *cm_core = &iwdev->cm_core; 2367 unsigned long flags; 2368 2369 spin_lock_irqsave(&cm_core->apbvt_lock, flags); 2370 if (--entry->use_cnt) { 2371 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2372 return; 2373 } 2374 2375 hash_del(&entry->hlist); 2376 /* apbvt_lock is held across CQP delete APBVT OP (non-waiting) to 2377 * protect against race where add APBVT CQP can race ahead of the delete 2378 * APBVT for same port. 2379 */ 2380 irdma_cqp_manage_apbvt_cmd(iwdev, entry->port, false); 2381 kfree(entry); 2382 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); 2383 } 2384 2385 /** 2386 * irdma_manage_arp_cache - manage hw arp cache 2387 * @rf: RDMA PCI function 2388 * @mac_addr: mac address ptr 2389 * @ip_addr: ip addr for arp cache 2390 * @ipv4: flag inicating IPv4 2391 * @action: add, delete or modify 2392 */ 2393 void irdma_manage_arp_cache(struct irdma_pci_f *rf, 2394 const unsigned char *mac_addr, 2395 u32 *ip_addr, bool ipv4, u32 action) 2396 { 2397 struct irdma_add_arp_cache_entry_info *info; 2398 struct irdma_cqp_request *cqp_request; 2399 struct cqp_cmds_info *cqp_info; 2400 int arp_index; 2401 2402 arp_index = irdma_arp_table(rf, ip_addr, ipv4, mac_addr, action); 2403 if (arp_index == -1) 2404 return; 2405 2406 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, false); 2407 if (!cqp_request) 2408 return; 2409 2410 cqp_info = &cqp_request->info; 2411 if (action == IRDMA_ARP_ADD) { 2412 cqp_info->cqp_cmd = IRDMA_OP_ADD_ARP_CACHE_ENTRY; 2413 info = &cqp_info->in.u.add_arp_cache_entry.info; 2414 memset(info, 0, sizeof(*info)); 2415 info->arp_index = (u16)arp_index; 2416 info->permanent = true; 2417 ether_addr_copy(info->mac_addr, mac_addr); 2418 cqp_info->in.u.add_arp_cache_entry.scratch = 2419 (uintptr_t)cqp_request; 2420 cqp_info->in.u.add_arp_cache_entry.cqp = &rf->cqp.sc_cqp; 2421 } else { 2422 cqp_info->cqp_cmd = IRDMA_OP_DELETE_ARP_CACHE_ENTRY; 2423 cqp_info->in.u.del_arp_cache_entry.scratch = 2424 (uintptr_t)cqp_request; 2425 cqp_info->in.u.del_arp_cache_entry.cqp = &rf->cqp.sc_cqp; 2426 cqp_info->in.u.del_arp_cache_entry.arp_index = arp_index; 2427 } 2428 2429 cqp_info->post_sq = 1; 2430 irdma_handle_cqp_op(rf, cqp_request); 2431 irdma_put_cqp_request(&rf->cqp, cqp_request); 2432 } 2433 2434 /** 2435 * irdma_send_syn_cqp_callback - do syn/ack after qhash 2436 * @cqp_request: qhash cqp completion 2437 */ 2438 static void irdma_send_syn_cqp_callback(struct irdma_cqp_request *cqp_request) 2439 { 2440 struct irdma_cm_node *cm_node = cqp_request->param; 2441 2442 irdma_send_syn(cm_node, 1); 2443 irdma_rem_ref_cm_node(cm_node); 2444 } 2445 2446 /** 2447 * irdma_manage_qhash - add or modify qhash 2448 * @iwdev: irdma device 2449 * @cminfo: cm info for qhash 2450 * @etype: type (syn or quad) 2451 * @mtype: type of qhash 2452 * @cmnode: cmnode associated with connection 2453 * @wait: wait for completion 2454 */ 2455 int irdma_manage_qhash(struct irdma_device *iwdev, struct irdma_cm_info *cminfo, 2456 enum irdma_quad_entry_type etype, 2457 enum irdma_quad_hash_manage_type mtype, void *cmnode, 2458 bool wait) 2459 { 2460 struct irdma_qhash_table_info *info; 2461 struct irdma_cqp *iwcqp = &iwdev->rf->cqp; 2462 struct irdma_cqp_request *cqp_request; 2463 struct cqp_cmds_info *cqp_info; 2464 struct irdma_cm_node *cm_node = cmnode; 2465 int status; 2466 2467 cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, wait); 2468 if (!cqp_request) 2469 return -ENOMEM; 2470 2471 cqp_info = &cqp_request->info; 2472 info = &cqp_info->in.u.manage_qhash_table_entry.info; 2473 memset(info, 0, sizeof(*info)); 2474 info->vsi = &iwdev->vsi; 2475 info->manage = mtype; 2476 info->entry_type = etype; 2477 if (cminfo->vlan_id < VLAN_N_VID) { 2478 info->vlan_valid = true; 2479 info->vlan_id = cminfo->vlan_id; 2480 } else { 2481 info->vlan_valid = false; 2482 } 2483 info->ipv4_valid = cminfo->ipv4; 2484 info->user_pri = cminfo->user_pri; 2485 ether_addr_copy(info->mac_addr, iwdev->netdev->dev_addr); 2486 info->qp_num = cminfo->qh_qpid; 2487 info->dest_port = cminfo->loc_port; 2488 info->dest_ip[0] = cminfo->loc_addr[0]; 2489 info->dest_ip[1] = cminfo->loc_addr[1]; 2490 info->dest_ip[2] = cminfo->loc_addr[2]; 2491 info->dest_ip[3] = cminfo->loc_addr[3]; 2492 if (etype == IRDMA_QHASH_TYPE_TCP_ESTABLISHED || 2493 etype == IRDMA_QHASH_TYPE_UDP_UNICAST || 2494 etype == IRDMA_QHASH_TYPE_UDP_MCAST || 2495 etype == IRDMA_QHASH_TYPE_ROCE_MCAST || 2496 etype == IRDMA_QHASH_TYPE_ROCEV2_HW) { 2497 info->src_port = cminfo->rem_port; 2498 info->src_ip[0] = cminfo->rem_addr[0]; 2499 info->src_ip[1] = cminfo->rem_addr[1]; 2500 info->src_ip[2] = cminfo->rem_addr[2]; 2501 info->src_ip[3] = cminfo->rem_addr[3]; 2502 } 2503 if (cmnode) { 2504 cqp_request->callback_fcn = irdma_send_syn_cqp_callback; 2505 cqp_request->param = cmnode; 2506 if (!wait) 2507 refcount_inc(&cm_node->refcnt); 2508 } 2509 if (info->ipv4_valid) 2510 ibdev_dbg(&iwdev->ibdev, 2511 "CM: %s caller: %pS loc_port=0x%04x rem_port=0x%04x loc_addr=%pI4 rem_addr=%pI4 mac=%pM, vlan_id=%d cm_node=%p\n", 2512 (!mtype) ? "DELETE" : "ADD", 2513 __builtin_return_address(0), info->dest_port, 2514 info->src_port, info->dest_ip, info->src_ip, 2515 info->mac_addr, cminfo->vlan_id, 2516 cmnode ? cmnode : NULL); 2517 else 2518 ibdev_dbg(&iwdev->ibdev, 2519 "CM: %s caller: %pS loc_port=0x%04x rem_port=0x%04x loc_addr=%pI6 rem_addr=%pI6 mac=%pM, vlan_id=%d cm_node=%p\n", 2520 (!mtype) ? "DELETE" : "ADD", 2521 __builtin_return_address(0), info->dest_port, 2522 info->src_port, info->dest_ip, info->src_ip, 2523 info->mac_addr, cminfo->vlan_id, 2524 cmnode ? cmnode : NULL); 2525 2526 cqp_info->in.u.manage_qhash_table_entry.cqp = &iwdev->rf->cqp.sc_cqp; 2527 cqp_info->in.u.manage_qhash_table_entry.scratch = (uintptr_t)cqp_request; 2528 cqp_info->cqp_cmd = IRDMA_OP_MANAGE_QHASH_TABLE_ENTRY; 2529 cqp_info->post_sq = 1; 2530 status = irdma_handle_cqp_op(iwdev->rf, cqp_request); 2531 if (status && cm_node && !wait) 2532 irdma_rem_ref_cm_node(cm_node); 2533 2534 irdma_put_cqp_request(iwcqp, cqp_request); 2535 2536 return status; 2537 } 2538 2539 /** 2540 * irdma_hw_flush_wqes_callback - Check return code after flush 2541 * @cqp_request: qhash cqp completion 2542 */ 2543 static void irdma_hw_flush_wqes_callback(struct irdma_cqp_request *cqp_request) 2544 { 2545 struct irdma_qp_flush_info *hw_info; 2546 struct irdma_sc_qp *qp; 2547 struct irdma_qp *iwqp; 2548 struct cqp_cmds_info *cqp_info; 2549 2550 cqp_info = &cqp_request->info; 2551 hw_info = &cqp_info->in.u.qp_flush_wqes.info; 2552 qp = cqp_info->in.u.qp_flush_wqes.qp; 2553 iwqp = qp->qp_uk.back_qp; 2554 2555 if (cqp_request->compl_info.maj_err_code) 2556 return; 2557 2558 if (hw_info->rq && 2559 (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_SQ_WQE_FLUSHED || 2560 cqp_request->compl_info.min_err_code == 0)) { 2561 /* RQ WQE flush was requested but did not happen */ 2562 qp->qp_uk.rq_flush_complete = true; 2563 } 2564 if (hw_info->sq && 2565 (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_RQ_WQE_FLUSHED || 2566 cqp_request->compl_info.min_err_code == 0)) { 2567 if (IRDMA_RING_MORE_WORK(qp->qp_uk.sq_ring)) { 2568 ibdev_err(&iwqp->iwdev->ibdev, "Flush QP[%d] failed, SQ has more work", 2569 qp->qp_uk.qp_id); 2570 irdma_ib_qp_event(iwqp, IRDMA_QP_EVENT_CATASTROPHIC); 2571 } 2572 qp->qp_uk.sq_flush_complete = true; 2573 } 2574 } 2575 2576 /** 2577 * irdma_hw_flush_wqes - flush qp's wqe 2578 * @rf: RDMA PCI function 2579 * @qp: hardware control qp 2580 * @info: info for flush 2581 * @wait: flag wait for completion 2582 */ 2583 int irdma_hw_flush_wqes(struct irdma_pci_f *rf, struct irdma_sc_qp *qp, 2584 struct irdma_qp_flush_info *info, bool wait) 2585 { 2586 int status; 2587 struct irdma_qp_flush_info *hw_info; 2588 struct irdma_cqp_request *cqp_request; 2589 struct cqp_cmds_info *cqp_info; 2590 struct irdma_qp *iwqp = qp->qp_uk.back_qp; 2591 2592 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait); 2593 if (!cqp_request) 2594 return -ENOMEM; 2595 2596 cqp_info = &cqp_request->info; 2597 if (!wait) 2598 cqp_request->callback_fcn = irdma_hw_flush_wqes_callback; 2599 hw_info = &cqp_request->info.in.u.qp_flush_wqes.info; 2600 memcpy(hw_info, info, sizeof(*hw_info)); 2601 cqp_info->cqp_cmd = IRDMA_OP_QP_FLUSH_WQES; 2602 cqp_info->post_sq = 1; 2603 cqp_info->in.u.qp_flush_wqes.qp = qp; 2604 cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)cqp_request; 2605 status = irdma_handle_cqp_op(rf, cqp_request); 2606 if (status) { 2607 qp->qp_uk.sq_flush_complete = true; 2608 qp->qp_uk.rq_flush_complete = true; 2609 irdma_put_cqp_request(&rf->cqp, cqp_request); 2610 return status; 2611 } 2612 2613 if (!wait || cqp_request->compl_info.maj_err_code) 2614 goto put_cqp; 2615 2616 if (info->rq) { 2617 if (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_SQ_WQE_FLUSHED || 2618 cqp_request->compl_info.min_err_code == 0) { 2619 /* RQ WQE flush was requested but did not happen */ 2620 qp->qp_uk.rq_flush_complete = true; 2621 } 2622 } 2623 if (info->sq) { 2624 if (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_RQ_WQE_FLUSHED || 2625 cqp_request->compl_info.min_err_code == 0) { 2626 /* 2627 * Handling case where WQE is posted to empty SQ when 2628 * flush has not completed 2629 */ 2630 if (IRDMA_RING_MORE_WORK(qp->qp_uk.sq_ring)) { 2631 struct irdma_cqp_request *new_req; 2632 2633 if (!qp->qp_uk.sq_flush_complete) 2634 goto put_cqp; 2635 qp->qp_uk.sq_flush_complete = false; 2636 qp->flush_sq = false; 2637 2638 info->rq = false; 2639 info->sq = true; 2640 new_req = irdma_alloc_and_get_cqp_request(&rf->cqp, true); 2641 if (!new_req) { 2642 status = -ENOMEM; 2643 goto put_cqp; 2644 } 2645 cqp_info = &new_req->info; 2646 hw_info = &new_req->info.in.u.qp_flush_wqes.info; 2647 memcpy(hw_info, info, sizeof(*hw_info)); 2648 cqp_info->cqp_cmd = IRDMA_OP_QP_FLUSH_WQES; 2649 cqp_info->post_sq = 1; 2650 cqp_info->in.u.qp_flush_wqes.qp = qp; 2651 cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)new_req; 2652 2653 status = irdma_handle_cqp_op(rf, new_req); 2654 if (new_req->compl_info.maj_err_code || 2655 new_req->compl_info.min_err_code != IRDMA_CQP_COMPL_SQ_WQE_FLUSHED || 2656 status) { 2657 ibdev_err(&iwqp->iwdev->ibdev, "fatal QP event: SQ in error but not flushed, qp: %d", 2658 iwqp->ibqp.qp_num); 2659 qp->qp_uk.sq_flush_complete = false; 2660 irdma_ib_qp_event(iwqp, IRDMA_QP_EVENT_CATASTROPHIC); 2661 } 2662 irdma_put_cqp_request(&rf->cqp, new_req); 2663 } else { 2664 /* SQ WQE flush was requested but did not happen */ 2665 qp->qp_uk.sq_flush_complete = true; 2666 } 2667 } else { 2668 if (!IRDMA_RING_MORE_WORK(qp->qp_uk.sq_ring)) 2669 qp->qp_uk.sq_flush_complete = true; 2670 } 2671 } 2672 2673 ibdev_dbg(&rf->iwdev->ibdev, 2674 "VERBS: qp_id=%d qp_type=%d qpstate=%d ibqpstate=%d last_aeq=%d hw_iw_state=%d maj_err_code=%d min_err_code=%d\n", 2675 iwqp->ibqp.qp_num, rf->protocol_used, iwqp->iwarp_state, 2676 iwqp->ibqp_state, iwqp->last_aeq, iwqp->hw_iwarp_state, 2677 cqp_request->compl_info.maj_err_code, 2678 cqp_request->compl_info.min_err_code); 2679 put_cqp: 2680 irdma_put_cqp_request(&rf->cqp, cqp_request); 2681 2682 return status; 2683 } 2684 2685 /** 2686 * irdma_gen_ae - generate AE 2687 * @rf: RDMA PCI function 2688 * @qp: qp associated with AE 2689 * @info: info for ae 2690 * @wait: wait for completion 2691 */ 2692 void irdma_gen_ae(struct irdma_pci_f *rf, struct irdma_sc_qp *qp, 2693 struct irdma_gen_ae_info *info, bool wait) 2694 { 2695 struct irdma_gen_ae_info *ae_info; 2696 struct irdma_cqp_request *cqp_request; 2697 struct cqp_cmds_info *cqp_info; 2698 2699 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait); 2700 if (!cqp_request) 2701 return; 2702 2703 cqp_info = &cqp_request->info; 2704 ae_info = &cqp_request->info.in.u.gen_ae.info; 2705 memcpy(ae_info, info, sizeof(*ae_info)); 2706 cqp_info->cqp_cmd = IRDMA_OP_GEN_AE; 2707 cqp_info->post_sq = 1; 2708 cqp_info->in.u.gen_ae.qp = qp; 2709 cqp_info->in.u.gen_ae.scratch = (uintptr_t)cqp_request; 2710 2711 irdma_handle_cqp_op(rf, cqp_request); 2712 irdma_put_cqp_request(&rf->cqp, cqp_request); 2713 } 2714 2715 void irdma_flush_wqes(struct irdma_qp *iwqp, u32 flush_mask) 2716 { 2717 struct irdma_qp_flush_info info = {}; 2718 struct irdma_pci_f *rf = iwqp->iwdev->rf; 2719 u8 flush_code = iwqp->sc_qp.flush_code; 2720 2721 if (!(flush_mask & IRDMA_FLUSH_SQ) && !(flush_mask & IRDMA_FLUSH_RQ)) 2722 return; 2723 2724 /* Set flush info fields*/ 2725 info.sq = flush_mask & IRDMA_FLUSH_SQ; 2726 info.rq = flush_mask & IRDMA_FLUSH_RQ; 2727 2728 /* Generate userflush errors in CQE */ 2729 info.sq_major_code = IRDMA_FLUSH_MAJOR_ERR; 2730 info.sq_minor_code = FLUSH_GENERAL_ERR; 2731 info.rq_major_code = IRDMA_FLUSH_MAJOR_ERR; 2732 info.rq_minor_code = FLUSH_GENERAL_ERR; 2733 info.userflushcode = true; 2734 2735 if (flush_mask & IRDMA_REFLUSH) { 2736 if (info.sq) 2737 iwqp->sc_qp.flush_sq = false; 2738 if (info.rq) 2739 iwqp->sc_qp.flush_rq = false; 2740 } else { 2741 if (flush_code) { 2742 if (info.sq && iwqp->sc_qp.sq_flush_code) 2743 info.sq_minor_code = flush_code; 2744 if (info.rq && iwqp->sc_qp.rq_flush_code) 2745 info.rq_minor_code = flush_code; 2746 } 2747 if (!iwqp->user_mode) 2748 queue_delayed_work(iwqp->iwdev->cleanup_wq, 2749 &iwqp->dwork_flush, 2750 msecs_to_jiffies(IRDMA_FLUSH_DELAY_MS)); 2751 } 2752 2753 /* Issue flush */ 2754 (void)irdma_hw_flush_wqes(rf, &iwqp->sc_qp, &info, 2755 flush_mask & IRDMA_FLUSH_WAIT); 2756 iwqp->flush_issued = true; 2757 } 2758