1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 #include <linux/acpi.h> 34 #include <linux/module.h> 35 #include <linux/pci.h> 36 #include <rdma/ib_addr.h> 37 #include <rdma/ib_smi.h> 38 #include <rdma/ib_user_verbs.h> 39 #include <rdma/ib_cache.h> 40 #include "hns_roce_common.h" 41 #include "hns_roce_device.h" 42 #include "hns_roce_hem.h" 43 #include "hns_roce_hw_v2.h" 44 45 static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u32 port, 46 const u8 *addr) 47 { 48 u8 phy_port; 49 u32 i; 50 51 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 52 return 0; 53 54 if (!memcmp(hr_dev->dev_addr[port], addr, ETH_ALEN)) 55 return 0; 56 57 for (i = 0; i < ETH_ALEN; i++) 58 hr_dev->dev_addr[port][i] = addr[i]; 59 60 phy_port = hr_dev->iboe.phy_port[port]; 61 return hr_dev->hw->set_mac(hr_dev, phy_port, addr); 62 } 63 64 static int hns_roce_add_gid(const struct ib_gid_attr *attr, void **context) 65 { 66 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device); 67 u32 port = attr->port_num - 1; 68 int ret; 69 70 if (port >= hr_dev->caps.num_ports) 71 return -EINVAL; 72 73 ret = hr_dev->hw->set_gid(hr_dev, attr->index, &attr->gid, attr); 74 75 return ret; 76 } 77 78 static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context) 79 { 80 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device); 81 u32 port = attr->port_num - 1; 82 int ret; 83 84 if (port >= hr_dev->caps.num_ports) 85 return -EINVAL; 86 87 ret = hr_dev->hw->set_gid(hr_dev, attr->index, NULL, NULL); 88 89 return ret; 90 } 91 92 static int handle_en_event(struct hns_roce_dev *hr_dev, u32 port, 93 unsigned long event) 94 { 95 struct device *dev = hr_dev->dev; 96 struct net_device *netdev; 97 int ret = 0; 98 99 netdev = hr_dev->iboe.netdevs[port]; 100 if (!netdev) { 101 dev_err(dev, "can't find netdev on port(%u)!\n", port); 102 return -ENODEV; 103 } 104 105 switch (event) { 106 case NETDEV_UP: 107 case NETDEV_CHANGE: 108 case NETDEV_REGISTER: 109 case NETDEV_CHANGEADDR: 110 ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr); 111 break; 112 case NETDEV_DOWN: 113 /* 114 * In v1 engine, only support all ports closed together. 115 */ 116 break; 117 default: 118 dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event)); 119 break; 120 } 121 122 return ret; 123 } 124 125 static int hns_roce_netdev_event(struct notifier_block *self, 126 unsigned long event, void *ptr) 127 { 128 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 129 struct hns_roce_ib_iboe *iboe = NULL; 130 struct hns_roce_dev *hr_dev = NULL; 131 int ret; 132 u32 port; 133 134 hr_dev = container_of(self, struct hns_roce_dev, iboe.nb); 135 iboe = &hr_dev->iboe; 136 137 for (port = 0; port < hr_dev->caps.num_ports; port++) { 138 if (dev == iboe->netdevs[port]) { 139 ret = handle_en_event(hr_dev, port, event); 140 if (ret) 141 return NOTIFY_DONE; 142 break; 143 } 144 } 145 146 return NOTIFY_DONE; 147 } 148 149 static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev) 150 { 151 int ret; 152 u8 i; 153 154 for (i = 0; i < hr_dev->caps.num_ports; i++) { 155 ret = hns_roce_set_mac(hr_dev, i, 156 hr_dev->iboe.netdevs[i]->dev_addr); 157 if (ret) 158 return ret; 159 } 160 161 return 0; 162 } 163 164 static int hns_roce_query_device(struct ib_device *ib_dev, 165 struct ib_device_attr *props, 166 struct ib_udata *uhw) 167 { 168 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 169 170 memset(props, 0, sizeof(*props)); 171 172 props->fw_ver = hr_dev->caps.fw_ver; 173 props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid); 174 props->max_mr_size = (u64)(~(0ULL)); 175 props->page_size_cap = hr_dev->caps.page_size_cap; 176 props->vendor_id = hr_dev->vendor_id; 177 props->vendor_part_id = hr_dev->vendor_part_id; 178 props->hw_ver = hr_dev->hw_rev; 179 props->max_qp = hr_dev->caps.num_qps; 180 props->max_qp_wr = hr_dev->caps.max_wqes; 181 props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT | 182 IB_DEVICE_RC_RNR_NAK_GEN; 183 props->max_send_sge = hr_dev->caps.max_sq_sg; 184 props->max_recv_sge = hr_dev->caps.max_rq_sg; 185 props->max_sge_rd = hr_dev->caps.max_sq_sg; 186 props->max_cq = hr_dev->caps.num_cqs; 187 props->max_cqe = hr_dev->caps.max_cqes; 188 props->max_mr = hr_dev->caps.num_mtpts; 189 props->max_pd = hr_dev->caps.num_pds; 190 props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma; 191 props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma; 192 props->atomic_cap = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_ATOMIC ? 193 IB_ATOMIC_HCA : IB_ATOMIC_NONE; 194 props->max_pkeys = 1; 195 props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay; 196 props->max_ah = INT_MAX; 197 props->cq_caps.max_cq_moderation_period = HNS_ROCE_MAX_CQ_PERIOD; 198 props->cq_caps.max_cq_moderation_count = HNS_ROCE_MAX_CQ_COUNT; 199 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08) 200 props->cq_caps.max_cq_moderation_period = HNS_ROCE_MAX_CQ_PERIOD_HIP08; 201 202 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 203 props->max_srq = hr_dev->caps.num_srqs; 204 props->max_srq_wr = hr_dev->caps.max_srq_wrs; 205 props->max_srq_sge = hr_dev->caps.max_srq_sges; 206 } 207 208 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR && 209 hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { 210 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 211 props->max_fast_reg_page_list_len = HNS_ROCE_FRMR_MAX_PA; 212 } 213 214 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC) 215 props->device_cap_flags |= IB_DEVICE_XRC; 216 217 return 0; 218 } 219 220 static int hns_roce_query_port(struct ib_device *ib_dev, u32 port_num, 221 struct ib_port_attr *props) 222 { 223 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev); 224 struct device *dev = hr_dev->dev; 225 struct net_device *net_dev; 226 unsigned long flags; 227 enum ib_mtu mtu; 228 u32 port; 229 int ret; 230 231 port = port_num - 1; 232 233 /* props being zeroed by the caller, avoid zeroing it here */ 234 235 props->max_mtu = hr_dev->caps.max_mtu; 236 props->gid_tbl_len = hr_dev->caps.gid_table_len[port]; 237 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP | 238 IB_PORT_VENDOR_CLASS_SUP | 239 IB_PORT_BOOT_MGMT_SUP; 240 props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN; 241 props->pkey_tbl_len = 1; 242 ret = ib_get_eth_speed(ib_dev, port_num, &props->active_speed, 243 &props->active_width); 244 if (ret) 245 ibdev_warn(ib_dev, "failed to get speed, ret = %d.\n", ret); 246 247 spin_lock_irqsave(&hr_dev->iboe.lock, flags); 248 249 net_dev = hr_dev->iboe.netdevs[port]; 250 if (!net_dev) { 251 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 252 dev_err(dev, "find netdev %u failed!\n", port); 253 return -EINVAL; 254 } 255 256 mtu = iboe_get_mtu(net_dev->mtu); 257 props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256; 258 props->state = netif_running(net_dev) && netif_carrier_ok(net_dev) ? 259 IB_PORT_ACTIVE : 260 IB_PORT_DOWN; 261 props->phys_state = props->state == IB_PORT_ACTIVE ? 262 IB_PORT_PHYS_STATE_LINK_UP : 263 IB_PORT_PHYS_STATE_DISABLED; 264 265 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 266 267 return 0; 268 } 269 270 static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device, 271 u32 port_num) 272 { 273 return IB_LINK_LAYER_ETHERNET; 274 } 275 276 static int hns_roce_query_pkey(struct ib_device *ib_dev, u32 port, u16 index, 277 u16 *pkey) 278 { 279 if (index > 0) 280 return -EINVAL; 281 282 *pkey = PKEY_ID; 283 284 return 0; 285 } 286 287 static int hns_roce_modify_device(struct ib_device *ib_dev, int mask, 288 struct ib_device_modify *props) 289 { 290 unsigned long flags; 291 292 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 293 return -EOPNOTSUPP; 294 295 if (mask & IB_DEVICE_MODIFY_NODE_DESC) { 296 spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags); 297 memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE); 298 spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags); 299 } 300 301 return 0; 302 } 303 304 struct hns_user_mmap_entry * 305 hns_roce_user_mmap_entry_insert(struct ib_ucontext *ucontext, u64 address, 306 size_t length, 307 enum hns_roce_mmap_type mmap_type) 308 { 309 struct hns_user_mmap_entry *entry; 310 int ret; 311 312 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 313 if (!entry) 314 return NULL; 315 316 entry->address = address; 317 entry->mmap_type = mmap_type; 318 319 switch (mmap_type) { 320 /* pgoff 0 must be used by DB for compatibility */ 321 case HNS_ROCE_MMAP_TYPE_DB: 322 ret = rdma_user_mmap_entry_insert_exact( 323 ucontext, &entry->rdma_entry, length, 0); 324 break; 325 case HNS_ROCE_MMAP_TYPE_DWQE: 326 ret = rdma_user_mmap_entry_insert_range( 327 ucontext, &entry->rdma_entry, length, 1, 328 U32_MAX); 329 break; 330 default: 331 ret = -EINVAL; 332 break; 333 } 334 335 if (ret) { 336 kfree(entry); 337 return NULL; 338 } 339 340 return entry; 341 } 342 343 static void hns_roce_dealloc_uar_entry(struct hns_roce_ucontext *context) 344 { 345 if (context->db_mmap_entry) 346 rdma_user_mmap_entry_remove( 347 &context->db_mmap_entry->rdma_entry); 348 } 349 350 static int hns_roce_alloc_uar_entry(struct ib_ucontext *uctx) 351 { 352 struct hns_roce_ucontext *context = to_hr_ucontext(uctx); 353 u64 address; 354 355 address = context->uar.pfn << PAGE_SHIFT; 356 context->db_mmap_entry = hns_roce_user_mmap_entry_insert( 357 uctx, address, PAGE_SIZE, HNS_ROCE_MMAP_TYPE_DB); 358 if (!context->db_mmap_entry) 359 return -ENOMEM; 360 361 return 0; 362 } 363 364 static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx, 365 struct ib_udata *udata) 366 { 367 struct hns_roce_ucontext *context = to_hr_ucontext(uctx); 368 struct hns_roce_dev *hr_dev = to_hr_dev(uctx->device); 369 struct hns_roce_ib_alloc_ucontext_resp resp = {}; 370 struct hns_roce_ib_alloc_ucontext ucmd = {}; 371 int ret = -EAGAIN; 372 373 if (!hr_dev->active) 374 goto error_out; 375 376 resp.qp_tab_size = hr_dev->caps.num_qps; 377 resp.srq_tab_size = hr_dev->caps.num_srqs; 378 379 ret = ib_copy_from_udata(&ucmd, udata, 380 min(udata->inlen, sizeof(ucmd))); 381 if (ret) 382 goto error_out; 383 384 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 385 context->config = ucmd.config & HNS_ROCE_EXSGE_FLAGS; 386 387 if (context->config & HNS_ROCE_EXSGE_FLAGS) { 388 resp.config |= HNS_ROCE_RSP_EXSGE_FLAGS; 389 resp.max_inline_data = hr_dev->caps.max_sq_inline; 390 } 391 392 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) { 393 context->config |= ucmd.config & HNS_ROCE_RQ_INLINE_FLAGS; 394 if (context->config & HNS_ROCE_RQ_INLINE_FLAGS) 395 resp.config |= HNS_ROCE_RSP_RQ_INLINE_FLAGS; 396 } 397 398 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQE_INLINE) { 399 context->config |= ucmd.config & HNS_ROCE_CQE_INLINE_FLAGS; 400 if (context->config & HNS_ROCE_CQE_INLINE_FLAGS) 401 resp.config |= HNS_ROCE_RSP_CQE_INLINE_FLAGS; 402 } 403 404 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) 405 resp.congest_type = hr_dev->caps.cong_cap; 406 407 ret = hns_roce_uar_alloc(hr_dev, &context->uar); 408 if (ret) 409 goto error_out; 410 411 ret = hns_roce_alloc_uar_entry(uctx); 412 if (ret) 413 goto error_fail_uar_entry; 414 415 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB || 416 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) { 417 INIT_LIST_HEAD(&context->page_list); 418 mutex_init(&context->page_mutex); 419 } 420 421 resp.cqe_size = hr_dev->caps.cqe_sz; 422 423 ret = ib_copy_to_udata(udata, &resp, 424 min(udata->outlen, sizeof(resp))); 425 if (ret) 426 goto error_fail_copy_to_udata; 427 428 return 0; 429 430 error_fail_copy_to_udata: 431 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB || 432 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) 433 mutex_destroy(&context->page_mutex); 434 hns_roce_dealloc_uar_entry(context); 435 436 error_fail_uar_entry: 437 ida_free(&hr_dev->uar_ida.ida, (int)context->uar.logic_idx); 438 439 error_out: 440 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_UCTX_ALLOC_ERR_CNT]); 441 442 return ret; 443 } 444 445 static void hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext) 446 { 447 struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext); 448 struct hns_roce_dev *hr_dev = to_hr_dev(ibcontext->device); 449 450 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB || 451 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) 452 mutex_destroy(&context->page_mutex); 453 454 hns_roce_dealloc_uar_entry(context); 455 456 ida_free(&hr_dev->uar_ida.ida, (int)context->uar.logic_idx); 457 } 458 459 static int hns_roce_mmap(struct ib_ucontext *uctx, struct vm_area_struct *vma) 460 { 461 struct hns_roce_dev *hr_dev = to_hr_dev(uctx->device); 462 struct rdma_user_mmap_entry *rdma_entry; 463 struct hns_user_mmap_entry *entry; 464 phys_addr_t pfn; 465 pgprot_t prot; 466 int ret; 467 468 if (hr_dev->dis_db) { 469 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_MMAP_ERR_CNT]); 470 return -EPERM; 471 } 472 473 rdma_entry = rdma_user_mmap_entry_get_pgoff(uctx, vma->vm_pgoff); 474 if (!rdma_entry) { 475 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_MMAP_ERR_CNT]); 476 return -EINVAL; 477 } 478 479 entry = to_hns_mmap(rdma_entry); 480 pfn = entry->address >> PAGE_SHIFT; 481 482 switch (entry->mmap_type) { 483 case HNS_ROCE_MMAP_TYPE_DB: 484 case HNS_ROCE_MMAP_TYPE_DWQE: 485 prot = pgprot_device(vma->vm_page_prot); 486 break; 487 default: 488 ret = -EINVAL; 489 goto out; 490 } 491 492 ret = rdma_user_mmap_io(uctx, vma, pfn, rdma_entry->npages * PAGE_SIZE, 493 prot, rdma_entry); 494 495 out: 496 rdma_user_mmap_entry_put(rdma_entry); 497 if (ret) 498 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_MMAP_ERR_CNT]); 499 500 return ret; 501 } 502 503 static void hns_roce_free_mmap(struct rdma_user_mmap_entry *rdma_entry) 504 { 505 struct hns_user_mmap_entry *entry = to_hns_mmap(rdma_entry); 506 507 kfree(entry); 508 } 509 510 static int hns_roce_port_immutable(struct ib_device *ib_dev, u32 port_num, 511 struct ib_port_immutable *immutable) 512 { 513 struct ib_port_attr attr; 514 int ret; 515 516 ret = ib_query_port(ib_dev, port_num, &attr); 517 if (ret) 518 return ret; 519 520 immutable->pkey_tbl_len = attr.pkey_tbl_len; 521 immutable->gid_tbl_len = attr.gid_tbl_len; 522 523 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 524 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 525 if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2) 526 immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 527 528 return 0; 529 } 530 531 static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext) 532 { 533 } 534 535 static void hns_roce_get_fw_ver(struct ib_device *device, char *str) 536 { 537 u64 fw_ver = to_hr_dev(device)->caps.fw_ver; 538 unsigned int major, minor, sub_minor; 539 540 major = upper_32_bits(fw_ver); 541 minor = high_16_bits(lower_32_bits(fw_ver)); 542 sub_minor = low_16_bits(fw_ver); 543 544 snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u.%04u", major, minor, 545 sub_minor); 546 } 547 548 #define HNS_ROCE_HW_CNT(ename, cname) \ 549 [HNS_ROCE_HW_##ename##_CNT].name = cname 550 551 static const struct rdma_stat_desc hns_roce_port_stats_descs[] = { 552 HNS_ROCE_HW_CNT(RX_RC_PKT, "rx_rc_pkt"), 553 HNS_ROCE_HW_CNT(RX_UC_PKT, "rx_uc_pkt"), 554 HNS_ROCE_HW_CNT(RX_UD_PKT, "rx_ud_pkt"), 555 HNS_ROCE_HW_CNT(RX_XRC_PKT, "rx_xrc_pkt"), 556 HNS_ROCE_HW_CNT(RX_PKT, "rx_pkt"), 557 HNS_ROCE_HW_CNT(RX_ERR_PKT, "rx_err_pkt"), 558 HNS_ROCE_HW_CNT(RX_CNP_PKT, "rx_cnp_pkt"), 559 HNS_ROCE_HW_CNT(TX_RC_PKT, "tx_rc_pkt"), 560 HNS_ROCE_HW_CNT(TX_UC_PKT, "tx_uc_pkt"), 561 HNS_ROCE_HW_CNT(TX_UD_PKT, "tx_ud_pkt"), 562 HNS_ROCE_HW_CNT(TX_XRC_PKT, "tx_xrc_pkt"), 563 HNS_ROCE_HW_CNT(TX_PKT, "tx_pkt"), 564 HNS_ROCE_HW_CNT(TX_ERR_PKT, "tx_err_pkt"), 565 HNS_ROCE_HW_CNT(TX_CNP_PKT, "tx_cnp_pkt"), 566 HNS_ROCE_HW_CNT(TRP_GET_MPT_ERR_PKT, "trp_get_mpt_err_pkt"), 567 HNS_ROCE_HW_CNT(TRP_GET_IRRL_ERR_PKT, "trp_get_irrl_err_pkt"), 568 HNS_ROCE_HW_CNT(ECN_DB, "ecn_doorbell"), 569 HNS_ROCE_HW_CNT(RX_BUF, "rx_buffer"), 570 HNS_ROCE_HW_CNT(TRP_RX_SOF, "trp_rx_sof"), 571 HNS_ROCE_HW_CNT(CQ_CQE, "cq_cqe"), 572 HNS_ROCE_HW_CNT(CQ_POE, "cq_poe"), 573 HNS_ROCE_HW_CNT(CQ_NOTIFY, "cq_notify"), 574 }; 575 576 static struct rdma_hw_stats *hns_roce_alloc_hw_port_stats( 577 struct ib_device *device, u32 port_num) 578 { 579 struct hns_roce_dev *hr_dev = to_hr_dev(device); 580 581 if (port_num > hr_dev->caps.num_ports) { 582 ibdev_err(device, "invalid port num.\n"); 583 return NULL; 584 } 585 586 return rdma_alloc_hw_stats_struct(hns_roce_port_stats_descs, 587 ARRAY_SIZE(hns_roce_port_stats_descs), 588 RDMA_HW_STATS_DEFAULT_LIFESPAN); 589 } 590 591 static int hns_roce_get_hw_stats(struct ib_device *device, 592 struct rdma_hw_stats *stats, 593 u32 port, int index) 594 { 595 struct hns_roce_dev *hr_dev = to_hr_dev(device); 596 int num_counters = HNS_ROCE_HW_CNT_TOTAL; 597 int ret; 598 599 if (port == 0) 600 return 0; 601 602 if (port > hr_dev->caps.num_ports) 603 return -EINVAL; 604 605 ret = hr_dev->hw->query_hw_counter(hr_dev, stats->value, port, 606 &num_counters); 607 if (ret) { 608 ibdev_err(device, "failed to query hw counter, ret = %d\n", 609 ret); 610 return ret; 611 } 612 613 return num_counters; 614 } 615 616 static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev) 617 { 618 struct hns_roce_ib_iboe *iboe = &hr_dev->iboe; 619 620 hr_dev->active = false; 621 unregister_netdevice_notifier(&iboe->nb); 622 ib_unregister_device(&hr_dev->ib_dev); 623 } 624 625 static const struct ib_device_ops hns_roce_dev_ops = { 626 .owner = THIS_MODULE, 627 .driver_id = RDMA_DRIVER_HNS, 628 .uverbs_abi_ver = 1, 629 .uverbs_no_driver_id_binding = 1, 630 631 .get_dev_fw_str = hns_roce_get_fw_ver, 632 .add_gid = hns_roce_add_gid, 633 .alloc_pd = hns_roce_alloc_pd, 634 .alloc_ucontext = hns_roce_alloc_ucontext, 635 .create_ah = hns_roce_create_ah, 636 .create_user_ah = hns_roce_create_ah, 637 .create_cq = hns_roce_create_cq, 638 .create_qp = hns_roce_create_qp, 639 .dealloc_pd = hns_roce_dealloc_pd, 640 .dealloc_ucontext = hns_roce_dealloc_ucontext, 641 .del_gid = hns_roce_del_gid, 642 .dereg_mr = hns_roce_dereg_mr, 643 .destroy_ah = hns_roce_destroy_ah, 644 .destroy_cq = hns_roce_destroy_cq, 645 .disassociate_ucontext = hns_roce_disassociate_ucontext, 646 .get_dma_mr = hns_roce_get_dma_mr, 647 .get_link_layer = hns_roce_get_link_layer, 648 .get_port_immutable = hns_roce_port_immutable, 649 .mmap = hns_roce_mmap, 650 .mmap_free = hns_roce_free_mmap, 651 .modify_device = hns_roce_modify_device, 652 .modify_qp = hns_roce_modify_qp, 653 .query_ah = hns_roce_query_ah, 654 .query_device = hns_roce_query_device, 655 .query_pkey = hns_roce_query_pkey, 656 .query_port = hns_roce_query_port, 657 .reg_user_mr = hns_roce_reg_user_mr, 658 659 INIT_RDMA_OBJ_SIZE(ib_ah, hns_roce_ah, ibah), 660 INIT_RDMA_OBJ_SIZE(ib_cq, hns_roce_cq, ib_cq), 661 INIT_RDMA_OBJ_SIZE(ib_pd, hns_roce_pd, ibpd), 662 INIT_RDMA_OBJ_SIZE(ib_qp, hns_roce_qp, ibqp), 663 INIT_RDMA_OBJ_SIZE(ib_ucontext, hns_roce_ucontext, ibucontext), 664 }; 665 666 static const struct ib_device_ops hns_roce_dev_hw_stats_ops = { 667 .alloc_hw_port_stats = hns_roce_alloc_hw_port_stats, 668 .get_hw_stats = hns_roce_get_hw_stats, 669 }; 670 671 static const struct ib_device_ops hns_roce_dev_mr_ops = { 672 .rereg_user_mr = hns_roce_rereg_user_mr, 673 }; 674 675 static const struct ib_device_ops hns_roce_dev_mw_ops = { 676 .alloc_mw = hns_roce_alloc_mw, 677 .dealloc_mw = hns_roce_dealloc_mw, 678 679 INIT_RDMA_OBJ_SIZE(ib_mw, hns_roce_mw, ibmw), 680 }; 681 682 static const struct ib_device_ops hns_roce_dev_frmr_ops = { 683 .alloc_mr = hns_roce_alloc_mr, 684 .map_mr_sg = hns_roce_map_mr_sg, 685 }; 686 687 static const struct ib_device_ops hns_roce_dev_srq_ops = { 688 .create_srq = hns_roce_create_srq, 689 .destroy_srq = hns_roce_destroy_srq, 690 691 INIT_RDMA_OBJ_SIZE(ib_srq, hns_roce_srq, ibsrq), 692 }; 693 694 static const struct ib_device_ops hns_roce_dev_xrcd_ops = { 695 .alloc_xrcd = hns_roce_alloc_xrcd, 696 .dealloc_xrcd = hns_roce_dealloc_xrcd, 697 698 INIT_RDMA_OBJ_SIZE(ib_xrcd, hns_roce_xrcd, ibxrcd), 699 }; 700 701 static const struct ib_device_ops hns_roce_dev_restrack_ops = { 702 .fill_res_cq_entry = hns_roce_fill_res_cq_entry, 703 .fill_res_cq_entry_raw = hns_roce_fill_res_cq_entry_raw, 704 .fill_res_qp_entry = hns_roce_fill_res_qp_entry, 705 .fill_res_qp_entry_raw = hns_roce_fill_res_qp_entry_raw, 706 .fill_res_mr_entry = hns_roce_fill_res_mr_entry, 707 .fill_res_mr_entry_raw = hns_roce_fill_res_mr_entry_raw, 708 .fill_res_srq_entry = hns_roce_fill_res_srq_entry, 709 .fill_res_srq_entry_raw = hns_roce_fill_res_srq_entry_raw, 710 }; 711 712 static int hns_roce_register_device(struct hns_roce_dev *hr_dev) 713 { 714 int ret; 715 struct hns_roce_ib_iboe *iboe = NULL; 716 struct ib_device *ib_dev = NULL; 717 struct device *dev = hr_dev->dev; 718 unsigned int i; 719 720 iboe = &hr_dev->iboe; 721 spin_lock_init(&iboe->lock); 722 723 ib_dev = &hr_dev->ib_dev; 724 725 ib_dev->node_type = RDMA_NODE_IB_CA; 726 ib_dev->dev.parent = dev; 727 728 ib_dev->phys_port_cnt = hr_dev->caps.num_ports; 729 ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey; 730 ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors; 731 732 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR) 733 ib_set_device_ops(ib_dev, &hns_roce_dev_mr_ops); 734 735 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_MW) 736 ib_set_device_ops(ib_dev, &hns_roce_dev_mw_ops); 737 738 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR) 739 ib_set_device_ops(ib_dev, &hns_roce_dev_frmr_ops); 740 741 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 742 ib_set_device_ops(ib_dev, &hns_roce_dev_srq_ops); 743 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_srq_ops); 744 } 745 746 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC) 747 ib_set_device_ops(ib_dev, &hns_roce_dev_xrcd_ops); 748 749 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09 && 750 !hr_dev->is_vf) 751 ib_set_device_ops(ib_dev, &hns_roce_dev_hw_stats_ops); 752 753 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_ops); 754 ib_set_device_ops(ib_dev, &hns_roce_dev_ops); 755 ib_set_device_ops(ib_dev, &hns_roce_dev_restrack_ops); 756 for (i = 0; i < hr_dev->caps.num_ports; i++) { 757 if (!hr_dev->iboe.netdevs[i]) 758 continue; 759 760 ret = ib_device_set_netdev(ib_dev, hr_dev->iboe.netdevs[i], 761 i + 1); 762 if (ret) 763 return ret; 764 } 765 dma_set_max_seg_size(dev, SZ_2G); 766 ret = ib_register_device(ib_dev, "hns_%d", dev); 767 if (ret) { 768 dev_err(dev, "ib_register_device failed!\n"); 769 return ret; 770 } 771 772 ret = hns_roce_setup_mtu_mac(hr_dev); 773 if (ret) { 774 dev_err(dev, "setup_mtu_mac failed!\n"); 775 goto error_failed_setup_mtu_mac; 776 } 777 778 iboe->nb.notifier_call = hns_roce_netdev_event; 779 ret = register_netdevice_notifier(&iboe->nb); 780 if (ret) { 781 dev_err(dev, "register_netdevice_notifier failed!\n"); 782 goto error_failed_setup_mtu_mac; 783 } 784 785 hr_dev->active = true; 786 return 0; 787 788 error_failed_setup_mtu_mac: 789 ib_unregister_device(ib_dev); 790 791 return ret; 792 } 793 794 static int hns_roce_init_hem(struct hns_roce_dev *hr_dev) 795 { 796 struct device *dev = hr_dev->dev; 797 int ret; 798 799 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table, 800 HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz, 801 hr_dev->caps.num_mtpts); 802 if (ret) { 803 dev_err(dev, "failed to init MTPT context memory, aborting.\n"); 804 return ret; 805 } 806 807 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table, 808 HEM_TYPE_QPC, hr_dev->caps.qpc_sz, 809 hr_dev->caps.num_qps); 810 if (ret) { 811 dev_err(dev, "failed to init QP context memory, aborting.\n"); 812 goto err_unmap_dmpt; 813 } 814 815 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table, 816 HEM_TYPE_IRRL, 817 hr_dev->caps.irrl_entry_sz * 818 hr_dev->caps.max_qp_init_rdma, 819 hr_dev->caps.num_qps); 820 if (ret) { 821 dev_err(dev, "failed to init irrl_table memory, aborting.\n"); 822 goto err_unmap_qp; 823 } 824 825 if (hr_dev->caps.trrl_entry_sz) { 826 ret = hns_roce_init_hem_table(hr_dev, 827 &hr_dev->qp_table.trrl_table, 828 HEM_TYPE_TRRL, 829 hr_dev->caps.trrl_entry_sz * 830 hr_dev->caps.max_qp_dest_rdma, 831 hr_dev->caps.num_qps); 832 if (ret) { 833 dev_err(dev, 834 "failed to init trrl_table memory, aborting.\n"); 835 goto err_unmap_irrl; 836 } 837 } 838 839 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table, 840 HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz, 841 hr_dev->caps.num_cqs); 842 if (ret) { 843 dev_err(dev, "failed to init CQ context memory, aborting.\n"); 844 goto err_unmap_trrl; 845 } 846 847 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) { 848 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->srq_table.table, 849 HEM_TYPE_SRQC, 850 hr_dev->caps.srqc_entry_sz, 851 hr_dev->caps.num_srqs); 852 if (ret) { 853 dev_err(dev, 854 "failed to init SRQ context memory, aborting.\n"); 855 goto err_unmap_cq; 856 } 857 } 858 859 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) { 860 ret = hns_roce_init_hem_table(hr_dev, 861 &hr_dev->qp_table.sccc_table, 862 HEM_TYPE_SCCC, 863 hr_dev->caps.sccc_sz, 864 hr_dev->caps.num_qps); 865 if (ret) { 866 dev_err(dev, 867 "failed to init SCC context memory, aborting.\n"); 868 goto err_unmap_srq; 869 } 870 } 871 872 if (hr_dev->caps.qpc_timer_entry_sz) { 873 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qpc_timer_table, 874 HEM_TYPE_QPC_TIMER, 875 hr_dev->caps.qpc_timer_entry_sz, 876 hr_dev->caps.qpc_timer_bt_num); 877 if (ret) { 878 dev_err(dev, 879 "failed to init QPC timer memory, aborting.\n"); 880 goto err_unmap_ctx; 881 } 882 } 883 884 if (hr_dev->caps.cqc_timer_entry_sz) { 885 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cqc_timer_table, 886 HEM_TYPE_CQC_TIMER, 887 hr_dev->caps.cqc_timer_entry_sz, 888 hr_dev->caps.cqc_timer_bt_num); 889 if (ret) { 890 dev_err(dev, 891 "failed to init CQC timer memory, aborting.\n"); 892 goto err_unmap_qpc_timer; 893 } 894 } 895 896 if (hr_dev->caps.gmv_entry_sz) { 897 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->gmv_table, 898 HEM_TYPE_GMV, 899 hr_dev->caps.gmv_entry_sz, 900 hr_dev->caps.gmv_entry_num); 901 if (ret) { 902 dev_err(dev, 903 "failed to init gmv table memory, ret = %d\n", 904 ret); 905 goto err_unmap_cqc_timer; 906 } 907 } 908 909 return 0; 910 911 err_unmap_cqc_timer: 912 if (hr_dev->caps.cqc_timer_entry_sz) 913 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cqc_timer_table); 914 915 err_unmap_qpc_timer: 916 if (hr_dev->caps.qpc_timer_entry_sz) 917 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qpc_timer_table); 918 919 err_unmap_ctx: 920 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) 921 hns_roce_cleanup_hem_table(hr_dev, 922 &hr_dev->qp_table.sccc_table); 923 err_unmap_srq: 924 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) 925 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->srq_table.table); 926 927 err_unmap_cq: 928 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table); 929 930 err_unmap_trrl: 931 if (hr_dev->caps.trrl_entry_sz) 932 hns_roce_cleanup_hem_table(hr_dev, 933 &hr_dev->qp_table.trrl_table); 934 935 err_unmap_irrl: 936 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table); 937 938 err_unmap_qp: 939 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table); 940 941 err_unmap_dmpt: 942 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table); 943 944 return ret; 945 } 946 947 static void hns_roce_teardown_hca(struct hns_roce_dev *hr_dev) 948 { 949 hns_roce_cleanup_bitmap(hr_dev); 950 951 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB || 952 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) 953 mutex_destroy(&hr_dev->pgdir_mutex); 954 } 955 956 /** 957 * hns_roce_setup_hca - setup host channel adapter 958 * @hr_dev: pointer to hns roce device 959 * Return : int 960 */ 961 static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev) 962 { 963 struct device *dev = hr_dev->dev; 964 int ret; 965 966 spin_lock_init(&hr_dev->sm_lock); 967 968 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB || 969 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) { 970 INIT_LIST_HEAD(&hr_dev->pgdir_list); 971 mutex_init(&hr_dev->pgdir_mutex); 972 } 973 974 hns_roce_init_uar_table(hr_dev); 975 976 ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar); 977 if (ret) { 978 dev_err(dev, "failed to allocate priv_uar.\n"); 979 goto err_uar_table_free; 980 } 981 982 ret = hns_roce_init_qp_table(hr_dev); 983 if (ret) { 984 dev_err(dev, "failed to init qp_table.\n"); 985 goto err_uar_table_free; 986 } 987 988 hns_roce_init_pd_table(hr_dev); 989 990 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC) 991 hns_roce_init_xrcd_table(hr_dev); 992 993 hns_roce_init_mr_table(hr_dev); 994 995 hns_roce_init_cq_table(hr_dev); 996 997 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) 998 hns_roce_init_srq_table(hr_dev); 999 1000 return 0; 1001 1002 err_uar_table_free: 1003 ida_destroy(&hr_dev->uar_ida.ida); 1004 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB || 1005 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) 1006 mutex_destroy(&hr_dev->pgdir_mutex); 1007 1008 return ret; 1009 } 1010 1011 static void check_and_get_armed_cq(struct list_head *cq_list, struct ib_cq *cq) 1012 { 1013 struct hns_roce_cq *hr_cq = to_hr_cq(cq); 1014 unsigned long flags; 1015 1016 spin_lock_irqsave(&hr_cq->lock, flags); 1017 if (cq->comp_handler) { 1018 if (!hr_cq->is_armed) { 1019 hr_cq->is_armed = 1; 1020 list_add_tail(&hr_cq->node, cq_list); 1021 } 1022 } 1023 spin_unlock_irqrestore(&hr_cq->lock, flags); 1024 } 1025 1026 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev) 1027 { 1028 struct hns_roce_qp *hr_qp; 1029 struct hns_roce_cq *hr_cq; 1030 struct list_head cq_list; 1031 unsigned long flags_qp; 1032 unsigned long flags; 1033 1034 INIT_LIST_HEAD(&cq_list); 1035 1036 spin_lock_irqsave(&hr_dev->qp_list_lock, flags); 1037 list_for_each_entry(hr_qp, &hr_dev->qp_list, node) { 1038 spin_lock_irqsave(&hr_qp->sq.lock, flags_qp); 1039 if (hr_qp->sq.tail != hr_qp->sq.head) 1040 check_and_get_armed_cq(&cq_list, hr_qp->ibqp.send_cq); 1041 spin_unlock_irqrestore(&hr_qp->sq.lock, flags_qp); 1042 1043 spin_lock_irqsave(&hr_qp->rq.lock, flags_qp); 1044 if ((!hr_qp->ibqp.srq) && (hr_qp->rq.tail != hr_qp->rq.head)) 1045 check_and_get_armed_cq(&cq_list, hr_qp->ibqp.recv_cq); 1046 spin_unlock_irqrestore(&hr_qp->rq.lock, flags_qp); 1047 } 1048 1049 list_for_each_entry(hr_cq, &cq_list, node) 1050 hns_roce_cq_completion(hr_dev, hr_cq->cqn); 1051 1052 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); 1053 } 1054 1055 static int hns_roce_alloc_dfx_cnt(struct hns_roce_dev *hr_dev) 1056 { 1057 hr_dev->dfx_cnt = kvcalloc(HNS_ROCE_DFX_CNT_TOTAL, sizeof(atomic64_t), 1058 GFP_KERNEL); 1059 if (!hr_dev->dfx_cnt) 1060 return -ENOMEM; 1061 1062 return 0; 1063 } 1064 1065 static void hns_roce_dealloc_dfx_cnt(struct hns_roce_dev *hr_dev) 1066 { 1067 kvfree(hr_dev->dfx_cnt); 1068 } 1069 1070 int hns_roce_init(struct hns_roce_dev *hr_dev) 1071 { 1072 struct device *dev = hr_dev->dev; 1073 int ret; 1074 1075 hr_dev->is_reset = false; 1076 1077 ret = hns_roce_alloc_dfx_cnt(hr_dev); 1078 if (ret) 1079 return ret; 1080 1081 if (hr_dev->hw->cmq_init) { 1082 ret = hr_dev->hw->cmq_init(hr_dev); 1083 if (ret) { 1084 dev_err(dev, "init RoCE Command Queue failed!\n"); 1085 goto error_failed_alloc_dfx_cnt; 1086 } 1087 } 1088 1089 ret = hr_dev->hw->hw_profile(hr_dev); 1090 if (ret) { 1091 dev_err(dev, "get RoCE engine profile failed!\n"); 1092 goto error_failed_cmd_init; 1093 } 1094 1095 ret = hns_roce_cmd_init(hr_dev); 1096 if (ret) { 1097 dev_err(dev, "cmd init failed!\n"); 1098 goto error_failed_cmd_init; 1099 } 1100 1101 /* EQ depends on poll mode, event mode depends on EQ */ 1102 ret = hr_dev->hw->init_eq(hr_dev); 1103 if (ret) { 1104 dev_err(dev, "eq init failed!\n"); 1105 goto error_failed_eq_table; 1106 } 1107 1108 if (hr_dev->cmd_mod) { 1109 ret = hns_roce_cmd_use_events(hr_dev); 1110 if (ret) 1111 dev_warn(dev, 1112 "Cmd event mode failed, set back to poll!\n"); 1113 } 1114 1115 ret = hns_roce_init_hem(hr_dev); 1116 if (ret) { 1117 dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n"); 1118 goto error_failed_init_hem; 1119 } 1120 1121 ret = hns_roce_setup_hca(hr_dev); 1122 if (ret) { 1123 dev_err(dev, "setup hca failed!\n"); 1124 goto error_failed_setup_hca; 1125 } 1126 1127 if (hr_dev->hw->hw_init) { 1128 ret = hr_dev->hw->hw_init(hr_dev); 1129 if (ret) { 1130 dev_err(dev, "hw_init failed!\n"); 1131 goto error_failed_engine_init; 1132 } 1133 } 1134 1135 INIT_LIST_HEAD(&hr_dev->qp_list); 1136 spin_lock_init(&hr_dev->qp_list_lock); 1137 1138 ret = hns_roce_register_device(hr_dev); 1139 if (ret) 1140 goto error_failed_register_device; 1141 1142 hns_roce_register_debugfs(hr_dev); 1143 1144 return 0; 1145 1146 error_failed_register_device: 1147 if (hr_dev->hw->hw_exit) 1148 hr_dev->hw->hw_exit(hr_dev); 1149 1150 error_failed_engine_init: 1151 hns_roce_teardown_hca(hr_dev); 1152 1153 error_failed_setup_hca: 1154 hns_roce_cleanup_hem(hr_dev); 1155 1156 error_failed_init_hem: 1157 if (hr_dev->cmd_mod) 1158 hns_roce_cmd_use_polling(hr_dev); 1159 hr_dev->hw->cleanup_eq(hr_dev); 1160 1161 error_failed_eq_table: 1162 hns_roce_cmd_cleanup(hr_dev); 1163 1164 error_failed_cmd_init: 1165 if (hr_dev->hw->cmq_exit) 1166 hr_dev->hw->cmq_exit(hr_dev); 1167 1168 error_failed_alloc_dfx_cnt: 1169 hns_roce_dealloc_dfx_cnt(hr_dev); 1170 1171 return ret; 1172 } 1173 1174 void hns_roce_exit(struct hns_roce_dev *hr_dev) 1175 { 1176 hns_roce_unregister_debugfs(hr_dev); 1177 hns_roce_unregister_device(hr_dev); 1178 1179 if (hr_dev->hw->hw_exit) 1180 hr_dev->hw->hw_exit(hr_dev); 1181 hns_roce_teardown_hca(hr_dev); 1182 hns_roce_cleanup_hem(hr_dev); 1183 1184 if (hr_dev->cmd_mod) 1185 hns_roce_cmd_use_polling(hr_dev); 1186 1187 hr_dev->hw->cleanup_eq(hr_dev); 1188 hns_roce_cmd_cleanup(hr_dev); 1189 if (hr_dev->hw->cmq_exit) 1190 hr_dev->hw->cmq_exit(hr_dev); 1191 hns_roce_dealloc_dfx_cnt(hr_dev); 1192 } 1193 1194 MODULE_LICENSE("Dual BSD/GPL"); 1195 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); 1196 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>"); 1197 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); 1198 MODULE_DESCRIPTION("HNS RoCE Driver"); 1199