1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: Main component of the bnxt_re driver 37 */ 38 39 #include <linux/module.h> 40 #include <linux/netdevice.h> 41 #include <linux/ethtool.h> 42 #include <linux/mutex.h> 43 #include <linux/list.h> 44 #include <linux/rculist.h> 45 #include <linux/spinlock.h> 46 #include <linux/pci.h> 47 #include <net/dcbnl.h> 48 #include <net/ipv6.h> 49 #include <net/addrconf.h> 50 #include <linux/if_ether.h> 51 #include <linux/auxiliary_bus.h> 52 53 #include <rdma/ib_verbs.h> 54 #include <rdma/ib_user_verbs.h> 55 #include <rdma/ib_umem.h> 56 #include <rdma/ib_addr.h> 57 #include <linux/hashtable.h> 58 59 #include "bnxt_ulp.h" 60 #include "roce_hsi.h" 61 #include "qplib_res.h" 62 #include "qplib_sp.h" 63 #include "qplib_fp.h" 64 #include "qplib_rcfw.h" 65 #include "bnxt_re.h" 66 #include "ib_verbs.h" 67 #include <rdma/bnxt_re-abi.h> 68 #include "bnxt.h" 69 #include "hw_counters.h" 70 #include "debugfs.h" 71 72 static char version[] = 73 BNXT_RE_DESC "\n"; 74 75 MODULE_AUTHOR("Eddie Wai <eddie.wai@broadcom.com>"); 76 MODULE_DESCRIPTION(BNXT_RE_DESC); 77 MODULE_LICENSE("Dual BSD/GPL"); 78 79 /* globals */ 80 static DEFINE_MUTEX(bnxt_re_mutex); 81 82 static int bnxt_re_hwrm_qcaps(struct bnxt_re_dev *rdev); 83 84 static int bnxt_re_hwrm_qcfg(struct bnxt_re_dev *rdev, u32 *db_len, 85 u32 *offset); 86 static void bnxt_re_dispatch_event(struct ib_device *ibdev, struct ib_qp *qp, 87 u8 port_num, enum ib_event_type event); 88 static void bnxt_re_set_db_offset(struct bnxt_re_dev *rdev) 89 { 90 struct bnxt_qplib_chip_ctx *cctx; 91 struct bnxt_en_dev *en_dev; 92 struct bnxt_qplib_res *res; 93 u32 l2db_len = 0; 94 u32 offset = 0; 95 u32 barlen; 96 int rc; 97 98 res = &rdev->qplib_res; 99 en_dev = rdev->en_dev; 100 cctx = rdev->chip_ctx; 101 102 /* Issue qcfg */ 103 rc = bnxt_re_hwrm_qcfg(rdev, &l2db_len, &offset); 104 if (rc) 105 dev_info(rdev_to_dev(rdev), 106 "Couldn't get DB bar size, Low latency framework is disabled\n"); 107 /* set register offsets for both UC and WC */ 108 if (bnxt_qplib_is_chip_gen_p7(cctx)) { 109 res->dpi_tbl.ucreg.offset = offset; 110 res->dpi_tbl.wcreg.offset = en_dev->l2_db_size; 111 } else { 112 res->dpi_tbl.ucreg.offset = res->is_vf ? BNXT_QPLIB_DBR_VF_DB_OFFSET : 113 BNXT_QPLIB_DBR_PF_DB_OFFSET; 114 res->dpi_tbl.wcreg.offset = res->dpi_tbl.ucreg.offset; 115 } 116 117 /* If WC mapping is disabled by L2 driver then en_dev->l2_db_size 118 * is equal to the DB-Bar actual size. This indicates that L2 119 * is mapping entire bar as UC-. RoCE driver can't enable WC mapping 120 * in such cases and DB-push will be disabled. 121 */ 122 barlen = pci_resource_len(res->pdev, RCFW_DBR_PCI_BAR_REGION); 123 if (cctx->modes.db_push && l2db_len && en_dev->l2_db_size != barlen) { 124 res->dpi_tbl.wcreg.offset = en_dev->l2_db_size; 125 dev_info(rdev_to_dev(rdev), "Low latency framework is enabled\n"); 126 } 127 } 128 129 static void bnxt_re_set_drv_mode(struct bnxt_re_dev *rdev) 130 { 131 struct bnxt_qplib_chip_ctx *cctx; 132 133 cctx = rdev->chip_ctx; 134 cctx->modes.wqe_mode = bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx) ? 135 BNXT_QPLIB_WQE_MODE_VARIABLE : BNXT_QPLIB_WQE_MODE_STATIC; 136 if (bnxt_re_hwrm_qcaps(rdev)) 137 dev_err(rdev_to_dev(rdev), 138 "Failed to query hwrm qcaps\n"); 139 if (bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx)) { 140 cctx->modes.toggle_bits |= BNXT_QPLIB_CQ_TOGGLE_BIT; 141 cctx->modes.toggle_bits |= BNXT_QPLIB_SRQ_TOGGLE_BIT; 142 } 143 } 144 145 static void bnxt_re_destroy_chip_ctx(struct bnxt_re_dev *rdev) 146 { 147 struct bnxt_qplib_chip_ctx *chip_ctx; 148 149 if (!rdev->chip_ctx) 150 return; 151 152 kfree(rdev->dev_attr); 153 rdev->dev_attr = NULL; 154 155 chip_ctx = rdev->chip_ctx; 156 rdev->chip_ctx = NULL; 157 rdev->rcfw.res = NULL; 158 rdev->qplib_res.cctx = NULL; 159 rdev->qplib_res.pdev = NULL; 160 rdev->qplib_res.netdev = NULL; 161 kfree(chip_ctx); 162 } 163 164 static int bnxt_re_setup_chip_ctx(struct bnxt_re_dev *rdev) 165 { 166 struct bnxt_qplib_chip_ctx *chip_ctx; 167 struct bnxt_en_dev *en_dev; 168 int rc = -ENOMEM; 169 170 en_dev = rdev->en_dev; 171 172 rdev->qplib_res.pdev = en_dev->pdev; 173 chip_ctx = kzalloc(sizeof(*chip_ctx), GFP_KERNEL); 174 if (!chip_ctx) 175 return -ENOMEM; 176 chip_ctx->chip_num = en_dev->chip_num; 177 chip_ctx->hw_stats_size = en_dev->hw_ring_stats_size; 178 179 rdev->chip_ctx = chip_ctx; 180 /* rest members to follow eventually */ 181 182 rdev->qplib_res.cctx = rdev->chip_ctx; 183 rdev->rcfw.res = &rdev->qplib_res; 184 rdev->dev_attr = kzalloc(sizeof(*rdev->dev_attr), GFP_KERNEL); 185 if (!rdev->dev_attr) 186 goto free_chip_ctx; 187 rdev->qplib_res.dattr = rdev->dev_attr; 188 rdev->qplib_res.is_vf = BNXT_EN_VF(en_dev); 189 rdev->qplib_res.en_dev = en_dev; 190 191 bnxt_re_set_drv_mode(rdev); 192 193 bnxt_re_set_db_offset(rdev); 194 rc = bnxt_qplib_map_db_bar(&rdev->qplib_res); 195 if (rc) 196 goto free_dev_attr; 197 198 if (bnxt_qplib_determine_atomics(en_dev->pdev)) 199 ibdev_info(&rdev->ibdev, 200 "platform doesn't support global atomics."); 201 return 0; 202 free_dev_attr: 203 kfree(rdev->dev_attr); 204 rdev->dev_attr = NULL; 205 free_chip_ctx: 206 kfree(rdev->chip_ctx); 207 rdev->chip_ctx = NULL; 208 return rc; 209 } 210 211 /* SR-IOV helper functions */ 212 213 static void bnxt_re_get_sriov_func_type(struct bnxt_re_dev *rdev) 214 { 215 if (BNXT_EN_VF(rdev->en_dev)) 216 rdev->is_virtfn = 1; 217 } 218 219 /* Set the maximum number of each resource that the driver actually wants 220 * to allocate. This may be up to the maximum number the firmware has 221 * reserved for the function. The driver may choose to allocate fewer 222 * resources than the firmware maximum. 223 */ 224 static void bnxt_re_limit_pf_res(struct bnxt_re_dev *rdev) 225 { 226 struct bnxt_qplib_dev_attr *attr; 227 struct bnxt_qplib_ctx *ctx; 228 int i; 229 230 attr = rdev->dev_attr; 231 ctx = &rdev->qplib_ctx; 232 233 ctx->qpc_count = min_t(u32, BNXT_RE_MAX_QPC_COUNT, 234 attr->max_qp); 235 ctx->mrw_count = BNXT_RE_MAX_MRW_COUNT_256K; 236 /* Use max_mr from fw since max_mrw does not get set */ 237 ctx->mrw_count = min_t(u32, ctx->mrw_count, attr->max_mr); 238 ctx->srqc_count = min_t(u32, BNXT_RE_MAX_SRQC_COUNT, 239 attr->max_srq); 240 ctx->cq_count = min_t(u32, BNXT_RE_MAX_CQ_COUNT, attr->max_cq); 241 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 242 for (i = 0; i < MAX_TQM_ALLOC_REQ; i++) 243 rdev->qplib_ctx.tqm_ctx.qcount[i] = 244 rdev->dev_attr->tqm_alloc_reqs[i]; 245 } 246 247 static void bnxt_re_limit_vf_res(struct bnxt_qplib_ctx *qplib_ctx, u32 num_vf) 248 { 249 struct bnxt_qplib_vf_res *vf_res; 250 u32 mrws = 0; 251 u32 vf_pct; 252 u32 nvfs; 253 254 vf_res = &qplib_ctx->vf_res; 255 /* 256 * Reserve a set of resources for the PF. Divide the remaining 257 * resources among the VFs 258 */ 259 vf_pct = 100 - BNXT_RE_PCT_RSVD_FOR_PF; 260 nvfs = num_vf; 261 num_vf = 100 * num_vf; 262 vf_res->max_qp_per_vf = (qplib_ctx->qpc_count * vf_pct) / num_vf; 263 vf_res->max_srq_per_vf = (qplib_ctx->srqc_count * vf_pct) / num_vf; 264 vf_res->max_cq_per_vf = (qplib_ctx->cq_count * vf_pct) / num_vf; 265 /* 266 * The driver allows many more MRs than other resources. If the 267 * firmware does also, then reserve a fixed amount for the PF and 268 * divide the rest among VFs. VFs may use many MRs for NFS 269 * mounts, ISER, NVME applications, etc. If the firmware severely 270 * restricts the number of MRs, then let PF have half and divide 271 * the rest among VFs, as for the other resource types. 272 */ 273 if (qplib_ctx->mrw_count < BNXT_RE_MAX_MRW_COUNT_64K) { 274 mrws = qplib_ctx->mrw_count * vf_pct; 275 nvfs = num_vf; 276 } else { 277 mrws = qplib_ctx->mrw_count - BNXT_RE_RESVD_MR_FOR_PF; 278 } 279 vf_res->max_mrw_per_vf = (mrws / nvfs); 280 vf_res->max_gid_per_vf = BNXT_RE_MAX_GID_PER_VF; 281 } 282 283 static void bnxt_re_set_resource_limits(struct bnxt_re_dev *rdev) 284 { 285 u32 num_vfs; 286 287 memset(&rdev->qplib_ctx.vf_res, 0, sizeof(struct bnxt_qplib_vf_res)); 288 bnxt_re_limit_pf_res(rdev); 289 290 num_vfs = bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ? 291 BNXT_RE_GEN_P5_MAX_VF : rdev->num_vfs; 292 if (num_vfs) 293 bnxt_re_limit_vf_res(&rdev->qplib_ctx, num_vfs); 294 } 295 296 static void bnxt_re_vf_res_config(struct bnxt_re_dev *rdev) 297 { 298 /* 299 * Use the total VF count since the actual VF count may not be 300 * available at this point. 301 */ 302 rdev->num_vfs = pci_sriov_get_totalvfs(rdev->en_dev->pdev); 303 if (!rdev->num_vfs) 304 return; 305 306 bnxt_re_set_resource_limits(rdev); 307 bnxt_qplib_set_func_resources(&rdev->qplib_res, &rdev->rcfw, 308 &rdev->qplib_ctx); 309 } 310 311 struct bnxt_re_dcb_work { 312 struct work_struct work; 313 struct bnxt_re_dev *rdev; 314 struct hwrm_async_event_cmpl cmpl; 315 }; 316 317 static bool bnxt_re_is_qp1_qp(struct bnxt_re_qp *qp) 318 { 319 return qp->ib_qp.qp_type == IB_QPT_GSI; 320 } 321 322 static struct bnxt_re_qp *bnxt_re_get_qp1_qp(struct bnxt_re_dev *rdev) 323 { 324 struct bnxt_re_qp *qp; 325 326 mutex_lock(&rdev->qp_lock); 327 list_for_each_entry(qp, &rdev->qp_list, list) { 328 if (bnxt_re_is_qp1_qp(qp)) { 329 mutex_unlock(&rdev->qp_lock); 330 return qp; 331 } 332 } 333 mutex_unlock(&rdev->qp_lock); 334 return NULL; 335 } 336 337 static int bnxt_re_update_qp1_tos_dscp(struct bnxt_re_dev *rdev) 338 { 339 struct bnxt_re_qp *qp; 340 341 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 342 return 0; 343 344 qp = bnxt_re_get_qp1_qp(rdev); 345 if (!qp) 346 return 0; 347 348 qp->qplib_qp.modify_flags = CMDQ_MODIFY_QP_MODIFY_MASK_TOS_DSCP; 349 qp->qplib_qp.tos_dscp = rdev->cc_param.qp1_tos_dscp; 350 351 return bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 352 } 353 354 static void bnxt_re_init_dcb_wq(struct bnxt_re_dev *rdev) 355 { 356 rdev->dcb_wq = create_singlethread_workqueue("bnxt_re_dcb_wq"); 357 } 358 359 static void bnxt_re_uninit_dcb_wq(struct bnxt_re_dev *rdev) 360 { 361 if (!rdev->dcb_wq) 362 return; 363 destroy_workqueue(rdev->dcb_wq); 364 } 365 366 static void bnxt_re_dcb_wq_task(struct work_struct *work) 367 { 368 struct bnxt_re_dcb_work *dcb_work = 369 container_of(work, struct bnxt_re_dcb_work, work); 370 struct bnxt_re_dev *rdev = dcb_work->rdev; 371 struct bnxt_qplib_cc_param *cc_param; 372 int rc; 373 374 if (!rdev) 375 goto free_dcb; 376 377 cc_param = &rdev->cc_param; 378 rc = bnxt_qplib_query_cc_param(&rdev->qplib_res, cc_param); 379 if (rc) { 380 ibdev_dbg(&rdev->ibdev, "Failed to query ccparam rc:%d", rc); 381 goto free_dcb; 382 } 383 if (cc_param->qp1_tos_dscp != cc_param->tos_dscp) { 384 cc_param->qp1_tos_dscp = cc_param->tos_dscp; 385 rc = bnxt_re_update_qp1_tos_dscp(rdev); 386 if (rc) { 387 ibdev_dbg(&rdev->ibdev, "%s: Failed to modify QP1 rc:%d", 388 __func__, rc); 389 goto free_dcb; 390 } 391 } 392 393 free_dcb: 394 kfree(dcb_work); 395 } 396 397 static void bnxt_re_async_notifier(void *handle, struct hwrm_async_event_cmpl *cmpl) 398 { 399 struct bnxt_re_dev *rdev = (struct bnxt_re_dev *)handle; 400 struct bnxt_re_dcb_work *dcb_work; 401 u32 data1, data2; 402 u16 event_id; 403 404 event_id = le16_to_cpu(cmpl->event_id); 405 data1 = le32_to_cpu(cmpl->event_data1); 406 data2 = le32_to_cpu(cmpl->event_data2); 407 408 ibdev_dbg(&rdev->ibdev, "Async event_id = %d data1 = %d data2 = %d", 409 event_id, data1, data2); 410 411 switch (event_id) { 412 case ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE: 413 dcb_work = kzalloc(sizeof(*dcb_work), GFP_ATOMIC); 414 if (!dcb_work) 415 break; 416 417 dcb_work->rdev = rdev; 418 memcpy(&dcb_work->cmpl, cmpl, sizeof(*cmpl)); 419 INIT_WORK(&dcb_work->work, bnxt_re_dcb_wq_task); 420 queue_work(rdev->dcb_wq, &dcb_work->work); 421 break; 422 default: 423 break; 424 } 425 } 426 427 static void bnxt_re_stop_irq(void *handle, bool reset) 428 { 429 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(handle); 430 struct bnxt_qplib_rcfw *rcfw; 431 struct bnxt_re_dev *rdev; 432 struct bnxt_qplib_nq *nq; 433 int indx; 434 435 rdev = en_info->rdev; 436 rcfw = &rdev->rcfw; 437 438 if (reset) { 439 set_bit(ERR_DEVICE_DETACHED, &rdev->rcfw.cmdq.flags); 440 set_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags); 441 wake_up_all(&rdev->rcfw.cmdq.waitq); 442 bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1, 443 IB_EVENT_DEVICE_FATAL); 444 } 445 446 for (indx = BNXT_RE_NQ_IDX; indx < rdev->nqr->num_msix; indx++) { 447 nq = &rdev->nqr->nq[indx - 1]; 448 bnxt_qplib_nq_stop_irq(nq, false); 449 } 450 451 bnxt_qplib_rcfw_stop_irq(rcfw, false); 452 } 453 454 static void bnxt_re_start_irq(void *handle, struct bnxt_msix_entry *ent) 455 { 456 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(handle); 457 struct bnxt_msix_entry *msix_ent; 458 struct bnxt_qplib_rcfw *rcfw; 459 struct bnxt_re_dev *rdev; 460 struct bnxt_qplib_nq *nq; 461 int indx, rc; 462 463 rdev = en_info->rdev; 464 msix_ent = rdev->nqr->msix_entries; 465 rcfw = &rdev->rcfw; 466 if (!ent) { 467 /* Not setting the f/w timeout bit in rcfw. 468 * During the driver unload the first command 469 * to f/w will timeout and that will set the 470 * timeout bit. 471 */ 472 ibdev_err(&rdev->ibdev, "Failed to re-start IRQs\n"); 473 return; 474 } 475 476 /* Vectors may change after restart, so update with new vectors 477 * in device sctructure. 478 */ 479 for (indx = 0; indx < rdev->nqr->num_msix; indx++) 480 rdev->nqr->msix_entries[indx].vector = ent[indx].vector; 481 482 rc = bnxt_qplib_rcfw_start_irq(rcfw, msix_ent[BNXT_RE_AEQ_IDX].vector, 483 false); 484 if (rc) { 485 ibdev_warn(&rdev->ibdev, "Failed to reinit CREQ\n"); 486 return; 487 } 488 for (indx = BNXT_RE_NQ_IDX ; indx < rdev->nqr->num_msix; indx++) { 489 nq = &rdev->nqr->nq[indx - 1]; 490 rc = bnxt_qplib_nq_start_irq(nq, indx - 1, 491 msix_ent[indx].vector, false); 492 if (rc) { 493 ibdev_warn(&rdev->ibdev, "Failed to reinit NQ index %d\n", 494 indx - 1); 495 return; 496 } 497 } 498 } 499 500 static struct bnxt_ulp_ops bnxt_re_ulp_ops = { 501 .ulp_async_notifier = bnxt_re_async_notifier, 502 .ulp_irq_stop = bnxt_re_stop_irq, 503 .ulp_irq_restart = bnxt_re_start_irq 504 }; 505 506 /* RoCE -> Net driver */ 507 508 static int bnxt_re_register_netdev(struct bnxt_re_dev *rdev) 509 { 510 struct bnxt_en_dev *en_dev; 511 512 en_dev = rdev->en_dev; 513 return bnxt_register_dev(en_dev, &bnxt_re_ulp_ops, rdev->adev); 514 } 515 516 static void bnxt_re_init_hwrm_hdr(struct input *hdr, u16 opcd) 517 { 518 hdr->req_type = cpu_to_le16(opcd); 519 hdr->cmpl_ring = cpu_to_le16(-1); 520 hdr->target_id = cpu_to_le16(-1); 521 } 522 523 static void bnxt_re_fill_fw_msg(struct bnxt_fw_msg *fw_msg, void *msg, 524 int msg_len, void *resp, int resp_max_len, 525 int timeout) 526 { 527 fw_msg->msg = msg; 528 fw_msg->msg_len = msg_len; 529 fw_msg->resp = resp; 530 fw_msg->resp_max_len = resp_max_len; 531 fw_msg->timeout = timeout; 532 } 533 534 /* Query device config using common hwrm */ 535 static int bnxt_re_hwrm_qcfg(struct bnxt_re_dev *rdev, u32 *db_len, 536 u32 *offset) 537 { 538 struct bnxt_en_dev *en_dev = rdev->en_dev; 539 struct hwrm_func_qcfg_output resp = {0}; 540 struct hwrm_func_qcfg_input req = {0}; 541 struct bnxt_fw_msg fw_msg = {}; 542 int rc; 543 544 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_QCFG); 545 req.fid = cpu_to_le16(0xffff); 546 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 547 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 548 rc = bnxt_send_msg(en_dev, &fw_msg); 549 if (!rc) { 550 *db_len = PAGE_ALIGN(le16_to_cpu(resp.l2_doorbell_bar_size_kb) * 1024); 551 *offset = PAGE_ALIGN(le16_to_cpu(resp.legacy_l2_db_size_kb) * 1024); 552 } 553 return rc; 554 } 555 556 /* Query function capabilities using common hwrm */ 557 int bnxt_re_hwrm_qcaps(struct bnxt_re_dev *rdev) 558 { 559 struct bnxt_en_dev *en_dev = rdev->en_dev; 560 struct hwrm_func_qcaps_output resp = {}; 561 struct hwrm_func_qcaps_input req = {}; 562 struct bnxt_qplib_chip_ctx *cctx; 563 struct bnxt_fw_msg fw_msg = {}; 564 u32 flags_ext2; 565 int rc; 566 567 cctx = rdev->chip_ctx; 568 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_QCAPS); 569 req.fid = cpu_to_le16(0xffff); 570 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 571 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 572 573 rc = bnxt_send_msg(en_dev, &fw_msg); 574 if (rc) 575 return rc; 576 cctx->modes.db_push = le32_to_cpu(resp.flags) & FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE; 577 578 flags_ext2 = le32_to_cpu(resp.flags_ext2); 579 cctx->modes.dbr_pacing = flags_ext2 & FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED || 580 flags_ext2 & FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED; 581 return 0; 582 } 583 584 static int bnxt_re_hwrm_dbr_pacing_qcfg(struct bnxt_re_dev *rdev) 585 { 586 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data; 587 struct hwrm_func_dbr_pacing_qcfg_output resp = {}; 588 struct hwrm_func_dbr_pacing_qcfg_input req = {}; 589 struct bnxt_en_dev *en_dev = rdev->en_dev; 590 struct bnxt_qplib_chip_ctx *cctx; 591 struct bnxt_fw_msg fw_msg = {}; 592 int rc; 593 594 cctx = rdev->chip_ctx; 595 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_FUNC_DBR_PACING_QCFG); 596 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 597 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 598 rc = bnxt_send_msg(en_dev, &fw_msg); 599 if (rc) 600 return rc; 601 602 if ((le32_to_cpu(resp.dbr_stat_db_fifo_reg) & 603 FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK) == 604 FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC) 605 cctx->dbr_stat_db_fifo = 606 le32_to_cpu(resp.dbr_stat_db_fifo_reg) & 607 ~FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK; 608 609 pacing_data->fifo_max_depth = le32_to_cpu(resp.dbr_stat_db_max_fifo_depth); 610 if (!pacing_data->fifo_max_depth) 611 pacing_data->fifo_max_depth = BNXT_RE_MAX_FIFO_DEPTH(cctx); 612 pacing_data->fifo_room_mask = le32_to_cpu(resp.dbr_stat_db_fifo_reg_fifo_room_mask); 613 pacing_data->fifo_room_shift = resp.dbr_stat_db_fifo_reg_fifo_room_shift; 614 615 return 0; 616 } 617 618 /* Update the pacing tunable parameters to the default values */ 619 static void bnxt_re_set_default_pacing_data(struct bnxt_re_dev *rdev) 620 { 621 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data; 622 623 pacing_data->do_pacing = rdev->pacing.dbr_def_do_pacing; 624 pacing_data->pacing_th = rdev->pacing.pacing_algo_th; 625 pacing_data->alarm_th = 626 pacing_data->pacing_th * BNXT_RE_PACING_ALARM_TH_MULTIPLE; 627 } 628 629 static u32 __get_fifo_occupancy(struct bnxt_re_dev *rdev) 630 { 631 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data; 632 u32 read_val, fifo_occup; 633 634 read_val = readl(rdev->en_dev->bar0 + rdev->pacing.dbr_db_fifo_reg_off); 635 fifo_occup = pacing_data->fifo_max_depth - 636 ((read_val & pacing_data->fifo_room_mask) >> 637 pacing_data->fifo_room_shift); 638 return fifo_occup; 639 } 640 641 static bool is_dbr_fifo_full(struct bnxt_re_dev *rdev) 642 { 643 u32 max_occup, fifo_occup; 644 645 fifo_occup = __get_fifo_occupancy(rdev); 646 max_occup = BNXT_RE_MAX_FIFO_DEPTH(rdev->chip_ctx) - 1; 647 if (fifo_occup == max_occup) 648 return true; 649 650 return false; 651 } 652 653 static void __wait_for_fifo_occupancy_below_th(struct bnxt_re_dev *rdev) 654 { 655 struct bnxt_qplib_db_pacing_data *pacing_data = rdev->qplib_res.pacing_data; 656 u32 retry_fifo_check = 1000; 657 u32 fifo_occup; 658 659 /* loop shouldn't run infintely as the occupancy usually goes 660 * below pacing algo threshold as soon as pacing kicks in. 661 */ 662 while (1) { 663 fifo_occup = __get_fifo_occupancy(rdev); 664 /* Fifo occupancy cannot be greater the MAX FIFO depth */ 665 if (fifo_occup > pacing_data->fifo_max_depth) 666 break; 667 668 if (fifo_occup < pacing_data->pacing_th) 669 break; 670 if (!retry_fifo_check--) { 671 dev_info_once(rdev_to_dev(rdev), 672 "%s: fifo_occup = 0x%xfifo_max_depth = 0x%x pacing_th = 0x%x\n", 673 __func__, fifo_occup, pacing_data->fifo_max_depth, 674 pacing_data->pacing_th); 675 break; 676 } 677 678 } 679 } 680 681 static void bnxt_re_db_fifo_check(struct work_struct *work) 682 { 683 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev, 684 dbq_fifo_check_work); 685 struct bnxt_qplib_db_pacing_data *pacing_data; 686 u32 pacing_save; 687 688 if (!mutex_trylock(&rdev->pacing.dbq_lock)) 689 return; 690 pacing_data = rdev->qplib_res.pacing_data; 691 pacing_save = rdev->pacing.do_pacing_save; 692 __wait_for_fifo_occupancy_below_th(rdev); 693 cancel_delayed_work_sync(&rdev->dbq_pacing_work); 694 if (pacing_save > rdev->pacing.dbr_def_do_pacing) { 695 /* Double the do_pacing value during the congestion */ 696 pacing_save = pacing_save << 1; 697 } else { 698 /* 699 * when a new congestion is detected increase the do_pacing 700 * by 8 times. And also increase the pacing_th by 4 times. The 701 * reason to increase pacing_th is to give more space for the 702 * queue to oscillate down without getting empty, but also more 703 * room for the queue to increase without causing another alarm. 704 */ 705 pacing_save = pacing_save << 3; 706 pacing_data->pacing_th = rdev->pacing.pacing_algo_th * 4; 707 } 708 709 if (pacing_save > BNXT_RE_MAX_DBR_DO_PACING) 710 pacing_save = BNXT_RE_MAX_DBR_DO_PACING; 711 712 pacing_data->do_pacing = pacing_save; 713 rdev->pacing.do_pacing_save = pacing_data->do_pacing; 714 pacing_data->alarm_th = 715 pacing_data->pacing_th * BNXT_RE_PACING_ALARM_TH_MULTIPLE; 716 schedule_delayed_work(&rdev->dbq_pacing_work, 717 msecs_to_jiffies(rdev->pacing.dbq_pacing_time)); 718 rdev->stats.pacing.alerts++; 719 mutex_unlock(&rdev->pacing.dbq_lock); 720 } 721 722 static void bnxt_re_pacing_timer_exp(struct work_struct *work) 723 { 724 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev, 725 dbq_pacing_work.work); 726 struct bnxt_qplib_db_pacing_data *pacing_data; 727 u32 fifo_occup; 728 729 if (!mutex_trylock(&rdev->pacing.dbq_lock)) 730 return; 731 732 pacing_data = rdev->qplib_res.pacing_data; 733 fifo_occup = __get_fifo_occupancy(rdev); 734 735 if (fifo_occup > pacing_data->pacing_th) 736 goto restart_timer; 737 738 /* 739 * Instead of immediately going back to the default do_pacing 740 * reduce it by 1/8 times and restart the timer. 741 */ 742 pacing_data->do_pacing = pacing_data->do_pacing - (pacing_data->do_pacing >> 3); 743 pacing_data->do_pacing = max_t(u32, rdev->pacing.dbr_def_do_pacing, pacing_data->do_pacing); 744 if (pacing_data->do_pacing <= rdev->pacing.dbr_def_do_pacing) { 745 bnxt_re_set_default_pacing_data(rdev); 746 rdev->stats.pacing.complete++; 747 goto dbq_unlock; 748 } 749 750 restart_timer: 751 schedule_delayed_work(&rdev->dbq_pacing_work, 752 msecs_to_jiffies(rdev->pacing.dbq_pacing_time)); 753 rdev->stats.pacing.resched++; 754 dbq_unlock: 755 rdev->pacing.do_pacing_save = pacing_data->do_pacing; 756 mutex_unlock(&rdev->pacing.dbq_lock); 757 } 758 759 void bnxt_re_pacing_alert(struct bnxt_re_dev *rdev) 760 { 761 struct bnxt_qplib_db_pacing_data *pacing_data; 762 763 if (!rdev->pacing.dbr_pacing) 764 return; 765 mutex_lock(&rdev->pacing.dbq_lock); 766 pacing_data = rdev->qplib_res.pacing_data; 767 768 /* 769 * Increase the alarm_th to max so that other user lib instances do not 770 * keep alerting the driver. 771 */ 772 pacing_data->alarm_th = pacing_data->fifo_max_depth; 773 pacing_data->do_pacing = BNXT_RE_MAX_DBR_DO_PACING; 774 cancel_work_sync(&rdev->dbq_fifo_check_work); 775 schedule_work(&rdev->dbq_fifo_check_work); 776 mutex_unlock(&rdev->pacing.dbq_lock); 777 } 778 779 static int bnxt_re_initialize_dbr_pacing(struct bnxt_re_dev *rdev) 780 { 781 /* Allocate a page for app use */ 782 rdev->pacing.dbr_page = (void *)__get_free_page(GFP_KERNEL); 783 if (!rdev->pacing.dbr_page) 784 return -ENOMEM; 785 786 memset((u8 *)rdev->pacing.dbr_page, 0, PAGE_SIZE); 787 rdev->qplib_res.pacing_data = (struct bnxt_qplib_db_pacing_data *)rdev->pacing.dbr_page; 788 789 if (bnxt_re_hwrm_dbr_pacing_qcfg(rdev)) { 790 free_page((u64)rdev->pacing.dbr_page); 791 rdev->pacing.dbr_page = NULL; 792 return -EIO; 793 } 794 795 /* MAP HW window 2 for reading db fifo depth */ 796 writel(rdev->chip_ctx->dbr_stat_db_fifo & BNXT_GRC_BASE_MASK, 797 rdev->en_dev->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 798 rdev->pacing.dbr_db_fifo_reg_off = 799 (rdev->chip_ctx->dbr_stat_db_fifo & BNXT_GRC_OFFSET_MASK) + 800 BNXT_RE_GRC_FIFO_REG_BASE; 801 rdev->pacing.dbr_bar_addr = 802 pci_resource_start(rdev->qplib_res.pdev, 0) + rdev->pacing.dbr_db_fifo_reg_off; 803 804 if (is_dbr_fifo_full(rdev)) { 805 free_page((u64)rdev->pacing.dbr_page); 806 rdev->pacing.dbr_page = NULL; 807 return -EIO; 808 } 809 810 rdev->pacing.pacing_algo_th = BNXT_RE_PACING_ALGO_THRESHOLD; 811 rdev->pacing.dbq_pacing_time = BNXT_RE_DBR_PACING_TIME; 812 rdev->pacing.dbr_def_do_pacing = BNXT_RE_DBR_DO_PACING_NO_CONGESTION; 813 rdev->pacing.do_pacing_save = rdev->pacing.dbr_def_do_pacing; 814 rdev->qplib_res.pacing_data->grc_reg_offset = rdev->pacing.dbr_db_fifo_reg_off; 815 bnxt_re_set_default_pacing_data(rdev); 816 /* Initialize worker for DBR Pacing */ 817 INIT_WORK(&rdev->dbq_fifo_check_work, bnxt_re_db_fifo_check); 818 INIT_DELAYED_WORK(&rdev->dbq_pacing_work, bnxt_re_pacing_timer_exp); 819 return 0; 820 } 821 822 static void bnxt_re_deinitialize_dbr_pacing(struct bnxt_re_dev *rdev) 823 { 824 cancel_work_sync(&rdev->dbq_fifo_check_work); 825 cancel_delayed_work_sync(&rdev->dbq_pacing_work); 826 if (rdev->pacing.dbr_page) 827 free_page((u64)rdev->pacing.dbr_page); 828 829 rdev->pacing.dbr_page = NULL; 830 rdev->pacing.dbr_pacing = false; 831 } 832 833 static int bnxt_re_net_ring_free(struct bnxt_re_dev *rdev, 834 u16 fw_ring_id, int type) 835 { 836 struct bnxt_en_dev *en_dev; 837 struct hwrm_ring_free_input req = {}; 838 struct hwrm_ring_free_output resp; 839 struct bnxt_fw_msg fw_msg = {}; 840 int rc = -EINVAL; 841 842 if (!rdev) 843 return rc; 844 845 en_dev = rdev->en_dev; 846 847 if (!en_dev) 848 return rc; 849 850 if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags)) 851 return 0; 852 853 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_RING_FREE); 854 req.ring_type = type; 855 req.ring_id = cpu_to_le16(fw_ring_id); 856 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 857 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 858 rc = bnxt_send_msg(en_dev, &fw_msg); 859 if (rc) 860 ibdev_err(&rdev->ibdev, "Failed to free HW ring:%d :%#x", 861 req.ring_id, rc); 862 return rc; 863 } 864 865 static int bnxt_re_net_ring_alloc(struct bnxt_re_dev *rdev, 866 struct bnxt_re_ring_attr *ring_attr, 867 u16 *fw_ring_id) 868 { 869 struct bnxt_en_dev *en_dev = rdev->en_dev; 870 struct hwrm_ring_alloc_input req = {}; 871 struct hwrm_ring_alloc_output resp; 872 struct bnxt_fw_msg fw_msg = {}; 873 int rc = -EINVAL; 874 875 if (!en_dev) 876 return rc; 877 878 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_RING_ALLOC); 879 req.enables = 0; 880 req.page_tbl_addr = cpu_to_le64(ring_attr->dma_arr[0]); 881 if (ring_attr->pages > 1) { 882 /* Page size is in log2 units */ 883 req.page_size = BNXT_PAGE_SHIFT; 884 req.page_tbl_depth = 1; 885 } 886 req.fbo = 0; 887 /* Association of ring index with doorbell index and MSIX number */ 888 req.logical_id = cpu_to_le16(ring_attr->lrid); 889 req.length = cpu_to_le32(ring_attr->depth + 1); 890 req.ring_type = ring_attr->type; 891 req.int_mode = ring_attr->mode; 892 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 893 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 894 rc = bnxt_send_msg(en_dev, &fw_msg); 895 if (!rc) 896 *fw_ring_id = le16_to_cpu(resp.ring_id); 897 898 return rc; 899 } 900 901 static int bnxt_re_net_stats_ctx_free(struct bnxt_re_dev *rdev, 902 u32 fw_stats_ctx_id) 903 { 904 struct bnxt_en_dev *en_dev = rdev->en_dev; 905 struct hwrm_stat_ctx_free_input req = {}; 906 struct hwrm_stat_ctx_free_output resp = {}; 907 struct bnxt_fw_msg fw_msg = {}; 908 int rc = -EINVAL; 909 910 if (!en_dev) 911 return rc; 912 913 if (test_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags)) 914 return 0; 915 916 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_STAT_CTX_FREE); 917 req.stat_ctx_id = cpu_to_le32(fw_stats_ctx_id); 918 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 919 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 920 rc = bnxt_send_msg(en_dev, &fw_msg); 921 if (rc) 922 ibdev_err(&rdev->ibdev, "Failed to free HW stats context %#x", 923 rc); 924 925 return rc; 926 } 927 928 static int bnxt_re_net_stats_ctx_alloc(struct bnxt_re_dev *rdev, 929 dma_addr_t dma_map, 930 u32 *fw_stats_ctx_id) 931 { 932 struct bnxt_qplib_chip_ctx *chip_ctx = rdev->chip_ctx; 933 struct hwrm_stat_ctx_alloc_output resp = {}; 934 struct hwrm_stat_ctx_alloc_input req = {}; 935 struct bnxt_en_dev *en_dev = rdev->en_dev; 936 struct bnxt_fw_msg fw_msg = {}; 937 int rc = -EINVAL; 938 939 *fw_stats_ctx_id = INVALID_STATS_CTX_ID; 940 941 if (!en_dev) 942 return rc; 943 944 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_STAT_CTX_ALLOC); 945 req.update_period_ms = cpu_to_le32(1000); 946 req.stats_dma_addr = cpu_to_le64(dma_map); 947 req.stats_dma_length = cpu_to_le16(chip_ctx->hw_stats_size); 948 req.stat_ctx_flags = STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE; 949 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 950 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 951 rc = bnxt_send_msg(en_dev, &fw_msg); 952 if (!rc) 953 *fw_stats_ctx_id = le32_to_cpu(resp.stat_ctx_id); 954 955 return rc; 956 } 957 958 static void bnxt_re_disassociate_ucontext(struct ib_ucontext *ibcontext) 959 { 960 } 961 962 /* Device */ 963 static ssize_t hw_rev_show(struct device *device, struct device_attribute *attr, 964 char *buf) 965 { 966 struct bnxt_re_dev *rdev = 967 rdma_device_to_drv_device(device, struct bnxt_re_dev, ibdev); 968 969 return sysfs_emit(buf, "0x%x\n", rdev->en_dev->pdev->vendor); 970 } 971 static DEVICE_ATTR_RO(hw_rev); 972 973 static ssize_t hca_type_show(struct device *device, 974 struct device_attribute *attr, char *buf) 975 { 976 struct bnxt_re_dev *rdev = 977 rdma_device_to_drv_device(device, struct bnxt_re_dev, ibdev); 978 979 return sysfs_emit(buf, "%s\n", rdev->ibdev.node_desc); 980 } 981 static DEVICE_ATTR_RO(hca_type); 982 983 static struct attribute *bnxt_re_attributes[] = { 984 &dev_attr_hw_rev.attr, 985 &dev_attr_hca_type.attr, 986 NULL 987 }; 988 989 static const struct attribute_group bnxt_re_dev_attr_group = { 990 .attrs = bnxt_re_attributes, 991 }; 992 993 static int bnxt_re_fill_res_mr_entry(struct sk_buff *msg, struct ib_mr *ib_mr) 994 { 995 struct bnxt_qplib_hwq *mr_hwq; 996 struct nlattr *table_attr; 997 struct bnxt_re_mr *mr; 998 999 table_attr = nla_nest_start(msg, RDMA_NLDEV_ATTR_DRIVER); 1000 if (!table_attr) 1001 return -EMSGSIZE; 1002 1003 mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 1004 mr_hwq = &mr->qplib_mr.hwq; 1005 1006 if (rdma_nl_put_driver_u32(msg, "page_size", 1007 mr_hwq->qe_ppg * mr_hwq->element_size)) 1008 goto err; 1009 if (rdma_nl_put_driver_u32(msg, "max_elements", mr_hwq->max_elements)) 1010 goto err; 1011 if (rdma_nl_put_driver_u32(msg, "element_size", mr_hwq->element_size)) 1012 goto err; 1013 if (rdma_nl_put_driver_u64_hex(msg, "hwq", (unsigned long)mr_hwq)) 1014 goto err; 1015 if (rdma_nl_put_driver_u64_hex(msg, "va", mr->qplib_mr.va)) 1016 goto err; 1017 1018 nla_nest_end(msg, table_attr); 1019 return 0; 1020 1021 err: 1022 nla_nest_cancel(msg, table_attr); 1023 return -EMSGSIZE; 1024 } 1025 1026 static int bnxt_re_fill_res_mr_entry_raw(struct sk_buff *msg, struct ib_mr *ib_mr) 1027 { 1028 struct bnxt_re_dev *rdev; 1029 struct bnxt_re_mr *mr; 1030 int err, len; 1031 void *data; 1032 1033 mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 1034 rdev = mr->rdev; 1035 1036 err = bnxt_re_read_context_allowed(rdev); 1037 if (err) 1038 return err; 1039 1040 len = bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx) ? BNXT_RE_CONTEXT_TYPE_MRW_SIZE_P7 : 1041 BNXT_RE_CONTEXT_TYPE_MRW_SIZE_P5; 1042 data = kzalloc(len, GFP_KERNEL); 1043 if (!data) 1044 return -ENOMEM; 1045 1046 err = bnxt_qplib_read_context(&rdev->rcfw, CMDQ_READ_CONTEXT_TYPE_MRW, 1047 mr->qplib_mr.lkey, len, data); 1048 if (!err) 1049 err = nla_put(msg, RDMA_NLDEV_ATTR_RES_RAW, len, data); 1050 1051 kfree(data); 1052 return err; 1053 } 1054 1055 static int bnxt_re_fill_res_cq_entry(struct sk_buff *msg, struct ib_cq *ib_cq) 1056 { 1057 struct bnxt_qplib_hwq *cq_hwq; 1058 struct nlattr *table_attr; 1059 struct bnxt_re_cq *cq; 1060 1061 cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 1062 cq_hwq = &cq->qplib_cq.hwq; 1063 1064 table_attr = nla_nest_start(msg, RDMA_NLDEV_ATTR_DRIVER); 1065 if (!table_attr) 1066 return -EMSGSIZE; 1067 1068 if (rdma_nl_put_driver_u32(msg, "cq_depth", cq_hwq->depth)) 1069 goto err; 1070 if (rdma_nl_put_driver_u32(msg, "max_elements", cq_hwq->max_elements)) 1071 goto err; 1072 if (rdma_nl_put_driver_u32(msg, "element_size", cq_hwq->element_size)) 1073 goto err; 1074 if (rdma_nl_put_driver_u32(msg, "max_wqe", cq->qplib_cq.max_wqe)) 1075 goto err; 1076 1077 nla_nest_end(msg, table_attr); 1078 return 0; 1079 1080 err: 1081 nla_nest_cancel(msg, table_attr); 1082 return -EMSGSIZE; 1083 } 1084 1085 static int bnxt_re_fill_res_cq_entry_raw(struct sk_buff *msg, struct ib_cq *ib_cq) 1086 { 1087 struct bnxt_re_dev *rdev; 1088 struct bnxt_re_cq *cq; 1089 int err, len; 1090 void *data; 1091 1092 cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 1093 rdev = cq->rdev; 1094 1095 err = bnxt_re_read_context_allowed(rdev); 1096 if (err) 1097 return err; 1098 1099 len = bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx) ? BNXT_RE_CONTEXT_TYPE_CQ_SIZE_P7 : 1100 BNXT_RE_CONTEXT_TYPE_CQ_SIZE_P5; 1101 data = kzalloc(len, GFP_KERNEL); 1102 if (!data) 1103 return -ENOMEM; 1104 1105 err = bnxt_qplib_read_context(&rdev->rcfw, 1106 CMDQ_READ_CONTEXT_TYPE_CQ, 1107 cq->qplib_cq.id, len, data); 1108 if (!err) 1109 err = nla_put(msg, RDMA_NLDEV_ATTR_RES_RAW, len, data); 1110 1111 kfree(data); 1112 return err; 1113 } 1114 1115 static int bnxt_re_fill_res_qp_entry(struct sk_buff *msg, struct ib_qp *ib_qp) 1116 { 1117 struct bnxt_qplib_qp *qplib_qp; 1118 struct nlattr *table_attr; 1119 struct bnxt_re_qp *qp; 1120 1121 table_attr = nla_nest_start(msg, RDMA_NLDEV_ATTR_DRIVER); 1122 if (!table_attr) 1123 return -EMSGSIZE; 1124 1125 qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 1126 qplib_qp = &qp->qplib_qp; 1127 1128 if (rdma_nl_put_driver_u32(msg, "sq_max_wqe", qplib_qp->sq.max_wqe)) 1129 goto err; 1130 if (rdma_nl_put_driver_u32(msg, "sq_max_sge", qplib_qp->sq.max_sge)) 1131 goto err; 1132 if (rdma_nl_put_driver_u32(msg, "sq_wqe_size", qplib_qp->sq.wqe_size)) 1133 goto err; 1134 if (rdma_nl_put_driver_u32(msg, "sq_swq_start", qplib_qp->sq.swq_start)) 1135 goto err; 1136 if (rdma_nl_put_driver_u32(msg, "sq_swq_last", qplib_qp->sq.swq_last)) 1137 goto err; 1138 if (rdma_nl_put_driver_u32(msg, "rq_max_wqe", qplib_qp->rq.max_wqe)) 1139 goto err; 1140 if (rdma_nl_put_driver_u32(msg, "rq_max_sge", qplib_qp->rq.max_sge)) 1141 goto err; 1142 if (rdma_nl_put_driver_u32(msg, "rq_wqe_size", qplib_qp->rq.wqe_size)) 1143 goto err; 1144 if (rdma_nl_put_driver_u32(msg, "rq_swq_start", qplib_qp->rq.swq_start)) 1145 goto err; 1146 if (rdma_nl_put_driver_u32(msg, "rq_swq_last", qplib_qp->rq.swq_last)) 1147 goto err; 1148 if (rdma_nl_put_driver_u32(msg, "timeout", qplib_qp->timeout)) 1149 goto err; 1150 1151 nla_nest_end(msg, table_attr); 1152 return 0; 1153 1154 err: 1155 nla_nest_cancel(msg, table_attr); 1156 return -EMSGSIZE; 1157 } 1158 1159 static int bnxt_re_fill_res_qp_entry_raw(struct sk_buff *msg, struct ib_qp *ibqp) 1160 { 1161 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibqp->device, ibdev); 1162 int err, len; 1163 void *data; 1164 1165 err = bnxt_re_read_context_allowed(rdev); 1166 if (err) 1167 return err; 1168 1169 len = bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx) ? BNXT_RE_CONTEXT_TYPE_QPC_SIZE_P7 : 1170 BNXT_RE_CONTEXT_TYPE_QPC_SIZE_P5; 1171 data = kzalloc(len, GFP_KERNEL); 1172 if (!data) 1173 return -ENOMEM; 1174 1175 err = bnxt_qplib_read_context(&rdev->rcfw, CMDQ_READ_CONTEXT_TYPE_QPC, 1176 ibqp->qp_num, len, data); 1177 if (!err) 1178 err = nla_put(msg, RDMA_NLDEV_ATTR_RES_RAW, len, data); 1179 1180 kfree(data); 1181 return err; 1182 } 1183 1184 static int bnxt_re_fill_res_srq_entry(struct sk_buff *msg, struct ib_srq *ib_srq) 1185 { 1186 struct nlattr *table_attr; 1187 struct bnxt_re_srq *srq; 1188 1189 table_attr = nla_nest_start(msg, RDMA_NLDEV_ATTR_DRIVER); 1190 if (!table_attr) 1191 return -EMSGSIZE; 1192 1193 srq = container_of(ib_srq, struct bnxt_re_srq, ib_srq); 1194 1195 if (rdma_nl_put_driver_u32_hex(msg, "wqe_size", srq->qplib_srq.wqe_size)) 1196 goto err; 1197 if (rdma_nl_put_driver_u32_hex(msg, "max_wqe", srq->qplib_srq.max_wqe)) 1198 goto err; 1199 if (rdma_nl_put_driver_u32_hex(msg, "max_sge", srq->qplib_srq.max_sge)) 1200 goto err; 1201 1202 nla_nest_end(msg, table_attr); 1203 return 0; 1204 1205 err: 1206 nla_nest_cancel(msg, table_attr); 1207 return -EMSGSIZE; 1208 } 1209 1210 static int bnxt_re_fill_res_srq_entry_raw(struct sk_buff *msg, struct ib_srq *ib_srq) 1211 { 1212 struct bnxt_re_dev *rdev; 1213 struct bnxt_re_srq *srq; 1214 int err, len; 1215 void *data; 1216 1217 srq = container_of(ib_srq, struct bnxt_re_srq, ib_srq); 1218 rdev = srq->rdev; 1219 1220 err = bnxt_re_read_context_allowed(rdev); 1221 if (err) 1222 return err; 1223 1224 len = bnxt_qplib_is_chip_gen_p7(rdev->chip_ctx) ? BNXT_RE_CONTEXT_TYPE_SRQ_SIZE_P7 : 1225 BNXT_RE_CONTEXT_TYPE_SRQ_SIZE_P5; 1226 1227 data = kzalloc(len, GFP_KERNEL); 1228 if (!data) 1229 return -ENOMEM; 1230 1231 err = bnxt_qplib_read_context(&rdev->rcfw, CMDQ_READ_CONTEXT_TYPE_SRQ, 1232 srq->qplib_srq.id, len, data); 1233 if (!err) 1234 err = nla_put(msg, RDMA_NLDEV_ATTR_RES_RAW, len, data); 1235 1236 kfree(data); 1237 return err; 1238 } 1239 1240 static const struct ib_device_ops bnxt_re_dev_ops = { 1241 .owner = THIS_MODULE, 1242 .driver_id = RDMA_DRIVER_BNXT_RE, 1243 .uverbs_abi_ver = BNXT_RE_ABI_VERSION, 1244 1245 .add_gid = bnxt_re_add_gid, 1246 .alloc_hw_port_stats = bnxt_re_ib_alloc_hw_port_stats, 1247 .alloc_mr = bnxt_re_alloc_mr, 1248 .alloc_pd = bnxt_re_alloc_pd, 1249 .alloc_ucontext = bnxt_re_alloc_ucontext, 1250 .create_ah = bnxt_re_create_ah, 1251 .create_cq = bnxt_re_create_cq, 1252 .create_qp = bnxt_re_create_qp, 1253 .create_srq = bnxt_re_create_srq, 1254 .create_user_ah = bnxt_re_create_ah, 1255 .dealloc_pd = bnxt_re_dealloc_pd, 1256 .dealloc_ucontext = bnxt_re_dealloc_ucontext, 1257 .del_gid = bnxt_re_del_gid, 1258 .dereg_mr = bnxt_re_dereg_mr, 1259 .destroy_ah = bnxt_re_destroy_ah, 1260 .destroy_cq = bnxt_re_destroy_cq, 1261 .destroy_qp = bnxt_re_destroy_qp, 1262 .destroy_srq = bnxt_re_destroy_srq, 1263 .device_group = &bnxt_re_dev_attr_group, 1264 .disassociate_ucontext = bnxt_re_disassociate_ucontext, 1265 .get_dev_fw_str = bnxt_re_query_fw_str, 1266 .get_dma_mr = bnxt_re_get_dma_mr, 1267 .get_hw_stats = bnxt_re_ib_get_hw_stats, 1268 .get_link_layer = bnxt_re_get_link_layer, 1269 .get_port_immutable = bnxt_re_get_port_immutable, 1270 .map_mr_sg = bnxt_re_map_mr_sg, 1271 .mmap = bnxt_re_mmap, 1272 .mmap_free = bnxt_re_mmap_free, 1273 .modify_qp = bnxt_re_modify_qp, 1274 .modify_srq = bnxt_re_modify_srq, 1275 .poll_cq = bnxt_re_poll_cq, 1276 .post_recv = bnxt_re_post_recv, 1277 .post_send = bnxt_re_post_send, 1278 .post_srq_recv = bnxt_re_post_srq_recv, 1279 .query_ah = bnxt_re_query_ah, 1280 .query_device = bnxt_re_query_device, 1281 .modify_device = bnxt_re_modify_device, 1282 .query_pkey = bnxt_re_query_pkey, 1283 .query_port = bnxt_re_query_port, 1284 .query_qp = bnxt_re_query_qp, 1285 .query_srq = bnxt_re_query_srq, 1286 .reg_user_mr = bnxt_re_reg_user_mr, 1287 .reg_user_mr_dmabuf = bnxt_re_reg_user_mr_dmabuf, 1288 .req_notify_cq = bnxt_re_req_notify_cq, 1289 .resize_cq = bnxt_re_resize_cq, 1290 INIT_RDMA_OBJ_SIZE(ib_ah, bnxt_re_ah, ib_ah), 1291 INIT_RDMA_OBJ_SIZE(ib_cq, bnxt_re_cq, ib_cq), 1292 INIT_RDMA_OBJ_SIZE(ib_pd, bnxt_re_pd, ib_pd), 1293 INIT_RDMA_OBJ_SIZE(ib_qp, bnxt_re_qp, ib_qp), 1294 INIT_RDMA_OBJ_SIZE(ib_srq, bnxt_re_srq, ib_srq), 1295 INIT_RDMA_OBJ_SIZE(ib_ucontext, bnxt_re_ucontext, ib_uctx), 1296 }; 1297 1298 static const struct ib_device_ops restrack_ops = { 1299 .fill_res_cq_entry = bnxt_re_fill_res_cq_entry, 1300 .fill_res_cq_entry_raw = bnxt_re_fill_res_cq_entry_raw, 1301 .fill_res_qp_entry = bnxt_re_fill_res_qp_entry, 1302 .fill_res_qp_entry_raw = bnxt_re_fill_res_qp_entry_raw, 1303 .fill_res_mr_entry = bnxt_re_fill_res_mr_entry, 1304 .fill_res_mr_entry_raw = bnxt_re_fill_res_mr_entry_raw, 1305 .fill_res_srq_entry = bnxt_re_fill_res_srq_entry, 1306 .fill_res_srq_entry_raw = bnxt_re_fill_res_srq_entry_raw, 1307 }; 1308 1309 static int bnxt_re_register_ib(struct bnxt_re_dev *rdev) 1310 { 1311 struct ib_device *ibdev = &rdev->ibdev; 1312 int ret; 1313 1314 /* ib device init */ 1315 ibdev->node_type = RDMA_NODE_IB_CA; 1316 strscpy(ibdev->node_desc, BNXT_RE_DESC " HCA", 1317 strlen(BNXT_RE_DESC) + 5); 1318 ibdev->phys_port_cnt = 1; 1319 1320 addrconf_addr_eui48((u8 *)&ibdev->node_guid, rdev->netdev->dev_addr); 1321 1322 ibdev->num_comp_vectors = rdev->nqr->num_msix - 1; 1323 ibdev->dev.parent = &rdev->en_dev->pdev->dev; 1324 ibdev->local_dma_lkey = BNXT_QPLIB_RSVD_LKEY; 1325 1326 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 1327 ibdev->driver_def = bnxt_re_uapi_defs; 1328 1329 ib_set_device_ops(ibdev, &bnxt_re_dev_ops); 1330 ib_set_device_ops(ibdev, &restrack_ops); 1331 ret = ib_device_set_netdev(&rdev->ibdev, rdev->netdev, 1); 1332 if (ret) 1333 return ret; 1334 1335 dma_set_max_seg_size(&rdev->en_dev->pdev->dev, UINT_MAX); 1336 ibdev->uverbs_cmd_mask |= BIT_ULL(IB_USER_VERBS_CMD_POLL_CQ); 1337 return ib_register_device(ibdev, "bnxt_re%d", &rdev->en_dev->pdev->dev); 1338 } 1339 1340 static struct bnxt_re_dev *bnxt_re_dev_add(struct auxiliary_device *adev, 1341 struct bnxt_en_dev *en_dev) 1342 { 1343 struct bnxt_re_dev *rdev; 1344 1345 /* Allocate bnxt_re_dev instance here */ 1346 rdev = ib_alloc_device(bnxt_re_dev, ibdev); 1347 if (!rdev) { 1348 ibdev_err(NULL, "%s: bnxt_re_dev allocation failure!", 1349 ROCE_DRV_MODULE_NAME); 1350 return NULL; 1351 } 1352 /* Default values */ 1353 rdev->nb.notifier_call = NULL; 1354 rdev->netdev = en_dev->net; 1355 rdev->en_dev = en_dev; 1356 rdev->adev = adev; 1357 rdev->id = rdev->en_dev->pdev->devfn; 1358 INIT_LIST_HEAD(&rdev->qp_list); 1359 mutex_init(&rdev->qp_lock); 1360 mutex_init(&rdev->pacing.dbq_lock); 1361 atomic_set(&rdev->stats.res.qp_count, 0); 1362 atomic_set(&rdev->stats.res.cq_count, 0); 1363 atomic_set(&rdev->stats.res.srq_count, 0); 1364 atomic_set(&rdev->stats.res.mr_count, 0); 1365 atomic_set(&rdev->stats.res.mw_count, 0); 1366 atomic_set(&rdev->stats.res.ah_count, 0); 1367 atomic_set(&rdev->stats.res.pd_count, 0); 1368 rdev->cosq[0] = 0xFFFF; 1369 rdev->cosq[1] = 0xFFFF; 1370 rdev->cq_coalescing.buf_maxtime = BNXT_QPLIB_CQ_COAL_DEF_BUF_MAXTIME; 1371 if (bnxt_re_chip_gen_p7(en_dev->chip_num)) { 1372 rdev->cq_coalescing.normal_maxbuf = BNXT_QPLIB_CQ_COAL_DEF_NORMAL_MAXBUF_P7; 1373 rdev->cq_coalescing.during_maxbuf = BNXT_QPLIB_CQ_COAL_DEF_DURING_MAXBUF_P7; 1374 } else { 1375 rdev->cq_coalescing.normal_maxbuf = BNXT_QPLIB_CQ_COAL_DEF_NORMAL_MAXBUF_P5; 1376 rdev->cq_coalescing.during_maxbuf = BNXT_QPLIB_CQ_COAL_DEF_DURING_MAXBUF_P5; 1377 } 1378 rdev->cq_coalescing.en_ring_idle_mode = BNXT_QPLIB_CQ_COAL_DEF_EN_RING_IDLE_MODE; 1379 1380 return rdev; 1381 } 1382 1383 static int bnxt_re_handle_unaffi_async_event(struct creq_func_event 1384 *unaffi_async) 1385 { 1386 switch (unaffi_async->event) { 1387 case CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR: 1388 break; 1389 case CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR: 1390 break; 1391 case CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR: 1392 break; 1393 case CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR: 1394 break; 1395 case CREQ_FUNC_EVENT_EVENT_CQ_ERROR: 1396 break; 1397 case CREQ_FUNC_EVENT_EVENT_TQM_ERROR: 1398 break; 1399 case CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR: 1400 break; 1401 case CREQ_FUNC_EVENT_EVENT_CFCS_ERROR: 1402 break; 1403 case CREQ_FUNC_EVENT_EVENT_CFCC_ERROR: 1404 break; 1405 case CREQ_FUNC_EVENT_EVENT_CFCM_ERROR: 1406 break; 1407 case CREQ_FUNC_EVENT_EVENT_TIM_ERROR: 1408 break; 1409 default: 1410 return -EINVAL; 1411 } 1412 return 0; 1413 } 1414 1415 static int bnxt_re_handle_qp_async_event(struct creq_qp_event *qp_event, 1416 struct bnxt_re_qp *qp) 1417 { 1418 struct creq_qp_error_notification *err_event; 1419 struct bnxt_re_srq *srq = NULL; 1420 struct ib_event event = {}; 1421 unsigned int flags; 1422 1423 if (qp->qplib_qp.srq) 1424 srq = container_of(qp->qplib_qp.srq, struct bnxt_re_srq, 1425 qplib_srq); 1426 1427 if (qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR && 1428 rdma_is_kernel_res(&qp->ib_qp.res)) { 1429 flags = bnxt_re_lock_cqs(qp); 1430 bnxt_qplib_add_flush_qp(&qp->qplib_qp); 1431 bnxt_re_unlock_cqs(qp, flags); 1432 } 1433 1434 event.device = &qp->rdev->ibdev; 1435 event.element.qp = &qp->ib_qp; 1436 event.event = IB_EVENT_QP_FATAL; 1437 1438 err_event = (struct creq_qp_error_notification *)qp_event; 1439 1440 switch (err_event->req_err_state_reason) { 1441 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_OPCODE_ERROR: 1442 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TIMEOUT_RETRY_LIMIT: 1443 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RNR_TIMEOUT_RETRY_LIMIT: 1444 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_2: 1445 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_3: 1446 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_READ_RESP: 1447 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_BIND: 1448 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_FAST_REG: 1449 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_INVALIDATE: 1450 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETRAN_LOCAL_ERROR: 1451 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_AV_DOMAIN_ERROR: 1452 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PROD_WQE_MSMTCH_ERROR: 1453 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PSN_RANGE_CHECK_ERROR: 1454 event.event = IB_EVENT_QP_ACCESS_ERR; 1455 break; 1456 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_1: 1457 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_4: 1458 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_READ_RESP_LENGTH: 1459 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_WQE_FORMAT_ERROR: 1460 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ORRQ_FORMAT_ERROR: 1461 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_AVID_ERROR: 1462 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SERV_TYPE_ERROR: 1463 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_OP_ERROR: 1464 event.event = IB_EVENT_QP_REQ_ERR; 1465 break; 1466 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_MEMORY_ERROR: 1467 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_MEMORY_ERROR: 1468 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CMP_ERROR: 1469 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CQ_LOAD_ERROR: 1470 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_PCI_ERROR: 1471 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_PCI_ERROR: 1472 case CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETX_SETUP_ERROR: 1473 event.event = IB_EVENT_QP_FATAL; 1474 break; 1475 1476 default: 1477 break; 1478 } 1479 1480 switch (err_event->res_err_state_reason) { 1481 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEED_MAX: 1482 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PAYLOAD_LENGTH_MISMATCH: 1483 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_SEQ_ERROR_RETRY_LIMIT: 1484 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_INVALID_R_KEY: 1485 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_DOMAIN_ERROR: 1486 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_NO_PERMISSION: 1487 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_RANGE_ERROR: 1488 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_INVALID_R_KEY: 1489 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_DOMAIN_ERROR: 1490 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_NO_PERMISSION: 1491 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_RANGE_ERROR: 1492 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNALIGN_ATOMIC: 1493 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_NOT_FOUND: 1494 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_INVALID_DUP_RKEY: 1495 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_FORMAT_ERROR: 1496 event.event = IB_EVENT_QP_ACCESS_ERR; 1497 break; 1498 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEEDS_WQE: 1499 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_WQE_FORMAT_ERROR: 1500 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNSUPPORTED_OPCODE: 1501 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_REM_INVALIDATE: 1502 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_OPCODE_ERROR: 1503 event.event = IB_EVENT_QP_REQ_ERR; 1504 break; 1505 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_OFLOW: 1506 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CMP_ERROR: 1507 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CQ_LOAD_ERROR: 1508 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_PCI_ERROR: 1509 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_PCI_ERROR: 1510 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_MEMORY_ERROR: 1511 event.event = IB_EVENT_QP_FATAL; 1512 break; 1513 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_LOAD_ERROR: 1514 case CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_ERROR: 1515 if (srq) 1516 event.event = IB_EVENT_SRQ_ERR; 1517 break; 1518 default: 1519 break; 1520 } 1521 1522 if (err_event->res_err_state_reason || err_event->req_err_state_reason) { 1523 ibdev_dbg(&qp->rdev->ibdev, 1524 "%s %s qp_id: %d cons (%d %d) req (%d %d) res (%d %d)\n", 1525 __func__, rdma_is_kernel_res(&qp->ib_qp.res) ? "kernel" : "user", 1526 qp->qplib_qp.id, 1527 err_event->sq_cons_idx, 1528 err_event->rq_cons_idx, 1529 err_event->req_slow_path_state, 1530 err_event->req_err_state_reason, 1531 err_event->res_slow_path_state, 1532 err_event->res_err_state_reason); 1533 } else { 1534 if (srq) 1535 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 1536 } 1537 1538 if (event.event == IB_EVENT_SRQ_ERR && srq->ib_srq.event_handler) { 1539 (*srq->ib_srq.event_handler)(&event, 1540 srq->ib_srq.srq_context); 1541 } else if (event.device && qp->ib_qp.event_handler) { 1542 qp->ib_qp.event_handler(&event, qp->ib_qp.qp_context); 1543 } 1544 1545 return 0; 1546 } 1547 1548 static int bnxt_re_handle_cq_async_error(void *event, struct bnxt_re_cq *cq) 1549 { 1550 struct creq_cq_error_notification *cqerr; 1551 struct ib_event ibevent = {}; 1552 1553 cqerr = event; 1554 switch (cqerr->cq_err_reason) { 1555 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_INVALID_ERROR: 1556 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_OVERFLOW_ERROR: 1557 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_LOAD_ERROR: 1558 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_INVALID_ERROR: 1559 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_OVERFLOW_ERROR: 1560 case CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR: 1561 ibevent.event = IB_EVENT_CQ_ERR; 1562 break; 1563 default: 1564 break; 1565 } 1566 1567 if (ibevent.event == IB_EVENT_CQ_ERR && cq->ib_cq.event_handler) { 1568 ibevent.element.cq = &cq->ib_cq; 1569 ibevent.device = &cq->rdev->ibdev; 1570 1571 ibdev_dbg(&cq->rdev->ibdev, 1572 "%s err reason %d\n", __func__, cqerr->cq_err_reason); 1573 cq->ib_cq.event_handler(&ibevent, cq->ib_cq.cq_context); 1574 } 1575 1576 return 0; 1577 } 1578 1579 static int bnxt_re_handle_affi_async_event(struct creq_qp_event *affi_async, 1580 void *obj) 1581 { 1582 struct bnxt_qplib_qp *lib_qp; 1583 struct bnxt_qplib_cq *lib_cq; 1584 struct bnxt_re_qp *qp; 1585 struct bnxt_re_cq *cq; 1586 int rc = 0; 1587 u8 event; 1588 1589 if (!obj) 1590 return rc; /* QP was already dead, still return success */ 1591 1592 event = affi_async->event; 1593 switch (event) { 1594 case CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION: 1595 lib_qp = obj; 1596 qp = container_of(lib_qp, struct bnxt_re_qp, qplib_qp); 1597 rc = bnxt_re_handle_qp_async_event(affi_async, qp); 1598 break; 1599 case CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION: 1600 lib_cq = obj; 1601 cq = container_of(lib_cq, struct bnxt_re_cq, qplib_cq); 1602 rc = bnxt_re_handle_cq_async_error(affi_async, cq); 1603 break; 1604 default: 1605 rc = -EINVAL; 1606 } 1607 return rc; 1608 } 1609 1610 static int bnxt_re_aeq_handler(struct bnxt_qplib_rcfw *rcfw, 1611 void *aeqe, void *obj) 1612 { 1613 struct creq_qp_event *affi_async; 1614 struct creq_func_event *unaffi_async; 1615 u8 type; 1616 int rc; 1617 1618 type = ((struct creq_base *)aeqe)->type; 1619 if (type == CREQ_BASE_TYPE_FUNC_EVENT) { 1620 unaffi_async = aeqe; 1621 rc = bnxt_re_handle_unaffi_async_event(unaffi_async); 1622 } else { 1623 affi_async = aeqe; 1624 rc = bnxt_re_handle_affi_async_event(affi_async, obj); 1625 } 1626 1627 return rc; 1628 } 1629 1630 static int bnxt_re_srqn_handler(struct bnxt_qplib_nq *nq, 1631 struct bnxt_qplib_srq *handle, u8 event) 1632 { 1633 struct bnxt_re_srq *srq = container_of(handle, struct bnxt_re_srq, 1634 qplib_srq); 1635 struct ib_event ib_event; 1636 1637 ib_event.device = &srq->rdev->ibdev; 1638 ib_event.element.srq = &srq->ib_srq; 1639 1640 if (srq->ib_srq.event_handler) { 1641 if (event == NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT) 1642 ib_event.event = IB_EVENT_SRQ_LIMIT_REACHED; 1643 (*srq->ib_srq.event_handler)(&ib_event, 1644 srq->ib_srq.srq_context); 1645 } 1646 return 0; 1647 } 1648 1649 static int bnxt_re_cqn_handler(struct bnxt_qplib_nq *nq, 1650 struct bnxt_qplib_cq *handle) 1651 { 1652 struct bnxt_re_cq *cq = container_of(handle, struct bnxt_re_cq, 1653 qplib_cq); 1654 1655 if (cq->ib_cq.comp_handler) 1656 (*cq->ib_cq.comp_handler)(&cq->ib_cq, cq->ib_cq.cq_context); 1657 1658 return 0; 1659 } 1660 1661 static void bnxt_re_cleanup_res(struct bnxt_re_dev *rdev) 1662 { 1663 int i; 1664 1665 for (i = 1; i < rdev->nqr->num_msix; i++) 1666 bnxt_qplib_disable_nq(&rdev->nqr->nq[i - 1]); 1667 1668 if (rdev->qplib_res.rcfw) 1669 bnxt_qplib_cleanup_res(&rdev->qplib_res); 1670 } 1671 1672 static int bnxt_re_init_res(struct bnxt_re_dev *rdev) 1673 { 1674 int num_vec_enabled = 0; 1675 int rc = 0, i; 1676 u32 db_offt; 1677 1678 bnxt_qplib_init_res(&rdev->qplib_res); 1679 1680 mutex_init(&rdev->nqr->load_lock); 1681 1682 for (i = 1; i < rdev->nqr->num_msix ; i++) { 1683 db_offt = rdev->nqr->msix_entries[i].db_offset; 1684 rc = bnxt_qplib_enable_nq(rdev->en_dev->pdev, &rdev->nqr->nq[i - 1], 1685 i - 1, rdev->nqr->msix_entries[i].vector, 1686 db_offt, &bnxt_re_cqn_handler, 1687 &bnxt_re_srqn_handler); 1688 if (rc) { 1689 ibdev_err(&rdev->ibdev, 1690 "Failed to enable NQ with rc = 0x%x", rc); 1691 goto fail; 1692 } 1693 num_vec_enabled++; 1694 } 1695 return 0; 1696 fail: 1697 for (i = num_vec_enabled; i >= 0; i--) 1698 bnxt_qplib_disable_nq(&rdev->nqr->nq[i]); 1699 return rc; 1700 } 1701 1702 static void bnxt_re_free_nq_res(struct bnxt_re_dev *rdev) 1703 { 1704 struct bnxt_qplib_nq *nq; 1705 u8 type; 1706 int i; 1707 1708 for (i = 0; i < rdev->nqr->num_msix - 1; i++) { 1709 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 1710 nq = &rdev->nqr->nq[i]; 1711 bnxt_re_net_ring_free(rdev, nq->ring_id, type); 1712 bnxt_qplib_free_nq(nq); 1713 nq->res = NULL; 1714 } 1715 } 1716 1717 static void bnxt_re_free_res(struct bnxt_re_dev *rdev) 1718 { 1719 bnxt_re_free_nq_res(rdev); 1720 1721 if (rdev->qplib_res.dpi_tbl.max) { 1722 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, 1723 &rdev->dpi_privileged); 1724 } 1725 if (rdev->qplib_res.rcfw) { 1726 bnxt_qplib_free_res(&rdev->qplib_res); 1727 rdev->qplib_res.rcfw = NULL; 1728 } 1729 } 1730 1731 static int bnxt_re_alloc_res(struct bnxt_re_dev *rdev) 1732 { 1733 struct bnxt_re_ring_attr rattr = {}; 1734 int num_vec_created = 0; 1735 int rc, i; 1736 u8 type; 1737 1738 /* Configure and allocate resources for qplib */ 1739 rdev->qplib_res.rcfw = &rdev->rcfw; 1740 rc = bnxt_qplib_get_dev_attr(&rdev->rcfw); 1741 if (rc) 1742 goto fail; 1743 1744 rc = bnxt_qplib_alloc_res(&rdev->qplib_res, rdev->netdev); 1745 if (rc) 1746 goto fail; 1747 1748 rc = bnxt_qplib_alloc_dpi(&rdev->qplib_res, 1749 &rdev->dpi_privileged, 1750 rdev, BNXT_QPLIB_DPI_TYPE_KERNEL); 1751 if (rc) 1752 goto dealloc_res; 1753 1754 for (i = 0; i < rdev->nqr->num_msix - 1; i++) { 1755 struct bnxt_qplib_nq *nq; 1756 1757 nq = &rdev->nqr->nq[i]; 1758 nq->hwq.max_elements = BNXT_QPLIB_NQE_MAX_CNT; 1759 rc = bnxt_qplib_alloc_nq(&rdev->qplib_res, nq); 1760 if (rc) { 1761 ibdev_err(&rdev->ibdev, "Alloc Failed NQ%d rc:%#x", 1762 i, rc); 1763 goto free_nq; 1764 } 1765 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 1766 rattr.dma_arr = nq->hwq.pbl[PBL_LVL_0].pg_map_arr; 1767 rattr.pages = nq->hwq.pbl[rdev->nqr->nq[i].hwq.level].pg_count; 1768 rattr.type = type; 1769 rattr.mode = RING_ALLOC_REQ_INT_MODE_MSIX; 1770 rattr.depth = BNXT_QPLIB_NQE_MAX_CNT - 1; 1771 rattr.lrid = rdev->nqr->msix_entries[i + 1].ring_idx; 1772 rc = bnxt_re_net_ring_alloc(rdev, &rattr, &nq->ring_id); 1773 if (rc) { 1774 ibdev_err(&rdev->ibdev, 1775 "Failed to allocate NQ fw id with rc = 0x%x", 1776 rc); 1777 bnxt_qplib_free_nq(nq); 1778 goto free_nq; 1779 } 1780 num_vec_created++; 1781 } 1782 return 0; 1783 free_nq: 1784 for (i = num_vec_created - 1; i >= 0; i--) { 1785 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 1786 bnxt_re_net_ring_free(rdev, rdev->nqr->nq[i].ring_id, type); 1787 bnxt_qplib_free_nq(&rdev->nqr->nq[i]); 1788 } 1789 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, 1790 &rdev->dpi_privileged); 1791 dealloc_res: 1792 bnxt_qplib_free_res(&rdev->qplib_res); 1793 1794 fail: 1795 rdev->qplib_res.rcfw = NULL; 1796 return rc; 1797 } 1798 1799 static void bnxt_re_dispatch_event(struct ib_device *ibdev, struct ib_qp *qp, 1800 u8 port_num, enum ib_event_type event) 1801 { 1802 struct ib_event ib_event; 1803 1804 ib_event.device = ibdev; 1805 if (qp) { 1806 ib_event.element.qp = qp; 1807 ib_event.event = event; 1808 if (qp->event_handler) 1809 qp->event_handler(&ib_event, qp->qp_context); 1810 1811 } else { 1812 ib_event.element.port_num = port_num; 1813 ib_event.event = event; 1814 ib_dispatch_event(&ib_event); 1815 } 1816 } 1817 1818 static bool bnxt_re_is_qp1_or_shadow_qp(struct bnxt_re_dev *rdev, 1819 struct bnxt_re_qp *qp) 1820 { 1821 return (qp->ib_qp.qp_type == IB_QPT_GSI) || 1822 (qp == rdev->gsi_ctx.gsi_sqp); 1823 } 1824 1825 static void bnxt_re_dev_stop(struct bnxt_re_dev *rdev) 1826 { 1827 struct bnxt_re_qp *qp; 1828 1829 mutex_lock(&rdev->qp_lock); 1830 list_for_each_entry(qp, &rdev->qp_list, list) { 1831 /* Modify the state of all QPs except QP1/Shadow QP */ 1832 if (!bnxt_re_is_qp1_or_shadow_qp(rdev, qp)) { 1833 if (qp->qplib_qp.state != 1834 CMDQ_MODIFY_QP_NEW_STATE_RESET && 1835 qp->qplib_qp.state != 1836 CMDQ_MODIFY_QP_NEW_STATE_ERR) 1837 bnxt_re_dispatch_event(&rdev->ibdev, &qp->ib_qp, 1838 1, IB_EVENT_QP_FATAL); 1839 } 1840 } 1841 mutex_unlock(&rdev->qp_lock); 1842 } 1843 1844 static int bnxt_re_update_gid(struct bnxt_re_dev *rdev) 1845 { 1846 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 1847 struct bnxt_qplib_gid gid; 1848 u16 gid_idx, index; 1849 int rc = 0; 1850 1851 if (!ib_device_try_get(&rdev->ibdev)) 1852 return 0; 1853 1854 for (index = 0; index < sgid_tbl->active; index++) { 1855 gid_idx = sgid_tbl->hw_id[index]; 1856 1857 if (!memcmp(&sgid_tbl->tbl[index], &bnxt_qplib_gid_zero, 1858 sizeof(bnxt_qplib_gid_zero))) 1859 continue; 1860 /* need to modify the VLAN enable setting of non VLAN GID only 1861 * as setting is done for VLAN GID while adding GID 1862 */ 1863 if (sgid_tbl->vlan[index]) 1864 continue; 1865 1866 memcpy(&gid, &sgid_tbl->tbl[index], sizeof(gid)); 1867 1868 rc = bnxt_qplib_update_sgid(sgid_tbl, &gid, gid_idx, 1869 rdev->qplib_res.netdev->dev_addr); 1870 } 1871 1872 ib_device_put(&rdev->ibdev); 1873 return rc; 1874 } 1875 1876 static u32 bnxt_re_get_priority_mask(struct bnxt_re_dev *rdev) 1877 { 1878 u32 prio_map = 0, tmp_map = 0; 1879 struct net_device *netdev; 1880 struct dcb_app app = {}; 1881 1882 netdev = rdev->netdev; 1883 1884 app.selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE; 1885 app.protocol = ETH_P_IBOE; 1886 tmp_map = dcb_ieee_getapp_mask(netdev, &app); 1887 prio_map = tmp_map; 1888 1889 app.selector = IEEE_8021QAZ_APP_SEL_DGRAM; 1890 app.protocol = ROCE_V2_UDP_DPORT; 1891 tmp_map = dcb_ieee_getapp_mask(netdev, &app); 1892 prio_map |= tmp_map; 1893 1894 return prio_map; 1895 } 1896 1897 static int bnxt_re_setup_qos(struct bnxt_re_dev *rdev) 1898 { 1899 u8 prio_map = 0; 1900 1901 /* Get priority for roce */ 1902 prio_map = bnxt_re_get_priority_mask(rdev); 1903 1904 if (prio_map == rdev->cur_prio_map) 1905 return 0; 1906 rdev->cur_prio_map = prio_map; 1907 /* Actual priorities are not programmed as they are already 1908 * done by L2 driver; just enable or disable priority vlan tagging 1909 */ 1910 if ((prio_map == 0 && rdev->qplib_res.prio) || 1911 (prio_map != 0 && !rdev->qplib_res.prio)) { 1912 rdev->qplib_res.prio = prio_map; 1913 bnxt_re_update_gid(rdev); 1914 } 1915 1916 return 0; 1917 } 1918 1919 static void bnxt_re_net_unregister_async_event(struct bnxt_re_dev *rdev) 1920 { 1921 if (rdev->is_virtfn) 1922 return; 1923 1924 memset(&rdev->event_bitmap, 0, sizeof(rdev->event_bitmap)); 1925 bnxt_register_async_events(rdev->en_dev, &rdev->event_bitmap, 1926 ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE); 1927 } 1928 1929 static void bnxt_re_net_register_async_event(struct bnxt_re_dev *rdev) 1930 { 1931 if (rdev->is_virtfn) 1932 return; 1933 1934 rdev->event_bitmap |= (1 << ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE); 1935 bnxt_register_async_events(rdev->en_dev, &rdev->event_bitmap, 1936 ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE); 1937 } 1938 1939 static void bnxt_re_query_hwrm_intf_version(struct bnxt_re_dev *rdev) 1940 { 1941 struct bnxt_en_dev *en_dev = rdev->en_dev; 1942 struct hwrm_ver_get_output resp = {}; 1943 struct hwrm_ver_get_input req = {}; 1944 struct bnxt_qplib_chip_ctx *cctx; 1945 struct bnxt_fw_msg fw_msg = {}; 1946 int rc; 1947 1948 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_VER_GET); 1949 req.hwrm_intf_maj = HWRM_VERSION_MAJOR; 1950 req.hwrm_intf_min = HWRM_VERSION_MINOR; 1951 req.hwrm_intf_upd = HWRM_VERSION_UPDATE; 1952 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), (void *)&resp, 1953 sizeof(resp), DFLT_HWRM_CMD_TIMEOUT); 1954 rc = bnxt_send_msg(en_dev, &fw_msg); 1955 if (rc) { 1956 ibdev_err(&rdev->ibdev, "Failed to query HW version, rc = 0x%x", 1957 rc); 1958 return; 1959 } 1960 1961 cctx = rdev->chip_ctx; 1962 cctx->hwrm_intf_ver = 1963 (u64)le16_to_cpu(resp.hwrm_intf_major) << 48 | 1964 (u64)le16_to_cpu(resp.hwrm_intf_minor) << 32 | 1965 (u64)le16_to_cpu(resp.hwrm_intf_build) << 16 | 1966 le16_to_cpu(resp.hwrm_intf_patch); 1967 1968 cctx->hwrm_cmd_max_timeout = le16_to_cpu(resp.max_req_timeout); 1969 1970 if (!cctx->hwrm_cmd_max_timeout) 1971 cctx->hwrm_cmd_max_timeout = RCFW_FW_STALL_MAX_TIMEOUT; 1972 } 1973 1974 static int bnxt_re_ib_init(struct bnxt_re_dev *rdev) 1975 { 1976 int rc; 1977 u32 event; 1978 1979 /* Register ib dev */ 1980 rc = bnxt_re_register_ib(rdev); 1981 if (rc) { 1982 pr_err("Failed to register with IB: %#x\n", rc); 1983 return rc; 1984 } 1985 dev_info(rdev_to_dev(rdev), "Device registered with IB successfully"); 1986 set_bit(BNXT_RE_FLAG_ISSUE_ROCE_STATS, &rdev->flags); 1987 1988 event = netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev) ? 1989 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 1990 1991 bnxt_re_dispatch_event(&rdev->ibdev, NULL, 1, event); 1992 1993 return rc; 1994 } 1995 1996 static int bnxt_re_alloc_nqr_mem(struct bnxt_re_dev *rdev) 1997 { 1998 rdev->nqr = kzalloc(sizeof(*rdev->nqr), GFP_KERNEL); 1999 if (!rdev->nqr) 2000 return -ENOMEM; 2001 2002 return 0; 2003 } 2004 2005 static void bnxt_re_free_nqr_mem(struct bnxt_re_dev *rdev) 2006 { 2007 kfree(rdev->nqr); 2008 rdev->nqr = NULL; 2009 } 2010 2011 static void bnxt_re_dev_uninit(struct bnxt_re_dev *rdev, u8 op_type) 2012 { 2013 u8 type; 2014 int rc; 2015 2016 bnxt_re_debugfs_rem_pdev(rdev); 2017 2018 bnxt_re_net_unregister_async_event(rdev); 2019 bnxt_re_uninit_dcb_wq(rdev); 2020 2021 if (test_and_clear_bit(BNXT_RE_FLAG_QOS_WORK_REG, &rdev->flags)) 2022 cancel_delayed_work_sync(&rdev->worker); 2023 2024 if (test_and_clear_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED, 2025 &rdev->flags)) 2026 bnxt_re_cleanup_res(rdev); 2027 if (test_and_clear_bit(BNXT_RE_FLAG_RESOURCES_ALLOCATED, &rdev->flags)) 2028 bnxt_re_free_res(rdev); 2029 2030 if (test_and_clear_bit(BNXT_RE_FLAG_RCFW_CHANNEL_EN, &rdev->flags)) { 2031 rc = bnxt_qplib_deinit_rcfw(&rdev->rcfw); 2032 if (rc) 2033 ibdev_warn(&rdev->ibdev, 2034 "Failed to deinitialize RCFW: %#x", rc); 2035 bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id); 2036 bnxt_qplib_free_ctx(&rdev->qplib_res, &rdev->qplib_ctx); 2037 bnxt_qplib_disable_rcfw_channel(&rdev->rcfw); 2038 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 2039 bnxt_re_net_ring_free(rdev, rdev->rcfw.creq.ring_id, type); 2040 bnxt_qplib_free_rcfw_channel(&rdev->rcfw); 2041 } 2042 2043 rdev->nqr->num_msix = 0; 2044 2045 if (rdev->pacing.dbr_pacing) 2046 bnxt_re_deinitialize_dbr_pacing(rdev); 2047 2048 bnxt_re_free_nqr_mem(rdev); 2049 bnxt_re_destroy_chip_ctx(rdev); 2050 if (op_type == BNXT_RE_COMPLETE_REMOVE) { 2051 if (test_and_clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags)) 2052 bnxt_unregister_dev(rdev->en_dev); 2053 } 2054 } 2055 2056 /* worker thread for polling periodic events. Now used for QoS programming*/ 2057 static void bnxt_re_worker(struct work_struct *work) 2058 { 2059 struct bnxt_re_dev *rdev = container_of(work, struct bnxt_re_dev, 2060 worker.work); 2061 2062 bnxt_re_setup_qos(rdev); 2063 schedule_delayed_work(&rdev->worker, msecs_to_jiffies(30000)); 2064 } 2065 2066 static int bnxt_re_dev_init(struct bnxt_re_dev *rdev, u8 op_type) 2067 { 2068 struct bnxt_re_ring_attr rattr = {}; 2069 struct bnxt_qplib_creq_ctx *creq; 2070 u32 db_offt; 2071 int vid; 2072 u8 type; 2073 int rc; 2074 2075 if (op_type == BNXT_RE_COMPLETE_INIT) { 2076 /* Registered a new RoCE device instance to netdev */ 2077 rc = bnxt_re_register_netdev(rdev); 2078 if (rc) { 2079 ibdev_err(&rdev->ibdev, 2080 "Failed to register with netedev: %#x\n", rc); 2081 return -EINVAL; 2082 } 2083 } 2084 set_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags); 2085 2086 if (rdev->en_dev->ulp_tbl->msix_requested < BNXT_RE_MIN_MSIX) { 2087 ibdev_err(&rdev->ibdev, 2088 "RoCE requires minimum 2 MSI-X vectors, but only %d reserved\n", 2089 rdev->en_dev->ulp_tbl->msix_requested); 2090 bnxt_unregister_dev(rdev->en_dev); 2091 clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags); 2092 return -EINVAL; 2093 } 2094 ibdev_dbg(&rdev->ibdev, "Got %d MSI-X vectors\n", 2095 rdev->en_dev->ulp_tbl->msix_requested); 2096 2097 rc = bnxt_re_setup_chip_ctx(rdev); 2098 if (rc) { 2099 bnxt_unregister_dev(rdev->en_dev); 2100 clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags); 2101 ibdev_err(&rdev->ibdev, "Failed to get chip context\n"); 2102 return -EINVAL; 2103 } 2104 2105 rc = bnxt_re_alloc_nqr_mem(rdev); 2106 if (rc) { 2107 bnxt_re_destroy_chip_ctx(rdev); 2108 bnxt_unregister_dev(rdev->en_dev); 2109 clear_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags); 2110 return rc; 2111 } 2112 rdev->nqr->num_msix = rdev->en_dev->ulp_tbl->msix_requested; 2113 memcpy(rdev->nqr->msix_entries, rdev->en_dev->msix_entries, 2114 sizeof(struct bnxt_msix_entry) * rdev->nqr->num_msix); 2115 2116 /* Check whether VF or PF */ 2117 bnxt_re_get_sriov_func_type(rdev); 2118 2119 bnxt_re_query_hwrm_intf_version(rdev); 2120 2121 /* Establish RCFW Communication Channel to initialize the context 2122 * memory for the function and all child VFs 2123 */ 2124 rc = bnxt_qplib_alloc_rcfw_channel(&rdev->qplib_res, &rdev->rcfw, 2125 &rdev->qplib_ctx, 2126 BNXT_RE_MAX_QPC_COUNT); 2127 if (rc) { 2128 ibdev_err(&rdev->ibdev, 2129 "Failed to allocate RCFW Channel: %#x\n", rc); 2130 goto fail; 2131 } 2132 2133 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 2134 creq = &rdev->rcfw.creq; 2135 rattr.dma_arr = creq->hwq.pbl[PBL_LVL_0].pg_map_arr; 2136 rattr.pages = creq->hwq.pbl[creq->hwq.level].pg_count; 2137 rattr.type = type; 2138 rattr.mode = RING_ALLOC_REQ_INT_MODE_MSIX; 2139 rattr.depth = BNXT_QPLIB_CREQE_MAX_CNT - 1; 2140 rattr.lrid = rdev->nqr->msix_entries[BNXT_RE_AEQ_IDX].ring_idx; 2141 rc = bnxt_re_net_ring_alloc(rdev, &rattr, &creq->ring_id); 2142 if (rc) { 2143 ibdev_err(&rdev->ibdev, "Failed to allocate CREQ: %#x\n", rc); 2144 goto free_rcfw; 2145 } 2146 db_offt = rdev->nqr->msix_entries[BNXT_RE_AEQ_IDX].db_offset; 2147 vid = rdev->nqr->msix_entries[BNXT_RE_AEQ_IDX].vector; 2148 rc = bnxt_qplib_enable_rcfw_channel(&rdev->rcfw, 2149 vid, db_offt, 2150 &bnxt_re_aeq_handler); 2151 if (rc) { 2152 ibdev_err(&rdev->ibdev, "Failed to enable RCFW channel: %#x\n", 2153 rc); 2154 goto free_ring; 2155 } 2156 2157 if (bnxt_qplib_dbr_pacing_en(rdev->chip_ctx)) { 2158 rc = bnxt_re_initialize_dbr_pacing(rdev); 2159 if (!rc) { 2160 rdev->pacing.dbr_pacing = true; 2161 } else { 2162 ibdev_err(&rdev->ibdev, 2163 "DBR pacing disabled with error : %d\n", rc); 2164 rdev->pacing.dbr_pacing = false; 2165 } 2166 } 2167 rc = bnxt_qplib_get_dev_attr(&rdev->rcfw); 2168 if (rc) 2169 goto disable_rcfw; 2170 2171 bnxt_re_set_resource_limits(rdev); 2172 2173 rc = bnxt_qplib_alloc_ctx(&rdev->qplib_res, &rdev->qplib_ctx, 0, 2174 bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)); 2175 if (rc) { 2176 ibdev_err(&rdev->ibdev, 2177 "Failed to allocate QPLIB context: %#x\n", rc); 2178 goto disable_rcfw; 2179 } 2180 rc = bnxt_re_net_stats_ctx_alloc(rdev, 2181 rdev->qplib_ctx.stats.dma_map, 2182 &rdev->qplib_ctx.stats.fw_id); 2183 if (rc) { 2184 ibdev_err(&rdev->ibdev, 2185 "Failed to allocate stats context: %#x\n", rc); 2186 goto free_ctx; 2187 } 2188 2189 rc = bnxt_qplib_init_rcfw(&rdev->rcfw, &rdev->qplib_ctx, 2190 rdev->is_virtfn); 2191 if (rc) { 2192 ibdev_err(&rdev->ibdev, 2193 "Failed to initialize RCFW: %#x\n", rc); 2194 goto free_sctx; 2195 } 2196 set_bit(BNXT_RE_FLAG_RCFW_CHANNEL_EN, &rdev->flags); 2197 2198 /* Resources based on the 'new' device caps */ 2199 rc = bnxt_re_alloc_res(rdev); 2200 if (rc) { 2201 ibdev_err(&rdev->ibdev, 2202 "Failed to allocate resources: %#x\n", rc); 2203 goto fail; 2204 } 2205 set_bit(BNXT_RE_FLAG_RESOURCES_ALLOCATED, &rdev->flags); 2206 rc = bnxt_re_init_res(rdev); 2207 if (rc) { 2208 ibdev_err(&rdev->ibdev, 2209 "Failed to initialize resources: %#x\n", rc); 2210 goto fail; 2211 } 2212 2213 set_bit(BNXT_RE_FLAG_RESOURCES_INITIALIZED, &rdev->flags); 2214 2215 if (!rdev->is_virtfn) { 2216 /* Query f/w defaults of CC params */ 2217 rc = bnxt_qplib_query_cc_param(&rdev->qplib_res, &rdev->cc_param); 2218 if (rc) 2219 ibdev_warn(&rdev->ibdev, "Failed to query CC defaults\n"); 2220 2221 rc = bnxt_re_setup_qos(rdev); 2222 if (rc) 2223 ibdev_info(&rdev->ibdev, 2224 "RoCE priority not yet configured\n"); 2225 2226 INIT_DELAYED_WORK(&rdev->worker, bnxt_re_worker); 2227 set_bit(BNXT_RE_FLAG_QOS_WORK_REG, &rdev->flags); 2228 schedule_delayed_work(&rdev->worker, msecs_to_jiffies(30000)); 2229 2230 if (!(rdev->qplib_res.en_dev->flags & BNXT_EN_FLAG_ROCE_VF_RES_MGMT)) 2231 bnxt_re_vf_res_config(rdev); 2232 } 2233 hash_init(rdev->cq_hash); 2234 if (rdev->chip_ctx->modes.toggle_bits & BNXT_QPLIB_SRQ_TOGGLE_BIT) 2235 hash_init(rdev->srq_hash); 2236 2237 bnxt_re_debugfs_add_pdev(rdev); 2238 2239 bnxt_re_init_dcb_wq(rdev); 2240 bnxt_re_net_register_async_event(rdev); 2241 2242 return 0; 2243 free_sctx: 2244 bnxt_re_net_stats_ctx_free(rdev, rdev->qplib_ctx.stats.fw_id); 2245 free_ctx: 2246 bnxt_qplib_free_ctx(&rdev->qplib_res, &rdev->qplib_ctx); 2247 disable_rcfw: 2248 bnxt_qplib_disable_rcfw_channel(&rdev->rcfw); 2249 free_ring: 2250 type = bnxt_qplib_get_ring_type(rdev->chip_ctx); 2251 bnxt_re_net_ring_free(rdev, rdev->rcfw.creq.ring_id, type); 2252 free_rcfw: 2253 bnxt_qplib_free_rcfw_channel(&rdev->rcfw); 2254 fail: 2255 bnxt_re_dev_uninit(rdev, BNXT_RE_COMPLETE_REMOVE); 2256 2257 return rc; 2258 } 2259 2260 static void bnxt_re_setup_cc(struct bnxt_re_dev *rdev, bool enable) 2261 { 2262 struct bnxt_qplib_cc_param cc_param = {}; 2263 2264 /* Do not enable congestion control on VFs */ 2265 if (rdev->is_virtfn) 2266 return; 2267 2268 /* Currently enabling only for GenP5 adapters */ 2269 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) 2270 return; 2271 2272 if (enable) { 2273 cc_param.enable = 1; 2274 cc_param.tos_ecn = 1; 2275 } 2276 2277 cc_param.mask = (CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC | 2278 CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN); 2279 2280 if (bnxt_qplib_modify_cc(&rdev->qplib_res, &cc_param)) 2281 ibdev_err(&rdev->ibdev, "Failed to setup CC enable = %d\n", enable); 2282 } 2283 2284 static void bnxt_re_update_en_info_rdev(struct bnxt_re_dev *rdev, 2285 struct bnxt_re_en_dev_info *en_info, 2286 struct auxiliary_device *adev) 2287 { 2288 /* Before updating the rdev pointer in bnxt_re_en_dev_info structure, 2289 * take the rtnl lock to avoid accessing invalid rdev pointer from 2290 * L2 ULP callbacks. This is applicable in all the places where rdev 2291 * pointer is updated in bnxt_re_en_dev_info. 2292 */ 2293 rtnl_lock(); 2294 en_info->rdev = rdev; 2295 rtnl_unlock(); 2296 } 2297 2298 static int bnxt_re_add_device(struct auxiliary_device *adev, u8 op_type) 2299 { 2300 struct bnxt_aux_priv *aux_priv = 2301 container_of(adev, struct bnxt_aux_priv, aux_dev); 2302 struct bnxt_re_en_dev_info *en_info; 2303 struct bnxt_en_dev *en_dev; 2304 struct bnxt_re_dev *rdev; 2305 int rc; 2306 2307 en_info = auxiliary_get_drvdata(adev); 2308 en_dev = en_info->en_dev; 2309 2310 2311 rdev = bnxt_re_dev_add(adev, en_dev); 2312 if (!rdev || !rdev_to_dev(rdev)) { 2313 rc = -ENOMEM; 2314 goto exit; 2315 } 2316 2317 bnxt_re_update_en_info_rdev(rdev, en_info, adev); 2318 2319 rc = bnxt_re_dev_init(rdev, op_type); 2320 if (rc) 2321 goto re_dev_dealloc; 2322 2323 rc = bnxt_re_ib_init(rdev); 2324 if (rc) { 2325 pr_err("Failed to register with IB: %s", 2326 aux_priv->aux_dev.name); 2327 goto re_dev_uninit; 2328 } 2329 2330 bnxt_re_setup_cc(rdev, true); 2331 2332 return 0; 2333 2334 re_dev_uninit: 2335 bnxt_re_update_en_info_rdev(NULL, en_info, adev); 2336 bnxt_re_dev_uninit(rdev, BNXT_RE_COMPLETE_REMOVE); 2337 re_dev_dealloc: 2338 ib_dealloc_device(&rdev->ibdev); 2339 exit: 2340 return rc; 2341 } 2342 2343 #define BNXT_ADEV_NAME "bnxt_en" 2344 2345 static void bnxt_re_remove_device(struct bnxt_re_dev *rdev, u8 op_type, 2346 struct auxiliary_device *aux_dev) 2347 { 2348 if (rdev->nb.notifier_call) { 2349 unregister_netdevice_notifier(&rdev->nb); 2350 rdev->nb.notifier_call = NULL; 2351 } else { 2352 /* If notifier is null, we should have already done a 2353 * clean up before coming here. 2354 */ 2355 return; 2356 } 2357 bnxt_re_setup_cc(rdev, false); 2358 ib_unregister_device(&rdev->ibdev); 2359 bnxt_re_dev_uninit(rdev, op_type); 2360 ib_dealloc_device(&rdev->ibdev); 2361 } 2362 2363 static void bnxt_re_remove(struct auxiliary_device *adev) 2364 { 2365 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev); 2366 struct bnxt_re_dev *rdev; 2367 2368 mutex_lock(&bnxt_re_mutex); 2369 rdev = en_info->rdev; 2370 2371 if (rdev) 2372 bnxt_re_remove_device(rdev, BNXT_RE_COMPLETE_REMOVE, adev); 2373 kfree(en_info); 2374 mutex_unlock(&bnxt_re_mutex); 2375 } 2376 2377 static int bnxt_re_probe(struct auxiliary_device *adev, 2378 const struct auxiliary_device_id *id) 2379 { 2380 struct bnxt_aux_priv *aux_priv = 2381 container_of(adev, struct bnxt_aux_priv, aux_dev); 2382 struct bnxt_re_en_dev_info *en_info; 2383 struct bnxt_en_dev *en_dev; 2384 int rc; 2385 2386 en_dev = aux_priv->edev; 2387 2388 mutex_lock(&bnxt_re_mutex); 2389 en_info = kzalloc(sizeof(*en_info), GFP_KERNEL); 2390 if (!en_info) { 2391 mutex_unlock(&bnxt_re_mutex); 2392 return -ENOMEM; 2393 } 2394 en_info->en_dev = en_dev; 2395 2396 auxiliary_set_drvdata(adev, en_info); 2397 2398 rc = bnxt_re_add_device(adev, BNXT_RE_COMPLETE_INIT); 2399 if (rc) 2400 kfree(en_info); 2401 2402 mutex_unlock(&bnxt_re_mutex); 2403 2404 return rc; 2405 } 2406 2407 static int bnxt_re_suspend(struct auxiliary_device *adev, pm_message_t state) 2408 { 2409 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev); 2410 struct bnxt_en_dev *en_dev; 2411 struct bnxt_re_dev *rdev; 2412 2413 rdev = en_info->rdev; 2414 en_dev = en_info->en_dev; 2415 mutex_lock(&bnxt_re_mutex); 2416 2417 ibdev_info(&rdev->ibdev, "Handle device suspend call"); 2418 /* Check the current device state from bnxt_en_dev and move the 2419 * device to detached state if FW_FATAL_COND is set. 2420 * This prevents more commands to HW during clean-up, 2421 * in case the device is already in error. 2422 */ 2423 if (test_bit(BNXT_STATE_FW_FATAL_COND, &rdev->en_dev->en_state)) { 2424 set_bit(ERR_DEVICE_DETACHED, &rdev->rcfw.cmdq.flags); 2425 set_bit(BNXT_RE_FLAG_ERR_DEVICE_DETACHED, &rdev->flags); 2426 wake_up_all(&rdev->rcfw.cmdq.waitq); 2427 bnxt_re_dev_stop(rdev); 2428 } 2429 2430 if (rdev->pacing.dbr_pacing) 2431 bnxt_re_set_pacing_dev_state(rdev); 2432 2433 ibdev_info(&rdev->ibdev, "%s: L2 driver notified to stop en_state 0x%lx", 2434 __func__, en_dev->en_state); 2435 bnxt_re_remove_device(rdev, BNXT_RE_PRE_RECOVERY_REMOVE, adev); 2436 mutex_unlock(&bnxt_re_mutex); 2437 2438 return 0; 2439 } 2440 2441 static int bnxt_re_resume(struct auxiliary_device *adev) 2442 { 2443 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev); 2444 struct bnxt_re_dev *rdev; 2445 2446 mutex_lock(&bnxt_re_mutex); 2447 bnxt_re_add_device(adev, BNXT_RE_POST_RECOVERY_INIT); 2448 rdev = en_info->rdev; 2449 ibdev_info(&rdev->ibdev, "Device resume completed"); 2450 mutex_unlock(&bnxt_re_mutex); 2451 2452 return 0; 2453 } 2454 2455 static void bnxt_re_shutdown(struct auxiliary_device *adev) 2456 { 2457 struct bnxt_re_en_dev_info *en_info = auxiliary_get_drvdata(adev); 2458 struct bnxt_re_dev *rdev; 2459 2460 rdev = en_info->rdev; 2461 ib_unregister_device(&rdev->ibdev); 2462 bnxt_re_dev_uninit(rdev, BNXT_RE_COMPLETE_REMOVE); 2463 } 2464 2465 static const struct auxiliary_device_id bnxt_re_id_table[] = { 2466 { .name = BNXT_ADEV_NAME ".rdma", }, 2467 {}, 2468 }; 2469 2470 MODULE_DEVICE_TABLE(auxiliary, bnxt_re_id_table); 2471 2472 static struct auxiliary_driver bnxt_re_driver = { 2473 .name = "rdma", 2474 .probe = bnxt_re_probe, 2475 .remove = bnxt_re_remove, 2476 .shutdown = bnxt_re_shutdown, 2477 .suspend = bnxt_re_suspend, 2478 .resume = bnxt_re_resume, 2479 .id_table = bnxt_re_id_table, 2480 }; 2481 2482 static int __init bnxt_re_mod_init(void) 2483 { 2484 int rc; 2485 2486 pr_info("%s: %s", ROCE_DRV_MODULE_NAME, version); 2487 bnxt_re_register_debugfs(); 2488 2489 rc = auxiliary_driver_register(&bnxt_re_driver); 2490 if (rc) { 2491 pr_err("%s: Failed to register auxiliary driver\n", 2492 ROCE_DRV_MODULE_NAME); 2493 goto err_debug; 2494 } 2495 return 0; 2496 err_debug: 2497 bnxt_re_unregister_debugfs(); 2498 return rc; 2499 } 2500 2501 static void __exit bnxt_re_mod_exit(void) 2502 { 2503 auxiliary_driver_unregister(&bnxt_re_driver); 2504 bnxt_re_unregister_debugfs(); 2505 } 2506 2507 module_init(bnxt_re_mod_init); 2508 module_exit(bnxt_re_mod_exit); 2509