1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Freescale Vybrid vf610 ADC driver 4 * 5 * Copyright 2013 Freescale Semiconductor, Inc. 6 */ 7 8 #include <linux/mod_devicetable.h> 9 #include <linux/module.h> 10 #include <linux/mutex.h> 11 #include <linux/property.h> 12 #include <linux/platform_device.h> 13 #include <linux/interrupt.h> 14 #include <linux/delay.h> 15 #include <linux/kernel.h> 16 #include <linux/slab.h> 17 #include <linux/io.h> 18 #include <linux/clk.h> 19 #include <linux/completion.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/err.h> 22 23 #include <linux/iio/iio.h> 24 #include <linux/iio/buffer.h> 25 #include <linux/iio/sysfs.h> 26 #include <linux/iio/trigger.h> 27 #include <linux/iio/trigger_consumer.h> 28 #include <linux/iio/triggered_buffer.h> 29 30 /* This will be the driver name the kernel reports */ 31 #define DRIVER_NAME "vf610-adc" 32 33 /* Vybrid/IMX ADC registers */ 34 #define VF610_REG_ADC_HC0 0x00 35 #define VF610_REG_ADC_HC1 0x04 36 #define VF610_REG_ADC_HS 0x08 37 #define VF610_REG_ADC_R0 0x0c 38 #define VF610_REG_ADC_R1 0x10 39 #define VF610_REG_ADC_CFG 0x14 40 #define VF610_REG_ADC_GC 0x18 41 #define VF610_REG_ADC_GS 0x1c 42 #define VF610_REG_ADC_CV 0x20 43 #define VF610_REG_ADC_OFS 0x24 44 #define VF610_REG_ADC_CAL 0x28 45 #define VF610_REG_ADC_PCTL 0x30 46 47 /* Configuration register field define */ 48 #define VF610_ADC_MODE_BIT8 0x00 49 #define VF610_ADC_MODE_BIT10 0x04 50 #define VF610_ADC_MODE_BIT12 0x08 51 #define VF610_ADC_MODE_MASK 0x0c 52 #define VF610_ADC_BUSCLK2_SEL 0x01 53 #define VF610_ADC_ALTCLK_SEL 0x02 54 #define VF610_ADC_ADACK_SEL 0x03 55 #define VF610_ADC_ADCCLK_MASK 0x03 56 #define VF610_ADC_CLK_DIV2 0x20 57 #define VF610_ADC_CLK_DIV4 0x40 58 #define VF610_ADC_CLK_DIV8 0x60 59 #define VF610_ADC_CLK_MASK 0x60 60 #define VF610_ADC_ADLSMP_LONG 0x10 61 #define VF610_ADC_ADSTS_SHORT 0x100 62 #define VF610_ADC_ADSTS_NORMAL 0x200 63 #define VF610_ADC_ADSTS_LONG 0x300 64 #define VF610_ADC_ADSTS_MASK 0x300 65 #define VF610_ADC_ADLPC_EN 0x80 66 #define VF610_ADC_ADHSC_EN 0x400 67 #define VF610_ADC_REFSEL_VALT 0x800 68 #define VF610_ADC_REFSEL_VBG 0x1000 69 #define VF610_ADC_ADTRG_HARD 0x2000 70 #define VF610_ADC_AVGS_8 0x4000 71 #define VF610_ADC_AVGS_16 0x8000 72 #define VF610_ADC_AVGS_32 0xC000 73 #define VF610_ADC_AVGS_MASK 0xC000 74 #define VF610_ADC_OVWREN 0x10000 75 76 /* General control register field define */ 77 #define VF610_ADC_ADACKEN 0x1 78 #define VF610_ADC_DMAEN 0x2 79 #define VF610_ADC_ACREN 0x4 80 #define VF610_ADC_ACFGT 0x8 81 #define VF610_ADC_ACFE 0x10 82 #define VF610_ADC_AVGEN 0x20 83 #define VF610_ADC_ADCON 0x40 84 #define VF610_ADC_CAL 0x80 85 86 /* Other field define */ 87 #define VF610_ADC_ADCHC(x) ((x) & 0x1F) 88 #define VF610_ADC_AIEN (0x1 << 7) 89 #define VF610_ADC_CONV_DISABLE 0x1F 90 #define VF610_ADC_HS_COCO0 0x1 91 #define VF610_ADC_CALF 0x2 92 #define VF610_ADC_TIMEOUT msecs_to_jiffies(100) 93 94 #define DEFAULT_SAMPLE_TIME 1000 95 96 /* V at 25°C of 696 mV */ 97 #define VF610_VTEMP25_3V0 950 98 /* V at 25°C of 699 mV */ 99 #define VF610_VTEMP25_3V3 867 100 /* Typical sensor slope coefficient at all temperatures */ 101 #define VF610_TEMP_SLOPE_COEFF 1840 102 103 enum clk_sel { 104 VF610_ADCIOC_BUSCLK_SET, 105 VF610_ADCIOC_ALTCLK_SET, 106 VF610_ADCIOC_ADACK_SET, 107 }; 108 109 enum vol_ref { 110 VF610_ADCIOC_VR_VREF_SET, 111 VF610_ADCIOC_VR_VALT_SET, 112 VF610_ADCIOC_VR_VBG_SET, 113 }; 114 115 enum average_sel { 116 VF610_ADC_SAMPLE_1, 117 VF610_ADC_SAMPLE_4, 118 VF610_ADC_SAMPLE_8, 119 VF610_ADC_SAMPLE_16, 120 VF610_ADC_SAMPLE_32, 121 }; 122 123 enum conversion_mode_sel { 124 VF610_ADC_CONV_NORMAL, 125 VF610_ADC_CONV_HIGH_SPEED, 126 VF610_ADC_CONV_LOW_POWER, 127 }; 128 129 enum lst_adder_sel { 130 VF610_ADCK_CYCLES_3, 131 VF610_ADCK_CYCLES_5, 132 VF610_ADCK_CYCLES_7, 133 VF610_ADCK_CYCLES_9, 134 VF610_ADCK_CYCLES_13, 135 VF610_ADCK_CYCLES_17, 136 VF610_ADCK_CYCLES_21, 137 VF610_ADCK_CYCLES_25, 138 }; 139 140 struct vf610_adc_feature { 141 enum clk_sel clk_sel; 142 enum vol_ref vol_ref; 143 enum conversion_mode_sel conv_mode; 144 145 int clk_div; 146 int sample_rate; 147 int res_mode; 148 u32 lst_adder_index; 149 u32 default_sample_time; 150 151 bool calibration; 152 bool ovwren; 153 }; 154 155 struct vf610_adc { 156 struct device *dev; 157 void __iomem *regs; 158 struct clk *clk; 159 160 /* lock to protect against multiple access to the device */ 161 struct mutex lock; 162 163 u32 vref_uv; 164 u32 value; 165 struct regulator *vref; 166 167 u32 max_adck_rate[3]; 168 struct vf610_adc_feature adc_feature; 169 170 u32 sample_freq_avail[5]; 171 172 struct completion completion; 173 /* Ensure the timestamp is naturally aligned */ 174 struct { 175 u16 chan; 176 aligned_s64 timestamp; 177 } scan; 178 }; 179 180 struct vf610_chip_info { 181 u8 num_channels; 182 }; 183 184 static const u32 vf610_hw_avgs[] = { 1, 4, 8, 16, 32 }; 185 static const u32 vf610_lst_adder[] = { 3, 5, 7, 9, 13, 17, 21, 25 }; 186 187 static inline void vf610_adc_calculate_rates(struct vf610_adc *info) 188 { 189 struct vf610_adc_feature *adc_feature = &info->adc_feature; 190 unsigned long adck_rate, ipg_rate = clk_get_rate(info->clk); 191 u32 adck_period, lst_addr_min; 192 int divisor, i; 193 194 adck_rate = info->max_adck_rate[adc_feature->conv_mode]; 195 196 if (adck_rate) { 197 /* calculate clk divider which is within specification */ 198 divisor = ipg_rate / adck_rate; 199 adc_feature->clk_div = 1 << fls(divisor + 1); 200 } else { 201 /* fall-back value using a safe divisor */ 202 adc_feature->clk_div = 8; 203 } 204 205 adck_rate = ipg_rate / adc_feature->clk_div; 206 207 /* 208 * Determine the long sample time adder value to be used based 209 * on the default minimum sample time provided. 210 */ 211 adck_period = NSEC_PER_SEC / adck_rate; 212 lst_addr_min = adc_feature->default_sample_time / adck_period; 213 for (i = 0; i < ARRAY_SIZE(vf610_lst_adder); i++) { 214 if (vf610_lst_adder[i] > lst_addr_min) { 215 adc_feature->lst_adder_index = i; 216 break; 217 } 218 } 219 220 /* 221 * Calculate ADC sample frequencies 222 * Sample time unit is ADCK cycles. ADCK clk source is ipg clock, 223 * which is the same as bus clock. 224 * 225 * ADC conversion time = SFCAdder + AverageNum x (BCT + LSTAdder) 226 * SFCAdder: fixed to 6 ADCK cycles 227 * AverageNum: 1, 4, 8, 16, 32 samples for hardware average. 228 * BCT (Base Conversion Time): fixed to 25 ADCK cycles for 12 bit mode 229 * LSTAdder(Long Sample Time): 3, 5, 7, 9, 13, 17, 21, 25 ADCK cycles 230 */ 231 for (i = 0; i < ARRAY_SIZE(vf610_hw_avgs); i++) 232 info->sample_freq_avail[i] = 233 adck_rate / (6 + vf610_hw_avgs[i] * 234 (25 + vf610_lst_adder[adc_feature->lst_adder_index])); 235 } 236 237 static inline void vf610_adc_cfg_init(struct vf610_adc *info) 238 { 239 struct vf610_adc_feature *adc_feature = &info->adc_feature; 240 241 /* set default Configuration for ADC controller */ 242 adc_feature->clk_sel = VF610_ADCIOC_BUSCLK_SET; 243 adc_feature->vol_ref = VF610_ADCIOC_VR_VREF_SET; 244 245 adc_feature->calibration = true; 246 adc_feature->ovwren = true; 247 248 adc_feature->res_mode = 12; 249 adc_feature->sample_rate = 1; 250 251 adc_feature->conv_mode = VF610_ADC_CONV_LOW_POWER; 252 253 vf610_adc_calculate_rates(info); 254 } 255 256 static void vf610_adc_cfg_post_set(struct vf610_adc *info) 257 { 258 struct vf610_adc_feature *adc_feature = &info->adc_feature; 259 int cfg_data = 0; 260 int gc_data = 0; 261 262 switch (adc_feature->clk_sel) { 263 case VF610_ADCIOC_ALTCLK_SET: 264 cfg_data |= VF610_ADC_ALTCLK_SEL; 265 break; 266 case VF610_ADCIOC_ADACK_SET: 267 cfg_data |= VF610_ADC_ADACK_SEL; 268 break; 269 default: 270 break; 271 } 272 273 /* low power set for calibration */ 274 cfg_data |= VF610_ADC_ADLPC_EN; 275 276 /* enable high speed for calibration */ 277 cfg_data |= VF610_ADC_ADHSC_EN; 278 279 /* voltage reference */ 280 switch (adc_feature->vol_ref) { 281 case VF610_ADCIOC_VR_VREF_SET: 282 break; 283 case VF610_ADCIOC_VR_VALT_SET: 284 cfg_data |= VF610_ADC_REFSEL_VALT; 285 break; 286 case VF610_ADCIOC_VR_VBG_SET: 287 cfg_data |= VF610_ADC_REFSEL_VBG; 288 break; 289 default: 290 dev_err(info->dev, "error voltage reference\n"); 291 } 292 293 /* data overwrite enable */ 294 if (adc_feature->ovwren) 295 cfg_data |= VF610_ADC_OVWREN; 296 297 writel(cfg_data, info->regs + VF610_REG_ADC_CFG); 298 writel(gc_data, info->regs + VF610_REG_ADC_GC); 299 } 300 301 static void vf610_adc_calibration(struct vf610_adc *info) 302 { 303 int adc_gc, hc_cfg; 304 305 if (!info->adc_feature.calibration) 306 return; 307 308 /* enable calibration interrupt */ 309 hc_cfg = VF610_ADC_AIEN | VF610_ADC_CONV_DISABLE; 310 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0); 311 312 adc_gc = readl(info->regs + VF610_REG_ADC_GC); 313 writel(adc_gc | VF610_ADC_CAL, info->regs + VF610_REG_ADC_GC); 314 315 if (!wait_for_completion_timeout(&info->completion, VF610_ADC_TIMEOUT)) 316 dev_err(info->dev, "Timeout for adc calibration\n"); 317 318 adc_gc = readl(info->regs + VF610_REG_ADC_GS); 319 if (adc_gc & VF610_ADC_CALF) 320 dev_err(info->dev, "ADC calibration failed\n"); 321 322 info->adc_feature.calibration = false; 323 } 324 325 static void vf610_adc_cfg_set(struct vf610_adc *info) 326 { 327 struct vf610_adc_feature *adc_feature = &(info->adc_feature); 328 int cfg_data; 329 330 cfg_data = readl(info->regs + VF610_REG_ADC_CFG); 331 332 cfg_data &= ~VF610_ADC_ADLPC_EN; 333 if (adc_feature->conv_mode == VF610_ADC_CONV_LOW_POWER) 334 cfg_data |= VF610_ADC_ADLPC_EN; 335 336 cfg_data &= ~VF610_ADC_ADHSC_EN; 337 if (adc_feature->conv_mode == VF610_ADC_CONV_HIGH_SPEED) 338 cfg_data |= VF610_ADC_ADHSC_EN; 339 340 writel(cfg_data, info->regs + VF610_REG_ADC_CFG); 341 } 342 343 static void vf610_adc_sample_set(struct vf610_adc *info) 344 { 345 struct vf610_adc_feature *adc_feature = &(info->adc_feature); 346 int cfg_data, gc_data; 347 348 cfg_data = readl(info->regs + VF610_REG_ADC_CFG); 349 gc_data = readl(info->regs + VF610_REG_ADC_GC); 350 351 /* resolution mode */ 352 cfg_data &= ~VF610_ADC_MODE_MASK; 353 switch (adc_feature->res_mode) { 354 case 8: 355 cfg_data |= VF610_ADC_MODE_BIT8; 356 break; 357 case 10: 358 cfg_data |= VF610_ADC_MODE_BIT10; 359 break; 360 case 12: 361 cfg_data |= VF610_ADC_MODE_BIT12; 362 break; 363 default: 364 dev_err(info->dev, "error resolution mode\n"); 365 break; 366 } 367 368 /* clock select and clock divider */ 369 cfg_data &= ~(VF610_ADC_CLK_MASK | VF610_ADC_ADCCLK_MASK); 370 switch (adc_feature->clk_div) { 371 case 1: 372 break; 373 case 2: 374 cfg_data |= VF610_ADC_CLK_DIV2; 375 break; 376 case 4: 377 cfg_data |= VF610_ADC_CLK_DIV4; 378 break; 379 case 8: 380 cfg_data |= VF610_ADC_CLK_DIV8; 381 break; 382 case 16: 383 switch (adc_feature->clk_sel) { 384 case VF610_ADCIOC_BUSCLK_SET: 385 cfg_data |= VF610_ADC_BUSCLK2_SEL | VF610_ADC_CLK_DIV8; 386 break; 387 default: 388 dev_err(info->dev, "error clk divider\n"); 389 break; 390 } 391 break; 392 } 393 394 /* 395 * Set ADLSMP and ADSTS based on the Long Sample Time Adder value 396 * determined. 397 */ 398 switch (adc_feature->lst_adder_index) { 399 case VF610_ADCK_CYCLES_3: 400 break; 401 case VF610_ADCK_CYCLES_5: 402 cfg_data |= VF610_ADC_ADSTS_SHORT; 403 break; 404 case VF610_ADCK_CYCLES_7: 405 cfg_data |= VF610_ADC_ADSTS_NORMAL; 406 break; 407 case VF610_ADCK_CYCLES_9: 408 cfg_data |= VF610_ADC_ADSTS_LONG; 409 break; 410 case VF610_ADCK_CYCLES_13: 411 cfg_data |= VF610_ADC_ADLSMP_LONG; 412 break; 413 case VF610_ADCK_CYCLES_17: 414 cfg_data |= VF610_ADC_ADLSMP_LONG; 415 cfg_data |= VF610_ADC_ADSTS_SHORT; 416 break; 417 case VF610_ADCK_CYCLES_21: 418 cfg_data |= VF610_ADC_ADLSMP_LONG; 419 cfg_data |= VF610_ADC_ADSTS_NORMAL; 420 break; 421 case VF610_ADCK_CYCLES_25: 422 cfg_data |= VF610_ADC_ADLSMP_LONG; 423 cfg_data |= VF610_ADC_ADSTS_NORMAL; 424 break; 425 default: 426 dev_err(info->dev, "error in sample time select\n"); 427 } 428 429 /* update hardware average selection */ 430 cfg_data &= ~VF610_ADC_AVGS_MASK; 431 gc_data &= ~VF610_ADC_AVGEN; 432 switch (adc_feature->sample_rate) { 433 case VF610_ADC_SAMPLE_1: 434 break; 435 case VF610_ADC_SAMPLE_4: 436 gc_data |= VF610_ADC_AVGEN; 437 break; 438 case VF610_ADC_SAMPLE_8: 439 gc_data |= VF610_ADC_AVGEN; 440 cfg_data |= VF610_ADC_AVGS_8; 441 break; 442 case VF610_ADC_SAMPLE_16: 443 gc_data |= VF610_ADC_AVGEN; 444 cfg_data |= VF610_ADC_AVGS_16; 445 break; 446 case VF610_ADC_SAMPLE_32: 447 gc_data |= VF610_ADC_AVGEN; 448 cfg_data |= VF610_ADC_AVGS_32; 449 break; 450 default: 451 dev_err(info->dev, 452 "error hardware sample average select\n"); 453 } 454 455 writel(cfg_data, info->regs + VF610_REG_ADC_CFG); 456 writel(gc_data, info->regs + VF610_REG_ADC_GC); 457 } 458 459 static void vf610_adc_hw_init(struct vf610_adc *info) 460 { 461 /* CFG: Feature set */ 462 vf610_adc_cfg_post_set(info); 463 vf610_adc_sample_set(info); 464 465 /* adc calibration */ 466 vf610_adc_calibration(info); 467 468 /* CFG: power and speed set */ 469 vf610_adc_cfg_set(info); 470 } 471 472 static int vf610_set_conversion_mode(struct iio_dev *indio_dev, 473 const struct iio_chan_spec *chan, 474 unsigned int mode) 475 { 476 struct vf610_adc *info = iio_priv(indio_dev); 477 478 mutex_lock(&info->lock); 479 info->adc_feature.conv_mode = mode; 480 vf610_adc_calculate_rates(info); 481 vf610_adc_hw_init(info); 482 mutex_unlock(&info->lock); 483 484 return 0; 485 } 486 487 static int vf610_get_conversion_mode(struct iio_dev *indio_dev, 488 const struct iio_chan_spec *chan) 489 { 490 struct vf610_adc *info = iio_priv(indio_dev); 491 492 return info->adc_feature.conv_mode; 493 } 494 495 static const char * const vf610_conv_modes[] = { "normal", "high-speed", 496 "low-power" }; 497 498 static const struct iio_enum vf610_conversion_mode = { 499 .items = vf610_conv_modes, 500 .num_items = ARRAY_SIZE(vf610_conv_modes), 501 .get = vf610_get_conversion_mode, 502 .set = vf610_set_conversion_mode, 503 }; 504 505 static const struct iio_chan_spec_ext_info vf610_ext_info[] = { 506 IIO_ENUM("conversion_mode", IIO_SHARED_BY_DIR, &vf610_conversion_mode), 507 {}, 508 }; 509 510 #define VF610_ADC_CHAN(_idx, _chan_type) { \ 511 .type = (_chan_type), \ 512 .indexed = 1, \ 513 .channel = (_idx), \ 514 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 515 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 516 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 517 .ext_info = vf610_ext_info, \ 518 .scan_index = (_idx), \ 519 .scan_type = { \ 520 .sign = 'u', \ 521 .realbits = 12, \ 522 .storagebits = 16, \ 523 }, \ 524 } 525 526 #define VF610_ADC_TEMPERATURE_CHAN(_idx, _chan_type) { \ 527 .type = (_chan_type), \ 528 .channel = (_idx), \ 529 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \ 530 .scan_index = (_idx), \ 531 .scan_type = { \ 532 .sign = 'u', \ 533 .realbits = 12, \ 534 .storagebits = 16, \ 535 }, \ 536 } 537 538 static const struct iio_chan_spec vf610_adc_iio_channels[] = { 539 VF610_ADC_CHAN(0, IIO_VOLTAGE), 540 VF610_ADC_CHAN(1, IIO_VOLTAGE), 541 VF610_ADC_CHAN(2, IIO_VOLTAGE), 542 VF610_ADC_CHAN(3, IIO_VOLTAGE), 543 VF610_ADC_CHAN(4, IIO_VOLTAGE), 544 VF610_ADC_CHAN(5, IIO_VOLTAGE), 545 VF610_ADC_CHAN(6, IIO_VOLTAGE), 546 VF610_ADC_CHAN(7, IIO_VOLTAGE), 547 VF610_ADC_CHAN(8, IIO_VOLTAGE), 548 VF610_ADC_CHAN(9, IIO_VOLTAGE), 549 VF610_ADC_CHAN(10, IIO_VOLTAGE), 550 VF610_ADC_CHAN(11, IIO_VOLTAGE), 551 VF610_ADC_CHAN(12, IIO_VOLTAGE), 552 VF610_ADC_CHAN(13, IIO_VOLTAGE), 553 VF610_ADC_CHAN(14, IIO_VOLTAGE), 554 VF610_ADC_CHAN(15, IIO_VOLTAGE), 555 VF610_ADC_TEMPERATURE_CHAN(26, IIO_TEMP), 556 IIO_CHAN_SOFT_TIMESTAMP(32), 557 /* sentinel */ 558 }; 559 560 static int vf610_adc_read_data(struct vf610_adc *info) 561 { 562 int result; 563 564 result = readl(info->regs + VF610_REG_ADC_R0); 565 566 switch (info->adc_feature.res_mode) { 567 case 8: 568 result &= 0xFF; 569 break; 570 case 10: 571 result &= 0x3FF; 572 break; 573 case 12: 574 result &= 0xFFF; 575 break; 576 default: 577 break; 578 } 579 580 return result; 581 } 582 583 static irqreturn_t vf610_adc_isr(int irq, void *dev_id) 584 { 585 struct iio_dev *indio_dev = dev_id; 586 struct vf610_adc *info = iio_priv(indio_dev); 587 int coco; 588 589 coco = readl(info->regs + VF610_REG_ADC_HS); 590 if (coco & VF610_ADC_HS_COCO0) { 591 info->value = vf610_adc_read_data(info); 592 if (iio_buffer_enabled(indio_dev)) { 593 info->scan.chan = info->value; 594 iio_push_to_buffers_with_timestamp(indio_dev, 595 &info->scan, 596 iio_get_time_ns(indio_dev)); 597 iio_trigger_notify_done(indio_dev->trig); 598 } else 599 complete(&info->completion); 600 } 601 602 return IRQ_HANDLED; 603 } 604 605 static ssize_t vf610_show_samp_freq_avail(struct device *dev, 606 struct device_attribute *attr, char *buf) 607 { 608 struct vf610_adc *info = iio_priv(dev_to_iio_dev(dev)); 609 size_t len = 0; 610 int i; 611 612 for (i = 0; i < ARRAY_SIZE(info->sample_freq_avail); i++) 613 len += scnprintf(buf + len, PAGE_SIZE - len, 614 "%u ", info->sample_freq_avail[i]); 615 616 /* replace trailing space by newline */ 617 buf[len - 1] = '\n'; 618 619 return len; 620 } 621 622 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(vf610_show_samp_freq_avail); 623 624 static struct attribute *vf610_attributes[] = { 625 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 626 NULL 627 }; 628 629 static const struct attribute_group vf610_attribute_group = { 630 .attrs = vf610_attributes, 631 }; 632 633 static int vf610_read_sample(struct iio_dev *indio_dev, 634 struct iio_chan_spec const *chan, int *val) 635 { 636 struct vf610_adc *info = iio_priv(indio_dev); 637 unsigned int hc_cfg; 638 int ret; 639 640 ret = iio_device_claim_direct_mode(indio_dev); 641 if (ret) 642 return ret; 643 644 mutex_lock(&info->lock); 645 reinit_completion(&info->completion); 646 hc_cfg = VF610_ADC_ADCHC(chan->channel); 647 hc_cfg |= VF610_ADC_AIEN; 648 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0); 649 ret = wait_for_completion_interruptible_timeout(&info->completion, 650 VF610_ADC_TIMEOUT); 651 if (ret == 0) { 652 ret = -ETIMEDOUT; 653 goto out_unlock; 654 } 655 656 if (ret < 0) 657 goto out_unlock; 658 659 switch (chan->type) { 660 case IIO_VOLTAGE: 661 *val = info->value; 662 break; 663 case IIO_TEMP: 664 /* 665 * Calculate in degree Celsius times 1000 666 * Using the typical sensor slope of 1.84 mV/°C 667 * and VREFH_ADC at 3.3V, V at 25°C of 699 mV 668 */ 669 *val = 25000 - ((int)info->value - VF610_VTEMP25_3V3) * 670 1000000 / VF610_TEMP_SLOPE_COEFF; 671 672 break; 673 default: 674 ret = -EINVAL; 675 break; 676 } 677 678 out_unlock: 679 mutex_unlock(&info->lock); 680 iio_device_release_direct_mode(indio_dev); 681 682 return ret; 683 } 684 685 static int vf610_read_raw(struct iio_dev *indio_dev, 686 struct iio_chan_spec const *chan, 687 int *val, 688 int *val2, 689 long mask) 690 { 691 struct vf610_adc *info = iio_priv(indio_dev); 692 long ret; 693 694 switch (mask) { 695 case IIO_CHAN_INFO_RAW: 696 case IIO_CHAN_INFO_PROCESSED: 697 ret = vf610_read_sample(indio_dev, chan, val); 698 if (ret < 0) 699 return ret; 700 701 return IIO_VAL_INT; 702 703 case IIO_CHAN_INFO_SCALE: 704 *val = info->vref_uv / 1000; 705 *val2 = info->adc_feature.res_mode; 706 return IIO_VAL_FRACTIONAL_LOG2; 707 708 case IIO_CHAN_INFO_SAMP_FREQ: 709 *val = info->sample_freq_avail[info->adc_feature.sample_rate]; 710 *val2 = 0; 711 return IIO_VAL_INT; 712 713 default: 714 break; 715 } 716 717 return -EINVAL; 718 } 719 720 static int vf610_write_raw(struct iio_dev *indio_dev, 721 struct iio_chan_spec const *chan, 722 int val, 723 int val2, 724 long mask) 725 { 726 struct vf610_adc *info = iio_priv(indio_dev); 727 int i; 728 729 switch (mask) { 730 case IIO_CHAN_INFO_SAMP_FREQ: 731 for (i = 0; 732 i < ARRAY_SIZE(info->sample_freq_avail); 733 i++) 734 if (val == info->sample_freq_avail[i]) { 735 info->adc_feature.sample_rate = i; 736 vf610_adc_sample_set(info); 737 return 0; 738 } 739 break; 740 741 default: 742 break; 743 } 744 745 return -EINVAL; 746 } 747 748 static int vf610_adc_buffer_postenable(struct iio_dev *indio_dev) 749 { 750 struct vf610_adc *info = iio_priv(indio_dev); 751 unsigned int channel; 752 int val; 753 754 val = readl(info->regs + VF610_REG_ADC_GC); 755 val |= VF610_ADC_ADCON; 756 writel(val, info->regs + VF610_REG_ADC_GC); 757 758 channel = find_first_bit(indio_dev->active_scan_mask, 759 iio_get_masklength(indio_dev)); 760 761 val = VF610_ADC_ADCHC(channel); 762 val |= VF610_ADC_AIEN; 763 764 writel(val, info->regs + VF610_REG_ADC_HC0); 765 766 return 0; 767 } 768 769 static int vf610_adc_buffer_predisable(struct iio_dev *indio_dev) 770 { 771 struct vf610_adc *info = iio_priv(indio_dev); 772 unsigned int hc_cfg = 0; 773 int val; 774 775 val = readl(info->regs + VF610_REG_ADC_GC); 776 val &= ~VF610_ADC_ADCON; 777 writel(val, info->regs + VF610_REG_ADC_GC); 778 779 hc_cfg |= VF610_ADC_CONV_DISABLE; 780 hc_cfg &= ~VF610_ADC_AIEN; 781 782 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0); 783 784 return 0; 785 } 786 787 static const struct iio_buffer_setup_ops iio_triggered_buffer_setup_ops = { 788 .postenable = &vf610_adc_buffer_postenable, 789 .predisable = &vf610_adc_buffer_predisable, 790 .validate_scan_mask = &iio_validate_scan_mask_onehot, 791 }; 792 793 static int vf610_adc_reg_access(struct iio_dev *indio_dev, 794 unsigned reg, unsigned writeval, 795 unsigned *readval) 796 { 797 struct vf610_adc *info = iio_priv(indio_dev); 798 799 if ((readval == NULL) || 800 ((reg % 4) || (reg > VF610_REG_ADC_PCTL))) 801 return -EINVAL; 802 803 *readval = readl(info->regs + reg); 804 805 return 0; 806 } 807 808 static const struct iio_info vf610_adc_iio_info = { 809 .read_raw = &vf610_read_raw, 810 .write_raw = &vf610_write_raw, 811 .debugfs_reg_access = &vf610_adc_reg_access, 812 .attrs = &vf610_attribute_group, 813 }; 814 815 static const struct vf610_chip_info vf610_chip_info = { 816 .num_channels = ARRAY_SIZE(vf610_adc_iio_channels), 817 }; 818 819 static const struct vf610_chip_info imx6sx_chip_info = { 820 .num_channels = 4, 821 }; 822 823 static const struct of_device_id vf610_adc_match[] = { 824 { .compatible = "fsl,imx6sx-adc", .data = &imx6sx_chip_info}, 825 { .compatible = "fsl,vf610-adc", .data = &vf610_chip_info}, 826 { /* sentinel */ } 827 }; 828 MODULE_DEVICE_TABLE(of, vf610_adc_match); 829 830 static void vf610_adc_action_remove(void *d) 831 { 832 struct vf610_adc *info = d; 833 834 regulator_disable(info->vref); 835 } 836 837 static int vf610_adc_probe(struct platform_device *pdev) 838 { 839 const struct vf610_chip_info *chip_info; 840 struct device *dev = &pdev->dev; 841 struct vf610_adc *info; 842 struct iio_dev *indio_dev; 843 int irq; 844 int ret; 845 846 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct vf610_adc)); 847 if (!indio_dev) 848 return dev_err_probe(&pdev->dev, -ENOMEM, "Failed allocating iio device\n"); 849 850 info = iio_priv(indio_dev); 851 info->dev = &pdev->dev; 852 853 info->regs = devm_platform_ioremap_resource(pdev, 0); 854 if (IS_ERR(info->regs)) 855 return PTR_ERR(info->regs); 856 857 chip_info = device_get_match_data(dev); 858 859 irq = platform_get_irq(pdev, 0); 860 if (irq < 0) 861 return irq; 862 863 ret = devm_request_irq(info->dev, irq, 864 vf610_adc_isr, 0, 865 dev_name(&pdev->dev), indio_dev); 866 if (ret < 0) 867 return dev_err_probe(&pdev->dev, ret, "failed requesting irq, irq = %d\n", irq); 868 869 info->clk = devm_clk_get_enabled(&pdev->dev, "adc"); 870 if (IS_ERR(info->clk)) 871 return dev_err_probe(&pdev->dev, PTR_ERR(info->clk), "failed getting clock\n"); 872 873 info->vref = devm_regulator_get(&pdev->dev, "vref"); 874 if (IS_ERR(info->vref)) 875 return PTR_ERR(info->vref); 876 877 ret = regulator_enable(info->vref); 878 if (ret) 879 return ret; 880 881 ret = devm_add_action_or_reset(&pdev->dev, vf610_adc_action_remove, info); 882 if (ret) 883 return ret; 884 885 info->vref_uv = regulator_get_voltage(info->vref); 886 887 device_property_read_u32_array(dev, "fsl,adck-max-frequency", info->max_adck_rate, 3); 888 889 info->adc_feature.default_sample_time = DEFAULT_SAMPLE_TIME; 890 device_property_read_u32(dev, "min-sample-time", &info->adc_feature.default_sample_time); 891 892 platform_set_drvdata(pdev, indio_dev); 893 894 init_completion(&info->completion); 895 896 indio_dev->name = dev_name(&pdev->dev); 897 indio_dev->info = &vf610_adc_iio_info; 898 indio_dev->modes = INDIO_DIRECT_MODE; 899 indio_dev->channels = vf610_adc_iio_channels; 900 indio_dev->num_channels = chip_info->num_channels; 901 902 vf610_adc_cfg_init(info); 903 vf610_adc_hw_init(info); 904 905 ret = devm_iio_triggered_buffer_setup(&pdev->dev, indio_dev, &iio_pollfunc_store_time, 906 NULL, &iio_triggered_buffer_setup_ops); 907 if (ret < 0) 908 return dev_err_probe(&pdev->dev, ret, "Couldn't initialise the buffer\n"); 909 910 mutex_init(&info->lock); 911 912 ret = devm_iio_device_register(&pdev->dev, indio_dev); 913 if (ret) 914 return dev_err_probe(&pdev->dev, ret, "Couldn't register the device.\n"); 915 916 return 0; 917 } 918 919 static int vf610_adc_suspend(struct device *dev) 920 { 921 struct iio_dev *indio_dev = dev_get_drvdata(dev); 922 struct vf610_adc *info = iio_priv(indio_dev); 923 int hc_cfg; 924 925 /* ADC controller enters to stop mode */ 926 hc_cfg = readl(info->regs + VF610_REG_ADC_HC0); 927 hc_cfg |= VF610_ADC_CONV_DISABLE; 928 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0); 929 930 clk_disable_unprepare(info->clk); 931 regulator_disable(info->vref); 932 933 return 0; 934 } 935 936 static int vf610_adc_resume(struct device *dev) 937 { 938 struct iio_dev *indio_dev = dev_get_drvdata(dev); 939 struct vf610_adc *info = iio_priv(indio_dev); 940 int ret; 941 942 ret = regulator_enable(info->vref); 943 if (ret) 944 return ret; 945 946 ret = clk_prepare_enable(info->clk); 947 if (ret) 948 goto disable_reg; 949 950 vf610_adc_hw_init(info); 951 952 return 0; 953 954 disable_reg: 955 regulator_disable(info->vref); 956 return ret; 957 } 958 959 static DEFINE_SIMPLE_DEV_PM_OPS(vf610_adc_pm_ops, vf610_adc_suspend, 960 vf610_adc_resume); 961 962 static struct platform_driver vf610_adc_driver = { 963 .probe = vf610_adc_probe, 964 .driver = { 965 .name = DRIVER_NAME, 966 .of_match_table = vf610_adc_match, 967 .pm = pm_sleep_ptr(&vf610_adc_pm_ops), 968 }, 969 }; 970 971 module_platform_driver(vf610_adc_driver); 972 973 MODULE_AUTHOR("Fugang Duan <B38611@freescale.com>"); 974 MODULE_DESCRIPTION("Freescale VF610 ADC driver"); 975 MODULE_LICENSE("GPL v2"); 976