1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * AD7606 SPI ADC driver 4 * 5 * Copyright 2011 Analog Devices Inc. 6 */ 7 8 #include <linux/cleanup.h> 9 #include <linux/delay.h> 10 #include <linux/device.h> 11 #include <linux/err.h> 12 #include <linux/gpio/consumer.h> 13 #include <linux/interrupt.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/property.h> 17 #include <linux/pwm.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/sched.h> 20 #include <linux/slab.h> 21 #include <linux/sysfs.h> 22 #include <linux/units.h> 23 #include <linux/util_macros.h> 24 25 #include <linux/iio/backend.h> 26 #include <linux/iio/buffer.h> 27 #include <linux/iio/iio.h> 28 #include <linux/iio/sysfs.h> 29 #include <linux/iio/trigger.h> 30 #include <linux/iio/triggered_buffer.h> 31 #include <linux/iio/trigger_consumer.h> 32 33 #include "ad7606.h" 34 35 /* 36 * Scales are computed as 5000/32768 and 10000/32768 respectively, 37 * so that when applied to the raw values they provide mV values. 38 * The scale arrays are kept as IIO_VAL_INT_PLUS_MICRO, so index 39 * X is the integer part and X + 1 is the fractional part. 40 */ 41 static const unsigned int ad7606_16bit_hw_scale_avail[2][2] = { 42 { 0, 152588 }, { 0, 305176 } 43 }; 44 45 static const unsigned int ad7606_18bit_hw_scale_avail[2][2] = { 46 { 0, 38147 }, { 0, 76294 } 47 }; 48 49 static const unsigned int ad7606c_16bit_single_ended_unipolar_scale_avail[3][2] = { 50 { 0, 76294 }, { 0, 152588 }, { 0, 190735 } 51 }; 52 53 static const unsigned int ad7606c_16bit_single_ended_bipolar_scale_avail[5][2] = { 54 { 0, 76294 }, { 0, 152588 }, { 0, 190735 }, { 0, 305176 }, { 0, 381470 } 55 }; 56 57 static const unsigned int ad7606c_16bit_differential_bipolar_scale_avail[4][2] = { 58 { 0, 152588 }, { 0, 305176 }, { 0, 381470 }, { 0, 610352 } 59 }; 60 61 static const unsigned int ad7606c_18bit_single_ended_unipolar_scale_avail[3][2] = { 62 { 0, 19073 }, { 0, 38147 }, { 0, 47684 } 63 }; 64 65 static const unsigned int ad7606c_18bit_single_ended_bipolar_scale_avail[5][2] = { 66 { 0, 19073 }, { 0, 38147 }, { 0, 47684 }, { 0, 76294 }, { 0, 95367 } 67 }; 68 69 static const unsigned int ad7606c_18bit_differential_bipolar_scale_avail[4][2] = { 70 { 0, 38147 }, { 0, 76294 }, { 0, 95367 }, { 0, 152588 } 71 }; 72 73 static const unsigned int ad7606_16bit_sw_scale_avail[3][2] = { 74 { 0, 76293 }, { 0, 152588 }, { 0, 305176 } 75 }; 76 77 static const unsigned int ad7607_hw_scale_avail[2][2] = { 78 { 0, 610352 }, { 1, 220703 } 79 }; 80 81 static const unsigned int ad7609_hw_scale_avail[2][2] = { 82 { 0, 152588 }, { 0, 305176 } 83 }; 84 85 static const unsigned int ad7606_oversampling_avail[7] = { 86 1, 2, 4, 8, 16, 32, 64, 87 }; 88 89 static const unsigned int ad7606b_oversampling_avail[9] = { 90 1, 2, 4, 8, 16, 32, 64, 128, 256, 91 }; 92 93 static const unsigned int ad7616_oversampling_avail[8] = { 94 1, 2, 4, 8, 16, 32, 64, 128, 95 }; 96 97 static const struct iio_chan_spec ad7605_channels[] = { 98 IIO_CHAN_SOFT_TIMESTAMP(4), 99 AD7605_CHANNEL(0), 100 AD7605_CHANNEL(1), 101 AD7605_CHANNEL(2), 102 AD7605_CHANNEL(3), 103 }; 104 105 static const struct iio_chan_spec ad7606_channels_16bit[] = { 106 IIO_CHAN_SOFT_TIMESTAMP(8), 107 AD7606_CHANNEL(0, 16), 108 AD7606_CHANNEL(1, 16), 109 AD7606_CHANNEL(2, 16), 110 AD7606_CHANNEL(3, 16), 111 AD7606_CHANNEL(4, 16), 112 AD7606_CHANNEL(5, 16), 113 AD7606_CHANNEL(6, 16), 114 AD7606_CHANNEL(7, 16), 115 }; 116 117 static const struct iio_chan_spec ad7606_channels_18bit[] = { 118 IIO_CHAN_SOFT_TIMESTAMP(8), 119 AD7606_CHANNEL(0, 18), 120 AD7606_CHANNEL(1, 18), 121 AD7606_CHANNEL(2, 18), 122 AD7606_CHANNEL(3, 18), 123 AD7606_CHANNEL(4, 18), 124 AD7606_CHANNEL(5, 18), 125 AD7606_CHANNEL(6, 18), 126 AD7606_CHANNEL(7, 18), 127 }; 128 129 static const struct iio_chan_spec ad7607_channels[] = { 130 IIO_CHAN_SOFT_TIMESTAMP(8), 131 AD7606_CHANNEL(0, 14), 132 AD7606_CHANNEL(1, 14), 133 AD7606_CHANNEL(2, 14), 134 AD7606_CHANNEL(3, 14), 135 AD7606_CHANNEL(4, 14), 136 AD7606_CHANNEL(5, 14), 137 AD7606_CHANNEL(6, 14), 138 AD7606_CHANNEL(7, 14), 139 }; 140 141 static const struct iio_chan_spec ad7608_channels[] = { 142 IIO_CHAN_SOFT_TIMESTAMP(8), 143 AD7606_CHANNEL(0, 18), 144 AD7606_CHANNEL(1, 18), 145 AD7606_CHANNEL(2, 18), 146 AD7606_CHANNEL(3, 18), 147 AD7606_CHANNEL(4, 18), 148 AD7606_CHANNEL(5, 18), 149 AD7606_CHANNEL(6, 18), 150 AD7606_CHANNEL(7, 18), 151 }; 152 153 /* 154 * The current assumption that this driver makes for AD7616, is that it's 155 * working in Hardware Mode with Serial, Burst and Sequencer modes activated. 156 * To activate them, following pins must be pulled high: 157 * -SER/PAR 158 * -SEQEN 159 * And following pins must be pulled low: 160 * -WR/BURST 161 * -DB4/SER1W 162 */ 163 static const struct iio_chan_spec ad7616_channels[] = { 164 IIO_CHAN_SOFT_TIMESTAMP(16), 165 AD7606_CHANNEL(0, 16), 166 AD7606_CHANNEL(1, 16), 167 AD7606_CHANNEL(2, 16), 168 AD7606_CHANNEL(3, 16), 169 AD7606_CHANNEL(4, 16), 170 AD7606_CHANNEL(5, 16), 171 AD7606_CHANNEL(6, 16), 172 AD7606_CHANNEL(7, 16), 173 AD7606_CHANNEL(8, 16), 174 AD7606_CHANNEL(9, 16), 175 AD7606_CHANNEL(10, 16), 176 AD7606_CHANNEL(11, 16), 177 AD7606_CHANNEL(12, 16), 178 AD7606_CHANNEL(13, 16), 179 AD7606_CHANNEL(14, 16), 180 AD7606_CHANNEL(15, 16), 181 }; 182 183 static int ad7606c_18bit_chan_scale_setup(struct iio_dev *indio_dev, 184 struct iio_chan_spec *chan, int ch); 185 static int ad7606c_16bit_chan_scale_setup(struct iio_dev *indio_dev, 186 struct iio_chan_spec *chan, int ch); 187 static int ad7606_16bit_chan_scale_setup(struct iio_dev *indio_dev, 188 struct iio_chan_spec *chan, int ch); 189 static int ad7607_chan_scale_setup(struct iio_dev *indio_dev, 190 struct iio_chan_spec *chan, int ch); 191 static int ad7608_chan_scale_setup(struct iio_dev *indio_dev, 192 struct iio_chan_spec *chan, int ch); 193 static int ad7609_chan_scale_setup(struct iio_dev *indio_dev, 194 struct iio_chan_spec *chan, int ch); 195 static int ad7616_sw_mode_setup(struct iio_dev *indio_dev); 196 static int ad7606b_sw_mode_setup(struct iio_dev *indio_dev); 197 198 const struct ad7606_chip_info ad7605_4_info = { 199 .channels = ad7605_channels, 200 .name = "ad7605-4", 201 .num_adc_channels = 4, 202 .num_channels = 5, 203 .scale_setup_cb = ad7606_16bit_chan_scale_setup, 204 }; 205 EXPORT_SYMBOL_NS_GPL(ad7605_4_info, "IIO_AD7606"); 206 207 const struct ad7606_chip_info ad7606_8_info = { 208 .channels = ad7606_channels_16bit, 209 .name = "ad7606-8", 210 .num_adc_channels = 8, 211 .num_channels = 9, 212 .oversampling_avail = ad7606_oversampling_avail, 213 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), 214 .scale_setup_cb = ad7606_16bit_chan_scale_setup, 215 }; 216 EXPORT_SYMBOL_NS_GPL(ad7606_8_info, "IIO_AD7606"); 217 218 const struct ad7606_chip_info ad7606_6_info = { 219 .channels = ad7606_channels_16bit, 220 .name = "ad7606-6", 221 .num_adc_channels = 6, 222 .num_channels = 7, 223 .oversampling_avail = ad7606_oversampling_avail, 224 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), 225 .scale_setup_cb = ad7606_16bit_chan_scale_setup, 226 }; 227 EXPORT_SYMBOL_NS_GPL(ad7606_6_info, "IIO_AD7606"); 228 229 const struct ad7606_chip_info ad7606_4_info = { 230 .channels = ad7606_channels_16bit, 231 .name = "ad7606-4", 232 .num_adc_channels = 4, 233 .num_channels = 5, 234 .oversampling_avail = ad7606_oversampling_avail, 235 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), 236 .scale_setup_cb = ad7606_16bit_chan_scale_setup, 237 }; 238 EXPORT_SYMBOL_NS_GPL(ad7606_4_info, "IIO_AD7606"); 239 240 const struct ad7606_chip_info ad7606b_info = { 241 .channels = ad7606_channels_16bit, 242 .max_samplerate = 800 * KILO, 243 .name = "ad7606b", 244 .num_adc_channels = 8, 245 .num_channels = 9, 246 .oversampling_avail = ad7606_oversampling_avail, 247 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), 248 .scale_setup_cb = ad7606_16bit_chan_scale_setup, 249 .sw_setup_cb = ad7606b_sw_mode_setup, 250 }; 251 EXPORT_SYMBOL_NS_GPL(ad7606b_info, "IIO_AD7606"); 252 253 const struct ad7606_chip_info ad7606c_16_info = { 254 .channels = ad7606_channels_16bit, 255 .name = "ad7606c16", 256 .num_adc_channels = 8, 257 .num_channels = 9, 258 .oversampling_avail = ad7606_oversampling_avail, 259 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), 260 .scale_setup_cb = ad7606c_16bit_chan_scale_setup, 261 .sw_setup_cb = ad7606b_sw_mode_setup, 262 }; 263 EXPORT_SYMBOL_NS_GPL(ad7606c_16_info, "IIO_AD7606"); 264 265 const struct ad7606_chip_info ad7607_info = { 266 .channels = ad7607_channels, 267 .name = "ad7607", 268 .num_adc_channels = 8, 269 .num_channels = 9, 270 .oversampling_avail = ad7606_oversampling_avail, 271 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), 272 .scale_setup_cb = ad7607_chan_scale_setup, 273 }; 274 EXPORT_SYMBOL_NS_GPL(ad7607_info, "IIO_AD7606"); 275 276 const struct ad7606_chip_info ad7608_info = { 277 .channels = ad7608_channels, 278 .name = "ad7608", 279 .num_adc_channels = 8, 280 .num_channels = 9, 281 .oversampling_avail = ad7606_oversampling_avail, 282 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), 283 .scale_setup_cb = ad7608_chan_scale_setup, 284 }; 285 EXPORT_SYMBOL_NS_GPL(ad7608_info, "IIO_AD7606"); 286 287 const struct ad7606_chip_info ad7609_info = { 288 .channels = ad7608_channels, 289 .name = "ad7609", 290 .num_adc_channels = 8, 291 .num_channels = 9, 292 .oversampling_avail = ad7606_oversampling_avail, 293 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), 294 .scale_setup_cb = ad7609_chan_scale_setup, 295 }; 296 EXPORT_SYMBOL_NS_GPL(ad7609_info, "IIO_AD7606"); 297 298 const struct ad7606_chip_info ad7606c_18_info = { 299 .channels = ad7606_channels_18bit, 300 .name = "ad7606c18", 301 .num_adc_channels = 8, 302 .num_channels = 9, 303 .oversampling_avail = ad7606_oversampling_avail, 304 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), 305 .scale_setup_cb = ad7606c_18bit_chan_scale_setup, 306 .sw_setup_cb = ad7606b_sw_mode_setup, 307 }; 308 EXPORT_SYMBOL_NS_GPL(ad7606c_18_info, "IIO_AD7606"); 309 310 const struct ad7606_chip_info ad7616_info = { 311 .channels = ad7616_channels, 312 .init_delay_ms = 15, 313 .name = "ad7616", 314 .num_adc_channels = 16, 315 .num_channels = 17, 316 .oversampling_avail = ad7616_oversampling_avail, 317 .oversampling_num = ARRAY_SIZE(ad7616_oversampling_avail), 318 .os_req_reset = true, 319 .scale_setup_cb = ad7606_16bit_chan_scale_setup, 320 .sw_setup_cb = ad7616_sw_mode_setup, 321 }; 322 EXPORT_SYMBOL_NS_GPL(ad7616_info, "IIO_AD7606"); 323 324 int ad7606_reset(struct ad7606_state *st) 325 { 326 if (st->gpio_reset) { 327 gpiod_set_value(st->gpio_reset, 1); 328 ndelay(100); /* t_reset >= 100ns */ 329 gpiod_set_value(st->gpio_reset, 0); 330 return 0; 331 } 332 333 return -ENODEV; 334 } 335 EXPORT_SYMBOL_NS_GPL(ad7606_reset, "IIO_AD7606"); 336 337 static int ad7606_16bit_chan_scale_setup(struct iio_dev *indio_dev, 338 struct iio_chan_spec *chan, int ch) 339 { 340 struct ad7606_state *st = iio_priv(indio_dev); 341 struct ad7606_chan_scale *cs = &st->chan_scales[ch]; 342 343 if (!st->sw_mode_en) { 344 /* tied to logic low, analog input range is +/- 5V */ 345 cs->range = 0; 346 cs->scale_avail = ad7606_16bit_hw_scale_avail; 347 cs->num_scales = ARRAY_SIZE(ad7606_16bit_hw_scale_avail); 348 return 0; 349 } 350 351 /* Scale of 0.076293 is only available in sw mode */ 352 /* After reset, in software mode, ±10 V is set by default */ 353 cs->range = 2; 354 cs->scale_avail = ad7606_16bit_sw_scale_avail; 355 cs->num_scales = ARRAY_SIZE(ad7606_16bit_sw_scale_avail); 356 357 return 0; 358 } 359 360 static int ad7606_get_chan_config(struct iio_dev *indio_dev, int ch, 361 bool *bipolar, bool *differential) 362 { 363 struct ad7606_state *st = iio_priv(indio_dev); 364 unsigned int num_channels = st->chip_info->num_adc_channels; 365 unsigned int offset = indio_dev->num_channels - st->chip_info->num_adc_channels; 366 struct device *dev = st->dev; 367 int ret; 368 369 *bipolar = false; 370 *differential = false; 371 372 device_for_each_child_node_scoped(dev, child) { 373 u32 pins[2]; 374 int reg; 375 376 ret = fwnode_property_read_u32(child, "reg", ®); 377 if (ret) 378 continue; 379 380 /* channel number (here) is from 1 to num_channels */ 381 if (reg < offset || reg > num_channels) { 382 dev_warn(dev, 383 "Invalid channel number (ignoring): %d\n", reg); 384 continue; 385 } 386 387 if (reg != (ch + 1)) 388 continue; 389 390 *bipolar = fwnode_property_read_bool(child, "bipolar"); 391 392 ret = fwnode_property_read_u32_array(child, "diff-channels", 393 pins, ARRAY_SIZE(pins)); 394 /* Channel is differential, if pins are the same as 'reg' */ 395 if (ret == 0 && (pins[0] != reg || pins[1] != reg)) { 396 dev_err(dev, 397 "Differential pins must be the same as 'reg'"); 398 return -EINVAL; 399 } 400 401 *differential = (ret == 0); 402 403 if (*differential && !*bipolar) { 404 dev_err(dev, 405 "'bipolar' must be added for diff channel %d\n", 406 reg); 407 return -EINVAL; 408 } 409 410 return 0; 411 } 412 413 return 0; 414 } 415 416 static int ad7606c_18bit_chan_scale_setup(struct iio_dev *indio_dev, 417 struct iio_chan_spec *chan, int ch) 418 { 419 struct ad7606_state *st = iio_priv(indio_dev); 420 struct ad7606_chan_scale *cs = &st->chan_scales[ch]; 421 bool bipolar, differential; 422 int ret; 423 424 if (!st->sw_mode_en) { 425 cs->range = 0; 426 cs->scale_avail = ad7606_18bit_hw_scale_avail; 427 cs->num_scales = ARRAY_SIZE(ad7606_18bit_hw_scale_avail); 428 return 0; 429 } 430 431 ret = ad7606_get_chan_config(indio_dev, ch, &bipolar, &differential); 432 if (ret) 433 return ret; 434 435 if (differential) { 436 cs->scale_avail = ad7606c_18bit_differential_bipolar_scale_avail; 437 cs->num_scales = 438 ARRAY_SIZE(ad7606c_18bit_differential_bipolar_scale_avail); 439 /* Bipolar differential ranges start at 8 (b1000) */ 440 cs->reg_offset = 8; 441 cs->range = 1; 442 chan->differential = 1; 443 chan->channel2 = chan->channel; 444 445 return 0; 446 } 447 448 chan->differential = 0; 449 450 if (bipolar) { 451 cs->scale_avail = ad7606c_18bit_single_ended_bipolar_scale_avail; 452 cs->num_scales = 453 ARRAY_SIZE(ad7606c_18bit_single_ended_bipolar_scale_avail); 454 /* Bipolar single-ended ranges start at 0 (b0000) */ 455 cs->reg_offset = 0; 456 cs->range = 3; 457 chan->scan_type.sign = 's'; 458 459 return 0; 460 } 461 462 cs->scale_avail = ad7606c_18bit_single_ended_unipolar_scale_avail; 463 cs->num_scales = 464 ARRAY_SIZE(ad7606c_18bit_single_ended_unipolar_scale_avail); 465 /* Unipolar single-ended ranges start at 5 (b0101) */ 466 cs->reg_offset = 5; 467 cs->range = 1; 468 chan->scan_type.sign = 'u'; 469 470 return 0; 471 } 472 473 static int ad7606c_16bit_chan_scale_setup(struct iio_dev *indio_dev, 474 struct iio_chan_spec *chan, int ch) 475 { 476 struct ad7606_state *st = iio_priv(indio_dev); 477 struct ad7606_chan_scale *cs = &st->chan_scales[ch]; 478 bool bipolar, differential; 479 int ret; 480 481 if (!st->sw_mode_en) { 482 cs->range = 0; 483 cs->scale_avail = ad7606_16bit_hw_scale_avail; 484 cs->num_scales = ARRAY_SIZE(ad7606_16bit_hw_scale_avail); 485 return 0; 486 } 487 488 ret = ad7606_get_chan_config(indio_dev, ch, &bipolar, &differential); 489 if (ret) 490 return ret; 491 492 if (differential) { 493 cs->scale_avail = ad7606c_16bit_differential_bipolar_scale_avail; 494 cs->num_scales = 495 ARRAY_SIZE(ad7606c_16bit_differential_bipolar_scale_avail); 496 /* Bipolar differential ranges start at 8 (b1000) */ 497 cs->reg_offset = 8; 498 cs->range = 1; 499 chan->differential = 1; 500 chan->channel2 = chan->channel; 501 chan->scan_type.sign = 's'; 502 503 return 0; 504 } 505 506 chan->differential = 0; 507 508 if (bipolar) { 509 cs->scale_avail = ad7606c_16bit_single_ended_bipolar_scale_avail; 510 cs->num_scales = 511 ARRAY_SIZE(ad7606c_16bit_single_ended_bipolar_scale_avail); 512 /* Bipolar single-ended ranges start at 0 (b0000) */ 513 cs->reg_offset = 0; 514 cs->range = 3; 515 chan->scan_type.sign = 's'; 516 517 return 0; 518 } 519 520 cs->scale_avail = ad7606c_16bit_single_ended_unipolar_scale_avail; 521 cs->num_scales = 522 ARRAY_SIZE(ad7606c_16bit_single_ended_unipolar_scale_avail); 523 /* Unipolar single-ended ranges start at 5 (b0101) */ 524 cs->reg_offset = 5; 525 cs->range = 1; 526 chan->scan_type.sign = 'u'; 527 528 return 0; 529 } 530 531 static int ad7607_chan_scale_setup(struct iio_dev *indio_dev, 532 struct iio_chan_spec *chan, int ch) 533 { 534 struct ad7606_state *st = iio_priv(indio_dev); 535 struct ad7606_chan_scale *cs = &st->chan_scales[ch]; 536 537 cs->range = 0; 538 cs->scale_avail = ad7607_hw_scale_avail; 539 cs->num_scales = ARRAY_SIZE(ad7607_hw_scale_avail); 540 return 0; 541 } 542 543 static int ad7608_chan_scale_setup(struct iio_dev *indio_dev, 544 struct iio_chan_spec *chan, int ch) 545 { 546 struct ad7606_state *st = iio_priv(indio_dev); 547 struct ad7606_chan_scale *cs = &st->chan_scales[ch]; 548 549 cs->range = 0; 550 cs->scale_avail = ad7606_18bit_hw_scale_avail; 551 cs->num_scales = ARRAY_SIZE(ad7606_18bit_hw_scale_avail); 552 return 0; 553 } 554 555 static int ad7609_chan_scale_setup(struct iio_dev *indio_dev, 556 struct iio_chan_spec *chan, int ch) 557 { 558 struct ad7606_state *st = iio_priv(indio_dev); 559 struct ad7606_chan_scale *cs = &st->chan_scales[ch]; 560 561 cs->range = 0; 562 cs->scale_avail = ad7609_hw_scale_avail; 563 cs->num_scales = ARRAY_SIZE(ad7609_hw_scale_avail); 564 return 0; 565 } 566 567 static int ad7606_reg_access(struct iio_dev *indio_dev, 568 unsigned int reg, 569 unsigned int writeval, 570 unsigned int *readval) 571 { 572 struct ad7606_state *st = iio_priv(indio_dev); 573 int ret; 574 575 guard(mutex)(&st->lock); 576 577 if (readval) { 578 ret = st->bops->reg_read(st, reg); 579 if (ret < 0) 580 return ret; 581 *readval = ret; 582 return 0; 583 } else { 584 return st->bops->reg_write(st, reg, writeval); 585 } 586 } 587 588 static int ad7606_pwm_set_high(struct ad7606_state *st) 589 { 590 struct pwm_state cnvst_pwm_state; 591 int ret; 592 593 pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); 594 cnvst_pwm_state.enabled = true; 595 cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period; 596 597 ret = pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state); 598 599 return ret; 600 } 601 602 static int ad7606_pwm_set_low(struct ad7606_state *st) 603 { 604 struct pwm_state cnvst_pwm_state; 605 int ret; 606 607 pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); 608 cnvst_pwm_state.enabled = true; 609 cnvst_pwm_state.duty_cycle = 0; 610 611 ret = pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state); 612 613 return ret; 614 } 615 616 static int ad7606_pwm_set_swing(struct ad7606_state *st) 617 { 618 struct pwm_state cnvst_pwm_state; 619 620 pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); 621 cnvst_pwm_state.enabled = true; 622 cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period / 2; 623 624 return pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state); 625 } 626 627 static bool ad7606_pwm_is_swinging(struct ad7606_state *st) 628 { 629 struct pwm_state cnvst_pwm_state; 630 631 pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); 632 633 return cnvst_pwm_state.duty_cycle != cnvst_pwm_state.period && 634 cnvst_pwm_state.duty_cycle != 0; 635 } 636 637 static int ad7606_set_sampling_freq(struct ad7606_state *st, unsigned long freq) 638 { 639 struct pwm_state cnvst_pwm_state; 640 bool is_swinging = ad7606_pwm_is_swinging(st); 641 bool is_high; 642 643 if (freq == 0) 644 return -EINVAL; 645 646 /* Retrieve the previous state. */ 647 pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); 648 is_high = cnvst_pwm_state.duty_cycle == cnvst_pwm_state.period; 649 650 cnvst_pwm_state.period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, freq); 651 cnvst_pwm_state.polarity = PWM_POLARITY_NORMAL; 652 if (is_high) 653 cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period; 654 else if (is_swinging) 655 cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period / 2; 656 else 657 cnvst_pwm_state.duty_cycle = 0; 658 659 return pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state); 660 } 661 662 static int ad7606_read_samples(struct ad7606_state *st) 663 { 664 unsigned int num = st->chip_info->num_adc_channels; 665 666 return st->bops->read_block(st->dev, num, &st->data); 667 } 668 669 static irqreturn_t ad7606_trigger_handler(int irq, void *p) 670 { 671 struct iio_poll_func *pf = p; 672 struct iio_dev *indio_dev = pf->indio_dev; 673 struct ad7606_state *st = iio_priv(indio_dev); 674 int ret; 675 676 guard(mutex)(&st->lock); 677 678 ret = ad7606_read_samples(st); 679 if (ret) 680 goto error_ret; 681 682 iio_push_to_buffers_with_timestamp(indio_dev, &st->data, 683 iio_get_time_ns(indio_dev)); 684 error_ret: 685 iio_trigger_notify_done(indio_dev->trig); 686 /* The rising edge of the CONVST signal starts a new conversion. */ 687 gpiod_set_value(st->gpio_convst, 1); 688 689 return IRQ_HANDLED; 690 } 691 692 static int ad7606_scan_direct(struct iio_dev *indio_dev, unsigned int ch, 693 int *val) 694 { 695 struct ad7606_state *st = iio_priv(indio_dev); 696 unsigned int realbits = st->chip_info->channels[1].scan_type.realbits; 697 const struct iio_chan_spec *chan; 698 int ret; 699 700 if (st->gpio_convst) { 701 gpiod_set_value(st->gpio_convst, 1); 702 } else { 703 ret = ad7606_pwm_set_high(st); 704 if (ret < 0) 705 return ret; 706 } 707 708 /* 709 * If no backend, wait for the interruption on busy pin, otherwise just add 710 * a delay to leave time for the data to be available. For now, the latter 711 * will not happen because IIO_CHAN_INFO_RAW is not supported for the backend. 712 * TODO: Add support for reading a single value when the backend is used. 713 */ 714 if (!st->back) { 715 ret = wait_for_completion_timeout(&st->completion, 716 msecs_to_jiffies(1000)); 717 if (!ret) { 718 ret = -ETIMEDOUT; 719 goto error_ret; 720 } 721 } else { 722 fsleep(1); 723 } 724 725 ret = ad7606_read_samples(st); 726 if (ret) 727 goto error_ret; 728 729 chan = &indio_dev->channels[ch + 1]; 730 if (chan->scan_type.sign == 'u') { 731 if (realbits > 16) 732 *val = st->data.buf32[ch]; 733 else 734 *val = st->data.buf16[ch]; 735 } else { 736 if (realbits > 16) 737 *val = sign_extend32(st->data.buf32[ch], realbits - 1); 738 else 739 *val = sign_extend32(st->data.buf16[ch], realbits - 1); 740 } 741 742 error_ret: 743 if (!st->gpio_convst) { 744 ret = ad7606_pwm_set_low(st); 745 if (ret < 0) 746 return ret; 747 } 748 gpiod_set_value(st->gpio_convst, 0); 749 750 return ret; 751 } 752 753 static int ad7606_read_raw(struct iio_dev *indio_dev, 754 struct iio_chan_spec const *chan, 755 int *val, 756 int *val2, 757 long m) 758 { 759 int ret, ch = 0; 760 struct ad7606_state *st = iio_priv(indio_dev); 761 struct ad7606_chan_scale *cs; 762 struct pwm_state cnvst_pwm_state; 763 764 switch (m) { 765 case IIO_CHAN_INFO_RAW: 766 if (!iio_device_claim_direct(indio_dev)) 767 return -EBUSY; 768 ret = ad7606_scan_direct(indio_dev, chan->address, val); 769 iio_device_release_direct(indio_dev); 770 if (ret < 0) 771 return ret; 772 return IIO_VAL_INT; 773 case IIO_CHAN_INFO_SCALE: 774 if (st->sw_mode_en) 775 ch = chan->address; 776 cs = &st->chan_scales[ch]; 777 *val = cs->scale_avail[cs->range][0]; 778 *val2 = cs->scale_avail[cs->range][1]; 779 return IIO_VAL_INT_PLUS_MICRO; 780 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 781 *val = st->oversampling; 782 return IIO_VAL_INT; 783 case IIO_CHAN_INFO_SAMP_FREQ: 784 /* 785 * TODO: return the real frequency intead of the requested one once 786 * pwm_get_state_hw comes upstream. 787 */ 788 pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); 789 *val = DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, cnvst_pwm_state.period); 790 return IIO_VAL_INT; 791 } 792 return -EINVAL; 793 } 794 795 static ssize_t in_voltage_scale_available_show(struct device *dev, 796 struct device_attribute *attr, 797 char *buf) 798 { 799 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 800 struct ad7606_state *st = iio_priv(indio_dev); 801 struct ad7606_chan_scale *cs = &st->chan_scales[0]; 802 const unsigned int (*vals)[2] = cs->scale_avail; 803 unsigned int i; 804 size_t len = 0; 805 806 for (i = 0; i < cs->num_scales; i++) 807 len += scnprintf(buf + len, PAGE_SIZE - len, "%u.%06u ", 808 vals[i][0], vals[i][1]); 809 buf[len - 1] = '\n'; 810 811 return len; 812 } 813 814 static IIO_DEVICE_ATTR_RO(in_voltage_scale_available, 0); 815 816 static int ad7606_write_scale_hw(struct iio_dev *indio_dev, int ch, int val) 817 { 818 struct ad7606_state *st = iio_priv(indio_dev); 819 820 gpiod_set_value(st->gpio_range, val); 821 822 return 0; 823 } 824 825 static int ad7606_write_os_hw(struct iio_dev *indio_dev, int val) 826 { 827 struct ad7606_state *st = iio_priv(indio_dev); 828 DECLARE_BITMAP(values, 3); 829 830 values[0] = val & GENMASK(2, 0); 831 832 gpiod_multi_set_value_cansleep(st->gpio_os, values); 833 834 /* AD7616 requires a reset to update value */ 835 if (st->chip_info->os_req_reset) 836 ad7606_reset(st); 837 838 return 0; 839 } 840 841 static int ad7606_write_raw(struct iio_dev *indio_dev, 842 struct iio_chan_spec const *chan, 843 int val, 844 int val2, 845 long mask) 846 { 847 struct ad7606_state *st = iio_priv(indio_dev); 848 unsigned int scale_avail_uv[AD760X_MAX_SCALES]; 849 struct ad7606_chan_scale *cs; 850 int i, ret, ch = 0; 851 852 guard(mutex)(&st->lock); 853 854 switch (mask) { 855 case IIO_CHAN_INFO_SCALE: 856 if (st->sw_mode_en) 857 ch = chan->address; 858 cs = &st->chan_scales[ch]; 859 for (i = 0; i < cs->num_scales; i++) { 860 scale_avail_uv[i] = cs->scale_avail[i][0] * MICRO + 861 cs->scale_avail[i][1]; 862 } 863 val = (val * MICRO) + val2; 864 i = find_closest(val, scale_avail_uv, cs->num_scales); 865 866 if (!iio_device_claim_direct(indio_dev)) 867 return -EBUSY; 868 ret = st->write_scale(indio_dev, ch, i + cs->reg_offset); 869 iio_device_release_direct(indio_dev); 870 if (ret < 0) 871 return ret; 872 cs->range = i; 873 874 return 0; 875 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 876 if (val2) 877 return -EINVAL; 878 i = find_closest(val, st->oversampling_avail, 879 st->num_os_ratios); 880 881 if (!iio_device_claim_direct(indio_dev)) 882 return -EBUSY; 883 ret = st->write_os(indio_dev, i); 884 iio_device_release_direct(indio_dev); 885 if (ret < 0) 886 return ret; 887 st->oversampling = st->oversampling_avail[i]; 888 889 return 0; 890 case IIO_CHAN_INFO_SAMP_FREQ: 891 if (val < 0 && val2 != 0) 892 return -EINVAL; 893 return ad7606_set_sampling_freq(st, val); 894 default: 895 return -EINVAL; 896 } 897 } 898 899 static ssize_t ad7606_oversampling_ratio_avail(struct device *dev, 900 struct device_attribute *attr, 901 char *buf) 902 { 903 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 904 struct ad7606_state *st = iio_priv(indio_dev); 905 const unsigned int *vals = st->oversampling_avail; 906 unsigned int i; 907 size_t len = 0; 908 909 for (i = 0; i < st->num_os_ratios; i++) 910 len += scnprintf(buf + len, PAGE_SIZE - len, "%u ", vals[i]); 911 buf[len - 1] = '\n'; 912 913 return len; 914 } 915 916 static IIO_DEVICE_ATTR(oversampling_ratio_available, 0444, 917 ad7606_oversampling_ratio_avail, NULL, 0); 918 919 static struct attribute *ad7606_attributes_os_and_range[] = { 920 &iio_dev_attr_in_voltage_scale_available.dev_attr.attr, 921 &iio_dev_attr_oversampling_ratio_available.dev_attr.attr, 922 NULL, 923 }; 924 925 static const struct attribute_group ad7606_attribute_group_os_and_range = { 926 .attrs = ad7606_attributes_os_and_range, 927 }; 928 929 static struct attribute *ad7606_attributes_os[] = { 930 &iio_dev_attr_oversampling_ratio_available.dev_attr.attr, 931 NULL, 932 }; 933 934 static const struct attribute_group ad7606_attribute_group_os = { 935 .attrs = ad7606_attributes_os, 936 }; 937 938 static struct attribute *ad7606_attributes_range[] = { 939 &iio_dev_attr_in_voltage_scale_available.dev_attr.attr, 940 NULL, 941 }; 942 943 static const struct attribute_group ad7606_attribute_group_range = { 944 .attrs = ad7606_attributes_range, 945 }; 946 947 static int ad7606_request_gpios(struct ad7606_state *st) 948 { 949 struct device *dev = st->dev; 950 951 st->gpio_convst = devm_gpiod_get_optional(dev, "adi,conversion-start", 952 GPIOD_OUT_LOW); 953 954 if (IS_ERR(st->gpio_convst)) 955 return PTR_ERR(st->gpio_convst); 956 957 st->gpio_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 958 if (IS_ERR(st->gpio_reset)) 959 return PTR_ERR(st->gpio_reset); 960 961 st->gpio_range = devm_gpiod_get_optional(dev, "adi,range", 962 GPIOD_OUT_LOW); 963 if (IS_ERR(st->gpio_range)) 964 return PTR_ERR(st->gpio_range); 965 966 st->gpio_standby = devm_gpiod_get_optional(dev, "standby", 967 GPIOD_OUT_LOW); 968 if (IS_ERR(st->gpio_standby)) 969 return PTR_ERR(st->gpio_standby); 970 971 st->gpio_frstdata = devm_gpiod_get_optional(dev, "adi,first-data", 972 GPIOD_IN); 973 if (IS_ERR(st->gpio_frstdata)) 974 return PTR_ERR(st->gpio_frstdata); 975 976 if (!st->chip_info->oversampling_num) 977 return 0; 978 979 st->gpio_os = devm_gpiod_get_array_optional(dev, 980 "adi,oversampling-ratio", 981 GPIOD_OUT_LOW); 982 return PTR_ERR_OR_ZERO(st->gpio_os); 983 } 984 985 /* 986 * The BUSY signal indicates when conversions are in progress, so when a rising 987 * edge of CONVST is applied, BUSY goes logic high and transitions low at the 988 * end of the entire conversion process. The falling edge of the BUSY signal 989 * triggers this interrupt. 990 */ 991 static irqreturn_t ad7606_interrupt(int irq, void *dev_id) 992 { 993 struct iio_dev *indio_dev = dev_id; 994 struct ad7606_state *st = iio_priv(indio_dev); 995 int ret; 996 997 if (iio_buffer_enabled(indio_dev)) { 998 if (st->gpio_convst) { 999 gpiod_set_value(st->gpio_convst, 0); 1000 } else { 1001 ret = ad7606_pwm_set_low(st); 1002 if (ret < 0) { 1003 dev_err(st->dev, "PWM set low failed"); 1004 goto done; 1005 } 1006 } 1007 iio_trigger_poll_nested(st->trig); 1008 } else { 1009 complete(&st->completion); 1010 } 1011 1012 done: 1013 return IRQ_HANDLED; 1014 }; 1015 1016 static int ad7606_validate_trigger(struct iio_dev *indio_dev, 1017 struct iio_trigger *trig) 1018 { 1019 struct ad7606_state *st = iio_priv(indio_dev); 1020 1021 if (st->trig != trig) 1022 return -EINVAL; 1023 1024 return 0; 1025 } 1026 1027 static int ad7606_buffer_postenable(struct iio_dev *indio_dev) 1028 { 1029 struct ad7606_state *st = iio_priv(indio_dev); 1030 1031 gpiod_set_value(st->gpio_convst, 1); 1032 1033 return 0; 1034 } 1035 1036 static int ad7606_buffer_predisable(struct iio_dev *indio_dev) 1037 { 1038 struct ad7606_state *st = iio_priv(indio_dev); 1039 1040 gpiod_set_value(st->gpio_convst, 0); 1041 1042 return 0; 1043 } 1044 1045 static int ad7606_read_avail(struct iio_dev *indio_dev, 1046 struct iio_chan_spec const *chan, 1047 const int **vals, int *type, int *length, 1048 long info) 1049 { 1050 struct ad7606_state *st = iio_priv(indio_dev); 1051 struct ad7606_chan_scale *cs; 1052 unsigned int ch = 0; 1053 1054 switch (info) { 1055 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1056 *vals = st->oversampling_avail; 1057 *length = st->num_os_ratios; 1058 *type = IIO_VAL_INT; 1059 1060 return IIO_AVAIL_LIST; 1061 1062 case IIO_CHAN_INFO_SCALE: 1063 if (st->sw_mode_en) 1064 ch = chan->address; 1065 1066 cs = &st->chan_scales[ch]; 1067 *vals = (int *)cs->scale_avail; 1068 *length = cs->num_scales * 2; 1069 *type = IIO_VAL_INT_PLUS_MICRO; 1070 1071 return IIO_AVAIL_LIST; 1072 } 1073 return -EINVAL; 1074 } 1075 1076 static int ad7606_backend_buffer_postenable(struct iio_dev *indio_dev) 1077 { 1078 struct ad7606_state *st = iio_priv(indio_dev); 1079 1080 return ad7606_pwm_set_swing(st); 1081 } 1082 1083 static int ad7606_backend_buffer_predisable(struct iio_dev *indio_dev) 1084 { 1085 struct ad7606_state *st = iio_priv(indio_dev); 1086 1087 return ad7606_pwm_set_low(st); 1088 } 1089 1090 static int ad7606_update_scan_mode(struct iio_dev *indio_dev, 1091 const unsigned long *scan_mask) 1092 { 1093 struct ad7606_state *st = iio_priv(indio_dev); 1094 1095 /* 1096 * The update scan mode is only for iio backend compatible drivers. 1097 * If the specific update_scan_mode is not defined in the bus ops, 1098 * just do nothing and return 0. 1099 */ 1100 if (!st->bops->update_scan_mode) 1101 return 0; 1102 1103 return st->bops->update_scan_mode(indio_dev, scan_mask); 1104 } 1105 1106 static const struct iio_buffer_setup_ops ad7606_buffer_ops = { 1107 .postenable = &ad7606_buffer_postenable, 1108 .predisable = &ad7606_buffer_predisable, 1109 }; 1110 1111 static const struct iio_buffer_setup_ops ad7606_backend_buffer_ops = { 1112 .postenable = &ad7606_backend_buffer_postenable, 1113 .predisable = &ad7606_backend_buffer_predisable, 1114 }; 1115 1116 static const struct iio_info ad7606_info_no_os_or_range = { 1117 .read_raw = &ad7606_read_raw, 1118 .validate_trigger = &ad7606_validate_trigger, 1119 .update_scan_mode = &ad7606_update_scan_mode, 1120 }; 1121 1122 static const struct iio_info ad7606_info_os_and_range = { 1123 .read_raw = &ad7606_read_raw, 1124 .write_raw = &ad7606_write_raw, 1125 .attrs = &ad7606_attribute_group_os_and_range, 1126 .validate_trigger = &ad7606_validate_trigger, 1127 .update_scan_mode = &ad7606_update_scan_mode, 1128 }; 1129 1130 static const struct iio_info ad7606_info_sw_mode = { 1131 .read_raw = &ad7606_read_raw, 1132 .write_raw = &ad7606_write_raw, 1133 .read_avail = &ad7606_read_avail, 1134 .debugfs_reg_access = &ad7606_reg_access, 1135 .validate_trigger = &ad7606_validate_trigger, 1136 .update_scan_mode = &ad7606_update_scan_mode, 1137 }; 1138 1139 static const struct iio_info ad7606_info_os = { 1140 .read_raw = &ad7606_read_raw, 1141 .write_raw = &ad7606_write_raw, 1142 .attrs = &ad7606_attribute_group_os, 1143 .validate_trigger = &ad7606_validate_trigger, 1144 .update_scan_mode = &ad7606_update_scan_mode, 1145 }; 1146 1147 static const struct iio_info ad7606_info_range = { 1148 .read_raw = &ad7606_read_raw, 1149 .write_raw = &ad7606_write_raw, 1150 .attrs = &ad7606_attribute_group_range, 1151 .validate_trigger = &ad7606_validate_trigger, 1152 .update_scan_mode = &ad7606_update_scan_mode, 1153 }; 1154 1155 static const struct iio_trigger_ops ad7606_trigger_ops = { 1156 .validate_device = iio_trigger_validate_own_device, 1157 }; 1158 1159 static int ad7606_write_mask(struct ad7606_state *st, unsigned int addr, 1160 unsigned long mask, unsigned int val) 1161 { 1162 int readval; 1163 1164 readval = st->bops->reg_read(st, addr); 1165 if (readval < 0) 1166 return readval; 1167 1168 readval &= ~mask; 1169 readval |= val; 1170 1171 return st->bops->reg_write(st, addr, readval); 1172 } 1173 1174 static int ad7616_write_scale_sw(struct iio_dev *indio_dev, int ch, int val) 1175 { 1176 struct ad7606_state *st = iio_priv(indio_dev); 1177 unsigned int ch_addr, mode, ch_index; 1178 1179 /* 1180 * Ad7616 has 16 channels divided in group A and group B. 1181 * The range of channels from A are stored in registers with address 4 1182 * while channels from B are stored in register with address 6. 1183 * The last bit from channels determines if it is from group A or B 1184 * because the order of channels in iio is 0A, 0B, 1A, 1B... 1185 */ 1186 ch_index = ch >> 1; 1187 1188 ch_addr = AD7616_RANGE_CH_ADDR(ch_index); 1189 1190 if ((ch & 0x1) == 0) /* channel A */ 1191 ch_addr += AD7616_RANGE_CH_A_ADDR_OFF; 1192 else /* channel B */ 1193 ch_addr += AD7616_RANGE_CH_B_ADDR_OFF; 1194 1195 /* 0b01 for 2.5v, 0b10 for 5v and 0b11 for 10v */ 1196 mode = AD7616_RANGE_CH_MODE(ch_index, ((val + 1) & 0b11)); 1197 1198 return ad7606_write_mask(st, ch_addr, AD7616_RANGE_CH_MSK(ch_index), 1199 mode); 1200 } 1201 1202 static int ad7616_write_os_sw(struct iio_dev *indio_dev, int val) 1203 { 1204 struct ad7606_state *st = iio_priv(indio_dev); 1205 1206 return ad7606_write_mask(st, AD7616_CONFIGURATION_REGISTER, 1207 AD7616_OS_MASK, val << 2); 1208 } 1209 1210 static int ad7606_write_scale_sw(struct iio_dev *indio_dev, int ch, int val) 1211 { 1212 struct ad7606_state *st = iio_priv(indio_dev); 1213 1214 return ad7606_write_mask(st, AD7606_RANGE_CH_ADDR(ch), 1215 AD7606_RANGE_CH_MSK(ch), 1216 AD7606_RANGE_CH_MODE(ch, val)); 1217 } 1218 1219 static int ad7606_write_os_sw(struct iio_dev *indio_dev, int val) 1220 { 1221 struct ad7606_state *st = iio_priv(indio_dev); 1222 1223 return st->bops->reg_write(st, AD7606_OS_MODE, val); 1224 } 1225 1226 static int ad7616_sw_mode_setup(struct iio_dev *indio_dev) 1227 { 1228 struct ad7606_state *st = iio_priv(indio_dev); 1229 int ret; 1230 1231 /* 1232 * Scale can be configured individually for each channel 1233 * in software mode. 1234 */ 1235 1236 st->write_scale = ad7616_write_scale_sw; 1237 st->write_os = &ad7616_write_os_sw; 1238 1239 ret = st->bops->sw_mode_config(indio_dev); 1240 if (ret) 1241 return ret; 1242 1243 /* Activate Burst mode and SEQEN MODE */ 1244 return ad7606_write_mask(st, AD7616_CONFIGURATION_REGISTER, 1245 AD7616_BURST_MODE | AD7616_SEQEN_MODE, 1246 AD7616_BURST_MODE | AD7616_SEQEN_MODE); 1247 } 1248 1249 static int ad7606b_sw_mode_setup(struct iio_dev *indio_dev) 1250 { 1251 struct ad7606_state *st = iio_priv(indio_dev); 1252 DECLARE_BITMAP(os, 3); 1253 1254 bitmap_fill(os, 3); 1255 /* 1256 * Software mode is enabled when all three oversampling 1257 * pins are set to high. If oversampling gpios are defined 1258 * in the device tree, then they need to be set to high, 1259 * otherwise, they must be hardwired to VDD 1260 */ 1261 if (st->gpio_os) 1262 gpiod_multi_set_value_cansleep(st->gpio_os, os); 1263 1264 /* OS of 128 and 256 are available only in software mode */ 1265 st->oversampling_avail = ad7606b_oversampling_avail; 1266 st->num_os_ratios = ARRAY_SIZE(ad7606b_oversampling_avail); 1267 1268 st->write_scale = ad7606_write_scale_sw; 1269 st->write_os = &ad7606_write_os_sw; 1270 1271 return st->bops->sw_mode_config(indio_dev); 1272 } 1273 1274 static int ad7606_chan_scales_setup(struct iio_dev *indio_dev) 1275 { 1276 struct ad7606_state *st = iio_priv(indio_dev); 1277 unsigned int offset = indio_dev->num_channels - st->chip_info->num_adc_channels; 1278 struct iio_chan_spec *chans; 1279 size_t size; 1280 int ch, ret; 1281 1282 /* Clone IIO channels, since some may be differential */ 1283 size = indio_dev->num_channels * sizeof(*indio_dev->channels); 1284 chans = devm_kzalloc(st->dev, size, GFP_KERNEL); 1285 if (!chans) 1286 return -ENOMEM; 1287 1288 memcpy(chans, indio_dev->channels, size); 1289 indio_dev->channels = chans; 1290 1291 for (ch = 0; ch < st->chip_info->num_adc_channels; ch++) { 1292 ret = st->chip_info->scale_setup_cb(indio_dev, &chans[ch + offset], ch); 1293 if (ret) 1294 return ret; 1295 } 1296 1297 return 0; 1298 } 1299 1300 static void ad7606_pwm_disable(void *data) 1301 { 1302 pwm_disable(data); 1303 } 1304 1305 int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, 1306 const struct ad7606_chip_info *chip_info, 1307 const struct ad7606_bus_ops *bops) 1308 { 1309 struct ad7606_state *st; 1310 int ret; 1311 struct iio_dev *indio_dev; 1312 1313 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1314 if (!indio_dev) 1315 return -ENOMEM; 1316 1317 st = iio_priv(indio_dev); 1318 dev_set_drvdata(dev, indio_dev); 1319 1320 st->dev = dev; 1321 mutex_init(&st->lock); 1322 st->bops = bops; 1323 st->base_address = base_address; 1324 st->oversampling = 1; 1325 1326 ret = devm_regulator_get_enable(dev, "avcc"); 1327 if (ret) 1328 return dev_err_probe(dev, ret, 1329 "Failed to enable specified AVcc supply\n"); 1330 1331 st->chip_info = chip_info; 1332 1333 if (st->chip_info->oversampling_num) { 1334 st->oversampling_avail = st->chip_info->oversampling_avail; 1335 st->num_os_ratios = st->chip_info->oversampling_num; 1336 } 1337 1338 ret = ad7606_request_gpios(st); 1339 if (ret) 1340 return ret; 1341 1342 if (st->gpio_os) { 1343 if (st->gpio_range) 1344 indio_dev->info = &ad7606_info_os_and_range; 1345 else 1346 indio_dev->info = &ad7606_info_os; 1347 } else { 1348 if (st->gpio_range) 1349 indio_dev->info = &ad7606_info_range; 1350 else 1351 indio_dev->info = &ad7606_info_no_os_or_range; 1352 } 1353 indio_dev->modes = INDIO_DIRECT_MODE; 1354 indio_dev->name = chip_info->name; 1355 indio_dev->channels = st->chip_info->channels; 1356 indio_dev->num_channels = st->chip_info->num_channels; 1357 1358 ret = ad7606_reset(st); 1359 if (ret) 1360 dev_warn(st->dev, "failed to RESET: no RESET GPIO specified\n"); 1361 1362 /* AD7616 requires al least 15ms to reconfigure after a reset */ 1363 if (st->chip_info->init_delay_ms) { 1364 if (msleep_interruptible(st->chip_info->init_delay_ms)) 1365 return -ERESTARTSYS; 1366 } 1367 1368 /* If convst pin is not defined, setup PWM. */ 1369 if (!st->gpio_convst) { 1370 st->cnvst_pwm = devm_pwm_get(dev, NULL); 1371 if (IS_ERR(st->cnvst_pwm)) 1372 return PTR_ERR(st->cnvst_pwm); 1373 1374 /* The PWM is initialized at 1MHz to have a fast enough GPIO emulation. */ 1375 ret = ad7606_set_sampling_freq(st, 1 * MEGA); 1376 if (ret) 1377 return ret; 1378 1379 ret = ad7606_pwm_set_low(st); 1380 if (ret) 1381 return ret; 1382 1383 /* 1384 * PWM is not disabled when sampling stops, but instead its duty cycle is set 1385 * to 0% to be sure we have a "low" state. After we unload the driver, let's 1386 * disable the PWM. 1387 */ 1388 ret = devm_add_action_or_reset(dev, ad7606_pwm_disable, 1389 st->cnvst_pwm); 1390 if (ret) 1391 return ret; 1392 } 1393 1394 if (st->bops->iio_backend_config) { 1395 /* 1396 * If there is a backend, the PWM should not overpass the maximum sampling 1397 * frequency the chip supports. 1398 */ 1399 ret = ad7606_set_sampling_freq(st, 1400 chip_info->max_samplerate ? : 2 * KILO); 1401 if (ret) 1402 return ret; 1403 1404 ret = st->bops->iio_backend_config(dev, indio_dev); 1405 if (ret) 1406 return ret; 1407 1408 indio_dev->setup_ops = &ad7606_backend_buffer_ops; 1409 } else { 1410 1411 /* Reserve the PWM use only for backend (force gpio_convst definition) */ 1412 if (!st->gpio_convst) 1413 return dev_err_probe(dev, -EINVAL, 1414 "No backend, connect convst to a GPIO"); 1415 1416 init_completion(&st->completion); 1417 st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", 1418 indio_dev->name, 1419 iio_device_id(indio_dev)); 1420 if (!st->trig) 1421 return -ENOMEM; 1422 1423 st->trig->ops = &ad7606_trigger_ops; 1424 iio_trigger_set_drvdata(st->trig, indio_dev); 1425 ret = devm_iio_trigger_register(dev, st->trig); 1426 if (ret) 1427 return ret; 1428 1429 indio_dev->trig = iio_trigger_get(st->trig); 1430 1431 ret = devm_request_threaded_irq(dev, irq, NULL, &ad7606_interrupt, 1432 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1433 chip_info->name, indio_dev); 1434 if (ret) 1435 return ret; 1436 1437 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, 1438 &iio_pollfunc_store_time, 1439 &ad7606_trigger_handler, 1440 &ad7606_buffer_ops); 1441 if (ret) 1442 return ret; 1443 } 1444 1445 st->write_scale = ad7606_write_scale_hw; 1446 st->write_os = ad7606_write_os_hw; 1447 1448 st->sw_mode_en = st->chip_info->sw_setup_cb && 1449 device_property_present(st->dev, "adi,sw-mode"); 1450 if (st->sw_mode_en) { 1451 indio_dev->info = &ad7606_info_sw_mode; 1452 st->chip_info->sw_setup_cb(indio_dev); 1453 } 1454 1455 ret = ad7606_chan_scales_setup(indio_dev); 1456 if (ret) 1457 return ret; 1458 1459 return devm_iio_device_register(dev, indio_dev); 1460 } 1461 EXPORT_SYMBOL_NS_GPL(ad7606_probe, "IIO_AD7606"); 1462 1463 #ifdef CONFIG_PM_SLEEP 1464 1465 static int ad7606_suspend(struct device *dev) 1466 { 1467 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1468 struct ad7606_state *st = iio_priv(indio_dev); 1469 1470 if (st->gpio_standby) { 1471 gpiod_set_value(st->gpio_range, 1); 1472 gpiod_set_value(st->gpio_standby, 1); 1473 } 1474 1475 return 0; 1476 } 1477 1478 static int ad7606_resume(struct device *dev) 1479 { 1480 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1481 struct ad7606_state *st = iio_priv(indio_dev); 1482 1483 if (st->gpio_standby) { 1484 gpiod_set_value(st->gpio_range, st->chan_scales[0].range); 1485 gpiod_set_value(st->gpio_standby, 1); 1486 ad7606_reset(st); 1487 } 1488 1489 return 0; 1490 } 1491 1492 SIMPLE_DEV_PM_OPS(ad7606_pm_ops, ad7606_suspend, ad7606_resume); 1493 EXPORT_SYMBOL_NS_GPL(ad7606_pm_ops, "IIO_AD7606"); 1494 1495 #endif 1496 1497 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 1498 MODULE_DESCRIPTION("Analog Devices AD7606 ADC"); 1499 MODULE_LICENSE("GPL v2"); 1500