1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Analog Devices AD7466/7/8 AD7476/5/7/8 (A) SPI ADC driver 4 * TI ADC081S/ADC101S/ADC121S 8/10/12-bit SPI ADC driver 5 * 6 * Copyright 2010 Analog Devices Inc. 7 */ 8 9 #include <linux/device.h> 10 #include <linux/kernel.h> 11 #include <linux/slab.h> 12 #include <linux/sysfs.h> 13 #include <linux/spi/spi.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/err.h> 17 #include <linux/module.h> 18 #include <linux/bitops.h> 19 #include <linux/delay.h> 20 21 #include <linux/iio/iio.h> 22 #include <linux/iio/sysfs.h> 23 #include <linux/iio/buffer.h> 24 #include <linux/iio/trigger_consumer.h> 25 #include <linux/iio/triggered_buffer.h> 26 27 struct ad7476_state; 28 29 struct ad7476_chip_info { 30 unsigned int int_vref_uv; 31 struct iio_chan_spec channel[2]; 32 /* channels used when convst gpio is defined */ 33 struct iio_chan_spec convst_channel[2]; 34 void (*reset)(struct ad7476_state *); 35 bool has_vref; 36 bool has_vdrive; 37 }; 38 39 struct ad7476_state { 40 struct spi_device *spi; 41 const struct ad7476_chip_info *chip_info; 42 struct regulator *ref_reg; 43 struct gpio_desc *convst_gpio; 44 struct spi_transfer xfer; 45 struct spi_message msg; 46 /* 47 * DMA (thus cache coherency maintenance) may require the 48 * transfer buffers to live in their own cache lines. 49 * Make the buffer large enough for one 16 bit sample and one 64 bit 50 * aligned 64 bit timestamp. 51 */ 52 unsigned char data[ALIGN(2, sizeof(s64)) + sizeof(s64)] __aligned(IIO_DMA_MINALIGN); 53 }; 54 55 enum ad7476_supported_device_ids { 56 ID_AD7091, 57 ID_AD7091R, 58 ID_AD7273, 59 ID_AD7274, 60 ID_AD7276, 61 ID_AD7277, 62 ID_AD7278, 63 ID_AD7466, 64 ID_AD7467, 65 ID_AD7468, 66 ID_AD7475, 67 ID_AD7495, 68 ID_AD7940, 69 ID_ADC081S, 70 ID_ADC101S, 71 ID_ADC121S, 72 ID_ADS7866, 73 ID_ADS7867, 74 ID_ADS7868, 75 ID_LTC2314_14, 76 }; 77 78 static void ad7091_convst(struct ad7476_state *st) 79 { 80 if (!st->convst_gpio) 81 return; 82 83 gpiod_set_value(st->convst_gpio, 0); 84 udelay(1); /* CONVST pulse width: 10 ns min */ 85 gpiod_set_value(st->convst_gpio, 1); 86 udelay(1); /* Conversion time: 650 ns max */ 87 } 88 89 static irqreturn_t ad7476_trigger_handler(int irq, void *p) 90 { 91 struct iio_poll_func *pf = p; 92 struct iio_dev *indio_dev = pf->indio_dev; 93 struct ad7476_state *st = iio_priv(indio_dev); 94 int b_sent; 95 96 ad7091_convst(st); 97 98 b_sent = spi_sync(st->spi, &st->msg); 99 if (b_sent < 0) 100 goto done; 101 102 iio_push_to_buffers_with_ts(indio_dev, st->data, sizeof(st->data), 103 iio_get_time_ns(indio_dev)); 104 done: 105 iio_trigger_notify_done(indio_dev->trig); 106 107 return IRQ_HANDLED; 108 } 109 110 static void ad7091_reset(struct ad7476_state *st) 111 { 112 /* Any transfers with 8 scl cycles will reset the device */ 113 spi_read(st->spi, st->data, 1); 114 } 115 116 static int ad7476_scan_direct(struct ad7476_state *st) 117 { 118 int ret; 119 120 ad7091_convst(st); 121 122 ret = spi_sync(st->spi, &st->msg); 123 if (ret) 124 return ret; 125 126 return be16_to_cpup((__be16 *)st->data); 127 } 128 129 static int ad7476_read_raw(struct iio_dev *indio_dev, 130 struct iio_chan_spec const *chan, 131 int *val, 132 int *val2, 133 long m) 134 { 135 int ret; 136 struct ad7476_state *st = iio_priv(indio_dev); 137 int scale_uv; 138 139 switch (m) { 140 case IIO_CHAN_INFO_RAW: 141 if (!iio_device_claim_direct(indio_dev)) 142 return -EBUSY; 143 ret = ad7476_scan_direct(st); 144 iio_device_release_direct(indio_dev); 145 146 if (ret < 0) 147 return ret; 148 *val = (ret >> st->chip_info->channel[0].scan_type.shift) & 149 GENMASK(st->chip_info->channel[0].scan_type.realbits - 1, 0); 150 return IIO_VAL_INT; 151 case IIO_CHAN_INFO_SCALE: 152 if (st->ref_reg) { 153 scale_uv = regulator_get_voltage(st->ref_reg); 154 if (scale_uv < 0) 155 return scale_uv; 156 } else { 157 scale_uv = st->chip_info->int_vref_uv; 158 } 159 *val = scale_uv / 1000; 160 *val2 = chan->scan_type.realbits; 161 return IIO_VAL_FRACTIONAL_LOG2; 162 } 163 return -EINVAL; 164 } 165 166 #define _AD7476_CHAN(bits, _shift, _info_mask_sep) \ 167 { \ 168 .type = IIO_VOLTAGE, \ 169 .indexed = 1, \ 170 .info_mask_separate = _info_mask_sep, \ 171 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 172 .scan_type = { \ 173 .sign = 'u', \ 174 .realbits = (bits), \ 175 .storagebits = 16, \ 176 .shift = (_shift), \ 177 .endianness = IIO_BE, \ 178 }, \ 179 } 180 181 #define ADC081S_CHAN(bits) _AD7476_CHAN((bits), 12 - (bits), \ 182 BIT(IIO_CHAN_INFO_RAW)) 183 #define AD7476_CHAN(bits) _AD7476_CHAN((bits), 13 - (bits), \ 184 BIT(IIO_CHAN_INFO_RAW)) 185 #define AD7940_CHAN(bits) _AD7476_CHAN((bits), 15 - (bits), \ 186 BIT(IIO_CHAN_INFO_RAW)) 187 #define AD7091R_CHAN(bits) _AD7476_CHAN((bits), 16 - (bits), 0) 188 #define AD7091R_CONVST_CHAN(bits) _AD7476_CHAN((bits), 16 - (bits), \ 189 BIT(IIO_CHAN_INFO_RAW)) 190 #define ADS786X_CHAN(bits) _AD7476_CHAN((bits), 12 - (bits), \ 191 BIT(IIO_CHAN_INFO_RAW)) 192 193 static const struct ad7476_chip_info ad7476_chip_info_tbl[] = { 194 [ID_AD7091] = { 195 .channel[0] = AD7091R_CHAN(12), 196 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 197 .convst_channel[0] = AD7091R_CONVST_CHAN(12), 198 .convst_channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 199 .reset = ad7091_reset, 200 }, 201 [ID_AD7091R] = { 202 .channel[0] = AD7091R_CHAN(12), 203 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 204 .convst_channel[0] = AD7091R_CONVST_CHAN(12), 205 .convst_channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 206 .int_vref_uv = 2500000, 207 .has_vref = true, 208 .reset = ad7091_reset, 209 }, 210 [ID_AD7273] = { 211 .channel[0] = AD7940_CHAN(10), 212 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 213 .has_vref = true, 214 }, 215 [ID_AD7274] = { 216 .channel[0] = AD7940_CHAN(12), 217 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 218 .has_vref = true, 219 }, 220 [ID_AD7276] = { 221 .channel[0] = AD7940_CHAN(12), 222 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 223 }, 224 [ID_AD7277] = { 225 .channel[0] = AD7940_CHAN(10), 226 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 227 }, 228 [ID_AD7278] = { 229 .channel[0] = AD7940_CHAN(8), 230 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 231 }, 232 [ID_AD7466] = { 233 .channel[0] = AD7476_CHAN(12), 234 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 235 }, 236 [ID_AD7467] = { 237 .channel[0] = AD7476_CHAN(10), 238 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 239 }, 240 [ID_AD7468] = { 241 .channel[0] = AD7476_CHAN(8), 242 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 243 }, 244 [ID_AD7475] = { 245 .channel[0] = AD7476_CHAN(12), 246 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 247 .has_vref = true, 248 .has_vdrive = true, 249 }, 250 [ID_AD7495] = { 251 .channel[0] = AD7476_CHAN(12), 252 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 253 .int_vref_uv = 2500000, 254 .has_vdrive = true, 255 }, 256 [ID_AD7940] = { 257 .channel[0] = AD7940_CHAN(14), 258 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 259 }, 260 [ID_ADC081S] = { 261 .channel[0] = ADC081S_CHAN(8), 262 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 263 }, 264 [ID_ADC101S] = { 265 .channel[0] = ADC081S_CHAN(10), 266 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 267 }, 268 [ID_ADC121S] = { 269 .channel[0] = ADC081S_CHAN(12), 270 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 271 }, 272 [ID_ADS7866] = { 273 .channel[0] = ADS786X_CHAN(12), 274 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 275 }, 276 [ID_ADS7867] = { 277 .channel[0] = ADS786X_CHAN(10), 278 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 279 }, 280 [ID_ADS7868] = { 281 .channel[0] = ADS786X_CHAN(8), 282 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 283 }, 284 [ID_LTC2314_14] = { 285 .channel[0] = AD7940_CHAN(14), 286 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 287 .has_vref = true, 288 }, 289 }; 290 291 static const struct iio_info ad7476_info = { 292 .read_raw = &ad7476_read_raw, 293 }; 294 295 static void ad7476_reg_disable(void *data) 296 { 297 struct regulator *reg = data; 298 299 regulator_disable(reg); 300 } 301 302 static int ad7476_probe(struct spi_device *spi) 303 { 304 struct ad7476_state *st; 305 struct iio_dev *indio_dev; 306 struct regulator *reg; 307 int ret; 308 309 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 310 if (!indio_dev) 311 return -ENOMEM; 312 313 st = iio_priv(indio_dev); 314 st->chip_info = 315 &ad7476_chip_info_tbl[spi_get_device_id(spi)->driver_data]; 316 317 reg = devm_regulator_get(&spi->dev, "vcc"); 318 if (IS_ERR(reg)) 319 return PTR_ERR(reg); 320 321 ret = regulator_enable(reg); 322 if (ret) 323 return ret; 324 325 ret = devm_add_action_or_reset(&spi->dev, ad7476_reg_disable, reg); 326 if (ret) 327 return ret; 328 329 /* Either vcc or vref (below) as appropriate */ 330 if (!st->chip_info->int_vref_uv) 331 st->ref_reg = reg; 332 333 if (st->chip_info->has_vref) { 334 335 /* If a device has an internal reference vref is optional */ 336 if (st->chip_info->int_vref_uv) { 337 reg = devm_regulator_get_optional(&spi->dev, "vref"); 338 if (IS_ERR(reg) && (PTR_ERR(reg) != -ENODEV)) 339 return PTR_ERR(reg); 340 } else { 341 reg = devm_regulator_get(&spi->dev, "vref"); 342 if (IS_ERR(reg)) 343 return PTR_ERR(reg); 344 } 345 346 if (!IS_ERR(reg)) { 347 ret = regulator_enable(reg); 348 if (ret) 349 return ret; 350 351 ret = devm_add_action_or_reset(&spi->dev, 352 ad7476_reg_disable, 353 reg); 354 if (ret) 355 return ret; 356 st->ref_reg = reg; 357 } else { 358 /* 359 * Can only get here if device supports both internal 360 * and external reference, but the regulator connected 361 * to the external reference is not connected. 362 * Set the reference regulator pointer to NULL to 363 * indicate this. 364 */ 365 st->ref_reg = NULL; 366 } 367 } 368 369 if (st->chip_info->has_vdrive) { 370 ret = devm_regulator_get_enable(&spi->dev, "vdrive"); 371 if (ret) 372 return ret; 373 } 374 375 st->convst_gpio = devm_gpiod_get_optional(&spi->dev, 376 "adi,conversion-start", 377 GPIOD_OUT_LOW); 378 if (IS_ERR(st->convst_gpio)) 379 return PTR_ERR(st->convst_gpio); 380 381 st->spi = spi; 382 383 indio_dev->name = spi_get_device_id(spi)->name; 384 indio_dev->modes = INDIO_DIRECT_MODE; 385 indio_dev->channels = st->chip_info->channel; 386 indio_dev->num_channels = 2; 387 indio_dev->info = &ad7476_info; 388 389 if (st->convst_gpio) 390 indio_dev->channels = st->chip_info->convst_channel; 391 /* Setup default message */ 392 393 st->xfer.rx_buf = &st->data; 394 st->xfer.len = st->chip_info->channel[0].scan_type.storagebits / 8; 395 396 spi_message_init(&st->msg); 397 spi_message_add_tail(&st->xfer, &st->msg); 398 399 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL, 400 &ad7476_trigger_handler, NULL); 401 if (ret) 402 return ret; 403 404 if (st->chip_info->reset) 405 st->chip_info->reset(st); 406 407 return devm_iio_device_register(&spi->dev, indio_dev); 408 } 409 410 static const struct spi_device_id ad7476_id[] = { 411 { "ad7091", ID_AD7091 }, 412 { "ad7091r", ID_AD7091R }, 413 { "ad7273", ID_AD7273 }, 414 { "ad7274", ID_AD7274 }, 415 { "ad7276", ID_AD7276}, 416 { "ad7277", ID_AD7277 }, 417 { "ad7278", ID_AD7278 }, 418 { "ad7466", ID_AD7466 }, 419 { "ad7467", ID_AD7467 }, 420 { "ad7468", ID_AD7468 }, 421 { "ad7475", ID_AD7475 }, 422 { "ad7476", ID_AD7466 }, 423 { "ad7476a", ID_AD7466 }, 424 { "ad7477", ID_AD7467 }, 425 { "ad7477a", ID_AD7467 }, 426 { "ad7478", ID_AD7468 }, 427 { "ad7478a", ID_AD7468 }, 428 { "ad7495", ID_AD7495 }, 429 { "ad7910", ID_AD7467 }, 430 { "ad7920", ID_AD7466 }, 431 { "ad7940", ID_AD7940 }, 432 { "adc081s", ID_ADC081S }, 433 { "adc101s", ID_ADC101S }, 434 { "adc121s", ID_ADC121S }, 435 { "ads7866", ID_ADS7866 }, 436 { "ads7867", ID_ADS7867 }, 437 { "ads7868", ID_ADS7868 }, 438 { "ltc2314-14", ID_LTC2314_14 }, 439 { } 440 }; 441 MODULE_DEVICE_TABLE(spi, ad7476_id); 442 443 static struct spi_driver ad7476_driver = { 444 .driver = { 445 .name = "ad7476", 446 }, 447 .probe = ad7476_probe, 448 .id_table = ad7476_id, 449 }; 450 module_spi_driver(ad7476_driver); 451 452 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 453 MODULE_DESCRIPTION("Analog Devices AD7476 and similar 1-channel ADCs"); 454 MODULE_LICENSE("GPL v2"); 455