1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * AD717x and AD411x family SPI ADC driver 4 * 5 * Supported devices: 6 * AD4111/AD4112/AD4113/AD4114/AD4115/AD4116 7 * AD7172-2/AD7172-4/AD7173-8/AD7175-2 8 * AD7175-8/AD7176-2/AD7177-2 9 * 10 * Copyright (C) 2015, 2024 Analog Devices, Inc. 11 */ 12 13 #include <linux/array_size.h> 14 #include <linux/bitfield.h> 15 #include <linux/bitmap.h> 16 #include <linux/container_of.h> 17 #include <linux/clk.h> 18 #include <linux/clk-provider.h> 19 #include <linux/delay.h> 20 #include <linux/device.h> 21 #include <linux/err.h> 22 #include <linux/gpio/driver.h> 23 #include <linux/gpio/regmap.h> 24 #include <linux/idr.h> 25 #include <linux/interrupt.h> 26 #include <linux/math64.h> 27 #include <linux/module.h> 28 #include <linux/mod_devicetable.h> 29 #include <linux/property.h> 30 #include <linux/regmap.h> 31 #include <linux/regulator/consumer.h> 32 #include <linux/slab.h> 33 #include <linux/spi/spi.h> 34 #include <linux/types.h> 35 #include <linux/units.h> 36 37 #include <linux/iio/buffer.h> 38 #include <linux/iio/events.h> 39 #include <linux/iio/iio.h> 40 #include <linux/iio/trigger_consumer.h> 41 #include <linux/iio/triggered_buffer.h> 42 43 #include <linux/iio/adc/ad_sigma_delta.h> 44 45 #define AD7173_REG_COMMS 0x00 46 #define AD7173_REG_ADC_MODE 0x01 47 #define AD7173_REG_INTERFACE_MODE 0x02 48 #define AD7173_REG_CRC 0x03 49 #define AD7173_REG_DATA 0x04 50 #define AD7173_REG_GPIO 0x06 51 #define AD7173_REG_ID 0x07 52 #define AD7173_REG_CH(x) (0x10 + (x)) 53 #define AD7173_REG_SETUP(x) (0x20 + (x)) 54 #define AD7173_REG_FILTER(x) (0x28 + (x)) 55 #define AD7173_REG_OFFSET(x) (0x30 + (x)) 56 #define AD7173_REG_GAIN(x) (0x38 + (x)) 57 58 #define AD7173_RESET_LENGTH BITS_TO_BYTES(64) 59 60 #define AD7173_CH_ENABLE BIT(15) 61 #define AD7173_CH_SETUP_SEL_MASK GENMASK(14, 12) 62 #define AD7173_CH_SETUP_AINPOS_MASK GENMASK(9, 5) 63 #define AD7173_CH_SETUP_AINNEG_MASK GENMASK(4, 0) 64 65 #define AD7173_NO_AINS_PER_CHANNEL 2 66 #define AD7173_CH_ADDRESS(pos, neg) \ 67 (FIELD_PREP(AD7173_CH_SETUP_AINPOS_MASK, pos) | \ 68 FIELD_PREP(AD7173_CH_SETUP_AINNEG_MASK, neg)) 69 #define AD7173_AIN_TEMP_POS 17 70 #define AD7173_AIN_TEMP_NEG 18 71 #define AD7173_AIN_POW_MON_POS 19 72 #define AD7173_AIN_POW_MON_NEG 20 73 #define AD7173_AIN_REF_POS 21 74 #define AD7173_AIN_REF_NEG 22 75 76 #define AD7173_IS_REF_INPUT(x) ((x) == AD7173_AIN_REF_POS || \ 77 (x) == AD7173_AIN_REF_NEG) 78 79 #define AD7172_2_ID 0x00d0 80 #define AD7176_ID 0x0c90 81 #define AD7175_ID 0x0cd0 82 #define AD7175_2_ID 0x0cd0 83 #define AD7172_4_ID 0x2050 84 #define AD7173_ID 0x30d0 85 #define AD4111_ID AD7173_ID 86 #define AD4112_ID AD7173_ID 87 #define AD4114_ID AD7173_ID 88 #define AD4113_ID 0x31d0 89 #define AD4116_ID 0x34d0 90 #define AD4115_ID 0x38d0 91 #define AD7175_8_ID 0x3cd0 92 #define AD7177_ID 0x4fd0 93 #define AD7173_ID_MASK GENMASK(15, 4) 94 95 #define AD7173_ADC_MODE_REF_EN BIT(15) 96 #define AD7173_ADC_MODE_SING_CYC BIT(13) 97 #define AD7173_ADC_MODE_MODE_MASK GENMASK(6, 4) 98 #define AD7173_ADC_MODE_CLOCKSEL_MASK GENMASK(3, 2) 99 #define AD7173_ADC_MODE_CLOCKSEL_INT 0x0 100 #define AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT 0x1 101 #define AD7173_ADC_MODE_CLOCKSEL_EXT 0x2 102 #define AD7173_ADC_MODE_CLOCKSEL_XTAL 0x3 103 104 #define AD7173_GPIO_PDSW BIT(14) 105 #define AD7173_GPIO_OP_EN2_3 BIT(13) 106 #define AD4111_GPIO_GP_OW_EN BIT(12) 107 #define AD7173_GPIO_MUX_IO BIT(12) 108 #define AD7173_GPIO_SYNC_EN BIT(11) 109 #define AD7173_GPIO_ERR_EN BIT(10) 110 #define AD7173_GPIO_ERR_DAT BIT(9) 111 #define AD7173_GPIO_GP_DATA3 BIT(7) 112 #define AD7173_GPIO_GP_DATA2 BIT(6) 113 #define AD7173_GPIO_IP_EN1 BIT(5) 114 #define AD7173_GPIO_IP_EN0 BIT(4) 115 #define AD7173_GPIO_OP_EN1 BIT(3) 116 #define AD7173_GPIO_OP_EN0 BIT(2) 117 #define AD7173_GPIO_GP_DATA1 BIT(1) 118 #define AD7173_GPIO_GP_DATA0 BIT(0) 119 120 #define AD7173_GPO12_DATA(x) BIT((x) + 0) 121 #define AD7173_GPO23_DATA(x) BIT((x) + 4) 122 #define AD4111_GPO01_DATA(x) BIT((x) + 6) 123 #define AD7173_GPO_DATA(x) ((x) < 2 ? AD7173_GPO12_DATA(x) : AD7173_GPO23_DATA(x)) 124 125 #define AD7173_INTERFACE_DATA_STAT BIT(6) 126 #define AD7173_INTERFACE_DATA_STAT_EN(x) \ 127 FIELD_PREP(AD7173_INTERFACE_DATA_STAT, x) 128 129 #define AD7173_SETUP_BIPOLAR BIT(12) 130 #define AD7173_SETUP_AREF_BUF_MASK GENMASK(11, 10) 131 #define AD7173_SETUP_AIN_BUF_MASK GENMASK(9, 8) 132 133 #define AD7173_SETUP_REF_SEL_MASK GENMASK(5, 4) 134 #define AD7173_SETUP_REF_SEL_AVDD1_AVSS 0x3 135 #define AD7173_SETUP_REF_SEL_INT_REF 0x2 136 #define AD7173_SETUP_REF_SEL_EXT_REF2 0x1 137 #define AD7173_SETUP_REF_SEL_EXT_REF 0x0 138 #define AD7173_VOLTAGE_INT_REF_uV 2500000 139 #define AD7173_TEMP_SENSIIVITY_uV_per_C 477 140 #define AD7177_ODR_START_VALUE 0x07 141 #define AD4111_SHUNT_RESISTOR_OHM 50 142 #define AD4111_DIVIDER_RATIO 10 143 #define AD4111_CURRENT_CHAN_CUTOFF 16 144 #define AD4111_VINCOM_INPUT 0x10 145 146 /* pin < num_voltage_in is a normal voltage input */ 147 /* pin >= num_voltage_in_div is a voltage input without a divider */ 148 #define AD4111_IS_VINCOM_MISMATCH(pin1, pin2) ((pin1) == AD4111_VINCOM_INPUT && \ 149 (pin2) < st->info->num_voltage_in && \ 150 (pin2) >= st->info->num_voltage_in_div) 151 152 #define AD7173_FILTER_ODR0_MASK GENMASK(5, 0) 153 #define AD7173_MAX_CONFIGS 8 154 #define AD4111_OW_DET_THRSH_MV 300 155 156 #define AD7173_MODE_CAL_INT_ZERO 0x4 /* Internal Zero-Scale Calibration */ 157 #define AD7173_MODE_CAL_INT_FULL 0x5 /* Internal Full-Scale Calibration */ 158 #define AD7173_MODE_CAL_SYS_ZERO 0x6 /* System Zero-Scale Calibration */ 159 #define AD7173_MODE_CAL_SYS_FULL 0x7 /* System Full-Scale Calibration */ 160 161 struct ad7173_device_info { 162 const unsigned int *sinc5_data_rates; 163 unsigned int num_sinc5_data_rates; 164 unsigned int odr_start_value; 165 /* 166 * AD4116 has both inputs with a voltage divider and without. 167 * These inputs cannot be mixed in the channel configuration. 168 * Does not include the VINCOM input. 169 */ 170 unsigned int num_voltage_in_div; 171 unsigned int num_channels; 172 unsigned int num_configs; 173 unsigned int num_voltage_in; 174 unsigned int clock; 175 unsigned int id; 176 char *name; 177 const struct ad_sigma_delta_info *sd_info; 178 bool has_current_inputs; 179 bool has_vincom_input; 180 bool has_temp; 181 /* ((AVDD1 − AVSS)/5) */ 182 bool has_pow_supply_monitoring; 183 bool data_reg_only_16bit; 184 bool has_input_buf; 185 bool has_int_ref; 186 bool has_ref2; 187 bool has_internal_fs_calibration; 188 bool has_openwire_det; 189 bool higher_gpio_bits; 190 u8 num_gpios; 191 }; 192 193 struct ad7173_channel_config { 194 /* Openwire detection threshold */ 195 unsigned int openwire_thrsh_raw; 196 int openwire_comp_chan; 197 u8 cfg_slot; 198 bool live; 199 200 /* 201 * Following fields are used to compare equality. If you 202 * make adaptations in it, you most likely also have to adapt 203 * ad7173_find_live_config(), too. 204 */ 205 struct_group(config_props, 206 bool bipolar; 207 bool input_buf; 208 u8 odr; 209 u8 ref_sel; 210 ); 211 }; 212 213 struct ad7173_channel { 214 unsigned int ain; 215 struct ad7173_channel_config cfg; 216 u8 syscalib_mode; 217 bool openwire_det_en; 218 }; 219 220 struct ad7173_state { 221 struct ad_sigma_delta sd; 222 const struct ad7173_device_info *info; 223 struct ad7173_channel *channels; 224 struct regulator_bulk_data regulators[3]; 225 unsigned int adc_mode; 226 unsigned int interface_mode; 227 unsigned int num_channels; 228 struct ida cfg_slots_status; 229 unsigned long long config_usage_counter; 230 unsigned long long *config_cnts; 231 struct clk *ext_clk; 232 struct clk_hw int_clk_hw; 233 struct regmap *reg_gpiocon_regmap; 234 struct gpio_regmap *gpio_regmap; 235 }; 236 237 static unsigned int ad4115_sinc5_data_rates[] = { 238 24845000, 24845000, 20725000, 20725000, /* 0-3 */ 239 15564000, 13841000, 10390000, 10390000, /* 4-7 */ 240 4994000, 2499000, 1000000, 500000, /* 8-11 */ 241 395500, 200000, 100000, 59890, /* 12-15 */ 242 49920, 20000, 16660, 10000, /* 16-19 */ 243 5000, 2500, 2500, /* 20-22 */ 244 }; 245 246 static unsigned int ad4116_sinc5_data_rates[] = { 247 12422360, 12422360, 12422360, 12422360, /* 0-3 */ 248 10362690, 10362690, 7782100, 6290530, /* 4-7 */ 249 5194800, 2496900, 1007600, 499900, /* 8-11 */ 250 390600, 200300, 100000, 59750, /* 12-15 */ 251 49840, 20000, 16650, 10000, /* 16-19 */ 252 5000, 2500, 1250, /* 20-22 */ 253 }; 254 255 static const unsigned int ad7173_sinc5_data_rates[] = { 256 6211000, 6211000, 6211000, 6211000, 6211000, 6211000, 5181000, 4444000, /* 0-7 */ 257 3115000, 2597000, 1007000, 503800, 381000, 200300, 100500, 59520, /* 8-15 */ 258 49680, 20010, 16333, 10000, 5000, 2500, 1250, /* 16-22 */ 259 }; 260 261 static const unsigned int ad7175_sinc5_data_rates[] = { 262 50000000, 41667000, 31250000, 27778000, /* 0-3 */ 263 20833000, 17857000, 12500000, 10000000, /* 4-7 */ 264 5000000, 2500000, 1000000, 500000, /* 8-11 */ 265 397500, 200000, 100000, 59920, /* 12-15 */ 266 49960, 20000, 16666, 10000, /* 16-19 */ 267 5000, /* 20 */ 268 }; 269 270 static unsigned int ad4111_current_channel_config[] = { 271 /* Ain sel: pos neg */ 272 0x1E8, /* 15:IIN0+ 8:IIN0− */ 273 0x1C9, /* 14:IIN1+ 9:IIN1− */ 274 0x1AA, /* 13:IIN2+ 10:IIN2− */ 275 0x18B, /* 12:IIN3+ 11:IIN3− */ 276 }; 277 278 static const char *const ad7173_ref_sel_str[] = { 279 [AD7173_SETUP_REF_SEL_EXT_REF] = "vref", 280 [AD7173_SETUP_REF_SEL_EXT_REF2] = "vref2", 281 [AD7173_SETUP_REF_SEL_INT_REF] = "refout-avss", 282 [AD7173_SETUP_REF_SEL_AVDD1_AVSS] = "avdd", 283 }; 284 285 static const char *const ad7173_clk_sel[] = { 286 "ext-clk", "xtal" 287 }; 288 289 static const struct regmap_range ad7173_range_gpio[] = { 290 regmap_reg_range(AD7173_REG_GPIO, AD7173_REG_GPIO), 291 }; 292 293 static const struct regmap_access_table ad7173_access_table = { 294 .yes_ranges = ad7173_range_gpio, 295 .n_yes_ranges = ARRAY_SIZE(ad7173_range_gpio), 296 }; 297 298 static const struct regmap_config ad7173_regmap_config = { 299 .reg_bits = 8, 300 .val_bits = 16, 301 .rd_table = &ad7173_access_table, 302 .wr_table = &ad7173_access_table, 303 .read_flag_mask = BIT(6), 304 }; 305 306 enum { 307 AD7173_SYSCALIB_ZERO_SCALE, 308 AD7173_SYSCALIB_FULL_SCALE, 309 }; 310 311 static const char * const ad7173_syscalib_modes[] = { 312 [AD7173_SYSCALIB_ZERO_SCALE] = "zero_scale", 313 [AD7173_SYSCALIB_FULL_SCALE] = "full_scale", 314 }; 315 316 static int ad7173_set_syscalib_mode(struct iio_dev *indio_dev, 317 const struct iio_chan_spec *chan, 318 unsigned int mode) 319 { 320 struct ad7173_state *st = iio_priv(indio_dev); 321 322 st->channels[chan->channel].syscalib_mode = mode; 323 324 return 0; 325 } 326 327 static int ad7173_get_syscalib_mode(struct iio_dev *indio_dev, 328 const struct iio_chan_spec *chan) 329 { 330 struct ad7173_state *st = iio_priv(indio_dev); 331 332 return st->channels[chan->channel].syscalib_mode; 333 } 334 335 static ssize_t ad7173_write_syscalib(struct iio_dev *indio_dev, 336 uintptr_t private, 337 const struct iio_chan_spec *chan, 338 const char *buf, size_t len) 339 { 340 struct ad7173_state *st = iio_priv(indio_dev); 341 bool sys_calib; 342 int ret, mode; 343 344 ret = kstrtobool(buf, &sys_calib); 345 if (ret) 346 return ret; 347 348 if (!iio_device_claim_direct(indio_dev)) 349 return -EBUSY; 350 351 mode = st->channels[chan->channel].syscalib_mode; 352 if (sys_calib) { 353 if (mode == AD7173_SYSCALIB_ZERO_SCALE) 354 ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_SYS_ZERO, 355 chan->address); 356 else 357 ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_SYS_FULL, 358 chan->address); 359 } 360 361 iio_device_release_direct(indio_dev); 362 363 return ret ? : len; 364 } 365 366 static const struct iio_enum ad7173_syscalib_mode_enum = { 367 .items = ad7173_syscalib_modes, 368 .num_items = ARRAY_SIZE(ad7173_syscalib_modes), 369 .set = ad7173_set_syscalib_mode, 370 .get = ad7173_get_syscalib_mode 371 }; 372 373 static const struct iio_chan_spec_ext_info ad7173_calibsys_ext_info[] = { 374 { 375 .name = "sys_calibration", 376 .write = ad7173_write_syscalib, 377 .shared = IIO_SEPARATE, 378 }, 379 IIO_ENUM("sys_calibration_mode", IIO_SEPARATE, 380 &ad7173_syscalib_mode_enum), 381 IIO_ENUM_AVAILABLE("sys_calibration_mode", IIO_SHARED_BY_TYPE, 382 &ad7173_syscalib_mode_enum), 383 { } 384 }; 385 386 static int ad7173_calibrate_all(struct ad7173_state *st, struct iio_dev *indio_dev) 387 { 388 int ret; 389 int i; 390 391 for (i = 0; i < st->num_channels; i++) { 392 if (indio_dev->channels[i].type != IIO_VOLTAGE) 393 continue; 394 395 ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_INT_ZERO, st->channels[i].ain); 396 if (ret < 0) 397 return ret; 398 399 if (st->info->has_internal_fs_calibration) { 400 ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_INT_FULL, 401 st->channels[i].ain); 402 if (ret < 0) 403 return ret; 404 } 405 } 406 407 return 0; 408 } 409 410 /* 411 * Associative array of channel pairs for open wire detection 412 * The array is indexed by ain and gives the associated channel pair 413 * to perform the open wire detection with 414 * the channel pair [0] is for non differential and pair [1] 415 * is for differential inputs 416 */ 417 static int openwire_ain_to_channel_pair[][2][2] = { 418 /* AIN Single Differential */ 419 [0] = { { 0, 15 }, { 1, 2 } }, 420 [1] = { { 1, 2 }, { 2, 1 } }, 421 [2] = { { 3, 4 }, { 5, 6 } }, 422 [3] = { { 5, 6 }, { 6, 5 } }, 423 [4] = { { 7, 8 }, { 9, 10 } }, 424 [5] = { { 9, 10 }, { 10, 9 } }, 425 [6] = { { 11, 12 }, { 13, 14 } }, 426 [7] = { { 13, 14 }, { 14, 13 } }, 427 }; 428 429 /* 430 * Openwire detection on ad4111 works by running the same input measurement 431 * on two different channels and compare if the difference between the two 432 * measurements exceeds a certain value (typical 300mV) 433 */ 434 static int ad4111_openwire_event(struct iio_dev *indio_dev, 435 const struct iio_chan_spec *chan) 436 { 437 struct ad7173_state *st = iio_priv(indio_dev); 438 struct ad7173_channel *adchan = &st->channels[chan->address]; 439 struct ad7173_channel_config *cfg = &adchan->cfg; 440 int ret, val1, val2; 441 442 ret = regmap_set_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, 443 AD4111_GPIO_GP_OW_EN); 444 if (ret) 445 return ret; 446 447 adchan->cfg.openwire_comp_chan = 448 openwire_ain_to_channel_pair[chan->channel][chan->differential][0]; 449 450 ret = ad_sigma_delta_single_conversion(indio_dev, chan, &val1); 451 if (ret < 0) { 452 dev_err(&indio_dev->dev, 453 "Error running ad_sigma_delta single conversion: %d", ret); 454 goto out; 455 } 456 457 adchan->cfg.openwire_comp_chan = 458 openwire_ain_to_channel_pair[chan->channel][chan->differential][1]; 459 460 ret = ad_sigma_delta_single_conversion(indio_dev, chan, &val2); 461 if (ret < 0) { 462 dev_err(&indio_dev->dev, 463 "Error running ad_sigma_delta single conversion: %d", ret); 464 goto out; 465 } 466 467 if (abs(val1 - val2) > cfg->openwire_thrsh_raw) 468 iio_push_event(indio_dev, 469 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, chan->address, 470 IIO_EV_TYPE_FAULT, IIO_EV_DIR_FAULT_OPENWIRE), 471 iio_get_time_ns(indio_dev)); 472 473 out: 474 adchan->cfg.openwire_comp_chan = -1; 475 regmap_clear_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, 476 AD4111_GPIO_GP_OW_EN); 477 return ret; 478 } 479 480 static int ad7173_mask_xlate(struct gpio_regmap *gpio, unsigned int base, 481 unsigned int offset, unsigned int *reg, 482 unsigned int *mask) 483 { 484 *mask = AD7173_GPO_DATA(offset); 485 *reg = base; 486 return 0; 487 } 488 489 static int ad4111_mask_xlate(struct gpio_regmap *gpio, unsigned int base, 490 unsigned int offset, unsigned int *reg, 491 unsigned int *mask) 492 { 493 *mask = AD4111_GPO01_DATA(offset); 494 *reg = base; 495 return 0; 496 } 497 498 static void ad7173_gpio_disable(void *data) 499 { 500 struct ad7173_state *st = data; 501 unsigned int mask; 502 503 mask = AD7173_GPIO_OP_EN0 | AD7173_GPIO_OP_EN1 | AD7173_GPIO_OP_EN2_3; 504 regmap_update_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, mask, ~mask); 505 } 506 507 static int ad7173_gpio_init(struct ad7173_state *st) 508 { 509 struct gpio_regmap_config gpio_regmap = {}; 510 struct device *dev = &st->sd.spi->dev; 511 unsigned int mask; 512 int ret; 513 514 st->reg_gpiocon_regmap = devm_regmap_init_spi(st->sd.spi, &ad7173_regmap_config); 515 ret = PTR_ERR_OR_ZERO(st->reg_gpiocon_regmap); 516 if (ret) 517 return dev_err_probe(dev, ret, "Unable to init regmap\n"); 518 519 mask = AD7173_GPIO_OP_EN0 | AD7173_GPIO_OP_EN1 | AD7173_GPIO_OP_EN2_3; 520 regmap_update_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, mask, mask); 521 522 ret = devm_add_action_or_reset(dev, ad7173_gpio_disable, st); 523 if (ret) 524 return ret; 525 526 gpio_regmap.parent = dev; 527 gpio_regmap.regmap = st->reg_gpiocon_regmap; 528 gpio_regmap.ngpio = st->info->num_gpios; 529 gpio_regmap.reg_set_base = AD7173_REG_GPIO; 530 if (st->info->higher_gpio_bits) 531 gpio_regmap.reg_mask_xlate = ad4111_mask_xlate; 532 else 533 gpio_regmap.reg_mask_xlate = ad7173_mask_xlate; 534 535 st->gpio_regmap = devm_gpio_regmap_register(dev, &gpio_regmap); 536 ret = PTR_ERR_OR_ZERO(st->gpio_regmap); 537 if (ret) 538 return dev_err_probe(dev, ret, "Unable to init gpio-regmap\n"); 539 540 return 0; 541 } 542 543 static struct ad7173_state *ad_sigma_delta_to_ad7173(struct ad_sigma_delta *sd) 544 { 545 return container_of(sd, struct ad7173_state, sd); 546 } 547 548 static struct ad7173_state *clk_hw_to_ad7173(struct clk_hw *hw) 549 { 550 return container_of(hw, struct ad7173_state, int_clk_hw); 551 } 552 553 static void ad7173_ida_destroy(void *data) 554 { 555 struct ad7173_state *st = data; 556 557 ida_destroy(&st->cfg_slots_status); 558 } 559 560 static void ad7173_reset_usage_cnts(struct ad7173_state *st) 561 { 562 memset64(st->config_cnts, 0, st->info->num_configs); 563 st->config_usage_counter = 0; 564 } 565 566 static struct ad7173_channel_config * 567 ad7173_find_live_config(struct ad7173_state *st, struct ad7173_channel_config *cfg) 568 { 569 struct ad7173_channel_config *cfg_aux; 570 int i; 571 572 /* 573 * This is just to make sure that the comparison is adapted after 574 * struct ad7173_channel_config was changed. 575 */ 576 static_assert(sizeof_field(struct ad7173_channel_config, config_props) == 577 sizeof(struct { 578 bool bipolar; 579 bool input_buf; 580 u8 odr; 581 u8 ref_sel; 582 })); 583 584 for (i = 0; i < st->num_channels; i++) { 585 cfg_aux = &st->channels[i].cfg; 586 587 if (cfg_aux->live && 588 cfg->bipolar == cfg_aux->bipolar && 589 cfg->input_buf == cfg_aux->input_buf && 590 cfg->odr == cfg_aux->odr && 591 cfg->ref_sel == cfg_aux->ref_sel) 592 return cfg_aux; 593 } 594 return NULL; 595 } 596 597 /* Could be replaced with a generic LRU implementation */ 598 static int ad7173_free_config_slot_lru(struct ad7173_state *st) 599 { 600 int i, lru_position = 0; 601 602 for (i = 1; i < st->info->num_configs; i++) 603 if (st->config_cnts[i] < st->config_cnts[lru_position]) 604 lru_position = i; 605 606 for (i = 0; i < st->num_channels; i++) 607 if (st->channels[i].cfg.cfg_slot == lru_position) 608 st->channels[i].cfg.live = false; 609 610 ida_free(&st->cfg_slots_status, lru_position); 611 return ida_alloc(&st->cfg_slots_status, GFP_KERNEL); 612 } 613 614 /* Could be replaced with a generic LRU implementation */ 615 static int ad7173_load_config(struct ad7173_state *st, 616 struct ad7173_channel_config *cfg) 617 { 618 unsigned int config; 619 int free_cfg_slot, ret; 620 621 free_cfg_slot = ida_alloc_range(&st->cfg_slots_status, 0, 622 st->info->num_configs - 1, GFP_KERNEL); 623 if (free_cfg_slot < 0) 624 free_cfg_slot = ad7173_free_config_slot_lru(st); 625 626 cfg->cfg_slot = free_cfg_slot; 627 config = FIELD_PREP(AD7173_SETUP_REF_SEL_MASK, cfg->ref_sel); 628 629 if (cfg->bipolar) 630 config |= AD7173_SETUP_BIPOLAR; 631 632 if (cfg->input_buf) 633 config |= AD7173_SETUP_AIN_BUF_MASK; 634 635 ret = ad_sd_write_reg(&st->sd, AD7173_REG_SETUP(free_cfg_slot), 2, config); 636 if (ret) 637 return ret; 638 639 return ad_sd_write_reg(&st->sd, AD7173_REG_FILTER(free_cfg_slot), 2, 640 AD7173_FILTER_ODR0_MASK & cfg->odr); 641 } 642 643 static int ad7173_config_channel(struct ad7173_state *st, int addr) 644 { 645 struct ad7173_channel_config *cfg = &st->channels[addr].cfg; 646 struct ad7173_channel_config *live_cfg; 647 int ret; 648 649 if (!cfg->live) { 650 live_cfg = ad7173_find_live_config(st, cfg); 651 if (live_cfg) { 652 cfg->cfg_slot = live_cfg->cfg_slot; 653 } else { 654 ret = ad7173_load_config(st, cfg); 655 if (ret) 656 return ret; 657 cfg->live = true; 658 } 659 } 660 661 if (st->config_usage_counter == U64_MAX) 662 ad7173_reset_usage_cnts(st); 663 664 st->config_usage_counter++; 665 st->config_cnts[cfg->cfg_slot] = st->config_usage_counter; 666 667 return 0; 668 } 669 670 static int ad7173_set_channel(struct ad_sigma_delta *sd, unsigned int channel) 671 { 672 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 673 unsigned int val; 674 int ret; 675 676 ret = ad7173_config_channel(st, channel); 677 if (ret) 678 return ret; 679 680 val = AD7173_CH_ENABLE | 681 FIELD_PREP(AD7173_CH_SETUP_SEL_MASK, st->channels[channel].cfg.cfg_slot) | 682 st->channels[channel].ain; 683 684 if (st->channels[channel].cfg.openwire_comp_chan >= 0) 685 channel = st->channels[channel].cfg.openwire_comp_chan; 686 687 return ad_sd_write_reg(&st->sd, AD7173_REG_CH(channel), 2, val); 688 } 689 690 static int ad7173_set_mode(struct ad_sigma_delta *sd, 691 enum ad_sigma_delta_mode mode) 692 { 693 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 694 695 st->adc_mode &= ~AD7173_ADC_MODE_MODE_MASK; 696 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_MODE_MASK, mode); 697 698 return ad_sd_write_reg(&st->sd, AD7173_REG_ADC_MODE, 2, st->adc_mode); 699 } 700 701 static int ad7173_append_status(struct ad_sigma_delta *sd, bool append) 702 { 703 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 704 unsigned int interface_mode = st->interface_mode; 705 int ret; 706 707 interface_mode &= ~AD7173_INTERFACE_DATA_STAT; 708 interface_mode |= AD7173_INTERFACE_DATA_STAT_EN(append); 709 ret = ad_sd_write_reg(&st->sd, AD7173_REG_INTERFACE_MODE, 2, interface_mode); 710 if (ret) 711 return ret; 712 713 st->interface_mode = interface_mode; 714 715 return 0; 716 } 717 718 static int ad7173_disable_all(struct ad_sigma_delta *sd) 719 { 720 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 721 int ret; 722 int i; 723 724 for (i = 0; i < st->num_channels; i++) { 725 ret = ad_sd_write_reg(sd, AD7173_REG_CH(i), 2, 0); 726 if (ret < 0) 727 return ret; 728 } 729 730 return 0; 731 } 732 733 static int ad7173_disable_one(struct ad_sigma_delta *sd, unsigned int chan) 734 { 735 struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd); 736 737 if (st->channels[chan].cfg.openwire_comp_chan >= 0) 738 chan = st->channels[chan].cfg.openwire_comp_chan; 739 740 return ad_sd_write_reg(sd, AD7173_REG_CH(chan), 2, 0); 741 } 742 743 static const struct ad_sigma_delta_info ad7173_sigma_delta_info_4_slots = { 744 .set_channel = ad7173_set_channel, 745 .append_status = ad7173_append_status, 746 .disable_all = ad7173_disable_all, 747 .disable_one = ad7173_disable_one, 748 .set_mode = ad7173_set_mode, 749 .has_registers = true, 750 .has_named_irqs = true, 751 .addr_shift = 0, 752 .read_mask = BIT(6), 753 .status_ch_mask = GENMASK(3, 0), 754 .data_reg = AD7173_REG_DATA, 755 .num_resetclks = 64, 756 .num_slots = 4, 757 }; 758 759 static const struct ad_sigma_delta_info ad7173_sigma_delta_info_8_slots = { 760 .set_channel = ad7173_set_channel, 761 .append_status = ad7173_append_status, 762 .disable_all = ad7173_disable_all, 763 .disable_one = ad7173_disable_one, 764 .set_mode = ad7173_set_mode, 765 .has_registers = true, 766 .has_named_irqs = true, 767 .addr_shift = 0, 768 .read_mask = BIT(6), 769 .status_ch_mask = GENMASK(3, 0), 770 .data_reg = AD7173_REG_DATA, 771 .num_resetclks = 64, 772 .num_slots = 8, 773 }; 774 775 static const struct ad7173_device_info ad4111_device_info = { 776 .name = "ad4111", 777 .id = AD4111_ID, 778 .sd_info = &ad7173_sigma_delta_info_8_slots, 779 .num_voltage_in_div = 8, 780 .num_channels = 16, 781 .num_configs = 8, 782 .num_voltage_in = 8, 783 .num_gpios = 2, 784 .higher_gpio_bits = true, 785 .has_temp = true, 786 .has_vincom_input = true, 787 .has_input_buf = true, 788 .has_current_inputs = true, 789 .has_int_ref = true, 790 .has_internal_fs_calibration = true, 791 .has_openwire_det = true, 792 .clock = 2 * HZ_PER_MHZ, 793 .sinc5_data_rates = ad7173_sinc5_data_rates, 794 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 795 }; 796 797 static const struct ad7173_device_info ad4112_device_info = { 798 .name = "ad4112", 799 .id = AD4112_ID, 800 .sd_info = &ad7173_sigma_delta_info_8_slots, 801 .num_voltage_in_div = 8, 802 .num_channels = 16, 803 .num_configs = 8, 804 .num_voltage_in = 8, 805 .num_gpios = 2, 806 .higher_gpio_bits = true, 807 .has_vincom_input = true, 808 .has_temp = true, 809 .has_input_buf = true, 810 .has_current_inputs = true, 811 .has_int_ref = true, 812 .has_internal_fs_calibration = true, 813 .clock = 2 * HZ_PER_MHZ, 814 .sinc5_data_rates = ad7173_sinc5_data_rates, 815 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 816 }; 817 818 static const struct ad7173_device_info ad4113_device_info = { 819 .name = "ad4113", 820 .id = AD4113_ID, 821 .sd_info = &ad7173_sigma_delta_info_8_slots, 822 .num_voltage_in_div = 8, 823 .num_channels = 16, 824 .num_configs = 8, 825 .num_voltage_in = 8, 826 .num_gpios = 2, 827 .data_reg_only_16bit = true, 828 .higher_gpio_bits = true, 829 .has_vincom_input = true, 830 .has_input_buf = true, 831 .has_int_ref = true, 832 .clock = 2 * HZ_PER_MHZ, 833 .sinc5_data_rates = ad7173_sinc5_data_rates, 834 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 835 }; 836 837 static const struct ad7173_device_info ad4114_device_info = { 838 .name = "ad4114", 839 .id = AD4114_ID, 840 .sd_info = &ad7173_sigma_delta_info_8_slots, 841 .num_voltage_in_div = 16, 842 .num_channels = 16, 843 .num_configs = 8, 844 .num_voltage_in = 16, 845 .num_gpios = 4, 846 .has_vincom_input = true, 847 .has_temp = true, 848 .has_input_buf = true, 849 .has_int_ref = true, 850 .has_internal_fs_calibration = true, 851 .clock = 2 * HZ_PER_MHZ, 852 .sinc5_data_rates = ad7173_sinc5_data_rates, 853 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 854 }; 855 856 static const struct ad7173_device_info ad4115_device_info = { 857 .name = "ad4115", 858 .id = AD4115_ID, 859 .sd_info = &ad7173_sigma_delta_info_8_slots, 860 .num_voltage_in_div = 16, 861 .num_channels = 16, 862 .num_configs = 8, 863 .num_voltage_in = 16, 864 .num_gpios = 4, 865 .has_vincom_input = true, 866 .has_temp = true, 867 .has_input_buf = true, 868 .has_int_ref = true, 869 .has_internal_fs_calibration = true, 870 .clock = 8 * HZ_PER_MHZ, 871 .sinc5_data_rates = ad4115_sinc5_data_rates, 872 .num_sinc5_data_rates = ARRAY_SIZE(ad4115_sinc5_data_rates), 873 }; 874 875 static const struct ad7173_device_info ad4116_device_info = { 876 .name = "ad4116", 877 .id = AD4116_ID, 878 .sd_info = &ad7173_sigma_delta_info_8_slots, 879 .num_voltage_in_div = 11, 880 .num_channels = 16, 881 .num_configs = 8, 882 .num_voltage_in = 16, 883 .num_gpios = 4, 884 .has_vincom_input = true, 885 .has_temp = true, 886 .has_input_buf = true, 887 .has_int_ref = true, 888 .has_internal_fs_calibration = true, 889 .clock = 4 * HZ_PER_MHZ, 890 .sinc5_data_rates = ad4116_sinc5_data_rates, 891 .num_sinc5_data_rates = ARRAY_SIZE(ad4116_sinc5_data_rates), 892 }; 893 894 static const struct ad7173_device_info ad7172_2_device_info = { 895 .name = "ad7172-2", 896 .id = AD7172_2_ID, 897 .sd_info = &ad7173_sigma_delta_info_8_slots, 898 .num_voltage_in = 5, 899 .num_channels = 4, 900 .num_configs = 4, 901 .num_gpios = 2, 902 .has_temp = true, 903 .has_input_buf = true, 904 .has_int_ref = true, 905 .has_pow_supply_monitoring = true, 906 .clock = 2 * HZ_PER_MHZ, 907 .sinc5_data_rates = ad7173_sinc5_data_rates, 908 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 909 }; 910 911 static const struct ad7173_device_info ad7172_4_device_info = { 912 .name = "ad7172-4", 913 .id = AD7172_4_ID, 914 .sd_info = &ad7173_sigma_delta_info_8_slots, 915 .num_voltage_in = 9, 916 .num_channels = 8, 917 .num_configs = 8, 918 .num_gpios = 4, 919 .has_input_buf = true, 920 .has_ref2 = true, 921 .has_pow_supply_monitoring = true, 922 .clock = 2 * HZ_PER_MHZ, 923 .sinc5_data_rates = ad7173_sinc5_data_rates, 924 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 925 }; 926 927 static const struct ad7173_device_info ad7173_8_device_info = { 928 .name = "ad7173-8", 929 .id = AD7173_ID, 930 .sd_info = &ad7173_sigma_delta_info_8_slots, 931 .num_voltage_in = 17, 932 .num_channels = 16, 933 .num_configs = 8, 934 .num_gpios = 4, 935 .has_temp = true, 936 .has_input_buf = true, 937 .has_int_ref = true, 938 .has_ref2 = true, 939 .clock = 2 * HZ_PER_MHZ, 940 .sinc5_data_rates = ad7173_sinc5_data_rates, 941 .num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates), 942 }; 943 944 static const struct ad7173_device_info ad7175_2_device_info = { 945 .name = "ad7175-2", 946 .id = AD7175_2_ID, 947 .sd_info = &ad7173_sigma_delta_info_8_slots, 948 .num_voltage_in = 5, 949 .num_channels = 4, 950 .num_configs = 4, 951 .num_gpios = 2, 952 .has_temp = true, 953 .has_input_buf = true, 954 .has_int_ref = true, 955 .has_pow_supply_monitoring = true, 956 .clock = 16 * HZ_PER_MHZ, 957 .sinc5_data_rates = ad7175_sinc5_data_rates, 958 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 959 }; 960 961 static const struct ad7173_device_info ad7175_8_device_info = { 962 .name = "ad7175-8", 963 .id = AD7175_8_ID, 964 .sd_info = &ad7173_sigma_delta_info_8_slots, 965 .num_voltage_in = 17, 966 .num_channels = 16, 967 .num_configs = 8, 968 .num_gpios = 4, 969 .has_temp = true, 970 .has_input_buf = true, 971 .has_int_ref = true, 972 .has_ref2 = true, 973 .has_pow_supply_monitoring = true, 974 .clock = 16 * HZ_PER_MHZ, 975 .sinc5_data_rates = ad7175_sinc5_data_rates, 976 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 977 }; 978 979 static const struct ad7173_device_info ad7176_2_device_info = { 980 .name = "ad7176-2", 981 .id = AD7176_ID, 982 .sd_info = &ad7173_sigma_delta_info_4_slots, 983 .num_voltage_in = 5, 984 .num_channels = 4, 985 .num_configs = 4, 986 .num_gpios = 2, 987 .has_int_ref = true, 988 .clock = 16 * HZ_PER_MHZ, 989 .sinc5_data_rates = ad7175_sinc5_data_rates, 990 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 991 }; 992 993 static const struct ad7173_device_info ad7177_2_device_info = { 994 .name = "ad7177-2", 995 .id = AD7177_ID, 996 .sd_info = &ad7173_sigma_delta_info_4_slots, 997 .num_voltage_in = 5, 998 .num_channels = 4, 999 .num_configs = 4, 1000 .num_gpios = 2, 1001 .has_temp = true, 1002 .has_input_buf = true, 1003 .has_int_ref = true, 1004 .has_pow_supply_monitoring = true, 1005 .clock = 16 * HZ_PER_MHZ, 1006 .odr_start_value = AD7177_ODR_START_VALUE, 1007 .sinc5_data_rates = ad7175_sinc5_data_rates, 1008 .num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates), 1009 }; 1010 1011 static int ad7173_setup(struct iio_dev *indio_dev) 1012 { 1013 struct ad7173_state *st = iio_priv(indio_dev); 1014 struct device *dev = &st->sd.spi->dev; 1015 u8 buf[AD7173_RESET_LENGTH]; 1016 unsigned int id; 1017 int ret; 1018 1019 /* reset the serial interface */ 1020 memset(buf, 0xff, AD7173_RESET_LENGTH); 1021 ret = spi_write_then_read(st->sd.spi, buf, sizeof(buf), NULL, 0); 1022 if (ret < 0) 1023 return ret; 1024 1025 /* datasheet recommends a delay of at least 500us after reset */ 1026 fsleep(500); 1027 1028 ret = ad_sd_read_reg(&st->sd, AD7173_REG_ID, 2, &id); 1029 if (ret) 1030 return ret; 1031 1032 id &= AD7173_ID_MASK; 1033 if (id != st->info->id) 1034 dev_warn(dev, "Unexpected device id: 0x%04X, expected: 0x%04X\n", 1035 id, st->info->id); 1036 1037 st->adc_mode |= AD7173_ADC_MODE_SING_CYC; 1038 st->interface_mode = 0x0; 1039 1040 st->config_usage_counter = 0; 1041 st->config_cnts = devm_kcalloc(dev, st->info->num_configs, 1042 sizeof(*st->config_cnts), GFP_KERNEL); 1043 if (!st->config_cnts) 1044 return -ENOMEM; 1045 1046 ret = ad7173_calibrate_all(st, indio_dev); 1047 if (ret) 1048 return ret; 1049 1050 /* All channels are enabled by default after a reset */ 1051 return ad7173_disable_all(&st->sd); 1052 } 1053 1054 static unsigned int ad7173_get_ref_voltage_milli(struct ad7173_state *st, 1055 u8 reference_select) 1056 { 1057 int vref; 1058 1059 switch (reference_select) { 1060 case AD7173_SETUP_REF_SEL_EXT_REF: 1061 vref = regulator_get_voltage(st->regulators[0].consumer); 1062 break; 1063 1064 case AD7173_SETUP_REF_SEL_EXT_REF2: 1065 vref = regulator_get_voltage(st->regulators[1].consumer); 1066 break; 1067 1068 case AD7173_SETUP_REF_SEL_INT_REF: 1069 vref = AD7173_VOLTAGE_INT_REF_uV; 1070 break; 1071 1072 case AD7173_SETUP_REF_SEL_AVDD1_AVSS: 1073 vref = regulator_get_voltage(st->regulators[2].consumer); 1074 break; 1075 1076 default: 1077 return -EINVAL; 1078 } 1079 1080 if (vref < 0) 1081 return vref; 1082 1083 return vref / (MICRO / MILLI); 1084 } 1085 1086 static int ad7173_read_raw(struct iio_dev *indio_dev, 1087 struct iio_chan_spec const *chan, 1088 int *val, int *val2, long info) 1089 { 1090 struct ad7173_state *st = iio_priv(indio_dev); 1091 struct ad7173_channel *ch = &st->channels[chan->address]; 1092 unsigned int reg; 1093 u64 temp; 1094 int ret; 1095 1096 switch (info) { 1097 case IIO_CHAN_INFO_RAW: 1098 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val); 1099 if (ret < 0) 1100 return ret; 1101 1102 if (ch->openwire_det_en) { 1103 ret = ad4111_openwire_event(indio_dev, chan); 1104 if (ret < 0) 1105 return ret; 1106 } 1107 1108 return IIO_VAL_INT; 1109 case IIO_CHAN_INFO_SCALE: 1110 1111 switch (chan->type) { 1112 case IIO_TEMP: 1113 temp = AD7173_VOLTAGE_INT_REF_uV * MILLI; 1114 temp /= AD7173_TEMP_SENSIIVITY_uV_per_C; 1115 *val = temp; 1116 *val2 = chan->scan_type.realbits; 1117 return IIO_VAL_FRACTIONAL_LOG2; 1118 case IIO_VOLTAGE: 1119 *val = ad7173_get_ref_voltage_milli(st, ch->cfg.ref_sel); 1120 *val2 = chan->scan_type.realbits - !!(ch->cfg.bipolar); 1121 1122 if (chan->channel < st->info->num_voltage_in_div) 1123 *val *= AD4111_DIVIDER_RATIO; 1124 return IIO_VAL_FRACTIONAL_LOG2; 1125 case IIO_CURRENT: 1126 *val = ad7173_get_ref_voltage_milli(st, ch->cfg.ref_sel); 1127 *val /= AD4111_SHUNT_RESISTOR_OHM; 1128 *val2 = chan->scan_type.realbits - ch->cfg.bipolar; 1129 return IIO_VAL_FRACTIONAL_LOG2; 1130 default: 1131 return -EINVAL; 1132 } 1133 case IIO_CHAN_INFO_OFFSET: 1134 1135 switch (chan->type) { 1136 case IIO_TEMP: 1137 /* 0 Kelvin -> raw sample */ 1138 temp = -ABSOLUTE_ZERO_MILLICELSIUS; 1139 temp *= AD7173_TEMP_SENSIIVITY_uV_per_C; 1140 temp <<= chan->scan_type.realbits; 1141 temp = DIV_U64_ROUND_CLOSEST(temp, 1142 AD7173_VOLTAGE_INT_REF_uV * 1143 MILLI); 1144 *val = -temp; 1145 return IIO_VAL_INT; 1146 case IIO_VOLTAGE: 1147 case IIO_CURRENT: 1148 *val = -BIT(chan->scan_type.realbits - 1); 1149 return IIO_VAL_INT; 1150 default: 1151 return -EINVAL; 1152 } 1153 case IIO_CHAN_INFO_SAMP_FREQ: 1154 reg = st->channels[chan->address].cfg.odr; 1155 1156 *val = st->info->sinc5_data_rates[reg] / MILLI; 1157 *val2 = (st->info->sinc5_data_rates[reg] % MILLI) * (MICRO / MILLI); 1158 1159 return IIO_VAL_INT_PLUS_MICRO; 1160 default: 1161 return -EINVAL; 1162 } 1163 } 1164 1165 static int ad7173_write_raw(struct iio_dev *indio_dev, 1166 struct iio_chan_spec const *chan, 1167 int val, int val2, long info) 1168 { 1169 struct ad7173_state *st = iio_priv(indio_dev); 1170 struct ad7173_channel_config *cfg; 1171 unsigned int freq, i; 1172 int ret = 0; 1173 1174 if (!iio_device_claim_direct(indio_dev)) 1175 return -EBUSY; 1176 1177 switch (info) { 1178 /* 1179 * This attribute sets the sampling frequency for each channel individually. 1180 * There are no issues for raw or buffered reads of an individual channel. 1181 * 1182 * When multiple channels are enabled in buffered mode, the effective 1183 * sampling rate of a channel is lowered in correlation to the number 1184 * of channels enabled and the sampling rate of the other channels. 1185 * 1186 * Example: 3 channels enabled with rates CH1:6211sps CH2,CH3:10sps 1187 * While the reading of CH1 takes only 0.16ms, the reading of CH2 and CH3 1188 * will take 100ms each. 1189 * 1190 * This will cause the reading of CH1 to be actually done once every 1191 * 200.16ms, an effective rate of 4.99sps. 1192 */ 1193 case IIO_CHAN_INFO_SAMP_FREQ: 1194 freq = val * MILLI + val2 / MILLI; 1195 for (i = st->info->odr_start_value; i < st->info->num_sinc5_data_rates - 1; i++) 1196 if (freq >= st->info->sinc5_data_rates[i]) 1197 break; 1198 1199 cfg = &st->channels[chan->address].cfg; 1200 cfg->odr = i; 1201 cfg->live = false; 1202 break; 1203 1204 default: 1205 ret = -EINVAL; 1206 break; 1207 } 1208 1209 iio_device_release_direct(indio_dev); 1210 return ret; 1211 } 1212 1213 static int ad7173_update_scan_mode(struct iio_dev *indio_dev, 1214 const unsigned long *scan_mask) 1215 { 1216 struct ad7173_state *st = iio_priv(indio_dev); 1217 int i, ret; 1218 1219 for (i = 0; i < indio_dev->num_channels; i++) { 1220 if (test_bit(i, scan_mask)) 1221 ret = ad7173_set_channel(&st->sd, i); 1222 else 1223 ret = ad_sd_write_reg(&st->sd, AD7173_REG_CH(i), 2, 0); 1224 if (ret < 0) 1225 return ret; 1226 } 1227 1228 return 0; 1229 } 1230 1231 static int ad7173_debug_reg_access(struct iio_dev *indio_dev, unsigned int reg, 1232 unsigned int writeval, unsigned int *readval) 1233 { 1234 struct ad7173_state *st = iio_priv(indio_dev); 1235 u8 reg_size; 1236 1237 if (reg == AD7173_REG_COMMS) 1238 reg_size = 1; 1239 else if (reg == AD7173_REG_CRC || reg == AD7173_REG_DATA || 1240 reg >= AD7173_REG_OFFSET(0)) 1241 reg_size = 3; 1242 else 1243 reg_size = 2; 1244 1245 if (readval) 1246 return ad_sd_read_reg(&st->sd, reg, reg_size, readval); 1247 1248 return ad_sd_write_reg(&st->sd, reg, reg_size, writeval); 1249 } 1250 1251 static int ad7173_write_event_config(struct iio_dev *indio_dev, 1252 const struct iio_chan_spec *chan, 1253 enum iio_event_type type, 1254 enum iio_event_direction dir, 1255 bool state) 1256 { 1257 struct ad7173_state *st = iio_priv(indio_dev); 1258 struct ad7173_channel *adchan = &st->channels[chan->address]; 1259 1260 switch (type) { 1261 case IIO_EV_TYPE_FAULT: 1262 adchan->openwire_det_en = state; 1263 return 0; 1264 default: 1265 return -EINVAL; 1266 } 1267 } 1268 1269 static int ad7173_read_event_config(struct iio_dev *indio_dev, 1270 const struct iio_chan_spec *chan, 1271 enum iio_event_type type, 1272 enum iio_event_direction dir) 1273 { 1274 struct ad7173_state *st = iio_priv(indio_dev); 1275 struct ad7173_channel *adchan = &st->channels[chan->address]; 1276 1277 switch (type) { 1278 case IIO_EV_TYPE_FAULT: 1279 return adchan->openwire_det_en; 1280 default: 1281 return -EINVAL; 1282 } 1283 } 1284 1285 static const struct iio_event_spec ad4111_events[] = { 1286 { 1287 .type = IIO_EV_TYPE_FAULT, 1288 .dir = IIO_EV_DIR_FAULT_OPENWIRE, 1289 .mask_separate = BIT(IIO_EV_INFO_VALUE), 1290 .mask_shared_by_all = BIT(IIO_EV_INFO_ENABLE), 1291 }, 1292 }; 1293 1294 static const struct iio_info ad7173_info = { 1295 .read_raw = &ad7173_read_raw, 1296 .write_raw = &ad7173_write_raw, 1297 .debugfs_reg_access = &ad7173_debug_reg_access, 1298 .validate_trigger = ad_sd_validate_trigger, 1299 .update_scan_mode = ad7173_update_scan_mode, 1300 .write_event_config = ad7173_write_event_config, 1301 .read_event_config = ad7173_read_event_config, 1302 }; 1303 1304 static const struct iio_scan_type ad4113_scan_type = { 1305 .sign = 'u', 1306 .realbits = 16, 1307 .storagebits = 16, 1308 .endianness = IIO_BE, 1309 }; 1310 1311 static const struct iio_chan_spec ad7173_channel_template = { 1312 .type = IIO_VOLTAGE, 1313 .indexed = 1, 1314 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 1315 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ), 1316 .scan_type = { 1317 .sign = 'u', 1318 .realbits = 24, 1319 .storagebits = 32, 1320 .endianness = IIO_BE, 1321 }, 1322 .ext_info = ad7173_calibsys_ext_info, 1323 }; 1324 1325 static const struct iio_chan_spec ad7173_temp_iio_channel_template = { 1326 .type = IIO_TEMP, 1327 .channel = AD7173_AIN_TEMP_POS, 1328 .channel2 = AD7173_AIN_TEMP_NEG, 1329 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 1330 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET) | 1331 BIT(IIO_CHAN_INFO_SAMP_FREQ), 1332 .scan_type = { 1333 .sign = 'u', 1334 .realbits = 24, 1335 .storagebits = 32, 1336 .endianness = IIO_BE, 1337 }, 1338 }; 1339 1340 static void ad7173_disable_regulators(void *data) 1341 { 1342 struct ad7173_state *st = data; 1343 1344 regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators); 1345 } 1346 1347 static void ad7173_clk_disable_unprepare(void *clk) 1348 { 1349 clk_disable_unprepare(clk); 1350 } 1351 1352 static unsigned long ad7173_sel_clk(struct ad7173_state *st, 1353 unsigned int clk_sel) 1354 { 1355 int ret; 1356 1357 st->adc_mode &= ~AD7173_ADC_MODE_CLOCKSEL_MASK; 1358 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, clk_sel); 1359 ret = ad_sd_write_reg(&st->sd, AD7173_REG_ADC_MODE, 0x2, st->adc_mode); 1360 1361 return ret; 1362 } 1363 1364 static unsigned long ad7173_clk_recalc_rate(struct clk_hw *hw, 1365 unsigned long parent_rate) 1366 { 1367 struct ad7173_state *st = clk_hw_to_ad7173(hw); 1368 1369 return st->info->clock / HZ_PER_KHZ; 1370 } 1371 1372 static int ad7173_clk_output_is_enabled(struct clk_hw *hw) 1373 { 1374 struct ad7173_state *st = clk_hw_to_ad7173(hw); 1375 u32 clk_sel; 1376 1377 clk_sel = FIELD_GET(AD7173_ADC_MODE_CLOCKSEL_MASK, st->adc_mode); 1378 return clk_sel == AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT; 1379 } 1380 1381 static int ad7173_clk_output_prepare(struct clk_hw *hw) 1382 { 1383 struct ad7173_state *st = clk_hw_to_ad7173(hw); 1384 1385 return ad7173_sel_clk(st, AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT); 1386 } 1387 1388 static void ad7173_clk_output_unprepare(struct clk_hw *hw) 1389 { 1390 struct ad7173_state *st = clk_hw_to_ad7173(hw); 1391 1392 ad7173_sel_clk(st, AD7173_ADC_MODE_CLOCKSEL_INT); 1393 } 1394 1395 static const struct clk_ops ad7173_int_clk_ops = { 1396 .recalc_rate = ad7173_clk_recalc_rate, 1397 .is_enabled = ad7173_clk_output_is_enabled, 1398 .prepare = ad7173_clk_output_prepare, 1399 .unprepare = ad7173_clk_output_unprepare, 1400 }; 1401 1402 static int ad7173_register_clk_provider(struct iio_dev *indio_dev) 1403 { 1404 struct ad7173_state *st = iio_priv(indio_dev); 1405 struct device *dev = indio_dev->dev.parent; 1406 struct fwnode_handle *fwnode = dev_fwnode(dev); 1407 struct clk_init_data init = {}; 1408 int ret; 1409 1410 if (!IS_ENABLED(CONFIG_COMMON_CLK)) 1411 return 0; 1412 1413 init.name = fwnode_get_name(fwnode); 1414 init.ops = &ad7173_int_clk_ops; 1415 1416 st->int_clk_hw.init = &init; 1417 ret = devm_clk_hw_register(dev, &st->int_clk_hw); 1418 if (ret) 1419 return ret; 1420 1421 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 1422 &st->int_clk_hw); 1423 } 1424 1425 static int ad4111_validate_current_ain(struct ad7173_state *st, 1426 const unsigned int ain[AD7173_NO_AINS_PER_CHANNEL]) 1427 { 1428 struct device *dev = &st->sd.spi->dev; 1429 1430 if (!st->info->has_current_inputs) 1431 return dev_err_probe(dev, -EINVAL, 1432 "Model %s does not support current channels\n", 1433 st->info->name); 1434 1435 if (ain[0] >= ARRAY_SIZE(ad4111_current_channel_config)) 1436 return dev_err_probe(dev, -EINVAL, 1437 "For current channels single-channel must be <[0-3]>\n"); 1438 1439 return 0; 1440 } 1441 1442 static int ad7173_validate_voltage_ain_inputs(struct ad7173_state *st, 1443 unsigned int ain0, unsigned int ain1) 1444 { 1445 struct device *dev = &st->sd.spi->dev; 1446 bool special_input0, special_input1; 1447 1448 /* (AVDD1-AVSS)/5 power supply monitoring */ 1449 if (ain0 == AD7173_AIN_POW_MON_POS && ain1 == AD7173_AIN_POW_MON_NEG && 1450 st->info->has_pow_supply_monitoring) 1451 return 0; 1452 1453 special_input0 = AD7173_IS_REF_INPUT(ain0) || 1454 (ain0 == AD4111_VINCOM_INPUT && st->info->has_vincom_input); 1455 special_input1 = AD7173_IS_REF_INPUT(ain1) || 1456 (ain1 == AD4111_VINCOM_INPUT && st->info->has_vincom_input); 1457 1458 if ((ain0 >= st->info->num_voltage_in && !special_input0) || 1459 (ain1 >= st->info->num_voltage_in && !special_input1)) { 1460 if (ain0 == AD4111_VINCOM_INPUT || ain1 == AD4111_VINCOM_INPUT) 1461 return dev_err_probe(dev, -EINVAL, 1462 "VINCOM not supported for %s\n", st->info->name); 1463 1464 return dev_err_probe(dev, -EINVAL, 1465 "Input pin number out of range for pair (%d %d).\n", 1466 ain0, ain1); 1467 } 1468 1469 if (AD4111_IS_VINCOM_MISMATCH(ain0, ain1) || 1470 AD4111_IS_VINCOM_MISMATCH(ain1, ain0)) 1471 return dev_err_probe(dev, -EINVAL, 1472 "VINCOM must be paired with inputs having divider.\n"); 1473 1474 if (!special_input0 && !special_input1 && 1475 ((ain0 >= st->info->num_voltage_in_div) != 1476 (ain1 >= st->info->num_voltage_in_div))) 1477 return dev_err_probe(dev, -EINVAL, 1478 "Both inputs must either have a voltage divider or not have: (%d %d).\n", 1479 ain0, ain1); 1480 1481 return 0; 1482 } 1483 1484 static int ad7173_validate_reference(struct ad7173_state *st, int ref_sel) 1485 { 1486 struct device *dev = &st->sd.spi->dev; 1487 int ret; 1488 1489 if (ref_sel == AD7173_SETUP_REF_SEL_INT_REF && !st->info->has_int_ref) 1490 return dev_err_probe(dev, -EINVAL, 1491 "Internal reference is not available on current model.\n"); 1492 1493 if (ref_sel == AD7173_SETUP_REF_SEL_EXT_REF2 && !st->info->has_ref2) 1494 return dev_err_probe(dev, -EINVAL, 1495 "External reference 2 is not available on current model.\n"); 1496 1497 ret = ad7173_get_ref_voltage_milli(st, ref_sel); 1498 if (ret < 0) 1499 return dev_err_probe(dev, ret, "Cannot use reference %u\n", 1500 ref_sel); 1501 1502 return 0; 1503 } 1504 1505 static int ad7173_validate_openwire_ain_inputs(struct ad7173_state *st, 1506 bool differential, 1507 unsigned int ain0, 1508 unsigned int ain1) 1509 { 1510 /* 1511 * If the channel is configured as differential, 1512 * the ad4111 requires specific ains to be used together 1513 */ 1514 if (differential) 1515 return (ain0 % 2) ? (ain0 - 1) == ain1 : (ain0 + 1) == ain1; 1516 1517 return ain1 == AD4111_VINCOM_INPUT; 1518 } 1519 1520 static unsigned int ad7173_calc_openwire_thrsh_raw(struct ad7173_state *st, 1521 struct iio_chan_spec *chan, 1522 struct ad7173_channel *chan_st_priv, 1523 unsigned int thrsh_mv) { 1524 unsigned int thrsh_raw; 1525 1526 thrsh_raw = 1527 BIT(chan->scan_type.realbits - !!(chan_st_priv->cfg.bipolar)) 1528 * thrsh_mv 1529 / ad7173_get_ref_voltage_milli(st, chan_st_priv->cfg.ref_sel); 1530 if (chan->channel < st->info->num_voltage_in_div) 1531 thrsh_raw /= AD4111_DIVIDER_RATIO; 1532 1533 return thrsh_raw; 1534 } 1535 1536 static int ad7173_fw_parse_channel_config(struct iio_dev *indio_dev) 1537 { 1538 struct ad7173_channel *chans_st_arr, *chan_st_priv; 1539 struct ad7173_state *st = iio_priv(indio_dev); 1540 struct device *dev = indio_dev->dev.parent; 1541 struct iio_chan_spec *chan_arr, *chan; 1542 unsigned int ain[AD7173_NO_AINS_PER_CHANNEL], chan_index = 0; 1543 int ref_sel, ret, num_channels; 1544 1545 num_channels = device_get_child_node_count(dev); 1546 1547 if (st->info->has_temp) 1548 num_channels++; 1549 1550 if (num_channels == 0) 1551 return dev_err_probe(dev, -ENODATA, "No channels specified\n"); 1552 1553 if (num_channels > st->info->num_channels) 1554 return dev_err_probe(dev, -EINVAL, 1555 "Too many channels specified. Maximum is %d, not including temperature channel if supported.\n", 1556 st->info->num_channels); 1557 1558 indio_dev->num_channels = num_channels; 1559 st->num_channels = num_channels; 1560 1561 chan_arr = devm_kcalloc(dev, sizeof(*indio_dev->channels), 1562 st->num_channels, GFP_KERNEL); 1563 if (!chan_arr) 1564 return -ENOMEM; 1565 1566 chans_st_arr = devm_kcalloc(dev, st->num_channels, sizeof(*st->channels), 1567 GFP_KERNEL); 1568 if (!chans_st_arr) 1569 return -ENOMEM; 1570 1571 indio_dev->channels = chan_arr; 1572 st->channels = chans_st_arr; 1573 1574 if (st->info->has_temp) { 1575 chan_arr[chan_index] = ad7173_temp_iio_channel_template; 1576 chan_st_priv = &chans_st_arr[chan_index]; 1577 chan_st_priv->ain = 1578 AD7173_CH_ADDRESS(chan_arr[chan_index].channel, 1579 chan_arr[chan_index].channel2); 1580 chan_st_priv->cfg.bipolar = false; 1581 chan_st_priv->cfg.input_buf = st->info->has_input_buf; 1582 chan_st_priv->cfg.ref_sel = AD7173_SETUP_REF_SEL_INT_REF; 1583 chan_st_priv->cfg.openwire_comp_chan = -1; 1584 st->adc_mode |= AD7173_ADC_MODE_REF_EN; 1585 if (st->info->data_reg_only_16bit) 1586 chan_arr[chan_index].scan_type = ad4113_scan_type; 1587 1588 chan_index++; 1589 } 1590 1591 device_for_each_child_node_scoped(dev, child) { 1592 bool is_current_chan = false; 1593 1594 chan = &chan_arr[chan_index]; 1595 *chan = ad7173_channel_template; 1596 chan_st_priv = &chans_st_arr[chan_index]; 1597 ret = fwnode_property_read_u32_array(child, "diff-channels", 1598 ain, ARRAY_SIZE(ain)); 1599 if (ret) { 1600 ret = fwnode_property_read_u32(child, "single-channel", 1601 ain); 1602 if (ret) 1603 return dev_err_probe(dev, ret, 1604 "Channel must define one of diff-channels or single-channel.\n"); 1605 1606 is_current_chan = fwnode_property_read_bool(child, "adi,current-channel"); 1607 } else { 1608 chan->differential = true; 1609 } 1610 1611 if (is_current_chan) { 1612 ret = ad4111_validate_current_ain(st, ain); 1613 if (ret) 1614 return ret; 1615 } else { 1616 if (!chan->differential) { 1617 ret = fwnode_property_read_u32(child, 1618 "common-mode-channel", ain + 1); 1619 if (ret) 1620 return dev_err_probe(dev, ret, 1621 "common-mode-channel must be defined for single-ended channels.\n"); 1622 } 1623 ret = ad7173_validate_voltage_ain_inputs(st, ain[0], ain[1]); 1624 if (ret) 1625 return ret; 1626 } 1627 1628 ret = fwnode_property_match_property_string(child, 1629 "adi,reference-select", 1630 ad7173_ref_sel_str, 1631 ARRAY_SIZE(ad7173_ref_sel_str)); 1632 if (ret < 0) 1633 ref_sel = AD7173_SETUP_REF_SEL_INT_REF; 1634 else 1635 ref_sel = ret; 1636 1637 ret = ad7173_validate_reference(st, ref_sel); 1638 if (ret) 1639 return ret; 1640 1641 if (ref_sel == AD7173_SETUP_REF_SEL_INT_REF) 1642 st->adc_mode |= AD7173_ADC_MODE_REF_EN; 1643 chan_st_priv->cfg.ref_sel = ref_sel; 1644 1645 chan->address = chan_index; 1646 chan->scan_index = chan_index; 1647 chan->channel = ain[0]; 1648 chan_st_priv->cfg.input_buf = st->info->has_input_buf; 1649 chan_st_priv->cfg.odr = 0; 1650 chan_st_priv->cfg.openwire_comp_chan = -1; 1651 1652 chan_st_priv->cfg.bipolar = fwnode_property_read_bool(child, "bipolar"); 1653 if (chan_st_priv->cfg.bipolar) 1654 chan->info_mask_separate |= BIT(IIO_CHAN_INFO_OFFSET); 1655 1656 if (is_current_chan) { 1657 chan->type = IIO_CURRENT; 1658 chan->differential = false; 1659 chan->channel2 = 0; 1660 chan_st_priv->ain = ad4111_current_channel_config[ain[0]]; 1661 } else { 1662 chan_st_priv->cfg.input_buf = st->info->has_input_buf; 1663 chan->channel2 = ain[1]; 1664 chan_st_priv->ain = AD7173_CH_ADDRESS(ain[0], ain[1]); 1665 if (st->info->has_openwire_det && 1666 ad7173_validate_openwire_ain_inputs(st, chan->differential, ain[0], ain[1])) { 1667 chan->event_spec = ad4111_events; 1668 chan->num_event_specs = ARRAY_SIZE(ad4111_events); 1669 chan_st_priv->cfg.openwire_thrsh_raw = 1670 ad7173_calc_openwire_thrsh_raw(st, chan, chan_st_priv, 1671 AD4111_OW_DET_THRSH_MV); 1672 } 1673 } 1674 1675 if (st->info->data_reg_only_16bit) 1676 chan_arr[chan_index].scan_type = ad4113_scan_type; 1677 1678 chan_index++; 1679 } 1680 return 0; 1681 } 1682 1683 static int ad7173_fw_parse_device_config(struct iio_dev *indio_dev) 1684 { 1685 struct ad7173_state *st = iio_priv(indio_dev); 1686 struct device *dev = indio_dev->dev.parent; 1687 int ret; 1688 1689 st->regulators[0].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_EXT_REF]; 1690 st->regulators[1].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_EXT_REF2]; 1691 st->regulators[2].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_AVDD1_AVSS]; 1692 1693 /* 1694 * If a regulator is not available, it will be set to a dummy regulator. 1695 * Each channel reference is checked with regulator_get_voltage() before 1696 * setting attributes so if any channel uses a dummy supply the driver 1697 * probe will fail. 1698 */ 1699 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st->regulators), 1700 st->regulators); 1701 if (ret) 1702 return dev_err_probe(dev, ret, "Failed to get regulators\n"); 1703 1704 ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators); 1705 if (ret) 1706 return dev_err_probe(dev, ret, "Failed to enable regulators\n"); 1707 1708 ret = devm_add_action_or_reset(dev, ad7173_disable_regulators, st); 1709 if (ret) 1710 return dev_err_probe(dev, ret, 1711 "Failed to add regulators disable action\n"); 1712 1713 ret = device_property_match_property_string(dev, "clock-names", 1714 ad7173_clk_sel, 1715 ARRAY_SIZE(ad7173_clk_sel)); 1716 if (ret < 0) { 1717 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, 1718 AD7173_ADC_MODE_CLOCKSEL_INT); 1719 ad7173_register_clk_provider(indio_dev); 1720 } else { 1721 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, 1722 AD7173_ADC_MODE_CLOCKSEL_EXT + ret); 1723 st->ext_clk = devm_clk_get(dev, ad7173_clk_sel[ret]); 1724 if (IS_ERR(st->ext_clk)) 1725 return dev_err_probe(dev, PTR_ERR(st->ext_clk), 1726 "Failed to get external clock\n"); 1727 1728 ret = clk_prepare_enable(st->ext_clk); 1729 if (ret) 1730 return dev_err_probe(dev, ret, 1731 "Failed to enable external clock\n"); 1732 1733 ret = devm_add_action_or_reset(dev, ad7173_clk_disable_unprepare, 1734 st->ext_clk); 1735 if (ret) 1736 return ret; 1737 } 1738 1739 return ad7173_fw_parse_channel_config(indio_dev); 1740 } 1741 1742 static int ad7173_probe(struct spi_device *spi) 1743 { 1744 struct device *dev = &spi->dev; 1745 struct ad7173_state *st; 1746 struct iio_dev *indio_dev; 1747 int ret; 1748 1749 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1750 if (!indio_dev) 1751 return -ENOMEM; 1752 1753 st = iio_priv(indio_dev); 1754 st->info = spi_get_device_match_data(spi); 1755 if (!st->info) 1756 return -ENODEV; 1757 1758 ida_init(&st->cfg_slots_status); 1759 ret = devm_add_action_or_reset(dev, ad7173_ida_destroy, st); 1760 if (ret) 1761 return ret; 1762 1763 indio_dev->name = st->info->name; 1764 indio_dev->modes = INDIO_DIRECT_MODE; 1765 indio_dev->info = &ad7173_info; 1766 1767 spi->mode = SPI_MODE_3; 1768 spi_setup(spi); 1769 1770 ret = ad_sd_init(&st->sd, indio_dev, spi, st->info->sd_info); 1771 if (ret) 1772 return ret; 1773 1774 ret = ad7173_fw_parse_device_config(indio_dev); 1775 if (ret) 1776 return ret; 1777 1778 ret = devm_ad_sd_setup_buffer_and_trigger(dev, indio_dev); 1779 if (ret) 1780 return ret; 1781 1782 ret = ad7173_setup(indio_dev); 1783 if (ret) 1784 return ret; 1785 1786 ret = devm_iio_device_register(dev, indio_dev); 1787 if (ret) 1788 return ret; 1789 1790 return ad7173_gpio_init(st); 1791 } 1792 1793 static const struct of_device_id ad7173_of_match[] = { 1794 { .compatible = "adi,ad4111", .data = &ad4111_device_info }, 1795 { .compatible = "adi,ad4112", .data = &ad4112_device_info }, 1796 { .compatible = "adi,ad4113", .data = &ad4113_device_info }, 1797 { .compatible = "adi,ad4114", .data = &ad4114_device_info }, 1798 { .compatible = "adi,ad4115", .data = &ad4115_device_info }, 1799 { .compatible = "adi,ad4116", .data = &ad4116_device_info }, 1800 { .compatible = "adi,ad7172-2", .data = &ad7172_2_device_info }, 1801 { .compatible = "adi,ad7172-4", .data = &ad7172_4_device_info }, 1802 { .compatible = "adi,ad7173-8", .data = &ad7173_8_device_info }, 1803 { .compatible = "adi,ad7175-2", .data = &ad7175_2_device_info }, 1804 { .compatible = "adi,ad7175-8", .data = &ad7175_8_device_info }, 1805 { .compatible = "adi,ad7176-2", .data = &ad7176_2_device_info }, 1806 { .compatible = "adi,ad7177-2", .data = &ad7177_2_device_info }, 1807 { } 1808 }; 1809 MODULE_DEVICE_TABLE(of, ad7173_of_match); 1810 1811 static const struct spi_device_id ad7173_id_table[] = { 1812 { "ad4111", (kernel_ulong_t)&ad4111_device_info }, 1813 { "ad4112", (kernel_ulong_t)&ad4112_device_info }, 1814 { "ad4113", (kernel_ulong_t)&ad4113_device_info }, 1815 { "ad4114", (kernel_ulong_t)&ad4114_device_info }, 1816 { "ad4115", (kernel_ulong_t)&ad4115_device_info }, 1817 { "ad4116", (kernel_ulong_t)&ad4116_device_info }, 1818 { "ad7172-2", (kernel_ulong_t)&ad7172_2_device_info }, 1819 { "ad7172-4", (kernel_ulong_t)&ad7172_4_device_info }, 1820 { "ad7173-8", (kernel_ulong_t)&ad7173_8_device_info }, 1821 { "ad7175-2", (kernel_ulong_t)&ad7175_2_device_info }, 1822 { "ad7175-8", (kernel_ulong_t)&ad7175_8_device_info }, 1823 { "ad7176-2", (kernel_ulong_t)&ad7176_2_device_info }, 1824 { "ad7177-2", (kernel_ulong_t)&ad7177_2_device_info }, 1825 { } 1826 }; 1827 MODULE_DEVICE_TABLE(spi, ad7173_id_table); 1828 1829 static struct spi_driver ad7173_driver = { 1830 .driver = { 1831 .name = "ad7173", 1832 .of_match_table = ad7173_of_match, 1833 }, 1834 .probe = ad7173_probe, 1835 .id_table = ad7173_id_table, 1836 }; 1837 module_spi_driver(ad7173_driver); 1838 1839 MODULE_IMPORT_NS("IIO_AD_SIGMA_DELTA"); 1840 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafo.de>"); 1841 MODULE_AUTHOR("Dumitru Ceclan <dumitru.ceclan@analog.com>"); 1842 MODULE_DESCRIPTION("Analog Devices AD7173 and similar ADC driver"); 1843 MODULE_LICENSE("GPL"); 1844