1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NXP FXLS8962AF/FXLS8964AF Accelerometer Core Driver 4 * 5 * Copyright 2021 Connected Cars A/S 6 * 7 * Datasheet: 8 * https://www.nxp.com/docs/en/data-sheet/FXLS8962AF.pdf 9 * https://www.nxp.com/docs/en/data-sheet/FXLS8964AF.pdf 10 * 11 * Errata: 12 * https://www.nxp.com/docs/en/errata/ES_FXLS8962AF.pdf 13 */ 14 15 #include <linux/bits.h> 16 #include <linux/bitfield.h> 17 #include <linux/i2c.h> 18 #include <linux/irq.h> 19 #include <linux/module.h> 20 #include <linux/mod_devicetable.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/property.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/regmap.h> 25 #include <linux/types.h> 26 27 #include <linux/iio/buffer.h> 28 #include <linux/iio/events.h> 29 #include <linux/iio/iio.h> 30 #include <linux/iio/kfifo_buf.h> 31 #include <linux/iio/sysfs.h> 32 33 #include "fxls8962af.h" 34 35 #define FXLS8962AF_INT_STATUS 0x00 36 #define FXLS8962AF_INT_STATUS_SRC_BOOT BIT(0) 37 #define FXLS8962AF_INT_STATUS_SRC_SDCD_OT BIT(4) 38 #define FXLS8962AF_INT_STATUS_SRC_BUF BIT(5) 39 #define FXLS8962AF_INT_STATUS_SRC_DRDY BIT(7) 40 #define FXLS8962AF_TEMP_OUT 0x01 41 #define FXLS8962AF_VECM_LSB 0x02 42 #define FXLS8962AF_OUT_X_LSB 0x04 43 #define FXLS8962AF_OUT_Y_LSB 0x06 44 #define FXLS8962AF_OUT_Z_LSB 0x08 45 #define FXLS8962AF_BUF_STATUS 0x0b 46 #define FXLS8962AF_BUF_STATUS_BUF_CNT GENMASK(5, 0) 47 #define FXLS8962AF_BUF_STATUS_BUF_OVF BIT(6) 48 #define FXLS8962AF_BUF_STATUS_BUF_WMRK BIT(7) 49 #define FXLS8962AF_BUF_X_LSB 0x0c 50 #define FXLS8962AF_BUF_Y_LSB 0x0e 51 #define FXLS8962AF_BUF_Z_LSB 0x10 52 53 #define FXLS8962AF_PROD_REV 0x12 54 #define FXLS8962AF_WHO_AM_I 0x13 55 56 #define FXLS8962AF_SYS_MODE 0x14 57 #define FXLS8962AF_SENS_CONFIG1 0x15 58 #define FXLS8962AF_SENS_CONFIG1_ACTIVE BIT(0) 59 #define FXLS8962AF_SENS_CONFIG1_RST BIT(7) 60 #define FXLS8962AF_SC1_FSR_MASK GENMASK(2, 1) 61 #define FXLS8962AF_SC1_FSR_PREP(x) FIELD_PREP(FXLS8962AF_SC1_FSR_MASK, (x)) 62 #define FXLS8962AF_SC1_FSR_GET(x) FIELD_GET(FXLS8962AF_SC1_FSR_MASK, (x)) 63 64 #define FXLS8962AF_SENS_CONFIG2 0x16 65 #define FXLS8962AF_SENS_CONFIG3 0x17 66 #define FXLS8962AF_SC3_WAKE_ODR_MASK GENMASK(7, 4) 67 #define FXLS8962AF_SC3_WAKE_ODR_PREP(x) FIELD_PREP(FXLS8962AF_SC3_WAKE_ODR_MASK, (x)) 68 #define FXLS8962AF_SC3_WAKE_ODR_GET(x) FIELD_GET(FXLS8962AF_SC3_WAKE_ODR_MASK, (x)) 69 #define FXLS8962AF_SENS_CONFIG4 0x18 70 #define FXLS8962AF_SC4_INT_PP_OD_MASK BIT(1) 71 #define FXLS8962AF_SC4_INT_PP_OD_PREP(x) FIELD_PREP(FXLS8962AF_SC4_INT_PP_OD_MASK, (x)) 72 #define FXLS8962AF_SC4_INT_POL_MASK BIT(0) 73 #define FXLS8962AF_SC4_INT_POL_PREP(x) FIELD_PREP(FXLS8962AF_SC4_INT_POL_MASK, (x)) 74 #define FXLS8962AF_SENS_CONFIG5 0x19 75 76 #define FXLS8962AF_WAKE_IDLE_LSB 0x1b 77 #define FXLS8962AF_SLEEP_IDLE_LSB 0x1c 78 #define FXLS8962AF_ASLP_COUNT_LSB 0x1e 79 80 #define FXLS8962AF_INT_EN 0x20 81 #define FXLS8962AF_INT_EN_SDCD_OT_EN BIT(5) 82 #define FXLS8962AF_INT_EN_BUF_EN BIT(6) 83 #define FXLS8962AF_INT_PIN_SEL 0x21 84 #define FXLS8962AF_INT_PIN_SEL_MASK GENMASK(7, 0) 85 #define FXLS8962AF_INT_PIN_SEL_INT1 0x00 86 #define FXLS8962AF_INT_PIN_SEL_INT2 GENMASK(7, 0) 87 88 #define FXLS8962AF_OFF_X 0x22 89 #define FXLS8962AF_OFF_Y 0x23 90 #define FXLS8962AF_OFF_Z 0x24 91 92 #define FXLS8962AF_BUF_CONFIG1 0x26 93 #define FXLS8962AF_BC1_BUF_MODE_MASK GENMASK(6, 5) 94 #define FXLS8962AF_BC1_BUF_MODE_PREP(x) FIELD_PREP(FXLS8962AF_BC1_BUF_MODE_MASK, (x)) 95 #define FXLS8962AF_BUF_CONFIG2 0x27 96 #define FXLS8962AF_BUF_CONFIG2_BUF_WMRK GENMASK(5, 0) 97 98 #define FXLS8962AF_ORIENT_STATUS 0x28 99 #define FXLS8962AF_ORIENT_CONFIG 0x29 100 #define FXLS8962AF_ORIENT_DBCOUNT 0x2a 101 #define FXLS8962AF_ORIENT_BF_ZCOMP 0x2b 102 #define FXLS8962AF_ORIENT_THS_REG 0x2c 103 104 #define FXLS8962AF_SDCD_INT_SRC1 0x2d 105 #define FXLS8962AF_SDCD_INT_SRC1_X_OT BIT(5) 106 #define FXLS8962AF_SDCD_INT_SRC1_X_POL BIT(4) 107 #define FXLS8962AF_SDCD_INT_SRC1_Y_OT BIT(3) 108 #define FXLS8962AF_SDCD_INT_SRC1_Y_POL BIT(2) 109 #define FXLS8962AF_SDCD_INT_SRC1_Z_OT BIT(1) 110 #define FXLS8962AF_SDCD_INT_SRC1_Z_POL BIT(0) 111 #define FXLS8962AF_SDCD_INT_SRC2 0x2e 112 #define FXLS8962AF_SDCD_CONFIG1 0x2f 113 #define FXLS8962AF_SDCD_CONFIG1_Z_OT_EN BIT(3) 114 #define FXLS8962AF_SDCD_CONFIG1_Y_OT_EN BIT(4) 115 #define FXLS8962AF_SDCD_CONFIG1_X_OT_EN BIT(5) 116 #define FXLS8962AF_SDCD_CONFIG1_OT_ELE BIT(7) 117 #define FXLS8962AF_SDCD_CONFIG2 0x30 118 #define FXLS8962AF_SDCD_CONFIG2_SDCD_EN BIT(7) 119 #define FXLS8962AF_SC2_REF_UPDM_AC GENMASK(6, 5) 120 #define FXLS8962AF_SDCD_OT_DBCNT 0x31 121 #define FXLS8962AF_SDCD_WT_DBCNT 0x32 122 #define FXLS8962AF_SDCD_LTHS_LSB 0x33 123 #define FXLS8962AF_SDCD_UTHS_LSB 0x35 124 125 #define FXLS8962AF_SELF_TEST_CONFIG1 0x37 126 #define FXLS8962AF_SELF_TEST_CONFIG2 0x38 127 128 #define FXLS8962AF_MAX_REG 0x38 129 130 #define FXLS8962AF_DEVICE_ID 0x62 131 #define FXLS8964AF_DEVICE_ID 0x84 132 #define FXLS8974CF_DEVICE_ID 0x86 133 #define FXLS8967AF_DEVICE_ID 0x87 134 135 /* Raw temp channel offset */ 136 #define FXLS8962AF_TEMP_CENTER_VAL 25 137 138 #define FXLS8962AF_AUTO_SUSPEND_DELAY_MS 2000 139 140 #define FXLS8962AF_FIFO_LENGTH 32 141 #define FXLS8962AF_SCALE_TABLE_LEN 4 142 #define FXLS8962AF_SAMP_FREQ_TABLE_LEN 13 143 144 static const int fxls8962af_scale_table[FXLS8962AF_SCALE_TABLE_LEN][2] = { 145 {0, IIO_G_TO_M_S_2(980000)}, 146 {0, IIO_G_TO_M_S_2(1950000)}, 147 {0, IIO_G_TO_M_S_2(3910000)}, 148 {0, IIO_G_TO_M_S_2(7810000)}, 149 }; 150 151 static const int fxls8962af_samp_freq_table[FXLS8962AF_SAMP_FREQ_TABLE_LEN][2] = { 152 {3200, 0}, {1600, 0}, {800, 0}, {400, 0}, {200, 0}, {100, 0}, 153 {50, 0}, {25, 0}, {12, 500000}, {6, 250000}, {3, 125000}, 154 {1, 563000}, {0, 781000}, 155 }; 156 157 struct fxls8962af_chip_info { 158 const char *name; 159 const struct iio_chan_spec *channels; 160 int num_channels; 161 u8 chip_id; 162 }; 163 164 struct fxls8962af_data { 165 struct regmap *regmap; 166 const struct fxls8962af_chip_info *chip_info; 167 struct { 168 __le16 channels[3]; 169 aligned_s64 ts; 170 } scan; 171 int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */ 172 struct iio_mount_matrix orientation; 173 int irq; 174 u8 watermark; 175 u8 enable_event; 176 u16 lower_thres; 177 u16 upper_thres; 178 }; 179 180 const struct regmap_config fxls8962af_i2c_regmap_conf = { 181 .reg_bits = 8, 182 .val_bits = 8, 183 .max_register = FXLS8962AF_MAX_REG, 184 }; 185 EXPORT_SYMBOL_NS_GPL(fxls8962af_i2c_regmap_conf, "IIO_FXLS8962AF"); 186 187 const struct regmap_config fxls8962af_spi_regmap_conf = { 188 .reg_bits = 8, 189 .pad_bits = 8, 190 .val_bits = 8, 191 .max_register = FXLS8962AF_MAX_REG, 192 }; 193 EXPORT_SYMBOL_NS_GPL(fxls8962af_spi_regmap_conf, "IIO_FXLS8962AF"); 194 195 enum { 196 fxls8962af_idx_x, 197 fxls8962af_idx_y, 198 fxls8962af_idx_z, 199 fxls8962af_idx_ts, 200 }; 201 202 enum fxls8962af_int_pin { 203 FXLS8962AF_PIN_INT1, 204 FXLS8962AF_PIN_INT2, 205 }; 206 207 static int fxls8962af_power_on(struct fxls8962af_data *data) 208 { 209 struct device *dev = regmap_get_device(data->regmap); 210 int ret; 211 212 ret = pm_runtime_resume_and_get(dev); 213 if (ret) 214 dev_err(dev, "failed to power on\n"); 215 216 return ret; 217 } 218 219 static int fxls8962af_power_off(struct fxls8962af_data *data) 220 { 221 struct device *dev = regmap_get_device(data->regmap); 222 int ret; 223 224 pm_runtime_mark_last_busy(dev); 225 ret = pm_runtime_put_autosuspend(dev); 226 if (ret) 227 dev_err(dev, "failed to power off\n"); 228 229 return ret; 230 } 231 232 static int fxls8962af_standby(struct fxls8962af_data *data) 233 { 234 return regmap_clear_bits(data->regmap, FXLS8962AF_SENS_CONFIG1, 235 FXLS8962AF_SENS_CONFIG1_ACTIVE); 236 } 237 238 static int fxls8962af_active(struct fxls8962af_data *data) 239 { 240 return regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG1, 241 FXLS8962AF_SENS_CONFIG1_ACTIVE, 1); 242 } 243 244 static int fxls8962af_is_active(struct fxls8962af_data *data) 245 { 246 unsigned int reg; 247 int ret; 248 249 ret = regmap_read(data->regmap, FXLS8962AF_SENS_CONFIG1, ®); 250 if (ret) 251 return ret; 252 253 return reg & FXLS8962AF_SENS_CONFIG1_ACTIVE; 254 } 255 256 static int fxls8962af_get_out(struct fxls8962af_data *data, 257 struct iio_chan_spec const *chan, int *val) 258 { 259 struct device *dev = regmap_get_device(data->regmap); 260 __le16 raw_val; 261 int is_active; 262 int ret; 263 264 is_active = fxls8962af_is_active(data); 265 if (!is_active) { 266 ret = fxls8962af_power_on(data); 267 if (ret) 268 return ret; 269 } 270 271 ret = regmap_bulk_read(data->regmap, chan->address, 272 &raw_val, sizeof(data->lower_thres)); 273 274 if (!is_active) 275 fxls8962af_power_off(data); 276 277 if (ret) { 278 dev_err(dev, "failed to get out reg 0x%lx\n", chan->address); 279 return ret; 280 } 281 282 *val = sign_extend32(le16_to_cpu(raw_val), 283 chan->scan_type.realbits - 1); 284 285 return IIO_VAL_INT; 286 } 287 288 static int fxls8962af_read_avail(struct iio_dev *indio_dev, 289 struct iio_chan_spec const *chan, 290 const int **vals, int *type, int *length, 291 long mask) 292 { 293 switch (mask) { 294 case IIO_CHAN_INFO_SCALE: 295 *type = IIO_VAL_INT_PLUS_NANO; 296 *vals = (int *)fxls8962af_scale_table; 297 *length = ARRAY_SIZE(fxls8962af_scale_table) * 2; 298 return IIO_AVAIL_LIST; 299 case IIO_CHAN_INFO_SAMP_FREQ: 300 *type = IIO_VAL_INT_PLUS_MICRO; 301 *vals = (int *)fxls8962af_samp_freq_table; 302 *length = ARRAY_SIZE(fxls8962af_samp_freq_table) * 2; 303 return IIO_AVAIL_LIST; 304 default: 305 return -EINVAL; 306 } 307 } 308 309 static int fxls8962af_write_raw_get_fmt(struct iio_dev *indio_dev, 310 struct iio_chan_spec const *chan, 311 long mask) 312 { 313 switch (mask) { 314 case IIO_CHAN_INFO_SCALE: 315 return IIO_VAL_INT_PLUS_NANO; 316 case IIO_CHAN_INFO_SAMP_FREQ: 317 return IIO_VAL_INT_PLUS_MICRO; 318 default: 319 return IIO_VAL_INT_PLUS_NANO; 320 } 321 } 322 323 static int fxls8962af_update_config(struct fxls8962af_data *data, u8 reg, 324 u8 mask, u8 val) 325 { 326 int ret; 327 int is_active; 328 329 is_active = fxls8962af_is_active(data); 330 if (is_active) { 331 ret = fxls8962af_standby(data); 332 if (ret) 333 return ret; 334 } 335 336 ret = regmap_update_bits(data->regmap, reg, mask, val); 337 if (ret) 338 return ret; 339 340 if (is_active) { 341 ret = fxls8962af_active(data); 342 if (ret) 343 return ret; 344 } 345 346 return 0; 347 } 348 349 static int fxls8962af_set_full_scale(struct fxls8962af_data *data, u32 scale) 350 { 351 int i; 352 353 for (i = 0; i < ARRAY_SIZE(fxls8962af_scale_table); i++) 354 if (scale == fxls8962af_scale_table[i][1]) 355 break; 356 357 if (i == ARRAY_SIZE(fxls8962af_scale_table)) 358 return -EINVAL; 359 360 return fxls8962af_update_config(data, FXLS8962AF_SENS_CONFIG1, 361 FXLS8962AF_SC1_FSR_MASK, 362 FXLS8962AF_SC1_FSR_PREP(i)); 363 } 364 365 static unsigned int fxls8962af_read_full_scale(struct fxls8962af_data *data, 366 int *val) 367 { 368 int ret; 369 unsigned int reg; 370 u8 range_idx; 371 372 ret = regmap_read(data->regmap, FXLS8962AF_SENS_CONFIG1, ®); 373 if (ret) 374 return ret; 375 376 range_idx = FXLS8962AF_SC1_FSR_GET(reg); 377 378 *val = fxls8962af_scale_table[range_idx][1]; 379 380 return IIO_VAL_INT_PLUS_NANO; 381 } 382 383 static int fxls8962af_set_samp_freq(struct fxls8962af_data *data, u32 val, 384 u32 val2) 385 { 386 int i; 387 388 for (i = 0; i < ARRAY_SIZE(fxls8962af_samp_freq_table); i++) 389 if (val == fxls8962af_samp_freq_table[i][0] && 390 val2 == fxls8962af_samp_freq_table[i][1]) 391 break; 392 393 if (i == ARRAY_SIZE(fxls8962af_samp_freq_table)) 394 return -EINVAL; 395 396 return fxls8962af_update_config(data, FXLS8962AF_SENS_CONFIG3, 397 FXLS8962AF_SC3_WAKE_ODR_MASK, 398 FXLS8962AF_SC3_WAKE_ODR_PREP(i)); 399 } 400 401 static unsigned int fxls8962af_read_samp_freq(struct fxls8962af_data *data, 402 int *val, int *val2) 403 { 404 int ret; 405 unsigned int reg; 406 u8 range_idx; 407 408 ret = regmap_read(data->regmap, FXLS8962AF_SENS_CONFIG3, ®); 409 if (ret) 410 return ret; 411 412 range_idx = FXLS8962AF_SC3_WAKE_ODR_GET(reg); 413 414 *val = fxls8962af_samp_freq_table[range_idx][0]; 415 *val2 = fxls8962af_samp_freq_table[range_idx][1]; 416 417 return IIO_VAL_INT_PLUS_MICRO; 418 } 419 420 static int fxls8962af_read_raw(struct iio_dev *indio_dev, 421 struct iio_chan_spec const *chan, 422 int *val, int *val2, long mask) 423 { 424 struct fxls8962af_data *data = iio_priv(indio_dev); 425 426 switch (mask) { 427 case IIO_CHAN_INFO_RAW: 428 switch (chan->type) { 429 case IIO_TEMP: 430 case IIO_ACCEL: 431 return fxls8962af_get_out(data, chan, val); 432 default: 433 return -EINVAL; 434 } 435 case IIO_CHAN_INFO_OFFSET: 436 if (chan->type != IIO_TEMP) 437 return -EINVAL; 438 439 *val = FXLS8962AF_TEMP_CENTER_VAL; 440 return IIO_VAL_INT; 441 case IIO_CHAN_INFO_SCALE: 442 *val = 0; 443 return fxls8962af_read_full_scale(data, val2); 444 case IIO_CHAN_INFO_SAMP_FREQ: 445 return fxls8962af_read_samp_freq(data, val, val2); 446 default: 447 return -EINVAL; 448 } 449 } 450 451 static int fxls8962af_write_raw(struct iio_dev *indio_dev, 452 struct iio_chan_spec const *chan, 453 int val, int val2, long mask) 454 { 455 struct fxls8962af_data *data = iio_priv(indio_dev); 456 int ret; 457 458 switch (mask) { 459 case IIO_CHAN_INFO_SCALE: 460 if (val != 0) 461 return -EINVAL; 462 463 if (!iio_device_claim_direct(indio_dev)) 464 return -EBUSY; 465 466 ret = fxls8962af_set_full_scale(data, val2); 467 468 iio_device_release_direct(indio_dev); 469 return ret; 470 case IIO_CHAN_INFO_SAMP_FREQ: 471 if (!iio_device_claim_direct(indio_dev)) 472 return -EBUSY; 473 474 ret = fxls8962af_set_samp_freq(data, val, val2); 475 476 iio_device_release_direct(indio_dev); 477 return ret; 478 default: 479 return -EINVAL; 480 } 481 } 482 483 static int fxls8962af_event_setup(struct fxls8962af_data *data, int state) 484 { 485 /* Enable wakeup interrupt */ 486 int mask = FXLS8962AF_INT_EN_SDCD_OT_EN; 487 int value = state ? mask : 0; 488 489 return regmap_update_bits(data->regmap, FXLS8962AF_INT_EN, mask, value); 490 } 491 492 static int fxls8962af_set_watermark(struct iio_dev *indio_dev, unsigned val) 493 { 494 struct fxls8962af_data *data = iio_priv(indio_dev); 495 496 if (val > FXLS8962AF_FIFO_LENGTH) 497 val = FXLS8962AF_FIFO_LENGTH; 498 499 data->watermark = val; 500 501 return 0; 502 } 503 504 static int __fxls8962af_set_thresholds(struct fxls8962af_data *data, 505 const struct iio_chan_spec *chan, 506 enum iio_event_direction dir, 507 int val) 508 { 509 switch (dir) { 510 case IIO_EV_DIR_FALLING: 511 data->lower_thres = val; 512 return regmap_bulk_write(data->regmap, FXLS8962AF_SDCD_LTHS_LSB, 513 &data->lower_thres, sizeof(data->lower_thres)); 514 case IIO_EV_DIR_RISING: 515 data->upper_thres = val; 516 return regmap_bulk_write(data->regmap, FXLS8962AF_SDCD_UTHS_LSB, 517 &data->upper_thres, sizeof(data->upper_thres)); 518 default: 519 return -EINVAL; 520 } 521 } 522 523 static int fxls8962af_read_event(struct iio_dev *indio_dev, 524 const struct iio_chan_spec *chan, 525 enum iio_event_type type, 526 enum iio_event_direction dir, 527 enum iio_event_info info, 528 int *val, int *val2) 529 { 530 struct fxls8962af_data *data = iio_priv(indio_dev); 531 int ret; 532 533 if (type != IIO_EV_TYPE_THRESH) 534 return -EINVAL; 535 536 switch (dir) { 537 case IIO_EV_DIR_FALLING: 538 ret = regmap_bulk_read(data->regmap, FXLS8962AF_SDCD_LTHS_LSB, 539 &data->lower_thres, sizeof(data->lower_thres)); 540 if (ret) 541 return ret; 542 543 *val = sign_extend32(data->lower_thres, chan->scan_type.realbits - 1); 544 return IIO_VAL_INT; 545 case IIO_EV_DIR_RISING: 546 ret = regmap_bulk_read(data->regmap, FXLS8962AF_SDCD_UTHS_LSB, 547 &data->upper_thres, sizeof(data->upper_thres)); 548 if (ret) 549 return ret; 550 551 *val = sign_extend32(data->upper_thres, chan->scan_type.realbits - 1); 552 return IIO_VAL_INT; 553 default: 554 return -EINVAL; 555 } 556 } 557 558 static int fxls8962af_write_event(struct iio_dev *indio_dev, 559 const struct iio_chan_spec *chan, 560 enum iio_event_type type, 561 enum iio_event_direction dir, 562 enum iio_event_info info, 563 int val, int val2) 564 { 565 struct fxls8962af_data *data = iio_priv(indio_dev); 566 int ret, val_masked; 567 568 if (type != IIO_EV_TYPE_THRESH) 569 return -EINVAL; 570 571 if (val < -2048 || val > 2047) 572 return -EINVAL; 573 574 if (data->enable_event) 575 return -EBUSY; 576 577 val_masked = val & GENMASK(11, 0); 578 if (fxls8962af_is_active(data)) { 579 ret = fxls8962af_standby(data); 580 if (ret) 581 return ret; 582 583 ret = __fxls8962af_set_thresholds(data, chan, dir, val_masked); 584 if (ret) 585 return ret; 586 587 return fxls8962af_active(data); 588 } else { 589 return __fxls8962af_set_thresholds(data, chan, dir, val_masked); 590 } 591 } 592 593 static int 594 fxls8962af_read_event_config(struct iio_dev *indio_dev, 595 const struct iio_chan_spec *chan, 596 enum iio_event_type type, 597 enum iio_event_direction dir) 598 { 599 struct fxls8962af_data *data = iio_priv(indio_dev); 600 601 if (type != IIO_EV_TYPE_THRESH) 602 return -EINVAL; 603 604 switch (chan->channel2) { 605 case IIO_MOD_X: 606 return !!(FXLS8962AF_SDCD_CONFIG1_X_OT_EN & data->enable_event); 607 case IIO_MOD_Y: 608 return !!(FXLS8962AF_SDCD_CONFIG1_Y_OT_EN & data->enable_event); 609 case IIO_MOD_Z: 610 return !!(FXLS8962AF_SDCD_CONFIG1_Z_OT_EN & data->enable_event); 611 default: 612 return -EINVAL; 613 } 614 } 615 616 static int 617 fxls8962af_write_event_config(struct iio_dev *indio_dev, 618 const struct iio_chan_spec *chan, 619 enum iio_event_type type, 620 enum iio_event_direction dir, bool state) 621 { 622 struct fxls8962af_data *data = iio_priv(indio_dev); 623 u8 enable_event, enable_bits; 624 int ret, value; 625 626 if (type != IIO_EV_TYPE_THRESH) 627 return -EINVAL; 628 629 switch (chan->channel2) { 630 case IIO_MOD_X: 631 enable_bits = FXLS8962AF_SDCD_CONFIG1_X_OT_EN; 632 break; 633 case IIO_MOD_Y: 634 enable_bits = FXLS8962AF_SDCD_CONFIG1_Y_OT_EN; 635 break; 636 case IIO_MOD_Z: 637 enable_bits = FXLS8962AF_SDCD_CONFIG1_Z_OT_EN; 638 break; 639 default: 640 return -EINVAL; 641 } 642 643 if (state) 644 enable_event = data->enable_event | enable_bits; 645 else 646 enable_event = data->enable_event & ~enable_bits; 647 648 if (data->enable_event == enable_event) 649 return 0; 650 651 ret = fxls8962af_standby(data); 652 if (ret) 653 return ret; 654 655 /* Enable events */ 656 value = enable_event | FXLS8962AF_SDCD_CONFIG1_OT_ELE; 657 ret = regmap_write(data->regmap, FXLS8962AF_SDCD_CONFIG1, value); 658 if (ret) 659 return ret; 660 661 /* 662 * Enable update of SDCD_REF_X/Y/Z values with the current decimated and 663 * trimmed X/Y/Z acceleration input data. This allows for acceleration 664 * slope detection with Data(n) to Data(n–1) always used as the input 665 * to the window comparator. 666 */ 667 value = enable_event ? 668 FXLS8962AF_SDCD_CONFIG2_SDCD_EN | FXLS8962AF_SC2_REF_UPDM_AC : 669 0x00; 670 ret = regmap_write(data->regmap, FXLS8962AF_SDCD_CONFIG2, value); 671 if (ret) 672 return ret; 673 674 ret = fxls8962af_event_setup(data, state); 675 if (ret) 676 return ret; 677 678 data->enable_event = enable_event; 679 680 if (data->enable_event) { 681 fxls8962af_active(data); 682 ret = fxls8962af_power_on(data); 683 } else { 684 if (!iio_device_claim_direct(indio_dev)) 685 return -EBUSY; 686 687 /* Not in buffered mode so disable power */ 688 ret = fxls8962af_power_off(data); 689 690 iio_device_release_direct(indio_dev); 691 } 692 693 return ret; 694 } 695 696 static const struct iio_event_spec fxls8962af_event[] = { 697 { 698 .type = IIO_EV_TYPE_THRESH, 699 .dir = IIO_EV_DIR_EITHER, 700 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 701 }, 702 { 703 .type = IIO_EV_TYPE_THRESH, 704 .dir = IIO_EV_DIR_FALLING, 705 .mask_separate = BIT(IIO_EV_INFO_VALUE), 706 }, 707 { 708 .type = IIO_EV_TYPE_THRESH, 709 .dir = IIO_EV_DIR_RISING, 710 .mask_separate = BIT(IIO_EV_INFO_VALUE), 711 }, 712 }; 713 714 #define FXLS8962AF_CHANNEL(axis, reg, idx) { \ 715 .type = IIO_ACCEL, \ 716 .address = reg, \ 717 .modified = 1, \ 718 .channel2 = IIO_MOD_##axis, \ 719 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 720 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 721 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 722 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE) | \ 723 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 724 .scan_index = idx, \ 725 .scan_type = { \ 726 .sign = 's', \ 727 .realbits = 12, \ 728 .storagebits = 16, \ 729 .endianness = IIO_LE, \ 730 }, \ 731 .event_spec = fxls8962af_event, \ 732 .num_event_specs = ARRAY_SIZE(fxls8962af_event), \ 733 } 734 735 #define FXLS8962AF_TEMP_CHANNEL { \ 736 .type = IIO_TEMP, \ 737 .address = FXLS8962AF_TEMP_OUT, \ 738 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 739 BIT(IIO_CHAN_INFO_OFFSET),\ 740 .scan_index = -1, \ 741 .scan_type = { \ 742 .realbits = 8, \ 743 .storagebits = 8, \ 744 }, \ 745 } 746 747 static const struct iio_chan_spec fxls8962af_channels[] = { 748 FXLS8962AF_CHANNEL(X, FXLS8962AF_OUT_X_LSB, fxls8962af_idx_x), 749 FXLS8962AF_CHANNEL(Y, FXLS8962AF_OUT_Y_LSB, fxls8962af_idx_y), 750 FXLS8962AF_CHANNEL(Z, FXLS8962AF_OUT_Z_LSB, fxls8962af_idx_z), 751 IIO_CHAN_SOFT_TIMESTAMP(fxls8962af_idx_ts), 752 FXLS8962AF_TEMP_CHANNEL, 753 }; 754 755 static const struct fxls8962af_chip_info fxls_chip_info_table[] = { 756 [fxls8962af] = { 757 .chip_id = FXLS8962AF_DEVICE_ID, 758 .name = "fxls8962af", 759 .channels = fxls8962af_channels, 760 .num_channels = ARRAY_SIZE(fxls8962af_channels), 761 }, 762 [fxls8964af] = { 763 .chip_id = FXLS8964AF_DEVICE_ID, 764 .name = "fxls8964af", 765 .channels = fxls8962af_channels, 766 .num_channels = ARRAY_SIZE(fxls8962af_channels), 767 }, 768 [fxls8967af] = { 769 .chip_id = FXLS8967AF_DEVICE_ID, 770 .name = "fxls8967af", 771 .channels = fxls8962af_channels, 772 .num_channels = ARRAY_SIZE(fxls8962af_channels), 773 }, 774 [fxls8974cf] = { 775 .chip_id = FXLS8974CF_DEVICE_ID, 776 .name = "fxls8974cf", 777 .channels = fxls8962af_channels, 778 .num_channels = ARRAY_SIZE(fxls8962af_channels), 779 }, 780 }; 781 782 static const struct iio_info fxls8962af_info = { 783 .read_raw = &fxls8962af_read_raw, 784 .write_raw = &fxls8962af_write_raw, 785 .write_raw_get_fmt = fxls8962af_write_raw_get_fmt, 786 .read_event_value = fxls8962af_read_event, 787 .write_event_value = fxls8962af_write_event, 788 .read_event_config = fxls8962af_read_event_config, 789 .write_event_config = fxls8962af_write_event_config, 790 .read_avail = fxls8962af_read_avail, 791 .hwfifo_set_watermark = fxls8962af_set_watermark, 792 }; 793 794 static int fxls8962af_reset(struct fxls8962af_data *data) 795 { 796 struct device *dev = regmap_get_device(data->regmap); 797 unsigned int reg; 798 int ret; 799 800 ret = regmap_set_bits(data->regmap, FXLS8962AF_SENS_CONFIG1, 801 FXLS8962AF_SENS_CONFIG1_RST); 802 if (ret) 803 return ret; 804 805 /* TBOOT1, TBOOT2, specifies we have to wait between 1 - 17.7ms */ 806 ret = regmap_read_poll_timeout(data->regmap, FXLS8962AF_INT_STATUS, reg, 807 (reg & FXLS8962AF_INT_STATUS_SRC_BOOT), 808 1000, 18000); 809 if (ret == -ETIMEDOUT) 810 dev_err(dev, "reset timeout, int_status = 0x%x\n", reg); 811 812 return ret; 813 } 814 815 static int __fxls8962af_fifo_set_mode(struct fxls8962af_data *data, bool onoff) 816 { 817 int ret; 818 819 /* Enable watermark at max fifo size */ 820 ret = regmap_update_bits(data->regmap, FXLS8962AF_BUF_CONFIG2, 821 FXLS8962AF_BUF_CONFIG2_BUF_WMRK, 822 data->watermark); 823 if (ret) 824 return ret; 825 826 return regmap_update_bits(data->regmap, FXLS8962AF_BUF_CONFIG1, 827 FXLS8962AF_BC1_BUF_MODE_MASK, 828 FXLS8962AF_BC1_BUF_MODE_PREP(onoff)); 829 } 830 831 static int fxls8962af_buffer_preenable(struct iio_dev *indio_dev) 832 { 833 return fxls8962af_power_on(iio_priv(indio_dev)); 834 } 835 836 static int fxls8962af_buffer_postenable(struct iio_dev *indio_dev) 837 { 838 struct fxls8962af_data *data = iio_priv(indio_dev); 839 int ret; 840 841 fxls8962af_standby(data); 842 843 /* Enable buffer interrupt */ 844 ret = regmap_set_bits(data->regmap, FXLS8962AF_INT_EN, 845 FXLS8962AF_INT_EN_BUF_EN); 846 if (ret) 847 return ret; 848 849 ret = __fxls8962af_fifo_set_mode(data, true); 850 851 fxls8962af_active(data); 852 853 return ret; 854 } 855 856 static int fxls8962af_buffer_predisable(struct iio_dev *indio_dev) 857 { 858 struct fxls8962af_data *data = iio_priv(indio_dev); 859 int ret; 860 861 fxls8962af_standby(data); 862 863 /* Disable buffer interrupt */ 864 ret = regmap_clear_bits(data->regmap, FXLS8962AF_INT_EN, 865 FXLS8962AF_INT_EN_BUF_EN); 866 if (ret) 867 return ret; 868 869 ret = __fxls8962af_fifo_set_mode(data, false); 870 871 if (data->enable_event) 872 fxls8962af_active(data); 873 874 return ret; 875 } 876 877 static int fxls8962af_buffer_postdisable(struct iio_dev *indio_dev) 878 { 879 struct fxls8962af_data *data = iio_priv(indio_dev); 880 881 if (!data->enable_event) 882 fxls8962af_power_off(data); 883 884 return 0; 885 } 886 887 static const struct iio_buffer_setup_ops fxls8962af_buffer_ops = { 888 .preenable = fxls8962af_buffer_preenable, 889 .postenable = fxls8962af_buffer_postenable, 890 .predisable = fxls8962af_buffer_predisable, 891 .postdisable = fxls8962af_buffer_postdisable, 892 }; 893 894 static int fxls8962af_i2c_raw_read_errata3(struct fxls8962af_data *data, 895 u16 *buffer, int samples, 896 int sample_length) 897 { 898 int i, ret; 899 900 for (i = 0; i < samples; i++) { 901 ret = regmap_raw_read(data->regmap, FXLS8962AF_BUF_X_LSB, 902 &buffer[i * 3], sample_length); 903 if (ret) 904 return ret; 905 } 906 907 return 0; 908 } 909 910 static int fxls8962af_fifo_transfer(struct fxls8962af_data *data, 911 u16 *buffer, int samples) 912 { 913 struct device *dev = regmap_get_device(data->regmap); 914 int sample_length = 3 * sizeof(*buffer); 915 int total_length = samples * sample_length; 916 int ret; 917 918 if (i2c_verify_client(dev) && 919 data->chip_info->chip_id == FXLS8962AF_DEVICE_ID) 920 /* 921 * Due to errata bug (only applicable on fxls8962af): 922 * E3: FIFO burst read operation error using I2C interface 923 * We have to avoid burst reads on I2C.. 924 */ 925 ret = fxls8962af_i2c_raw_read_errata3(data, buffer, samples, 926 sample_length); 927 else 928 ret = regmap_raw_read(data->regmap, FXLS8962AF_BUF_X_LSB, buffer, 929 total_length); 930 931 if (ret) 932 dev_err(dev, "Error transferring data from fifo: %d\n", ret); 933 934 return ret; 935 } 936 937 static int fxls8962af_fifo_flush(struct iio_dev *indio_dev) 938 { 939 struct fxls8962af_data *data = iio_priv(indio_dev); 940 struct device *dev = regmap_get_device(data->regmap); 941 u16 buffer[FXLS8962AF_FIFO_LENGTH * 3]; 942 uint64_t sample_period; 943 unsigned int reg; 944 int64_t tstamp; 945 int ret, i; 946 u8 count; 947 948 ret = regmap_read(data->regmap, FXLS8962AF_BUF_STATUS, ®); 949 if (ret) 950 return ret; 951 952 if (reg & FXLS8962AF_BUF_STATUS_BUF_OVF) { 953 dev_err(dev, "Buffer overflow"); 954 return -EOVERFLOW; 955 } 956 957 count = reg & FXLS8962AF_BUF_STATUS_BUF_CNT; 958 if (!count) 959 return 0; 960 961 data->old_timestamp = data->timestamp; 962 data->timestamp = iio_get_time_ns(indio_dev); 963 964 /* 965 * Approximate timestamps for each of the sample based on the sampling, 966 * frequency, timestamp for last sample and number of samples. 967 */ 968 sample_period = (data->timestamp - data->old_timestamp); 969 do_div(sample_period, count); 970 tstamp = data->timestamp - (count - 1) * sample_period; 971 972 ret = fxls8962af_fifo_transfer(data, buffer, count); 973 if (ret) 974 return ret; 975 976 /* Demux hw FIFO into kfifo. */ 977 for (i = 0; i < count; i++) { 978 int j, bit; 979 980 j = 0; 981 iio_for_each_active_channel(indio_dev, bit) { 982 memcpy(&data->scan.channels[j++], &buffer[i * 3 + bit], 983 sizeof(data->scan.channels[0])); 984 } 985 986 iio_push_to_buffers_with_timestamp(indio_dev, &data->scan, 987 tstamp); 988 989 tstamp += sample_period; 990 } 991 992 return count; 993 } 994 995 static int fxls8962af_event_interrupt(struct iio_dev *indio_dev) 996 { 997 struct fxls8962af_data *data = iio_priv(indio_dev); 998 s64 ts = iio_get_time_ns(indio_dev); 999 unsigned int reg; 1000 u64 ev_code; 1001 int ret; 1002 1003 ret = regmap_read(data->regmap, FXLS8962AF_SDCD_INT_SRC1, ®); 1004 if (ret) 1005 return ret; 1006 1007 if (reg & FXLS8962AF_SDCD_INT_SRC1_X_OT) { 1008 ev_code = reg & FXLS8962AF_SDCD_INT_SRC1_X_POL ? 1009 IIO_EV_DIR_RISING : IIO_EV_DIR_FALLING; 1010 iio_push_event(indio_dev, 1011 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, 1012 IIO_EV_TYPE_THRESH, ev_code), ts); 1013 } 1014 1015 if (reg & FXLS8962AF_SDCD_INT_SRC1_Y_OT) { 1016 ev_code = reg & FXLS8962AF_SDCD_INT_SRC1_Y_POL ? 1017 IIO_EV_DIR_RISING : IIO_EV_DIR_FALLING; 1018 iio_push_event(indio_dev, 1019 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, 1020 IIO_EV_TYPE_THRESH, ev_code), ts); 1021 } 1022 1023 if (reg & FXLS8962AF_SDCD_INT_SRC1_Z_OT) { 1024 ev_code = reg & FXLS8962AF_SDCD_INT_SRC1_Z_POL ? 1025 IIO_EV_DIR_RISING : IIO_EV_DIR_FALLING; 1026 iio_push_event(indio_dev, 1027 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, 1028 IIO_EV_TYPE_THRESH, ev_code), ts); 1029 } 1030 1031 return 0; 1032 } 1033 1034 static irqreturn_t fxls8962af_interrupt(int irq, void *p) 1035 { 1036 struct iio_dev *indio_dev = p; 1037 struct fxls8962af_data *data = iio_priv(indio_dev); 1038 unsigned int reg; 1039 int ret; 1040 1041 ret = regmap_read(data->regmap, FXLS8962AF_INT_STATUS, ®); 1042 if (ret) 1043 return IRQ_NONE; 1044 1045 if (reg & FXLS8962AF_INT_STATUS_SRC_BUF) { 1046 ret = fxls8962af_fifo_flush(indio_dev); 1047 if (ret < 0) 1048 return IRQ_NONE; 1049 1050 return IRQ_HANDLED; 1051 } 1052 1053 if (reg & FXLS8962AF_INT_STATUS_SRC_SDCD_OT) { 1054 ret = fxls8962af_event_interrupt(indio_dev); 1055 if (ret < 0) 1056 return IRQ_NONE; 1057 1058 return IRQ_HANDLED; 1059 } 1060 1061 return IRQ_NONE; 1062 } 1063 1064 static void fxls8962af_pm_disable(void *dev_ptr) 1065 { 1066 struct device *dev = dev_ptr; 1067 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1068 1069 pm_runtime_disable(dev); 1070 pm_runtime_set_suspended(dev); 1071 pm_runtime_put_noidle(dev); 1072 1073 fxls8962af_standby(iio_priv(indio_dev)); 1074 } 1075 1076 static void fxls8962af_get_irq(struct device *dev, 1077 enum fxls8962af_int_pin *pin) 1078 { 1079 int irq; 1080 1081 irq = fwnode_irq_get_byname(dev_fwnode(dev), "INT2"); 1082 if (irq > 0) { 1083 *pin = FXLS8962AF_PIN_INT2; 1084 return; 1085 } 1086 1087 *pin = FXLS8962AF_PIN_INT1; 1088 } 1089 1090 static int fxls8962af_irq_setup(struct iio_dev *indio_dev, int irq) 1091 { 1092 struct fxls8962af_data *data = iio_priv(indio_dev); 1093 struct device *dev = regmap_get_device(data->regmap); 1094 unsigned long irq_type; 1095 bool irq_active_high; 1096 enum fxls8962af_int_pin int_pin; 1097 u8 int_pin_sel; 1098 int ret; 1099 1100 fxls8962af_get_irq(dev, &int_pin); 1101 switch (int_pin) { 1102 case FXLS8962AF_PIN_INT1: 1103 int_pin_sel = FXLS8962AF_INT_PIN_SEL_INT1; 1104 break; 1105 case FXLS8962AF_PIN_INT2: 1106 int_pin_sel = FXLS8962AF_INT_PIN_SEL_INT2; 1107 break; 1108 default: 1109 dev_err(dev, "unsupported int pin selected\n"); 1110 return -EINVAL; 1111 } 1112 1113 ret = regmap_update_bits(data->regmap, FXLS8962AF_INT_PIN_SEL, 1114 FXLS8962AF_INT_PIN_SEL_MASK, int_pin_sel); 1115 if (ret) 1116 return ret; 1117 1118 irq_type = irq_get_trigger_type(irq); 1119 switch (irq_type) { 1120 case IRQF_TRIGGER_HIGH: 1121 case IRQF_TRIGGER_RISING: 1122 irq_active_high = true; 1123 break; 1124 case IRQF_TRIGGER_LOW: 1125 case IRQF_TRIGGER_FALLING: 1126 irq_active_high = false; 1127 break; 1128 default: 1129 dev_info(dev, "mode %lx unsupported\n", irq_type); 1130 return -EINVAL; 1131 } 1132 1133 ret = regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG4, 1134 FXLS8962AF_SC4_INT_POL_MASK, 1135 FXLS8962AF_SC4_INT_POL_PREP(irq_active_high)); 1136 if (ret) 1137 return ret; 1138 1139 if (device_property_read_bool(dev, "drive-open-drain")) { 1140 ret = regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG4, 1141 FXLS8962AF_SC4_INT_PP_OD_MASK, 1142 FXLS8962AF_SC4_INT_PP_OD_PREP(1)); 1143 if (ret) 1144 return ret; 1145 1146 irq_type |= IRQF_SHARED; 1147 } 1148 1149 return devm_request_threaded_irq(dev, 1150 irq, 1151 NULL, fxls8962af_interrupt, 1152 irq_type | IRQF_ONESHOT, 1153 indio_dev->name, indio_dev); 1154 } 1155 1156 int fxls8962af_core_probe(struct device *dev, struct regmap *regmap, int irq) 1157 { 1158 struct fxls8962af_data *data; 1159 struct iio_dev *indio_dev; 1160 unsigned int reg; 1161 int ret, i; 1162 1163 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 1164 if (!indio_dev) 1165 return -ENOMEM; 1166 1167 data = iio_priv(indio_dev); 1168 dev_set_drvdata(dev, indio_dev); 1169 data->regmap = regmap; 1170 data->irq = irq; 1171 1172 ret = iio_read_mount_matrix(dev, &data->orientation); 1173 if (ret) 1174 return ret; 1175 1176 ret = devm_regulator_get_enable(dev, "vdd"); 1177 if (ret) 1178 return dev_err_probe(dev, ret, 1179 "Failed to get vdd regulator\n"); 1180 1181 ret = regmap_read(data->regmap, FXLS8962AF_WHO_AM_I, ®); 1182 if (ret) 1183 return ret; 1184 1185 for (i = 0; i < ARRAY_SIZE(fxls_chip_info_table); i++) { 1186 if (fxls_chip_info_table[i].chip_id == reg) { 1187 data->chip_info = &fxls_chip_info_table[i]; 1188 break; 1189 } 1190 } 1191 if (i == ARRAY_SIZE(fxls_chip_info_table)) { 1192 dev_err(dev, "failed to match device in table\n"); 1193 return -ENXIO; 1194 } 1195 1196 indio_dev->channels = data->chip_info->channels; 1197 indio_dev->num_channels = data->chip_info->num_channels; 1198 indio_dev->name = data->chip_info->name; 1199 indio_dev->info = &fxls8962af_info; 1200 indio_dev->modes = INDIO_DIRECT_MODE; 1201 1202 ret = fxls8962af_reset(data); 1203 if (ret) 1204 return ret; 1205 1206 if (irq) { 1207 ret = fxls8962af_irq_setup(indio_dev, irq); 1208 if (ret) 1209 return ret; 1210 1211 ret = devm_iio_kfifo_buffer_setup(dev, indio_dev, 1212 &fxls8962af_buffer_ops); 1213 if (ret) 1214 return ret; 1215 } 1216 1217 ret = pm_runtime_set_active(dev); 1218 if (ret) 1219 return ret; 1220 1221 pm_runtime_enable(dev); 1222 pm_runtime_set_autosuspend_delay(dev, FXLS8962AF_AUTO_SUSPEND_DELAY_MS); 1223 pm_runtime_use_autosuspend(dev); 1224 1225 ret = devm_add_action_or_reset(dev, fxls8962af_pm_disable, dev); 1226 if (ret) 1227 return ret; 1228 1229 if (device_property_read_bool(dev, "wakeup-source")) 1230 device_init_wakeup(dev, true); 1231 1232 return devm_iio_device_register(dev, indio_dev); 1233 } 1234 EXPORT_SYMBOL_NS_GPL(fxls8962af_core_probe, "IIO_FXLS8962AF"); 1235 1236 static int fxls8962af_runtime_suspend(struct device *dev) 1237 { 1238 struct fxls8962af_data *data = iio_priv(dev_get_drvdata(dev)); 1239 int ret; 1240 1241 ret = fxls8962af_standby(data); 1242 if (ret) { 1243 dev_err(dev, "powering off device failed\n"); 1244 return ret; 1245 } 1246 1247 return 0; 1248 } 1249 1250 static int fxls8962af_runtime_resume(struct device *dev) 1251 { 1252 struct fxls8962af_data *data = iio_priv(dev_get_drvdata(dev)); 1253 1254 return fxls8962af_active(data); 1255 } 1256 1257 static int fxls8962af_suspend(struct device *dev) 1258 { 1259 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1260 struct fxls8962af_data *data = iio_priv(indio_dev); 1261 1262 if (device_may_wakeup(dev) && data->enable_event) { 1263 enable_irq_wake(data->irq); 1264 1265 /* 1266 * Disable buffer, as the buffer is so small the device will wake 1267 * almost immediately. 1268 */ 1269 if (iio_buffer_enabled(indio_dev)) 1270 fxls8962af_buffer_predisable(indio_dev); 1271 } else { 1272 fxls8962af_runtime_suspend(dev); 1273 } 1274 1275 return 0; 1276 } 1277 1278 static int fxls8962af_resume(struct device *dev) 1279 { 1280 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1281 struct fxls8962af_data *data = iio_priv(indio_dev); 1282 1283 if (device_may_wakeup(dev) && data->enable_event) { 1284 disable_irq_wake(data->irq); 1285 1286 if (iio_buffer_enabled(indio_dev)) 1287 fxls8962af_buffer_postenable(indio_dev); 1288 } else { 1289 fxls8962af_runtime_resume(dev); 1290 } 1291 1292 return 0; 1293 } 1294 1295 EXPORT_NS_GPL_DEV_PM_OPS(fxls8962af_pm_ops, IIO_FXLS8962AF) = { 1296 SYSTEM_SLEEP_PM_OPS(fxls8962af_suspend, fxls8962af_resume) 1297 RUNTIME_PM_OPS(fxls8962af_runtime_suspend, fxls8962af_runtime_resume, NULL) 1298 }; 1299 1300 MODULE_AUTHOR("Sean Nyekjaer <sean@geanix.com>"); 1301 MODULE_DESCRIPTION("NXP FXLS8962AF/FXLS8964AF accelerometer driver"); 1302 MODULE_LICENSE("GPL v2"); 1303