1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RIIC driver 4 * 5 * Copyright (C) 2013 Wolfram Sang <wsa@sang-engineering.com> 6 * Copyright (C) 2013 Renesas Solutions Corp. 7 */ 8 9 /* 10 * This i2c core has a lot of interrupts, namely 8. We use their chaining as 11 * some kind of state machine. 12 * 13 * 1) The main xfer routine kicks off a transmission by putting the start bit 14 * (or repeated start) on the bus and enabling the transmit interrupt (TIE) 15 * since we need to send the target address + RW bit in every case. 16 * 17 * 2) TIE sends target address + RW bit and selects how to continue. 18 * 19 * 3a) Write case: We keep utilizing TIE as long as we have data to send. If we 20 * are done, we switch over to the transmission done interrupt (TEIE) and mark 21 * the message as completed (includes sending STOP) there. 22 * 23 * 3b) Read case: We switch over to receive interrupt (RIE). One dummy read is 24 * needed to start clocking, then we keep receiving until we are done. Note 25 * that we use the RDRFS mode all the time, i.e. we ACK/NACK every byte by 26 * writing to the ACKBT bit. I tried using the RDRFS mode only at the end of a 27 * message to create the final NACK as sketched in the datasheet. This caused 28 * some subtle races (when byte n was processed and byte n+1 was already 29 * waiting), though, and I started with the safe approach. 30 * 31 * 4) If we got a NACK somewhere, we flag the error and stop the transmission 32 * via NAKIE. 33 * 34 * Also check the comments in the interrupt routines for some gory details. 35 */ 36 37 #include <linux/bits.h> 38 #include <linux/clk.h> 39 #include <linux/completion.h> 40 #include <linux/err.h> 41 #include <linux/i2c.h> 42 #include <linux/interrupt.h> 43 #include <linux/io.h> 44 #include <linux/iopoll.h> 45 #include <linux/module.h> 46 #include <linux/of.h> 47 #include <linux/platform_device.h> 48 #include <linux/pm_runtime.h> 49 #include <linux/reset.h> 50 #include <linux/time.h> 51 52 #define ICCR1_ICE BIT(7) 53 #define ICCR1_IICRST BIT(6) 54 #define ICCR1_SOWP BIT(4) 55 #define ICCR1_SCLO BIT(3) 56 #define ICCR1_SDAO BIT(2) 57 #define ICCR1_SCLI BIT(1) 58 #define ICCR1_SDAI BIT(0) 59 60 #define ICCR2_BBSY BIT(7) 61 #define ICCR2_SP BIT(3) 62 #define ICCR2_RS BIT(2) 63 #define ICCR2_ST BIT(1) 64 65 #define ICMR1_CKS_MASK GENMASK(6, 4) 66 #define ICMR1_BCWP BIT(3) 67 #define ICMR1_CKS(_x) ((((_x) << 4) & ICMR1_CKS_MASK) | ICMR1_BCWP) 68 69 #define ICMR3_RDRFS BIT(5) 70 #define ICMR3_ACKWP BIT(4) 71 #define ICMR3_ACKBT BIT(3) 72 73 #define ICFER_FMPE BIT(7) 74 75 #define ICIER_TIE BIT(7) 76 #define ICIER_TEIE BIT(6) 77 #define ICIER_RIE BIT(5) 78 #define ICIER_NAKIE BIT(4) 79 #define ICIER_SPIE BIT(3) 80 81 #define ICSR2_NACKF BIT(4) 82 83 #define ICBR_RESERVED GENMASK(7, 5) /* Should be 1 on writes */ 84 85 #define RIIC_INIT_MSG -1 86 87 enum riic_reg_list { 88 RIIC_ICCR1 = 0, 89 RIIC_ICCR2, 90 RIIC_ICMR1, 91 RIIC_ICMR3, 92 RIIC_ICFER, 93 RIIC_ICSER, 94 RIIC_ICIER, 95 RIIC_ICSR2, 96 RIIC_ICBRL, 97 RIIC_ICBRH, 98 RIIC_ICDRT, 99 RIIC_ICDRR, 100 RIIC_REG_END, 101 }; 102 103 struct riic_of_data { 104 const u8 *regs; 105 bool fast_mode_plus; 106 }; 107 108 struct riic_dev { 109 void __iomem *base; 110 u8 *buf; 111 struct i2c_msg *msg; 112 int bytes_left; 113 int err; 114 int is_last; 115 const struct riic_of_data *info; 116 struct completion msg_done; 117 struct i2c_adapter adapter; 118 struct clk *clk; 119 struct reset_control *rstc; 120 struct i2c_timings i2c_t; 121 }; 122 123 struct riic_irq_desc { 124 int res_num; 125 irq_handler_t isr; 126 char *name; 127 }; 128 129 static inline void riic_writeb(struct riic_dev *riic, u8 val, u8 offset) 130 { 131 writeb(val, riic->base + riic->info->regs[offset]); 132 } 133 134 static inline u8 riic_readb(struct riic_dev *riic, u8 offset) 135 { 136 return readb(riic->base + riic->info->regs[offset]); 137 } 138 139 static inline void riic_clear_set_bit(struct riic_dev *riic, u8 clear, u8 set, u8 reg) 140 { 141 riic_writeb(riic, (riic_readb(riic, reg) & ~clear) | set, reg); 142 } 143 144 static int riic_bus_barrier(struct riic_dev *riic) 145 { 146 int ret; 147 u8 val; 148 149 /* 150 * The SDA line can still be low even when BBSY = 0. Therefore, after checking 151 * the BBSY flag, also verify that the SDA and SCL lines are not being held low. 152 */ 153 ret = readb_poll_timeout(riic->base + riic->info->regs[RIIC_ICCR2], val, 154 !(val & ICCR2_BBSY), 10, riic->adapter.timeout); 155 if (ret) 156 return i2c_recover_bus(&riic->adapter); 157 158 if ((riic_readb(riic, RIIC_ICCR1) & (ICCR1_SDAI | ICCR1_SCLI)) != 159 (ICCR1_SDAI | ICCR1_SCLI)) 160 return i2c_recover_bus(&riic->adapter); 161 162 return 0; 163 } 164 165 static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 166 { 167 struct riic_dev *riic = i2c_get_adapdata(adap); 168 struct device *dev = adap->dev.parent; 169 unsigned long time_left; 170 int i, ret; 171 u8 start_bit; 172 173 ret = pm_runtime_resume_and_get(dev); 174 if (ret) 175 return ret; 176 177 riic->err = riic_bus_barrier(riic); 178 if (riic->err) 179 goto out; 180 181 reinit_completion(&riic->msg_done); 182 183 riic_writeb(riic, 0, RIIC_ICSR2); 184 185 for (i = 0, start_bit = ICCR2_ST; i < num; i++) { 186 riic->bytes_left = RIIC_INIT_MSG; 187 riic->buf = msgs[i].buf; 188 riic->msg = &msgs[i]; 189 riic->is_last = (i == num - 1); 190 191 riic_writeb(riic, ICIER_NAKIE | ICIER_TIE, RIIC_ICIER); 192 193 riic_writeb(riic, start_bit, RIIC_ICCR2); 194 195 time_left = wait_for_completion_timeout(&riic->msg_done, riic->adapter.timeout); 196 if (time_left == 0) 197 riic->err = -ETIMEDOUT; 198 199 if (riic->err) 200 break; 201 202 start_bit = ICCR2_RS; 203 } 204 205 out: 206 pm_runtime_mark_last_busy(dev); 207 pm_runtime_put_autosuspend(dev); 208 209 return riic->err ?: num; 210 } 211 212 static irqreturn_t riic_tdre_isr(int irq, void *data) 213 { 214 struct riic_dev *riic = data; 215 u8 val; 216 217 if (!riic->bytes_left) 218 return IRQ_NONE; 219 220 if (riic->bytes_left == RIIC_INIT_MSG) { 221 if (riic->msg->flags & I2C_M_RD) 222 /* On read, switch over to receive interrupt */ 223 riic_clear_set_bit(riic, ICIER_TIE, ICIER_RIE, RIIC_ICIER); 224 else 225 /* On write, initialize length */ 226 riic->bytes_left = riic->msg->len; 227 228 val = i2c_8bit_addr_from_msg(riic->msg); 229 } else { 230 val = *riic->buf; 231 riic->buf++; 232 riic->bytes_left--; 233 } 234 235 /* 236 * Switch to transmission ended interrupt when done. Do check here 237 * after bytes_left was initialized to support SMBUS_QUICK (new msg has 238 * 0 length then) 239 */ 240 if (riic->bytes_left == 0) 241 riic_clear_set_bit(riic, ICIER_TIE, ICIER_TEIE, RIIC_ICIER); 242 243 /* 244 * This acks the TIE interrupt. We get another TIE immediately if our 245 * value could be moved to the shadow shift register right away. So 246 * this must be after updates to ICIER (where we want to disable TIE)! 247 */ 248 riic_writeb(riic, val, RIIC_ICDRT); 249 250 return IRQ_HANDLED; 251 } 252 253 static irqreturn_t riic_tend_isr(int irq, void *data) 254 { 255 struct riic_dev *riic = data; 256 257 if (riic_readb(riic, RIIC_ICSR2) & ICSR2_NACKF) { 258 /* We got a NACKIE */ 259 riic_readb(riic, RIIC_ICDRR); /* dummy read */ 260 riic_clear_set_bit(riic, ICSR2_NACKF, 0, RIIC_ICSR2); 261 riic->err = -ENXIO; 262 } else if (riic->bytes_left) { 263 return IRQ_NONE; 264 } 265 266 if (riic->is_last || riic->err) { 267 riic_clear_set_bit(riic, ICIER_TEIE, ICIER_SPIE, RIIC_ICIER); 268 riic_writeb(riic, ICCR2_SP, RIIC_ICCR2); 269 } else { 270 /* Transfer is complete, but do not send STOP */ 271 riic_clear_set_bit(riic, ICIER_TEIE, 0, RIIC_ICIER); 272 complete(&riic->msg_done); 273 } 274 275 return IRQ_HANDLED; 276 } 277 278 static irqreturn_t riic_rdrf_isr(int irq, void *data) 279 { 280 struct riic_dev *riic = data; 281 282 if (!riic->bytes_left) 283 return IRQ_NONE; 284 285 if (riic->bytes_left == RIIC_INIT_MSG) { 286 riic->bytes_left = riic->msg->len; 287 riic_readb(riic, RIIC_ICDRR); /* dummy read */ 288 return IRQ_HANDLED; 289 } 290 291 if (riic->bytes_left == 1) { 292 /* STOP must come before we set ACKBT! */ 293 if (riic->is_last) { 294 riic_clear_set_bit(riic, 0, ICIER_SPIE, RIIC_ICIER); 295 riic_writeb(riic, ICCR2_SP, RIIC_ICCR2); 296 } 297 298 riic_clear_set_bit(riic, 0, ICMR3_ACKBT, RIIC_ICMR3); 299 300 } else { 301 riic_clear_set_bit(riic, ICMR3_ACKBT, 0, RIIC_ICMR3); 302 } 303 304 /* Reading acks the RIE interrupt */ 305 *riic->buf = riic_readb(riic, RIIC_ICDRR); 306 riic->buf++; 307 riic->bytes_left--; 308 309 return IRQ_HANDLED; 310 } 311 312 static irqreturn_t riic_stop_isr(int irq, void *data) 313 { 314 struct riic_dev *riic = data; 315 316 /* read back registers to confirm writes have fully propagated */ 317 riic_writeb(riic, 0, RIIC_ICSR2); 318 riic_readb(riic, RIIC_ICSR2); 319 riic_writeb(riic, 0, RIIC_ICIER); 320 riic_readb(riic, RIIC_ICIER); 321 322 complete(&riic->msg_done); 323 324 return IRQ_HANDLED; 325 } 326 327 static u32 riic_func(struct i2c_adapter *adap) 328 { 329 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 330 } 331 332 static const struct i2c_algorithm riic_algo = { 333 .xfer = riic_xfer, 334 .functionality = riic_func, 335 }; 336 337 static int riic_init_hw(struct riic_dev *riic) 338 { 339 int ret; 340 unsigned long rate; 341 unsigned long ns_per_tick; 342 int total_ticks, cks, brl, brh; 343 struct i2c_timings *t = &riic->i2c_t; 344 struct device *dev = riic->adapter.dev.parent; 345 bool fast_mode_plus = riic->info->fast_mode_plus; 346 u32 max_freq = fast_mode_plus ? I2C_MAX_FAST_MODE_PLUS_FREQ 347 : I2C_MAX_FAST_MODE_FREQ; 348 349 if (t->bus_freq_hz > max_freq) 350 return dev_err_probe(dev, -EINVAL, 351 "unsupported bus speed %uHz (%u max)\n", 352 t->bus_freq_hz, max_freq); 353 354 rate = clk_get_rate(riic->clk); 355 356 /* 357 * Assume the default register settings: 358 * FER.SCLE = 1 (SCL sync circuit enabled, adds 2 or 3 cycles) 359 * FER.NFE = 1 (noise circuit enabled) 360 * MR3.NF = 0 (1 cycle of noise filtered out) 361 * 362 * Freq (CKS=000) = (I2CCLK + tr + tf)/ (BRH + 3 + 1) + (BRL + 3 + 1) 363 * Freq (CKS!=000) = (I2CCLK + tr + tf)/ (BRH + 2 + 1) + (BRL + 2 + 1) 364 */ 365 366 /* 367 * Determine reference clock rate. We must be able to get the desired 368 * frequency with only 62 clock ticks max (31 high, 31 low). 369 * Aim for a duty of 60% LOW, 40% HIGH. 370 */ 371 total_ticks = DIV_ROUND_UP(rate, t->bus_freq_hz ?: 1); 372 373 for (cks = 0; cks < 7; cks++) { 374 /* 375 * 60% low time must be less than BRL + 2 + 1 376 * BRL max register value is 0x1F. 377 */ 378 brl = ((total_ticks * 6) / 10); 379 if (brl <= (0x1F + 3)) 380 break; 381 382 total_ticks = DIV_ROUND_UP(total_ticks, 2); 383 rate /= 2; 384 } 385 386 if (brl > (0x1F + 3)) 387 return dev_err_probe(dev, -EINVAL, "invalid speed (%uHz). Too slow.\n", 388 t->bus_freq_hz); 389 390 brh = total_ticks - brl; 391 392 /* Remove automatic clock ticks for sync circuit and NF */ 393 if (cks == 0) { 394 brl -= 4; 395 brh -= 4; 396 } else { 397 brl -= 3; 398 brh -= 3; 399 } 400 401 /* 402 * Remove clock ticks for rise and fall times. Convert ns to clock 403 * ticks. 404 */ 405 ns_per_tick = NSEC_PER_SEC / rate; 406 brl -= t->scl_fall_ns / ns_per_tick; 407 brh -= t->scl_rise_ns / ns_per_tick; 408 409 /* Adjust for min register values for when SCLE=1 and NFE=1 */ 410 if (brl < 1) 411 brl = 1; 412 if (brh < 1) 413 brh = 1; 414 415 pr_debug("i2c-riic: freq=%lu, duty=%d, fall=%lu, rise=%lu, cks=%d, brl=%d, brh=%d\n", 416 rate / total_ticks, ((brl + 3) * 100) / (brl + brh + 6), 417 t->scl_fall_ns / ns_per_tick, t->scl_rise_ns / ns_per_tick, cks, brl, brh); 418 419 ret = pm_runtime_resume_and_get(dev); 420 if (ret) 421 return ret; 422 423 /* Changing the order of accessing IICRST and ICE may break things! */ 424 riic_writeb(riic, ICCR1_IICRST | ICCR1_SOWP, RIIC_ICCR1); 425 riic_clear_set_bit(riic, 0, ICCR1_ICE, RIIC_ICCR1); 426 427 riic_writeb(riic, ICMR1_CKS(cks), RIIC_ICMR1); 428 riic_writeb(riic, brh | ICBR_RESERVED, RIIC_ICBRH); 429 riic_writeb(riic, brl | ICBR_RESERVED, RIIC_ICBRL); 430 431 riic_writeb(riic, 0, RIIC_ICSER); 432 riic_writeb(riic, ICMR3_ACKWP | ICMR3_RDRFS, RIIC_ICMR3); 433 434 if (fast_mode_plus && t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) 435 riic_clear_set_bit(riic, 0, ICFER_FMPE, RIIC_ICFER); 436 437 riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1); 438 439 pm_runtime_mark_last_busy(dev); 440 pm_runtime_put_autosuspend(dev); 441 return 0; 442 } 443 444 static int riic_get_scl(struct i2c_adapter *adap) 445 { 446 struct riic_dev *riic = i2c_get_adapdata(adap); 447 448 return !!(riic_readb(riic, RIIC_ICCR1) & ICCR1_SCLI); 449 } 450 451 static int riic_get_sda(struct i2c_adapter *adap) 452 { 453 struct riic_dev *riic = i2c_get_adapdata(adap); 454 455 return !!(riic_readb(riic, RIIC_ICCR1) & ICCR1_SDAI); 456 } 457 458 static void riic_set_scl(struct i2c_adapter *adap, int val) 459 { 460 struct riic_dev *riic = i2c_get_adapdata(adap); 461 462 if (val) 463 riic_clear_set_bit(riic, ICCR1_SOWP, ICCR1_SCLO, RIIC_ICCR1); 464 else 465 riic_clear_set_bit(riic, ICCR1_SOWP | ICCR1_SCLO, 0, RIIC_ICCR1); 466 467 riic_clear_set_bit(riic, 0, ICCR1_SOWP, RIIC_ICCR1); 468 } 469 470 static void riic_set_sda(struct i2c_adapter *adap, int val) 471 { 472 struct riic_dev *riic = i2c_get_adapdata(adap); 473 474 if (val) 475 riic_clear_set_bit(riic, ICCR1_SOWP, ICCR1_SDAO, RIIC_ICCR1); 476 else 477 riic_clear_set_bit(riic, ICCR1_SOWP | ICCR1_SDAO, 0, RIIC_ICCR1); 478 479 riic_clear_set_bit(riic, 0, ICCR1_SOWP, RIIC_ICCR1); 480 } 481 482 static struct i2c_bus_recovery_info riic_bri = { 483 .recover_bus = i2c_generic_scl_recovery, 484 .get_scl = riic_get_scl, 485 .set_scl = riic_set_scl, 486 .get_sda = riic_get_sda, 487 .set_sda = riic_set_sda, 488 }; 489 490 static const struct riic_irq_desc riic_irqs[] = { 491 { .res_num = 0, .isr = riic_tend_isr, .name = "riic-tend" }, 492 { .res_num = 1, .isr = riic_rdrf_isr, .name = "riic-rdrf" }, 493 { .res_num = 2, .isr = riic_tdre_isr, .name = "riic-tdre" }, 494 { .res_num = 3, .isr = riic_stop_isr, .name = "riic-stop" }, 495 { .res_num = 5, .isr = riic_tend_isr, .name = "riic-nack" }, 496 }; 497 498 static int riic_i2c_probe(struct platform_device *pdev) 499 { 500 struct device *dev = &pdev->dev; 501 struct riic_dev *riic; 502 struct i2c_adapter *adap; 503 int i, ret; 504 505 riic = devm_kzalloc(dev, sizeof(*riic), GFP_KERNEL); 506 if (!riic) 507 return -ENOMEM; 508 509 riic->base = devm_platform_ioremap_resource(pdev, 0); 510 if (IS_ERR(riic->base)) 511 return PTR_ERR(riic->base); 512 513 riic->clk = devm_clk_get(dev, NULL); 514 if (IS_ERR(riic->clk)) 515 return dev_err_probe(dev, PTR_ERR(riic->clk), 516 "missing controller clock"); 517 518 riic->rstc = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL); 519 if (IS_ERR(riic->rstc)) 520 return dev_err_probe(dev, PTR_ERR(riic->rstc), 521 "failed to acquire deasserted reset\n"); 522 523 for (i = 0; i < ARRAY_SIZE(riic_irqs); i++) { 524 int irq; 525 526 irq = platform_get_irq(pdev, riic_irqs[i].res_num); 527 if (irq < 0) 528 return irq; 529 530 ret = devm_request_irq(dev, irq, riic_irqs[i].isr, 531 0, riic_irqs[i].name, riic); 532 if (ret) 533 return dev_err_probe(dev, ret, "failed to request irq %s\n", 534 riic_irqs[i].name); 535 } 536 537 riic->info = of_device_get_match_data(dev); 538 539 adap = &riic->adapter; 540 i2c_set_adapdata(adap, riic); 541 strscpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name)); 542 adap->owner = THIS_MODULE; 543 adap->algo = &riic_algo; 544 adap->dev.parent = dev; 545 adap->dev.of_node = dev->of_node; 546 adap->bus_recovery_info = &riic_bri; 547 548 init_completion(&riic->msg_done); 549 550 i2c_parse_fw_timings(dev, &riic->i2c_t, true); 551 552 /* Default 0 to save power. Can be overridden via sysfs for lower latency. */ 553 pm_runtime_set_autosuspend_delay(dev, 0); 554 pm_runtime_use_autosuspend(dev); 555 pm_runtime_enable(dev); 556 557 ret = riic_init_hw(riic); 558 if (ret) 559 goto out; 560 561 ret = i2c_add_adapter(adap); 562 if (ret) 563 goto out; 564 565 platform_set_drvdata(pdev, riic); 566 567 dev_info(dev, "registered with %dHz bus speed\n", riic->i2c_t.bus_freq_hz); 568 return 0; 569 570 out: 571 pm_runtime_disable(dev); 572 pm_runtime_dont_use_autosuspend(dev); 573 return ret; 574 } 575 576 static void riic_i2c_remove(struct platform_device *pdev) 577 { 578 struct riic_dev *riic = platform_get_drvdata(pdev); 579 struct device *dev = &pdev->dev; 580 int ret; 581 582 ret = pm_runtime_resume_and_get(dev); 583 if (!ret) { 584 riic_writeb(riic, 0, RIIC_ICIER); 585 pm_runtime_put(dev); 586 } 587 i2c_del_adapter(&riic->adapter); 588 pm_runtime_disable(dev); 589 pm_runtime_dont_use_autosuspend(dev); 590 } 591 592 static const u8 riic_rz_a_regs[RIIC_REG_END] = { 593 [RIIC_ICCR1] = 0x00, 594 [RIIC_ICCR2] = 0x04, 595 [RIIC_ICMR1] = 0x08, 596 [RIIC_ICMR3] = 0x10, 597 [RIIC_ICFER] = 0x14, 598 [RIIC_ICSER] = 0x18, 599 [RIIC_ICIER] = 0x1c, 600 [RIIC_ICSR2] = 0x24, 601 [RIIC_ICBRL] = 0x34, 602 [RIIC_ICBRH] = 0x38, 603 [RIIC_ICDRT] = 0x3c, 604 [RIIC_ICDRR] = 0x40, 605 }; 606 607 static const struct riic_of_data riic_rz_a_info = { 608 .regs = riic_rz_a_regs, 609 .fast_mode_plus = true, 610 }; 611 612 static const struct riic_of_data riic_rz_a1h_info = { 613 .regs = riic_rz_a_regs, 614 }; 615 616 static const u8 riic_rz_v2h_regs[RIIC_REG_END] = { 617 [RIIC_ICCR1] = 0x00, 618 [RIIC_ICCR2] = 0x01, 619 [RIIC_ICMR1] = 0x02, 620 [RIIC_ICMR3] = 0x04, 621 [RIIC_ICFER] = 0x05, 622 [RIIC_ICSER] = 0x06, 623 [RIIC_ICIER] = 0x07, 624 [RIIC_ICSR2] = 0x09, 625 [RIIC_ICBRL] = 0x10, 626 [RIIC_ICBRH] = 0x11, 627 [RIIC_ICDRT] = 0x12, 628 [RIIC_ICDRR] = 0x13, 629 }; 630 631 static const struct riic_of_data riic_rz_v2h_info = { 632 .regs = riic_rz_v2h_regs, 633 .fast_mode_plus = true, 634 }; 635 636 static int riic_i2c_suspend(struct device *dev) 637 { 638 struct riic_dev *riic = dev_get_drvdata(dev); 639 int ret; 640 641 ret = pm_runtime_resume_and_get(dev); 642 if (ret) 643 return ret; 644 645 i2c_mark_adapter_suspended(&riic->adapter); 646 647 /* Disable output on SDA, SCL pins. */ 648 riic_clear_set_bit(riic, ICCR1_ICE, 0, RIIC_ICCR1); 649 650 pm_runtime_mark_last_busy(dev); 651 pm_runtime_put_sync(dev); 652 653 return reset_control_assert(riic->rstc); 654 } 655 656 static int riic_i2c_resume(struct device *dev) 657 { 658 struct riic_dev *riic = dev_get_drvdata(dev); 659 int ret; 660 661 ret = reset_control_deassert(riic->rstc); 662 if (ret) 663 return ret; 664 665 ret = riic_init_hw(riic); 666 if (ret) { 667 /* 668 * In case this happens there is no way to recover from this 669 * state. The driver will remain loaded. We want to avoid 670 * keeping the reset line de-asserted for no reason. 671 */ 672 reset_control_assert(riic->rstc); 673 return ret; 674 } 675 676 i2c_mark_adapter_resumed(&riic->adapter); 677 678 return 0; 679 } 680 681 static const struct dev_pm_ops riic_i2c_pm_ops = { 682 SYSTEM_SLEEP_PM_OPS(riic_i2c_suspend, riic_i2c_resume) 683 }; 684 685 static const struct of_device_id riic_i2c_dt_ids[] = { 686 { .compatible = "renesas,riic-rz", .data = &riic_rz_a_info }, 687 { .compatible = "renesas,riic-r7s72100", .data = &riic_rz_a1h_info, }, 688 { .compatible = "renesas,riic-r9a09g057", .data = &riic_rz_v2h_info }, 689 { /* Sentinel */ }, 690 }; 691 692 static struct platform_driver riic_i2c_driver = { 693 .probe = riic_i2c_probe, 694 .remove = riic_i2c_remove, 695 .driver = { 696 .name = "i2c-riic", 697 .of_match_table = riic_i2c_dt_ids, 698 .pm = pm_ptr(&riic_i2c_pm_ops), 699 }, 700 }; 701 702 module_platform_driver(riic_i2c_driver); 703 704 MODULE_DESCRIPTION("Renesas RIIC adapter"); 705 MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>"); 706 MODULE_LICENSE("GPL v2"); 707 MODULE_DEVICE_TABLE(of, riic_i2c_dt_ids); 708