1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * This driver implements I2C master functionality using the LSI API2C 4 * controller. 5 * 6 * NOTE: The controller has a limitation in that it can only do transfers of 7 * maximum 255 bytes at a time. If a larger transfer is attempted, error code 8 * (-EINVAL) is returned. 9 */ 10 #include <linux/clk.h> 11 #include <linux/clkdev.h> 12 #include <linux/delay.h> 13 #include <linux/err.h> 14 #include <linux/i2c.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/module.h> 18 #include <linux/io.h> 19 #include <linux/kernel.h> 20 #include <linux/platform_device.h> 21 22 #define SCL_WAIT_TIMEOUT_NS 25000000 23 #define I2C_XFER_TIMEOUT (msecs_to_jiffies(250)) 24 #define I2C_STOP_TIMEOUT (msecs_to_jiffies(100)) 25 #define FIFO_SIZE 8 26 #define SEQ_LEN 2 27 28 #define GLOBAL_CONTROL 0x00 29 #define GLOBAL_MST_EN BIT(0) 30 #define GLOBAL_SLV_EN BIT(1) 31 #define GLOBAL_IBML_EN BIT(2) 32 #define INTERRUPT_STATUS 0x04 33 #define INTERRUPT_ENABLE 0x08 34 #define INT_SLV BIT(1) 35 #define INT_MST BIT(0) 36 #define WAIT_TIMER_CONTROL 0x0c 37 #define WT_EN BIT(15) 38 #define WT_VALUE(_x) ((_x) & 0x7fff) 39 #define IBML_TIMEOUT 0x10 40 #define IBML_LOW_MEXT 0x14 41 #define IBML_LOW_SEXT 0x18 42 #define TIMER_CLOCK_DIV 0x1c 43 #define I2C_BUS_MONITOR 0x20 44 #define BM_SDAC BIT(3) 45 #define BM_SCLC BIT(2) 46 #define BM_SDAS BIT(1) 47 #define BM_SCLS BIT(0) 48 #define SOFT_RESET 0x24 49 #define MST_COMMAND 0x28 50 #define CMD_BUSY (1<<3) 51 #define CMD_MANUAL (0x00 | CMD_BUSY) 52 #define CMD_AUTO (0x01 | CMD_BUSY) 53 #define CMD_SEQUENCE (0x02 | CMD_BUSY) 54 #define MST_RX_XFER 0x2c 55 #define MST_TX_XFER 0x30 56 #define MST_ADDR_1 0x34 57 #define MST_ADDR_2 0x38 58 #define MST_DATA 0x3c 59 #define MST_TX_FIFO 0x40 60 #define MST_RX_FIFO 0x44 61 #define MST_INT_ENABLE 0x48 62 #define MST_INT_STATUS 0x4c 63 #define MST_STATUS_RFL (1 << 13) /* RX FIFO serivce */ 64 #define MST_STATUS_TFL (1 << 12) /* TX FIFO service */ 65 #define MST_STATUS_SNS (1 << 11) /* Manual mode done */ 66 #define MST_STATUS_SS (1 << 10) /* Automatic mode done */ 67 #define MST_STATUS_SCC (1 << 9) /* Stop complete */ 68 #define MST_STATUS_IP (1 << 8) /* Invalid parameter */ 69 #define MST_STATUS_TSS (1 << 7) /* Timeout */ 70 #define MST_STATUS_AL (1 << 6) /* Arbitration lost */ 71 #define MST_STATUS_ND (1 << 5) /* NAK on data phase */ 72 #define MST_STATUS_NA (1 << 4) /* NAK on address phase */ 73 #define MST_STATUS_NAK (MST_STATUS_NA | \ 74 MST_STATUS_ND) 75 #define MST_STATUS_ERR (MST_STATUS_NAK | \ 76 MST_STATUS_AL | \ 77 MST_STATUS_IP) 78 #define MST_TX_BYTES_XFRD 0x50 79 #define MST_RX_BYTES_XFRD 0x54 80 #define SLV_ADDR_DEC_CTL 0x58 81 #define SLV_ADDR_DEC_GCE BIT(0) /* ACK to General Call Address from own master (loopback) */ 82 #define SLV_ADDR_DEC_OGCE BIT(1) /* ACK to General Call Address from external masters */ 83 #define SLV_ADDR_DEC_SA1E BIT(2) /* ACK to addr_1 enabled */ 84 #define SLV_ADDR_DEC_SA1M BIT(3) /* 10-bit addressing for addr_1 enabled */ 85 #define SLV_ADDR_DEC_SA2E BIT(4) /* ACK to addr_2 enabled */ 86 #define SLV_ADDR_DEC_SA2M BIT(5) /* 10-bit addressing for addr_2 enabled */ 87 #define SLV_ADDR_1 0x5c 88 #define SLV_ADDR_2 0x60 89 #define SLV_RX_CTL 0x64 90 #define SLV_RX_ACSA1 BIT(0) /* Generate ACK for writes to addr_1 */ 91 #define SLV_RX_ACSA2 BIT(1) /* Generate ACK for writes to addr_2 */ 92 #define SLV_RX_ACGCA BIT(2) /* ACK data phase transfers to General Call Address */ 93 #define SLV_DATA 0x68 94 #define SLV_RX_FIFO 0x6c 95 #define SLV_FIFO_DV1 BIT(0) /* Data Valid for addr_1 */ 96 #define SLV_FIFO_DV2 BIT(1) /* Data Valid for addr_2 */ 97 #define SLV_FIFO_AS BIT(2) /* (N)ACK Sent */ 98 #define SLV_FIFO_TNAK BIT(3) /* Timeout NACK */ 99 #define SLV_FIFO_STRC BIT(4) /* First byte after start condition received */ 100 #define SLV_FIFO_RSC BIT(5) /* Repeated Start Condition */ 101 #define SLV_FIFO_STPC BIT(6) /* Stop Condition */ 102 #define SLV_FIFO_DV (SLV_FIFO_DV1 | SLV_FIFO_DV2) 103 #define SLV_INT_ENABLE 0x70 104 #define SLV_INT_STATUS 0x74 105 #define SLV_STATUS_RFH BIT(0) /* FIFO service */ 106 #define SLV_STATUS_WTC BIT(1) /* Write transfer complete */ 107 #define SLV_STATUS_SRS1 BIT(2) /* Slave read from addr 1 */ 108 #define SLV_STATUS_SRRS1 BIT(3) /* Repeated start from addr 1 */ 109 #define SLV_STATUS_SRND1 BIT(4) /* Read request not following start condition */ 110 #define SLV_STATUS_SRC1 BIT(5) /* Read canceled */ 111 #define SLV_STATUS_SRAT1 BIT(6) /* Slave Read timed out */ 112 #define SLV_STATUS_SRDRE1 BIT(7) /* Data written after timed out */ 113 #define SLV_READ_DUMMY 0x78 114 #define SCL_HIGH_PERIOD 0x80 115 #define SCL_LOW_PERIOD 0x84 116 #define SPIKE_FLTR_LEN 0x88 117 #define SDA_SETUP_TIME 0x8c 118 #define SDA_HOLD_TIME 0x90 119 120 /** 121 * struct axxia_i2c_dev - I2C device context 122 * @base: pointer to register struct 123 * @msg: pointer to current message 124 * @msg_r: pointer to current read message (sequence transfer) 125 * @msg_xfrd: number of bytes transferred in tx_fifo 126 * @msg_xfrd_r: number of bytes transferred in rx_fifo 127 * @msg_err: error code for completed message 128 * @msg_complete: xfer completion object 129 * @dev: device reference 130 * @adapter: core i2c abstraction 131 * @i2c_clk: clock reference for i2c input clock 132 * @bus_clk_rate: current i2c bus clock rate 133 * @last: a flag indicating is this is last message in transfer 134 * @slave: associated &i2c_client 135 * @irq: platform device IRQ number 136 */ 137 struct axxia_i2c_dev { 138 void __iomem *base; 139 struct i2c_msg *msg; 140 struct i2c_msg *msg_r; 141 size_t msg_xfrd; 142 size_t msg_xfrd_r; 143 int msg_err; 144 struct completion msg_complete; 145 struct device *dev; 146 struct i2c_adapter adapter; 147 struct clk *i2c_clk; 148 u32 bus_clk_rate; 149 bool last; 150 struct i2c_client *slave; 151 int irq; 152 }; 153 154 static void i2c_int_disable(struct axxia_i2c_dev *idev, u32 mask) 155 { 156 u32 int_en; 157 158 int_en = readl(idev->base + MST_INT_ENABLE); 159 writel(int_en & ~mask, idev->base + MST_INT_ENABLE); 160 } 161 162 static void i2c_int_enable(struct axxia_i2c_dev *idev, u32 mask) 163 { 164 u32 int_en; 165 166 int_en = readl(idev->base + MST_INT_ENABLE); 167 writel(int_en | mask, idev->base + MST_INT_ENABLE); 168 } 169 170 /* 171 * ns_to_clk - Convert time (ns) to clock cycles for the given clock frequency. 172 */ 173 static u32 ns_to_clk(u64 ns, u32 clk_mhz) 174 { 175 return div_u64(ns * clk_mhz, 1000); 176 } 177 178 static int axxia_i2c_init(struct axxia_i2c_dev *idev) 179 { 180 u32 divisor = clk_get_rate(idev->i2c_clk) / idev->bus_clk_rate; 181 u32 clk_mhz = clk_get_rate(idev->i2c_clk) / 1000000; 182 u32 t_setup; 183 u32 t_high, t_low; 184 u32 tmo_clk; 185 u32 prescale; 186 unsigned long timeout; 187 188 dev_dbg(idev->dev, "rate=%uHz per_clk=%uMHz -> ratio=1:%u\n", 189 idev->bus_clk_rate, clk_mhz, divisor); 190 191 /* Reset controller */ 192 writel(0x01, idev->base + SOFT_RESET); 193 timeout = jiffies + msecs_to_jiffies(100); 194 while (readl(idev->base + SOFT_RESET) & 1) { 195 if (time_after(jiffies, timeout)) { 196 dev_warn(idev->dev, "Soft reset failed\n"); 197 break; 198 } 199 } 200 201 /* Enable Master Mode */ 202 writel(0x1, idev->base + GLOBAL_CONTROL); 203 204 if (idev->bus_clk_rate <= I2C_MAX_STANDARD_MODE_FREQ) { 205 /* Standard mode SCL 50/50, tSU:DAT = 250 ns */ 206 t_high = divisor * 1 / 2; 207 t_low = divisor * 1 / 2; 208 t_setup = ns_to_clk(250, clk_mhz); 209 } else { 210 /* Fast mode SCL 33/66, tSU:DAT = 100 ns */ 211 t_high = divisor * 1 / 3; 212 t_low = divisor * 2 / 3; 213 t_setup = ns_to_clk(100, clk_mhz); 214 } 215 216 /* SCL High Time */ 217 writel(t_high, idev->base + SCL_HIGH_PERIOD); 218 /* SCL Low Time */ 219 writel(t_low, idev->base + SCL_LOW_PERIOD); 220 /* SDA Setup Time */ 221 writel(t_setup, idev->base + SDA_SETUP_TIME); 222 /* SDA Hold Time, 300ns */ 223 writel(ns_to_clk(300, clk_mhz), idev->base + SDA_HOLD_TIME); 224 /* Filter <50ns spikes */ 225 writel(ns_to_clk(50, clk_mhz), idev->base + SPIKE_FLTR_LEN); 226 227 /* Configure Time-Out Registers */ 228 tmo_clk = ns_to_clk(SCL_WAIT_TIMEOUT_NS, clk_mhz); 229 230 /* Find prescaler value that makes tmo_clk fit in 15-bits counter. */ 231 for (prescale = 0; prescale < 15; ++prescale) { 232 if (tmo_clk <= 0x7fff) 233 break; 234 tmo_clk >>= 1; 235 } 236 if (tmo_clk > 0x7fff) 237 tmo_clk = 0x7fff; 238 239 /* Prescale divider (log2) */ 240 writel(prescale, idev->base + TIMER_CLOCK_DIV); 241 /* Timeout in divided clocks */ 242 writel(WT_EN | WT_VALUE(tmo_clk), idev->base + WAIT_TIMER_CONTROL); 243 244 /* Mask all master interrupt bits */ 245 i2c_int_disable(idev, ~0); 246 247 /* Interrupt enable */ 248 writel(0x01, idev->base + INTERRUPT_ENABLE); 249 250 return 0; 251 } 252 253 static int i2c_m_rd(const struct i2c_msg *msg) 254 { 255 return (msg->flags & I2C_M_RD) != 0; 256 } 257 258 static int i2c_m_recv_len(const struct i2c_msg *msg) 259 { 260 return (msg->flags & I2C_M_RECV_LEN) != 0; 261 } 262 263 /* 264 * axxia_i2c_empty_rx_fifo - Fetch data from RX FIFO and update SMBus block 265 * transfer length if this is the first byte of such a transfer. 266 */ 267 static int axxia_i2c_empty_rx_fifo(struct axxia_i2c_dev *idev) 268 { 269 struct i2c_msg *msg = idev->msg_r; 270 size_t rx_fifo_avail = readl(idev->base + MST_RX_FIFO); 271 int bytes_to_transfer = min(rx_fifo_avail, msg->len - idev->msg_xfrd_r); 272 273 while (bytes_to_transfer-- > 0) { 274 int c = readl(idev->base + MST_DATA); 275 276 if (idev->msg_xfrd_r == 0 && i2c_m_recv_len(msg)) { 277 /* 278 * Check length byte for SMBus block read 279 */ 280 if (c <= 0 || c > I2C_SMBUS_BLOCK_MAX) { 281 idev->msg_err = -EPROTO; 282 i2c_int_disable(idev, ~MST_STATUS_TSS); 283 complete(&idev->msg_complete); 284 break; 285 } 286 msg->len = 1 + c; 287 writel(msg->len, idev->base + MST_RX_XFER); 288 } 289 msg->buf[idev->msg_xfrd_r++] = c; 290 } 291 292 return 0; 293 } 294 295 /* 296 * axxia_i2c_fill_tx_fifo - Fill TX FIFO from current message buffer. 297 * @return: Number of bytes left to transfer. 298 */ 299 static int axxia_i2c_fill_tx_fifo(struct axxia_i2c_dev *idev) 300 { 301 struct i2c_msg *msg = idev->msg; 302 size_t tx_fifo_avail = FIFO_SIZE - readl(idev->base + MST_TX_FIFO); 303 int bytes_to_transfer = min(tx_fifo_avail, msg->len - idev->msg_xfrd); 304 int ret = msg->len - idev->msg_xfrd - bytes_to_transfer; 305 306 while (bytes_to_transfer-- > 0) 307 writel(msg->buf[idev->msg_xfrd++], idev->base + MST_DATA); 308 309 return ret; 310 } 311 312 static void axxia_i2c_slv_fifo_event(struct axxia_i2c_dev *idev) 313 { 314 u32 fifo_status = readl(idev->base + SLV_RX_FIFO); 315 u8 val; 316 317 dev_dbg(idev->dev, "slave irq fifo_status=0x%x\n", fifo_status); 318 319 if (fifo_status & SLV_FIFO_DV1) { 320 if (fifo_status & SLV_FIFO_STRC) 321 i2c_slave_event(idev->slave, 322 I2C_SLAVE_WRITE_REQUESTED, &val); 323 324 val = readl(idev->base + SLV_DATA); 325 i2c_slave_event(idev->slave, I2C_SLAVE_WRITE_RECEIVED, &val); 326 } 327 if (fifo_status & SLV_FIFO_STPC) { 328 readl(idev->base + SLV_DATA); /* dummy read */ 329 i2c_slave_event(idev->slave, I2C_SLAVE_STOP, &val); 330 } 331 if (fifo_status & SLV_FIFO_RSC) 332 readl(idev->base + SLV_DATA); /* dummy read */ 333 } 334 335 static irqreturn_t axxia_i2c_slv_isr(struct axxia_i2c_dev *idev) 336 { 337 u32 status = readl(idev->base + SLV_INT_STATUS); 338 u8 val; 339 340 dev_dbg(idev->dev, "slave irq status=0x%x\n", status); 341 342 if (status & SLV_STATUS_RFH) 343 axxia_i2c_slv_fifo_event(idev); 344 if (status & SLV_STATUS_SRS1) { 345 i2c_slave_event(idev->slave, I2C_SLAVE_READ_REQUESTED, &val); 346 writel(val, idev->base + SLV_DATA); 347 } 348 if (status & SLV_STATUS_SRND1) { 349 i2c_slave_event(idev->slave, I2C_SLAVE_READ_PROCESSED, &val); 350 writel(val, idev->base + SLV_DATA); 351 } 352 if (status & SLV_STATUS_SRC1) 353 i2c_slave_event(idev->slave, I2C_SLAVE_STOP, &val); 354 355 writel(INT_SLV, idev->base + INTERRUPT_STATUS); 356 return IRQ_HANDLED; 357 } 358 359 static irqreturn_t axxia_i2c_isr(int irq, void *_dev) 360 { 361 struct axxia_i2c_dev *idev = _dev; 362 irqreturn_t ret = IRQ_NONE; 363 u32 status; 364 365 status = readl(idev->base + INTERRUPT_STATUS); 366 367 if (status & INT_SLV) 368 ret = axxia_i2c_slv_isr(idev); 369 if (!(status & INT_MST)) 370 return ret; 371 372 /* Read interrupt status bits */ 373 status = readl(idev->base + MST_INT_STATUS); 374 375 if (!idev->msg) { 376 dev_warn(idev->dev, "unexpected interrupt\n"); 377 goto out; 378 } 379 380 /* RX FIFO needs service? */ 381 if (i2c_m_rd(idev->msg_r) && (status & MST_STATUS_RFL)) 382 axxia_i2c_empty_rx_fifo(idev); 383 384 /* TX FIFO needs service? */ 385 if (!i2c_m_rd(idev->msg) && (status & MST_STATUS_TFL)) { 386 if (axxia_i2c_fill_tx_fifo(idev) == 0) 387 i2c_int_disable(idev, MST_STATUS_TFL); 388 } 389 390 if (unlikely(status & MST_STATUS_ERR)) { 391 /* Transfer error */ 392 i2c_int_disable(idev, ~0); 393 if (status & MST_STATUS_AL) 394 idev->msg_err = -EAGAIN; 395 else if (status & MST_STATUS_NAK) 396 idev->msg_err = -ENXIO; 397 else 398 idev->msg_err = -EIO; 399 dev_dbg(idev->dev, "error %#x, addr=%#x rx=%u/%u tx=%u/%u\n", 400 status, 401 idev->msg->addr, 402 readl(idev->base + MST_RX_BYTES_XFRD), 403 readl(idev->base + MST_RX_XFER), 404 readl(idev->base + MST_TX_BYTES_XFRD), 405 readl(idev->base + MST_TX_XFER)); 406 complete(&idev->msg_complete); 407 } else if (status & MST_STATUS_SCC) { 408 /* Stop completed */ 409 i2c_int_disable(idev, ~MST_STATUS_TSS); 410 complete(&idev->msg_complete); 411 } else if (status & (MST_STATUS_SNS | MST_STATUS_SS)) { 412 /* Transfer done */ 413 int mask = idev->last ? ~0 : ~MST_STATUS_TSS; 414 415 i2c_int_disable(idev, mask); 416 if (i2c_m_rd(idev->msg_r) && idev->msg_xfrd_r < idev->msg_r->len) 417 axxia_i2c_empty_rx_fifo(idev); 418 complete(&idev->msg_complete); 419 } else if (status & MST_STATUS_TSS) { 420 /* Transfer timeout */ 421 idev->msg_err = -ETIMEDOUT; 422 i2c_int_disable(idev, ~MST_STATUS_TSS); 423 complete(&idev->msg_complete); 424 } 425 426 out: 427 /* Clear interrupt */ 428 writel(INT_MST, idev->base + INTERRUPT_STATUS); 429 430 return IRQ_HANDLED; 431 } 432 433 static void axxia_i2c_set_addr(struct axxia_i2c_dev *idev, struct i2c_msg *msg) 434 { 435 u32 addr_1, addr_2; 436 437 if (msg->flags & I2C_M_TEN) { 438 addr_1 = i2c_10bit_addr_hi_from_msg(msg); 439 addr_2 = i2c_10bit_addr_lo_from_msg(msg); 440 } else { 441 addr_1 = i2c_8bit_addr_from_msg(msg); 442 addr_2 = 0; 443 } 444 445 writel(addr_1, idev->base + MST_ADDR_1); 446 writel(addr_2, idev->base + MST_ADDR_2); 447 } 448 449 /* The NAK interrupt will be sent _before_ issuing STOP command 450 * so the controller might still be busy processing it. No 451 * interrupt will be sent at the end so we have to poll for it 452 */ 453 static int axxia_i2c_handle_seq_nak(struct axxia_i2c_dev *idev) 454 { 455 unsigned long timeout = jiffies + I2C_XFER_TIMEOUT; 456 457 do { 458 if ((readl(idev->base + MST_COMMAND) & CMD_BUSY) == 0) 459 return 0; 460 usleep_range(1, 100); 461 } while (time_before(jiffies, timeout)); 462 463 return -ETIMEDOUT; 464 } 465 466 static int axxia_i2c_xfer_seq(struct axxia_i2c_dev *idev, struct i2c_msg msgs[]) 467 { 468 u32 int_mask = MST_STATUS_ERR | MST_STATUS_SS | MST_STATUS_RFL; 469 u32 rlen = i2c_m_recv_len(&msgs[1]) ? I2C_SMBUS_BLOCK_MAX : msgs[1].len; 470 unsigned long time_left; 471 472 axxia_i2c_set_addr(idev, &msgs[0]); 473 474 writel(msgs[0].len, idev->base + MST_TX_XFER); 475 writel(rlen, idev->base + MST_RX_XFER); 476 477 idev->msg = &msgs[0]; 478 idev->msg_r = &msgs[1]; 479 idev->msg_xfrd = 0; 480 idev->msg_xfrd_r = 0; 481 idev->last = true; 482 axxia_i2c_fill_tx_fifo(idev); 483 484 writel(CMD_SEQUENCE, idev->base + MST_COMMAND); 485 486 reinit_completion(&idev->msg_complete); 487 i2c_int_enable(idev, int_mask); 488 489 time_left = wait_for_completion_timeout(&idev->msg_complete, 490 I2C_XFER_TIMEOUT); 491 492 if (idev->msg_err == -ENXIO) { 493 if (axxia_i2c_handle_seq_nak(idev)) 494 axxia_i2c_init(idev); 495 } else if (readl(idev->base + MST_COMMAND) & CMD_BUSY) { 496 dev_warn(idev->dev, "busy after xfer\n"); 497 } 498 499 if (time_left == 0) { 500 idev->msg_err = -ETIMEDOUT; 501 i2c_recover_bus(&idev->adapter); 502 axxia_i2c_init(idev); 503 } 504 505 if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO) 506 axxia_i2c_init(idev); 507 508 return idev->msg_err; 509 } 510 511 static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg, 512 bool last) 513 { 514 u32 int_mask = MST_STATUS_ERR; 515 u32 rx_xfer, tx_xfer; 516 unsigned long time_left; 517 unsigned int wt_value; 518 519 idev->msg = msg; 520 idev->msg_r = msg; 521 idev->msg_xfrd = 0; 522 idev->msg_xfrd_r = 0; 523 idev->last = last; 524 reinit_completion(&idev->msg_complete); 525 526 axxia_i2c_set_addr(idev, msg); 527 528 if (i2c_m_rd(msg)) { 529 /* I2C read transfer */ 530 rx_xfer = i2c_m_recv_len(msg) ? I2C_SMBUS_BLOCK_MAX : msg->len; 531 tx_xfer = 0; 532 } else { 533 /* I2C write transfer */ 534 rx_xfer = 0; 535 tx_xfer = msg->len; 536 } 537 538 writel(rx_xfer, idev->base + MST_RX_XFER); 539 writel(tx_xfer, idev->base + MST_TX_XFER); 540 541 if (i2c_m_rd(msg)) 542 int_mask |= MST_STATUS_RFL; 543 else if (axxia_i2c_fill_tx_fifo(idev) != 0) 544 int_mask |= MST_STATUS_TFL; 545 546 wt_value = WT_VALUE(readl(idev->base + WAIT_TIMER_CONTROL)); 547 /* Disable wait timer temporarly */ 548 writel(wt_value, idev->base + WAIT_TIMER_CONTROL); 549 /* Check if timeout error happened */ 550 if (idev->msg_err) 551 goto out; 552 553 if (!last) { 554 writel(CMD_MANUAL, idev->base + MST_COMMAND); 555 int_mask |= MST_STATUS_SNS; 556 } else { 557 writel(CMD_AUTO, idev->base + MST_COMMAND); 558 int_mask |= MST_STATUS_SS; 559 } 560 561 writel(WT_EN | wt_value, idev->base + WAIT_TIMER_CONTROL); 562 563 i2c_int_enable(idev, int_mask); 564 565 time_left = wait_for_completion_timeout(&idev->msg_complete, 566 I2C_XFER_TIMEOUT); 567 568 i2c_int_disable(idev, int_mask); 569 570 if (readl(idev->base + MST_COMMAND) & CMD_BUSY) 571 dev_warn(idev->dev, "busy after xfer\n"); 572 573 if (time_left == 0) { 574 idev->msg_err = -ETIMEDOUT; 575 i2c_recover_bus(&idev->adapter); 576 axxia_i2c_init(idev); 577 } 578 579 out: 580 if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO && 581 idev->msg_err != -ETIMEDOUT) 582 axxia_i2c_init(idev); 583 584 return idev->msg_err; 585 } 586 587 /* This function checks if the msgs[] array contains messages compatible with 588 * Sequence mode of operation. This mode assumes there will be exactly one 589 * write of non-zero length followed by exactly one read of non-zero length, 590 * both targeted at the same client device. 591 */ 592 static bool axxia_i2c_sequence_ok(struct i2c_msg msgs[], int num) 593 { 594 return num == SEQ_LEN && !i2c_m_rd(&msgs[0]) && i2c_m_rd(&msgs[1]) && 595 msgs[0].len > 0 && msgs[0].len <= FIFO_SIZE && 596 msgs[1].len > 0 && msgs[0].addr == msgs[1].addr; 597 } 598 599 static int 600 axxia_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 601 { 602 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap); 603 int i; 604 int ret = 0; 605 606 idev->msg_err = 0; 607 608 if (axxia_i2c_sequence_ok(msgs, num)) { 609 ret = axxia_i2c_xfer_seq(idev, msgs); 610 return ret ? : SEQ_LEN; 611 } 612 613 i2c_int_enable(idev, MST_STATUS_TSS); 614 615 for (i = 0; ret == 0 && i < num; ++i) 616 ret = axxia_i2c_xfer_msg(idev, &msgs[i], i == (num - 1)); 617 618 return ret ? : i; 619 } 620 621 static int axxia_i2c_get_scl(struct i2c_adapter *adap) 622 { 623 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap); 624 625 return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SCLS); 626 } 627 628 static void axxia_i2c_set_scl(struct i2c_adapter *adap, int val) 629 { 630 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap); 631 u32 tmp; 632 633 /* Preserve SDA Control */ 634 tmp = readl(idev->base + I2C_BUS_MONITOR) & BM_SDAC; 635 if (!val) 636 tmp |= BM_SCLC; 637 writel(tmp, idev->base + I2C_BUS_MONITOR); 638 } 639 640 static int axxia_i2c_get_sda(struct i2c_adapter *adap) 641 { 642 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap); 643 644 return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SDAS); 645 } 646 647 static struct i2c_bus_recovery_info axxia_i2c_recovery_info = { 648 .recover_bus = i2c_generic_scl_recovery, 649 .get_scl = axxia_i2c_get_scl, 650 .set_scl = axxia_i2c_set_scl, 651 .get_sda = axxia_i2c_get_sda, 652 }; 653 654 static u32 axxia_i2c_func(struct i2c_adapter *adap) 655 { 656 u32 caps = (I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | 657 I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA); 658 return caps; 659 } 660 661 static int axxia_i2c_reg_slave(struct i2c_client *slave) 662 { 663 struct axxia_i2c_dev *idev = i2c_get_adapdata(slave->adapter); 664 u32 slv_int_mask = SLV_STATUS_RFH; 665 u32 dec_ctl; 666 667 if (idev->slave) 668 return -EBUSY; 669 670 idev->slave = slave; 671 672 /* Enable slave mode as well */ 673 writel(GLOBAL_MST_EN | GLOBAL_SLV_EN, idev->base + GLOBAL_CONTROL); 674 writel(INT_MST | INT_SLV, idev->base + INTERRUPT_ENABLE); 675 676 /* Set slave address */ 677 dec_ctl = SLV_ADDR_DEC_SA1E; 678 if (slave->flags & I2C_CLIENT_TEN) 679 dec_ctl |= SLV_ADDR_DEC_SA1M; 680 681 writel(SLV_RX_ACSA1, idev->base + SLV_RX_CTL); 682 writel(dec_ctl, idev->base + SLV_ADDR_DEC_CTL); 683 writel(slave->addr, idev->base + SLV_ADDR_1); 684 685 /* Enable interrupts */ 686 slv_int_mask |= SLV_STATUS_SRS1 | SLV_STATUS_SRRS1 | SLV_STATUS_SRND1; 687 slv_int_mask |= SLV_STATUS_SRC1; 688 writel(slv_int_mask, idev->base + SLV_INT_ENABLE); 689 690 return 0; 691 } 692 693 static int axxia_i2c_unreg_slave(struct i2c_client *slave) 694 { 695 struct axxia_i2c_dev *idev = i2c_get_adapdata(slave->adapter); 696 697 /* Disable slave mode */ 698 writel(GLOBAL_MST_EN, idev->base + GLOBAL_CONTROL); 699 writel(INT_MST, idev->base + INTERRUPT_ENABLE); 700 701 synchronize_irq(idev->irq); 702 703 idev->slave = NULL; 704 705 return 0; 706 } 707 708 static const struct i2c_algorithm axxia_i2c_algo = { 709 .xfer = axxia_i2c_xfer, 710 .functionality = axxia_i2c_func, 711 .reg_slave = axxia_i2c_reg_slave, 712 .unreg_slave = axxia_i2c_unreg_slave, 713 }; 714 715 static const struct i2c_adapter_quirks axxia_i2c_quirks = { 716 .max_read_len = 255, 717 .max_write_len = 255, 718 }; 719 720 static int axxia_i2c_probe(struct platform_device *pdev) 721 { 722 struct device_node *np = pdev->dev.of_node; 723 struct axxia_i2c_dev *idev = NULL; 724 void __iomem *base; 725 int ret = 0; 726 727 idev = devm_kzalloc(&pdev->dev, sizeof(*idev), GFP_KERNEL); 728 if (!idev) 729 return -ENOMEM; 730 731 base = devm_platform_ioremap_resource(pdev, 0); 732 if (IS_ERR(base)) 733 return PTR_ERR(base); 734 735 idev->irq = platform_get_irq(pdev, 0); 736 if (idev->irq < 0) 737 return idev->irq; 738 739 idev->i2c_clk = devm_clk_get(&pdev->dev, "i2c"); 740 if (IS_ERR(idev->i2c_clk)) { 741 dev_err(&pdev->dev, "missing clock\n"); 742 return PTR_ERR(idev->i2c_clk); 743 } 744 745 idev->base = base; 746 idev->dev = &pdev->dev; 747 init_completion(&idev->msg_complete); 748 749 of_property_read_u32(np, "clock-frequency", &idev->bus_clk_rate); 750 if (idev->bus_clk_rate == 0) 751 idev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ; /* default clock rate */ 752 753 ret = clk_prepare_enable(idev->i2c_clk); 754 if (ret) { 755 dev_err(&pdev->dev, "failed to enable clock\n"); 756 return ret; 757 } 758 759 ret = axxia_i2c_init(idev); 760 if (ret) { 761 dev_err(&pdev->dev, "failed to initialize\n"); 762 goto error_disable_clk; 763 } 764 765 ret = devm_request_irq(&pdev->dev, idev->irq, axxia_i2c_isr, 0, 766 pdev->name, idev); 767 if (ret) { 768 dev_err(&pdev->dev, "failed to claim IRQ%d\n", idev->irq); 769 goto error_disable_clk; 770 } 771 772 i2c_set_adapdata(&idev->adapter, idev); 773 strscpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name)); 774 idev->adapter.owner = THIS_MODULE; 775 idev->adapter.algo = &axxia_i2c_algo; 776 idev->adapter.bus_recovery_info = &axxia_i2c_recovery_info; 777 idev->adapter.quirks = &axxia_i2c_quirks; 778 idev->adapter.dev.parent = &pdev->dev; 779 idev->adapter.dev.of_node = pdev->dev.of_node; 780 781 platform_set_drvdata(pdev, idev); 782 783 ret = i2c_add_adapter(&idev->adapter); 784 if (ret) 785 goto error_disable_clk; 786 787 return 0; 788 789 error_disable_clk: 790 clk_disable_unprepare(idev->i2c_clk); 791 return ret; 792 } 793 794 static void axxia_i2c_remove(struct platform_device *pdev) 795 { 796 struct axxia_i2c_dev *idev = platform_get_drvdata(pdev); 797 798 clk_disable_unprepare(idev->i2c_clk); 799 i2c_del_adapter(&idev->adapter); 800 } 801 802 /* Match table for of_platform binding */ 803 static const struct of_device_id axxia_i2c_of_match[] = { 804 { .compatible = "lsi,api2c", }, 805 {}, 806 }; 807 808 MODULE_DEVICE_TABLE(of, axxia_i2c_of_match); 809 810 static struct platform_driver axxia_i2c_driver = { 811 .probe = axxia_i2c_probe, 812 .remove = axxia_i2c_remove, 813 .driver = { 814 .name = "axxia-i2c", 815 .of_match_table = axxia_i2c_of_match, 816 }, 817 }; 818 819 module_platform_driver(axxia_i2c_driver); 820 821 MODULE_DESCRIPTION("Axxia I2C Bus driver"); 822 MODULE_AUTHOR("Anders Berg <anders.berg@lsi.com>"); 823 MODULE_LICENSE("GPL v2"); 824