1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright(c) 2023, Intel Corporation. All rights reserved. 4 */ 5 6 #include <linux/irq.h> 7 #include <linux/mei_aux.h> 8 #include <linux/pci.h> 9 #include <linux/sizes.h> 10 11 #include "xe_device_types.h" 12 #include "xe_drv.h" 13 #include "xe_heci_gsc.h" 14 #include "xe_platform_types.h" 15 #include "xe_survivability_mode.h" 16 17 #define GSC_BAR_LENGTH 0x00000FFC 18 19 #define DG1_GSC_HECI2_BASE 0x259000 20 #define PVC_GSC_HECI2_BASE 0x285000 21 #define DG2_GSC_HECI2_BASE 0x374000 22 23 static void heci_gsc_irq_mask(struct irq_data *d) 24 { 25 /* generic irq handling */ 26 } 27 28 static void heci_gsc_irq_unmask(struct irq_data *d) 29 { 30 /* generic irq handling */ 31 } 32 33 static const struct irq_chip heci_gsc_irq_chip = { 34 .name = "gsc_irq_chip", 35 .irq_mask = heci_gsc_irq_mask, 36 .irq_unmask = heci_gsc_irq_unmask, 37 }; 38 39 static int heci_gsc_irq_init(int irq) 40 { 41 irq_set_chip_and_handler_name(irq, &heci_gsc_irq_chip, 42 handle_simple_irq, "heci_gsc_irq_handler"); 43 44 return irq_set_chip_data(irq, NULL); 45 } 46 47 /** 48 * struct heci_gsc_def - graphics security controller heci interface definitions 49 * 50 * @name: name of the heci device 51 * @bar: address of the mmio bar 52 * @bar_size: size of the mmio bar 53 * @use_polling: indication of using polling mode for the device 54 * @slow_firmware: indication of whether the device is slow (needs longer timeouts) 55 */ 56 struct heci_gsc_def { 57 const char *name; 58 unsigned long bar; 59 size_t bar_size; 60 bool use_polling; 61 bool slow_firmware; 62 }; 63 64 /* gsc resources and definitions */ 65 static const struct heci_gsc_def heci_gsc_def_dg1 = { 66 .name = "mei-gscfi", 67 .bar = DG1_GSC_HECI2_BASE, 68 .bar_size = GSC_BAR_LENGTH, 69 }; 70 71 static const struct heci_gsc_def heci_gsc_def_dg2 = { 72 .name = "mei-gscfi", 73 .bar = DG2_GSC_HECI2_BASE, 74 .bar_size = GSC_BAR_LENGTH, 75 }; 76 77 static const struct heci_gsc_def heci_gsc_def_pvc = { 78 .name = "mei-gscfi", 79 .bar = PVC_GSC_HECI2_BASE, 80 .bar_size = GSC_BAR_LENGTH, 81 .slow_firmware = true, 82 }; 83 84 static void heci_gsc_release_dev(struct device *dev) 85 { 86 struct auxiliary_device *aux_dev = to_auxiliary_dev(dev); 87 struct mei_aux_device *adev = auxiliary_dev_to_mei_aux_dev(aux_dev); 88 89 kfree(adev); 90 } 91 92 void xe_heci_gsc_fini(struct xe_device *xe) 93 { 94 struct xe_heci_gsc *heci_gsc = &xe->heci_gsc; 95 96 if (!xe->info.has_heci_gscfi && !xe->info.has_heci_cscfi) 97 return; 98 99 if (heci_gsc->adev) { 100 struct auxiliary_device *aux_dev = &heci_gsc->adev->aux_dev; 101 102 auxiliary_device_delete(aux_dev); 103 auxiliary_device_uninit(aux_dev); 104 heci_gsc->adev = NULL; 105 } 106 107 if (heci_gsc->irq >= 0) 108 irq_free_desc(heci_gsc->irq); 109 heci_gsc->irq = -1; 110 } 111 112 static int heci_gsc_irq_setup(struct xe_device *xe) 113 { 114 struct xe_heci_gsc *heci_gsc = &xe->heci_gsc; 115 int ret; 116 117 heci_gsc->irq = irq_alloc_desc(0); 118 if (heci_gsc->irq < 0) { 119 drm_err(&xe->drm, "gsc irq error %d\n", heci_gsc->irq); 120 return heci_gsc->irq; 121 } 122 123 ret = heci_gsc_irq_init(heci_gsc->irq); 124 if (ret < 0) 125 drm_err(&xe->drm, "gsc irq init failed %d\n", ret); 126 127 return ret; 128 } 129 130 static int heci_gsc_add_device(struct xe_device *xe, const struct heci_gsc_def *def) 131 { 132 struct xe_heci_gsc *heci_gsc = &xe->heci_gsc; 133 struct pci_dev *pdev = to_pci_dev(xe->drm.dev); 134 struct auxiliary_device *aux_dev; 135 struct mei_aux_device *adev; 136 int ret; 137 138 adev = kzalloc(sizeof(*adev), GFP_KERNEL); 139 if (!adev) 140 return -ENOMEM; 141 adev->irq = heci_gsc->irq; 142 adev->bar.parent = &pdev->resource[0]; 143 adev->bar.start = def->bar + pdev->resource[0].start; 144 adev->bar.end = adev->bar.start + def->bar_size - 1; 145 adev->bar.flags = IORESOURCE_MEM; 146 adev->bar.desc = IORES_DESC_NONE; 147 adev->slow_firmware = def->slow_firmware; 148 149 aux_dev = &adev->aux_dev; 150 aux_dev->name = def->name; 151 aux_dev->id = (pci_domain_nr(pdev->bus) << 16) | 152 PCI_DEVID(pdev->bus->number, pdev->devfn); 153 aux_dev->dev.parent = &pdev->dev; 154 aux_dev->dev.release = heci_gsc_release_dev; 155 156 ret = auxiliary_device_init(aux_dev); 157 if (ret < 0) { 158 drm_err(&xe->drm, "gsc aux init failed %d\n", ret); 159 kfree(adev); 160 return ret; 161 } 162 163 heci_gsc->adev = adev; /* needed by the notifier */ 164 ret = auxiliary_device_add(aux_dev); 165 if (ret < 0) { 166 drm_err(&xe->drm, "gsc aux add failed %d\n", ret); 167 heci_gsc->adev = NULL; 168 169 /* adev will be freed with the put_device() and .release sequence */ 170 auxiliary_device_uninit(aux_dev); 171 } 172 return ret; 173 } 174 175 void xe_heci_gsc_init(struct xe_device *xe) 176 { 177 struct xe_heci_gsc *heci_gsc = &xe->heci_gsc; 178 const struct heci_gsc_def *def; 179 int ret; 180 181 if (!xe->info.has_heci_gscfi && !xe->info.has_heci_cscfi) 182 return; 183 184 heci_gsc->irq = -1; 185 186 if (xe->info.platform == XE_BATTLEMAGE) { 187 def = &heci_gsc_def_dg2; 188 } else if (xe->info.platform == XE_PVC) { 189 def = &heci_gsc_def_pvc; 190 } else if (xe->info.platform == XE_DG2) { 191 def = &heci_gsc_def_dg2; 192 } else if (xe->info.platform == XE_DG1) { 193 def = &heci_gsc_def_dg1; 194 } else { 195 drm_warn_once(&xe->drm, "Unknown platform\n"); 196 return; 197 } 198 199 if (!def->name) { 200 drm_warn_once(&xe->drm, "HECI is not implemented!\n"); 201 return; 202 } 203 204 if (!def->use_polling && !xe_survivability_mode_is_enabled(xe)) { 205 ret = heci_gsc_irq_setup(xe); 206 if (ret) 207 goto fail; 208 } 209 210 ret = heci_gsc_add_device(xe, def); 211 if (ret) 212 goto fail; 213 214 return; 215 fail: 216 xe_heci_gsc_fini(xe); 217 } 218 219 void xe_heci_gsc_irq_handler(struct xe_device *xe, u32 iir) 220 { 221 int ret; 222 223 if ((iir & GSC_IRQ_INTF(1)) == 0) 224 return; 225 226 if (!xe->info.has_heci_gscfi) { 227 drm_warn_once(&xe->drm, "GSC irq: not supported"); 228 return; 229 } 230 231 if (xe->heci_gsc.irq < 0) 232 return; 233 234 ret = generic_handle_irq(xe->heci_gsc.irq); 235 if (ret) 236 drm_err_ratelimited(&xe->drm, "error handling GSC irq: %d\n", ret); 237 } 238 239 void xe_heci_csc_irq_handler(struct xe_device *xe, u32 iir) 240 { 241 int ret; 242 243 if ((iir & CSC_IRQ_INTF(1)) == 0) 244 return; 245 246 if (!xe->info.has_heci_cscfi) { 247 drm_warn_once(&xe->drm, "CSC irq: not supported"); 248 return; 249 } 250 251 if (xe->heci_gsc.irq < 0) 252 return; 253 254 ret = generic_handle_irq(xe->heci_gsc.irq); 255 if (ret) 256 drm_err_ratelimited(&xe->drm, "error handling GSC irq: %d\n", ret); 257 } 258