1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2015-2018 Broadcom */ 3 4 #include <linux/delay.h> 5 #include <linux/mutex.h> 6 #include <linux/spinlock_types.h> 7 #include <linux/workqueue.h> 8 9 #include <drm/drm_encoder.h> 10 #include <drm/drm_gem.h> 11 #include <drm/drm_gem_shmem_helper.h> 12 #include <drm/gpu_scheduler.h> 13 14 #include "v3d_performance_counters.h" 15 16 #include "uapi/drm/v3d_drm.h" 17 18 struct clk; 19 struct platform_device; 20 struct reset_control; 21 22 #define V3D_MMU_PAGE_SHIFT 12 23 #define V3D_PAGE_FACTOR (PAGE_SIZE >> V3D_MMU_PAGE_SHIFT) 24 25 #define V3D_MAX_QUEUES (V3D_CPU + 1) 26 27 static inline char *v3d_queue_to_string(enum v3d_queue queue) 28 { 29 switch (queue) { 30 case V3D_BIN: return "bin"; 31 case V3D_RENDER: return "render"; 32 case V3D_TFU: return "tfu"; 33 case V3D_CSD: return "csd"; 34 case V3D_CACHE_CLEAN: return "cache_clean"; 35 case V3D_CPU: return "cpu"; 36 } 37 return "UNKNOWN"; 38 } 39 40 struct v3d_stats { 41 u64 start_ns; 42 u64 enabled_ns; 43 u64 jobs_completed; 44 45 /* 46 * This seqcount is used to protect the access to the GPU stats 47 * variables. It must be used as, while we are reading the stats, 48 * IRQs can happen and the stats can be updated. 49 */ 50 seqcount_t lock; 51 }; 52 53 struct v3d_queue_state { 54 struct drm_gpu_scheduler sched; 55 56 u64 fence_context; 57 u64 emit_seqno; 58 59 /* Stores the GPU stats for this queue in the global context. */ 60 struct v3d_stats stats; 61 }; 62 63 /* Performance monitor object. The perform lifetime is controlled by userspace 64 * using perfmon related ioctls. A perfmon can be attached to a submit_cl 65 * request, and when this is the case, HW perf counters will be activated just 66 * before the submit_cl is submitted to the GPU and disabled when the job is 67 * done. This way, only events related to a specific job will be counted. 68 */ 69 struct v3d_perfmon { 70 /* Tracks the number of users of the perfmon, when this counter reaches 71 * zero the perfmon is destroyed. 72 */ 73 refcount_t refcnt; 74 75 /* Protects perfmon stop, as it can be invoked from multiple places. */ 76 struct mutex lock; 77 78 /* Number of counters activated in this perfmon instance 79 * (should be less than DRM_V3D_MAX_PERF_COUNTERS). 80 */ 81 u8 ncounters; 82 83 /* Events counted by the HW perf counters. */ 84 u8 counters[DRM_V3D_MAX_PERF_COUNTERS]; 85 86 /* Storage for counter values. Counters are incremented by the 87 * HW perf counter values every time the perfmon is attached 88 * to a GPU job. This way, perfmon users don't have to 89 * retrieve the results after each job if they want to track 90 * events covering several submissions. Note that counter 91 * values can't be reset, but you can fake a reset by 92 * destroying the perfmon and creating a new one. 93 */ 94 u64 values[] __counted_by(ncounters); 95 }; 96 97 enum v3d_gen { 98 V3D_GEN_33 = 33, 99 V3D_GEN_41 = 41, 100 V3D_GEN_42 = 42, 101 V3D_GEN_71 = 71, 102 }; 103 104 struct v3d_dev { 105 struct drm_device drm; 106 107 /* Short representation (e.g. 33, 41) of the V3D tech version */ 108 enum v3d_gen ver; 109 110 /* Short representation (e.g. 5, 6) of the V3D tech revision */ 111 int rev; 112 113 bool single_irq_line; 114 115 struct v3d_perfmon_info perfmon_info; 116 117 void __iomem *hub_regs; 118 void __iomem *core_regs[3]; 119 void __iomem *bridge_regs; 120 void __iomem *gca_regs; 121 void __iomem *sms_regs; 122 struct clk *clk; 123 struct reset_control *reset; 124 125 /* Virtual and DMA addresses of the single shared page table. */ 126 volatile u32 *pt; 127 dma_addr_t pt_paddr; 128 129 /* Virtual and DMA addresses of the MMU's scratch page. When 130 * a read or write is invalid in the MMU, it will be 131 * redirected here. 132 */ 133 void *mmu_scratch; 134 dma_addr_t mmu_scratch_paddr; 135 /* virtual address bits from V3D to the MMU. */ 136 int va_width; 137 138 /* Number of V3D cores. */ 139 u32 cores; 140 141 /* Allocator managing the address space. All units are in 142 * number of pages. 143 */ 144 struct drm_mm mm; 145 spinlock_t mm_lock; 146 147 /* 148 * tmpfs instance used for shmem backed objects 149 */ 150 struct vfsmount *gemfs; 151 152 struct work_struct overflow_mem_work; 153 154 struct v3d_bin_job *bin_job; 155 struct v3d_render_job *render_job; 156 struct v3d_tfu_job *tfu_job; 157 struct v3d_csd_job *csd_job; 158 159 struct v3d_queue_state queue[V3D_MAX_QUEUES]; 160 161 /* Spinlock used to synchronize the overflow memory 162 * management against bin job submission. 163 */ 164 spinlock_t job_lock; 165 166 /* Used to track the active perfmon if any. */ 167 struct v3d_perfmon *active_perfmon; 168 169 /* Protects bo_stats */ 170 struct mutex bo_lock; 171 172 /* Lock taken when resetting the GPU, to keep multiple 173 * processes from trying to park the scheduler threads and 174 * reset at once. 175 */ 176 struct mutex reset_lock; 177 178 /* Lock taken when creating and pushing the GPU scheduler 179 * jobs, to keep the sched-fence seqnos in order. 180 */ 181 struct mutex sched_lock; 182 183 /* Lock taken during a cache clean and when initiating an L2 184 * flush, to keep L2 flushes from interfering with the 185 * synchronous L2 cleans. 186 */ 187 struct mutex cache_clean_lock; 188 189 struct { 190 u32 num_allocated; 191 u32 pages_allocated; 192 } bo_stats; 193 194 /* To support a performance analysis tool in user space, we require 195 * a single, globally configured performance monitor (perfmon) for 196 * all jobs. 197 */ 198 struct v3d_perfmon *global_perfmon; 199 }; 200 201 static inline struct v3d_dev * 202 to_v3d_dev(struct drm_device *dev) 203 { 204 return container_of(dev, struct v3d_dev, drm); 205 } 206 207 static inline bool 208 v3d_has_csd(struct v3d_dev *v3d) 209 { 210 return v3d->ver >= V3D_GEN_41; 211 } 212 213 #define v3d_to_pdev(v3d) to_platform_device((v3d)->drm.dev) 214 215 /* The per-fd struct, which tracks the MMU mappings. */ 216 struct v3d_file_priv { 217 struct v3d_dev *v3d; 218 219 struct { 220 struct idr idr; 221 struct mutex lock; 222 } perfmon; 223 224 struct drm_sched_entity sched_entity[V3D_MAX_QUEUES]; 225 226 /* Stores the GPU stats for a specific queue for this fd. */ 227 struct v3d_stats stats[V3D_MAX_QUEUES]; 228 }; 229 230 struct v3d_bo { 231 struct drm_gem_shmem_object base; 232 233 struct drm_mm_node node; 234 235 /* List entry for the BO's position in 236 * v3d_render_job->unref_list 237 */ 238 struct list_head unref_head; 239 240 void *vaddr; 241 }; 242 243 static inline struct v3d_bo * 244 to_v3d_bo(struct drm_gem_object *bo) 245 { 246 return (struct v3d_bo *)bo; 247 } 248 249 struct v3d_fence { 250 struct dma_fence base; 251 struct drm_device *dev; 252 /* v3d seqno for signaled() test */ 253 u64 seqno; 254 enum v3d_queue queue; 255 }; 256 257 static inline struct v3d_fence * 258 to_v3d_fence(struct dma_fence *fence) 259 { 260 return (struct v3d_fence *)fence; 261 } 262 263 #define V3D_READ(offset) readl(v3d->hub_regs + offset) 264 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset) 265 266 #define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset) 267 #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset) 268 269 #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset) 270 #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset) 271 272 #define V3D_SMS_IDLE 0x0 273 #define V3D_SMS_ISOLATING_FOR_RESET 0xa 274 #define V3D_SMS_RESETTING 0xb 275 #define V3D_SMS_ISOLATING_FOR_POWER_OFF 0xc 276 #define V3D_SMS_POWER_OFF_STATE 0xd 277 278 #define V3D_SMS_READ(offset) readl(v3d->sms_regs + (offset)) 279 #define V3D_SMS_WRITE(offset, val) writel(val, v3d->sms_regs + (offset)) 280 281 #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset) 282 #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset) 283 284 struct v3d_job { 285 struct drm_sched_job base; 286 287 struct kref refcount; 288 289 struct v3d_dev *v3d; 290 291 /* This is the array of BOs that were looked up at the start 292 * of submission. 293 */ 294 struct drm_gem_object **bo; 295 u32 bo_count; 296 297 /* v3d fence to be signaled by IRQ handler when the job is complete. */ 298 struct dma_fence *irq_fence; 299 300 /* scheduler fence for when the job is considered complete and 301 * the BO reservations can be released. 302 */ 303 struct dma_fence *done_fence; 304 305 /* Pointer to a performance monitor object if the user requested it, 306 * NULL otherwise. 307 */ 308 struct v3d_perfmon *perfmon; 309 310 /* File descriptor of the process that submitted the job that could be used 311 * for collecting stats by process of GPU usage. 312 */ 313 struct drm_file *file; 314 315 /* Callback for the freeing of the job on refcount going to 0. */ 316 void (*free)(struct kref *ref); 317 }; 318 319 struct v3d_bin_job { 320 struct v3d_job base; 321 322 /* GPU virtual addresses of the start/end of the CL job. */ 323 u32 start, end; 324 325 u32 timedout_ctca, timedout_ctra; 326 327 /* Corresponding render job, for attaching our overflow memory. */ 328 struct v3d_render_job *render; 329 330 /* Submitted tile memory allocation start/size, tile state. */ 331 u32 qma, qms, qts; 332 }; 333 334 struct v3d_render_job { 335 struct v3d_job base; 336 337 /* GPU virtual addresses of the start/end of the CL job. */ 338 u32 start, end; 339 340 u32 timedout_ctca, timedout_ctra; 341 342 /* List of overflow BOs used in the job that need to be 343 * released once the job is complete. 344 */ 345 struct list_head unref_list; 346 }; 347 348 struct v3d_tfu_job { 349 struct v3d_job base; 350 351 struct drm_v3d_submit_tfu args; 352 }; 353 354 struct v3d_csd_job { 355 struct v3d_job base; 356 357 u32 timedout_batches; 358 359 struct drm_v3d_submit_csd args; 360 }; 361 362 enum v3d_cpu_job_type { 363 V3D_CPU_JOB_TYPE_INDIRECT_CSD = 1, 364 V3D_CPU_JOB_TYPE_TIMESTAMP_QUERY, 365 V3D_CPU_JOB_TYPE_RESET_TIMESTAMP_QUERY, 366 V3D_CPU_JOB_TYPE_COPY_TIMESTAMP_QUERY, 367 V3D_CPU_JOB_TYPE_RESET_PERFORMANCE_QUERY, 368 V3D_CPU_JOB_TYPE_COPY_PERFORMANCE_QUERY, 369 }; 370 371 struct v3d_timestamp_query { 372 /* Offset of this query in the timestamp BO for its value. */ 373 u32 offset; 374 375 /* Syncobj that indicates the timestamp availability */ 376 struct drm_syncobj *syncobj; 377 }; 378 379 struct v3d_performance_query { 380 /* Performance monitor IDs for this query */ 381 u32 *kperfmon_ids; 382 383 /* Syncobj that indicates the query availability */ 384 struct drm_syncobj *syncobj; 385 }; 386 387 struct v3d_indirect_csd_info { 388 /* Indirect CSD */ 389 struct v3d_csd_job *job; 390 391 /* Clean cache job associated to the Indirect CSD job */ 392 struct v3d_job *clean_job; 393 394 /* Offset within the BO where the workgroup counts are stored */ 395 u32 offset; 396 397 /* Workgroups size */ 398 u32 wg_size; 399 400 /* Indices of the uniforms with the workgroup dispatch counts 401 * in the uniform stream. 402 */ 403 u32 wg_uniform_offsets[3]; 404 405 /* Indirect BO */ 406 struct drm_gem_object *indirect; 407 408 /* Context of the Indirect CSD job */ 409 struct ww_acquire_ctx acquire_ctx; 410 }; 411 412 struct v3d_timestamp_query_info { 413 struct v3d_timestamp_query *queries; 414 415 u32 count; 416 }; 417 418 struct v3d_performance_query_info { 419 struct v3d_performance_query *queries; 420 421 /* Number of performance queries */ 422 u32 count; 423 424 /* Number of performance monitors related to that query pool */ 425 u32 nperfmons; 426 427 /* Number of performance counters related to that query pool */ 428 u32 ncounters; 429 }; 430 431 struct v3d_copy_query_results_info { 432 /* Define if should write to buffer using 64 or 32 bits */ 433 bool do_64bit; 434 435 /* Define if it can write to buffer even if the query is not available */ 436 bool do_partial; 437 438 /* Define if it should write availability bit to buffer */ 439 bool availability_bit; 440 441 /* Offset of the copy buffer in the BO */ 442 u32 offset; 443 444 /* Stride of the copy buffer in the BO */ 445 u32 stride; 446 }; 447 448 struct v3d_cpu_job { 449 struct v3d_job base; 450 451 enum v3d_cpu_job_type job_type; 452 453 struct v3d_indirect_csd_info indirect_csd; 454 455 struct v3d_timestamp_query_info timestamp_query; 456 457 struct v3d_copy_query_results_info copy; 458 459 struct v3d_performance_query_info performance_query; 460 }; 461 462 typedef void (*v3d_cpu_job_fn)(struct v3d_cpu_job *); 463 464 struct v3d_submit_outsync { 465 struct drm_syncobj *syncobj; 466 }; 467 468 struct v3d_submit_ext { 469 u32 flags; 470 u32 wait_stage; 471 472 u32 in_sync_count; 473 u64 in_syncs; 474 475 u32 out_sync_count; 476 struct v3d_submit_outsync *out_syncs; 477 }; 478 479 /** 480 * __wait_for - magic wait macro 481 * 482 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's 483 * important that we check the condition again after having timed out, since the 484 * timeout could be due to preemption or similar and we've never had a chance to 485 * check the condition before the timeout. 486 */ 487 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \ 488 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \ 489 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \ 490 int ret__; \ 491 might_sleep(); \ 492 for (;;) { \ 493 const bool expired__ = ktime_after(ktime_get_raw(), end__); \ 494 OP; \ 495 /* Guarantee COND check prior to timeout */ \ 496 barrier(); \ 497 if (COND) { \ 498 ret__ = 0; \ 499 break; \ 500 } \ 501 if (expired__) { \ 502 ret__ = -ETIMEDOUT; \ 503 break; \ 504 } \ 505 usleep_range(wait__, wait__ * 2); \ 506 if (wait__ < (Wmax)) \ 507 wait__ <<= 1; \ 508 } \ 509 ret__; \ 510 }) 511 512 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \ 513 (Wmax)) 514 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000) 515 516 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) 517 { 518 /* nsecs_to_jiffies64() does not guard against overflow */ 519 if ((NSEC_PER_SEC % HZ) != 0 && 520 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ) 521 return MAX_JIFFY_OFFSET; 522 523 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); 524 } 525 526 /* v3d_bo.c */ 527 struct drm_gem_object *v3d_create_object(struct drm_device *dev, size_t size); 528 void v3d_free_object(struct drm_gem_object *gem_obj); 529 struct v3d_bo *v3d_bo_create(struct drm_device *dev, struct drm_file *file_priv, 530 size_t size); 531 void v3d_get_bo_vaddr(struct v3d_bo *bo); 532 void v3d_put_bo_vaddr(struct v3d_bo *bo); 533 int v3d_create_bo_ioctl(struct drm_device *dev, void *data, 534 struct drm_file *file_priv); 535 int v3d_mmap_bo_ioctl(struct drm_device *dev, void *data, 536 struct drm_file *file_priv); 537 int v3d_get_bo_offset_ioctl(struct drm_device *dev, void *data, 538 struct drm_file *file_priv); 539 int v3d_wait_bo_ioctl(struct drm_device *dev, void *data, 540 struct drm_file *file_priv); 541 struct drm_gem_object *v3d_prime_import_sg_table(struct drm_device *dev, 542 struct dma_buf_attachment *attach, 543 struct sg_table *sgt); 544 545 /* v3d_debugfs.c */ 546 void v3d_debugfs_init(struct drm_minor *minor); 547 548 /* v3d_drv.c */ 549 void v3d_get_stats(const struct v3d_stats *stats, u64 timestamp, 550 u64 *active_runtime, u64 *jobs_completed); 551 552 /* v3d_fence.c */ 553 extern const struct dma_fence_ops v3d_fence_ops; 554 struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue queue); 555 556 /* v3d_gem.c */ 557 int v3d_gem_init(struct drm_device *dev); 558 void v3d_gem_destroy(struct drm_device *dev); 559 void v3d_reset_sms(struct v3d_dev *v3d); 560 void v3d_reset(struct v3d_dev *v3d); 561 void v3d_invalidate_caches(struct v3d_dev *v3d); 562 void v3d_clean_caches(struct v3d_dev *v3d); 563 564 /* v3d_gemfs.c */ 565 extern bool super_pages; 566 void v3d_gemfs_init(struct v3d_dev *v3d); 567 void v3d_gemfs_fini(struct v3d_dev *v3d); 568 569 /* v3d_submit.c */ 570 void v3d_job_cleanup(struct v3d_job *job); 571 void v3d_job_put(struct v3d_job *job); 572 int v3d_submit_cl_ioctl(struct drm_device *dev, void *data, 573 struct drm_file *file_priv); 574 int v3d_submit_tfu_ioctl(struct drm_device *dev, void *data, 575 struct drm_file *file_priv); 576 int v3d_submit_csd_ioctl(struct drm_device *dev, void *data, 577 struct drm_file *file_priv); 578 int v3d_submit_cpu_ioctl(struct drm_device *dev, void *data, 579 struct drm_file *file_priv); 580 581 /* v3d_irq.c */ 582 int v3d_irq_init(struct v3d_dev *v3d); 583 void v3d_irq_enable(struct v3d_dev *v3d); 584 void v3d_irq_disable(struct v3d_dev *v3d); 585 void v3d_irq_reset(struct v3d_dev *v3d); 586 587 /* v3d_mmu.c */ 588 int v3d_mmu_flush_all(struct v3d_dev *v3d); 589 int v3d_mmu_set_page_table(struct v3d_dev *v3d); 590 void v3d_mmu_insert_ptes(struct v3d_bo *bo); 591 void v3d_mmu_remove_ptes(struct v3d_bo *bo); 592 593 /* v3d_sched.c */ 594 void v3d_timestamp_query_info_free(struct v3d_timestamp_query_info *query_info, 595 unsigned int count); 596 void v3d_performance_query_info_free(struct v3d_performance_query_info *query_info, 597 unsigned int count); 598 void v3d_job_update_stats(struct v3d_job *job, enum v3d_queue queue); 599 int v3d_sched_init(struct v3d_dev *v3d); 600 void v3d_sched_fini(struct v3d_dev *v3d); 601 602 /* v3d_perfmon.c */ 603 void v3d_perfmon_init(struct v3d_dev *v3d); 604 void v3d_perfmon_get(struct v3d_perfmon *perfmon); 605 void v3d_perfmon_put(struct v3d_perfmon *perfmon); 606 void v3d_perfmon_start(struct v3d_dev *v3d, struct v3d_perfmon *perfmon); 607 void v3d_perfmon_stop(struct v3d_dev *v3d, struct v3d_perfmon *perfmon, 608 bool capture); 609 struct v3d_perfmon *v3d_perfmon_find(struct v3d_file_priv *v3d_priv, int id); 610 void v3d_perfmon_open_file(struct v3d_file_priv *v3d_priv); 611 void v3d_perfmon_close_file(struct v3d_file_priv *v3d_priv); 612 int v3d_perfmon_create_ioctl(struct drm_device *dev, void *data, 613 struct drm_file *file_priv); 614 int v3d_perfmon_destroy_ioctl(struct drm_device *dev, void *data, 615 struct drm_file *file_priv); 616 int v3d_perfmon_get_values_ioctl(struct drm_device *dev, void *data, 617 struct drm_file *file_priv); 618 int v3d_perfmon_get_counter_ioctl(struct drm_device *dev, void *data, 619 struct drm_file *file_priv); 620 int v3d_perfmon_set_global_ioctl(struct drm_device *dev, void *data, 621 struct drm_file *file_priv); 622 623 /* v3d_sysfs.c */ 624 int v3d_sysfs_init(struct device *dev); 625 void v3d_sysfs_destroy(struct device *dev); 626