1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) Rockchip Electronics Co., Ltd. 4 * Zheng Yang <zhengyang@rock-chips.com> 5 * Yakir Yang <ykk@rock-chips.com> 6 */ 7 8 #include <linux/irq.h> 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/hdmi.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/mod_devicetable.h> 15 #include <linux/module.h> 16 #include <linux/mutex.h> 17 #include <linux/platform_device.h> 18 #include <linux/regmap.h> 19 20 #include <drm/drm_atomic.h> 21 #include <drm/drm_atomic_helper.h> 22 #include <drm/drm_edid.h> 23 #include <drm/drm_of.h> 24 #include <drm/drm_probe_helper.h> 25 #include <drm/drm_simple_kms_helper.h> 26 27 #include <drm/display/drm_hdmi_helper.h> 28 #include <drm/display/drm_hdmi_state_helper.h> 29 30 #include "rockchip_drm_drv.h" 31 32 #include "inno_hdmi.h" 33 34 #define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16) 35 36 #define INNO_HDMI_MIN_TMDS_CLOCK 25000000U 37 38 #define RK3036_GRF_SOC_CON2 0x148 39 #define RK3036_HDMI_PHSYNC BIT(4) 40 #define RK3036_HDMI_PVSYNC BIT(5) 41 42 enum inno_hdmi_dev_type { 43 RK3036_HDMI, 44 RK3128_HDMI, 45 }; 46 47 struct inno_hdmi_phy_config { 48 unsigned long pixelclock; 49 u8 pre_emphasis; 50 u8 voltage_level_control; 51 }; 52 53 struct inno_hdmi_variant { 54 enum inno_hdmi_dev_type dev_type; 55 struct inno_hdmi_phy_config *phy_configs; 56 struct inno_hdmi_phy_config *default_phy_config; 57 }; 58 59 struct inno_hdmi_i2c { 60 struct i2c_adapter adap; 61 62 u8 ddc_addr; 63 u8 segment_addr; 64 65 struct mutex lock; 66 struct completion cmp; 67 }; 68 69 struct inno_hdmi { 70 struct device *dev; 71 72 struct clk *pclk; 73 struct clk *refclk; 74 void __iomem *regs; 75 struct regmap *grf; 76 77 struct drm_connector connector; 78 struct rockchip_encoder encoder; 79 80 struct inno_hdmi_i2c *i2c; 81 struct i2c_adapter *ddc; 82 83 const struct inno_hdmi_variant *variant; 84 }; 85 86 struct inno_hdmi_connector_state { 87 struct drm_connector_state base; 88 unsigned int colorimetry; 89 }; 90 91 static struct inno_hdmi *encoder_to_inno_hdmi(struct drm_encoder *encoder) 92 { 93 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); 94 95 return container_of(rkencoder, struct inno_hdmi, encoder); 96 } 97 98 static struct inno_hdmi *connector_to_inno_hdmi(struct drm_connector *connector) 99 { 100 return container_of(connector, struct inno_hdmi, connector); 101 } 102 103 #define to_inno_hdmi_conn_state(conn_state) \ 104 container_of_const(conn_state, struct inno_hdmi_connector_state, base) 105 106 enum { 107 CSC_RGB_0_255_TO_ITU601_16_235_8BIT, 108 CSC_RGB_0_255_TO_ITU709_16_235_8BIT, 109 CSC_RGB_0_255_TO_RGB_16_235_8BIT, 110 }; 111 112 static const char coeff_csc[][24] = { 113 /* 114 * RGB2YUV:601 SD mode: 115 * Cb = -0.291G - 0.148R + 0.439B + 128 116 * Y = 0.504G + 0.257R + 0.098B + 16 117 * Cr = -0.368G + 0.439R - 0.071B + 128 118 */ 119 { 120 0x11, 0x5f, 0x01, 0x82, 0x10, 0x23, 0x00, 0x80, 121 0x02, 0x1c, 0x00, 0xa1, 0x00, 0x36, 0x00, 0x1e, 122 0x11, 0x29, 0x10, 0x59, 0x01, 0x82, 0x00, 0x80 123 }, 124 /* 125 * RGB2YUV:709 HD mode: 126 * Cb = - 0.338G - 0.101R + 0.439B + 128 127 * Y = 0.614G + 0.183R + 0.062B + 16 128 * Cr = - 0.399G + 0.439R - 0.040B + 128 129 */ 130 { 131 0x11, 0x98, 0x01, 0xc1, 0x10, 0x28, 0x00, 0x80, 132 0x02, 0x74, 0x00, 0xbb, 0x00, 0x3f, 0x00, 0x10, 133 0x11, 0x5a, 0x10, 0x67, 0x01, 0xc1, 0x00, 0x80 134 }, 135 /* 136 * RGB[0:255]2RGB[16:235]: 137 * R' = R x (235-16)/255 + 16; 138 * G' = G x (235-16)/255 + 16; 139 * B' = B x (235-16)/255 + 16; 140 */ 141 { 142 0x00, 0x00, 0x03, 0x6F, 0x00, 0x00, 0x00, 0x10, 143 0x03, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 144 0x00, 0x00, 0x00, 0x00, 0x03, 0x6F, 0x00, 0x10 145 }, 146 }; 147 148 static struct inno_hdmi_phy_config rk3036_hdmi_phy_configs[] = { 149 { 74250000, 0x3f, 0xbb }, 150 { 165000000, 0x6f, 0xbb }, 151 { ~0UL, 0x00, 0x00 } 152 }; 153 154 static struct inno_hdmi_phy_config rk3128_hdmi_phy_configs[] = { 155 { 74250000, 0x3f, 0xaa }, 156 { 165000000, 0x5f, 0xaa }, 157 { ~0UL, 0x00, 0x00 } 158 }; 159 160 static int inno_hdmi_find_phy_config(struct inno_hdmi *hdmi, 161 unsigned long pixelclk) 162 { 163 const struct inno_hdmi_phy_config *phy_configs = 164 hdmi->variant->phy_configs; 165 int i; 166 167 for (i = 0; phy_configs[i].pixelclock != ~0UL; i++) { 168 if (pixelclk <= phy_configs[i].pixelclock) 169 return i; 170 } 171 172 DRM_DEV_DEBUG(hdmi->dev, "No phy configuration for pixelclock %lu\n", 173 pixelclk); 174 175 return -EINVAL; 176 } 177 178 static inline u8 hdmi_readb(struct inno_hdmi *hdmi, u16 offset) 179 { 180 return readl_relaxed(hdmi->regs + (offset) * 0x04); 181 } 182 183 static inline void hdmi_writeb(struct inno_hdmi *hdmi, u16 offset, u32 val) 184 { 185 writel_relaxed(val, hdmi->regs + (offset) * 0x04); 186 } 187 188 static inline void hdmi_modb(struct inno_hdmi *hdmi, u16 offset, 189 u32 msk, u32 val) 190 { 191 u8 temp = hdmi_readb(hdmi, offset) & ~msk; 192 193 temp |= val & msk; 194 hdmi_writeb(hdmi, offset, temp); 195 } 196 197 static void inno_hdmi_i2c_init(struct inno_hdmi *hdmi, unsigned long long rate) 198 { 199 unsigned long long ddc_bus_freq = rate >> 2; 200 201 do_div(ddc_bus_freq, HDMI_SCL_RATE); 202 203 hdmi_writeb(hdmi, DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF); 204 hdmi_writeb(hdmi, DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF); 205 206 /* Clear the EDID interrupt flag and mute the interrupt */ 207 hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0); 208 hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY); 209 } 210 211 static void inno_hdmi_sys_power(struct inno_hdmi *hdmi, bool enable) 212 { 213 if (enable) 214 hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_ON); 215 else 216 hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_OFF); 217 } 218 219 static void inno_hdmi_standby(struct inno_hdmi *hdmi) 220 { 221 inno_hdmi_sys_power(hdmi, false); 222 223 hdmi_writeb(hdmi, HDMI_PHY_DRIVER, 0x00); 224 hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, 0x00); 225 hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x00); 226 hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15); 227 }; 228 229 static void inno_hdmi_power_up(struct inno_hdmi *hdmi, 230 unsigned long mpixelclock) 231 { 232 struct inno_hdmi_phy_config *phy_config; 233 int ret = inno_hdmi_find_phy_config(hdmi, mpixelclock); 234 235 if (ret < 0) { 236 phy_config = hdmi->variant->default_phy_config; 237 DRM_DEV_ERROR(hdmi->dev, 238 "Using default phy configuration for TMDS rate %lu", 239 mpixelclock); 240 } else { 241 phy_config = &hdmi->variant->phy_configs[ret]; 242 } 243 244 inno_hdmi_sys_power(hdmi, false); 245 246 hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, phy_config->pre_emphasis); 247 hdmi_writeb(hdmi, HDMI_PHY_DRIVER, phy_config->voltage_level_control); 248 hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15); 249 hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x14); 250 hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x10); 251 hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x0f); 252 hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x00); 253 hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x01); 254 255 inno_hdmi_sys_power(hdmi, true); 256 }; 257 258 static void inno_hdmi_reset(struct inno_hdmi *hdmi) 259 { 260 u32 val; 261 u32 msk; 262 263 hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_DIGITAL, v_NOT_RST_DIGITAL); 264 udelay(100); 265 266 hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_ANALOG, v_NOT_RST_ANALOG); 267 udelay(100); 268 269 msk = m_REG_CLK_INV | m_REG_CLK_SOURCE | m_POWER | m_INT_POL; 270 val = v_REG_CLK_INV | v_REG_CLK_SOURCE_SYS | v_PWR_ON | v_INT_POL_HIGH; 271 hdmi_modb(hdmi, HDMI_SYS_CTRL, msk, val); 272 273 inno_hdmi_standby(hdmi); 274 } 275 276 static int inno_hdmi_disable_frame(struct drm_connector *connector, 277 enum hdmi_infoframe_type type) 278 { 279 struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector); 280 281 if (type != HDMI_INFOFRAME_TYPE_AVI) { 282 drm_err(connector->dev, 283 "Unsupported infoframe type: %u\n", type); 284 return 0; 285 } 286 287 hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_BUF_INDEX, INFOFRAME_AVI); 288 289 return 0; 290 } 291 292 static int inno_hdmi_upload_frame(struct drm_connector *connector, 293 enum hdmi_infoframe_type type, 294 const u8 *buffer, size_t len) 295 { 296 struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector); 297 ssize_t i; 298 299 if (type != HDMI_INFOFRAME_TYPE_AVI) { 300 drm_err(connector->dev, 301 "Unsupported infoframe type: %u\n", type); 302 return 0; 303 } 304 305 inno_hdmi_disable_frame(connector, type); 306 307 for (i = 0; i < len; i++) 308 hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_ADDR + i, buffer[i]); 309 310 return 0; 311 } 312 313 static const struct drm_connector_hdmi_funcs inno_hdmi_hdmi_connector_funcs = { 314 .clear_infoframe = inno_hdmi_disable_frame, 315 .write_infoframe = inno_hdmi_upload_frame, 316 }; 317 318 static int inno_hdmi_config_video_csc(struct inno_hdmi *hdmi) 319 { 320 struct drm_connector *connector = &hdmi->connector; 321 struct drm_connector_state *conn_state = connector->state; 322 struct inno_hdmi_connector_state *inno_conn_state = 323 to_inno_hdmi_conn_state(conn_state); 324 int c0_c2_change = 0; 325 int csc_enable = 0; 326 int csc_mode = 0; 327 int auto_csc = 0; 328 int value; 329 int i; 330 331 /* Input video mode is SDR RGB24bit, data enable signal from external */ 332 hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL1, v_DE_EXTERNAL | 333 v_VIDEO_INPUT_FORMAT(VIDEO_INPUT_SDR_RGB444)); 334 335 /* Input color hardcode to RGB, and output color hardcode to RGB888 */ 336 value = v_VIDEO_INPUT_BITS(VIDEO_INPUT_8BITS) | 337 v_VIDEO_OUTPUT_COLOR(0) | 338 v_VIDEO_INPUT_CSP(0); 339 hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL2, value); 340 341 if (conn_state->hdmi.output_format == HDMI_COLORSPACE_RGB) { 342 if (conn_state->hdmi.is_limited_range) { 343 csc_mode = CSC_RGB_0_255_TO_RGB_16_235_8BIT; 344 auto_csc = AUTO_CSC_DISABLE; 345 c0_c2_change = C0_C2_CHANGE_DISABLE; 346 csc_enable = v_CSC_ENABLE; 347 348 } else { 349 value = v_SOF_DISABLE | v_COLOR_DEPTH_NOT_INDICATED(1); 350 hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value); 351 352 hdmi_modb(hdmi, HDMI_VIDEO_CONTRL, 353 m_VIDEO_AUTO_CSC | m_VIDEO_C0_C2_SWAP, 354 v_VIDEO_AUTO_CSC(AUTO_CSC_DISABLE) | 355 v_VIDEO_C0_C2_SWAP(C0_C2_CHANGE_DISABLE)); 356 return 0; 357 } 358 } else { 359 if (inno_conn_state->colorimetry == HDMI_COLORIMETRY_ITU_601) { 360 if (conn_state->hdmi.output_format == HDMI_COLORSPACE_YUV444) { 361 csc_mode = CSC_RGB_0_255_TO_ITU601_16_235_8BIT; 362 auto_csc = AUTO_CSC_DISABLE; 363 c0_c2_change = C0_C2_CHANGE_DISABLE; 364 csc_enable = v_CSC_ENABLE; 365 } 366 } else { 367 if (conn_state->hdmi.output_format == HDMI_COLORSPACE_YUV444) { 368 csc_mode = CSC_RGB_0_255_TO_ITU709_16_235_8BIT; 369 auto_csc = AUTO_CSC_DISABLE; 370 c0_c2_change = C0_C2_CHANGE_DISABLE; 371 csc_enable = v_CSC_ENABLE; 372 } 373 } 374 } 375 376 for (i = 0; i < 24; i++) 377 hdmi_writeb(hdmi, HDMI_VIDEO_CSC_COEF + i, 378 coeff_csc[csc_mode][i]); 379 380 value = v_SOF_DISABLE | csc_enable | v_COLOR_DEPTH_NOT_INDICATED(1); 381 hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value); 382 hdmi_modb(hdmi, HDMI_VIDEO_CONTRL, m_VIDEO_AUTO_CSC | 383 m_VIDEO_C0_C2_SWAP, v_VIDEO_AUTO_CSC(auto_csc) | 384 v_VIDEO_C0_C2_SWAP(c0_c2_change)); 385 386 return 0; 387 } 388 389 static int inno_hdmi_config_video_timing(struct inno_hdmi *hdmi, 390 struct drm_display_mode *mode) 391 { 392 int value, psync; 393 394 if (hdmi->variant->dev_type == RK3036_HDMI) { 395 psync = mode->flags & DRM_MODE_FLAG_PHSYNC ? RK3036_HDMI_PHSYNC : 0; 396 value = HIWORD_UPDATE(psync, RK3036_HDMI_PHSYNC); 397 psync = mode->flags & DRM_MODE_FLAG_PVSYNC ? RK3036_HDMI_PVSYNC : 0; 398 value |= HIWORD_UPDATE(psync, RK3036_HDMI_PVSYNC); 399 regmap_write(hdmi->grf, RK3036_GRF_SOC_CON2, value); 400 } 401 402 /* Set detail external video timing polarity and interlace mode */ 403 value = v_EXTERANL_VIDEO(1); 404 value |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 405 v_HSYNC_POLARITY(1) : v_HSYNC_POLARITY(0); 406 value |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 407 v_VSYNC_POLARITY(1) : v_VSYNC_POLARITY(0); 408 value |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 409 v_INETLACE(1) : v_INETLACE(0); 410 hdmi_writeb(hdmi, HDMI_VIDEO_TIMING_CTL, value); 411 412 /* Set detail external video timing */ 413 value = mode->htotal; 414 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_L, value & 0xFF); 415 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_H, (value >> 8) & 0xFF); 416 417 value = mode->htotal - mode->hdisplay; 418 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_L, value & 0xFF); 419 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_H, (value >> 8) & 0xFF); 420 421 value = mode->htotal - mode->hsync_start; 422 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_L, value & 0xFF); 423 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_H, (value >> 8) & 0xFF); 424 425 value = mode->hsync_end - mode->hsync_start; 426 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_L, value & 0xFF); 427 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_H, (value >> 8) & 0xFF); 428 429 value = mode->vtotal; 430 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_L, value & 0xFF); 431 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_H, (value >> 8) & 0xFF); 432 433 value = mode->vtotal - mode->vdisplay; 434 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VBLANK, value & 0xFF); 435 436 value = mode->vtotal - mode->vsync_start; 437 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDELAY, value & 0xFF); 438 439 value = mode->vsync_end - mode->vsync_start; 440 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDURATION, value & 0xFF); 441 442 hdmi_writeb(hdmi, HDMI_PHY_PRE_DIV_RATIO, 0x1e); 443 hdmi_writeb(hdmi, HDMI_PHY_FEEDBACK_DIV_RATIO_LOW, 0x2c); 444 hdmi_writeb(hdmi, HDMI_PHY_FEEDBACK_DIV_RATIO_HIGH, 0x01); 445 446 return 0; 447 } 448 449 static int inno_hdmi_setup(struct inno_hdmi *hdmi, 450 struct drm_atomic_state *state) 451 { 452 struct drm_connector *connector = &hdmi->connector; 453 struct drm_display_info *display = &connector->display_info; 454 struct drm_connector_state *new_conn_state; 455 struct drm_crtc_state *new_crtc_state; 456 457 new_conn_state = drm_atomic_get_new_connector_state(state, connector); 458 if (WARN_ON(!new_conn_state)) 459 return -EINVAL; 460 461 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); 462 if (WARN_ON(!new_crtc_state)) 463 return -EINVAL; 464 465 /* Mute video and audio output */ 466 hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK, 467 v_AUDIO_MUTE(1) | v_VIDEO_MUTE(1)); 468 469 /* Set HDMI Mode */ 470 hdmi_writeb(hdmi, HDMI_HDCP_CTRL, 471 v_HDMI_DVI(display->is_hdmi)); 472 473 inno_hdmi_config_video_timing(hdmi, &new_crtc_state->adjusted_mode); 474 475 inno_hdmi_config_video_csc(hdmi); 476 477 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); 478 479 /* 480 * When IP controller have configured to an accurate video 481 * timing, then the TMDS clock source would be switched to 482 * DCLK_LCDC, so we need to init the TMDS rate to mode pixel 483 * clock rate, and reconfigure the DDC clock. 484 */ 485 inno_hdmi_i2c_init(hdmi, new_conn_state->hdmi.tmds_char_rate); 486 487 /* Unmute video and audio output */ 488 hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK, 489 v_AUDIO_MUTE(0) | v_VIDEO_MUTE(0)); 490 491 inno_hdmi_power_up(hdmi, new_conn_state->hdmi.tmds_char_rate); 492 493 return 0; 494 } 495 496 static enum drm_mode_status inno_hdmi_display_mode_valid(struct inno_hdmi *hdmi, 497 const struct drm_display_mode *mode) 498 { 499 unsigned long mpixelclk, max_tolerance; 500 long rounded_refclk; 501 502 /* No support for double-clock modes */ 503 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 504 return MODE_BAD; 505 506 mpixelclk = mode->clock * 1000; 507 508 if (mpixelclk < INNO_HDMI_MIN_TMDS_CLOCK) 509 return MODE_CLOCK_LOW; 510 511 if (inno_hdmi_find_phy_config(hdmi, mpixelclk) < 0) 512 return MODE_CLOCK_HIGH; 513 514 if (hdmi->refclk) { 515 rounded_refclk = clk_round_rate(hdmi->refclk, mpixelclk); 516 if (rounded_refclk < 0) 517 return MODE_BAD; 518 519 /* Vesa DMT standard mentions +/- 0.5% max tolerance */ 520 max_tolerance = mpixelclk / 200; 521 if (abs_diff((unsigned long)rounded_refclk, mpixelclk) > max_tolerance) 522 return MODE_NOCLOCK; 523 } 524 525 return MODE_OK; 526 } 527 528 static void inno_hdmi_encoder_enable(struct drm_encoder *encoder, 529 struct drm_atomic_state *state) 530 { 531 struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder); 532 533 inno_hdmi_setup(hdmi, state); 534 } 535 536 static void inno_hdmi_encoder_disable(struct drm_encoder *encoder, 537 struct drm_atomic_state *state) 538 { 539 struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder); 540 541 inno_hdmi_standby(hdmi); 542 } 543 544 static int 545 inno_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 546 struct drm_crtc_state *crtc_state, 547 struct drm_connector_state *conn_state) 548 { 549 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); 550 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 551 u8 vic = drm_match_cea_mode(mode); 552 struct inno_hdmi_connector_state *inno_conn_state = 553 to_inno_hdmi_conn_state(conn_state); 554 555 s->output_mode = ROCKCHIP_OUT_MODE_P888; 556 s->output_type = DRM_MODE_CONNECTOR_HDMIA; 557 558 if (vic == 6 || vic == 7 || 559 vic == 21 || vic == 22 || 560 vic == 2 || vic == 3 || 561 vic == 17 || vic == 18) 562 inno_conn_state->colorimetry = HDMI_COLORIMETRY_ITU_601; 563 else 564 inno_conn_state->colorimetry = HDMI_COLORIMETRY_ITU_709; 565 566 return 0; 567 } 568 569 static const struct drm_encoder_helper_funcs inno_hdmi_encoder_helper_funcs = { 570 .atomic_check = inno_hdmi_encoder_atomic_check, 571 .atomic_enable = inno_hdmi_encoder_enable, 572 .atomic_disable = inno_hdmi_encoder_disable, 573 }; 574 575 static enum drm_connector_status 576 inno_hdmi_connector_detect(struct drm_connector *connector, bool force) 577 { 578 struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector); 579 580 return (hdmi_readb(hdmi, HDMI_STATUS) & m_HOTPLUG) ? 581 connector_status_connected : connector_status_disconnected; 582 } 583 584 static int inno_hdmi_connector_get_modes(struct drm_connector *connector) 585 { 586 struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector); 587 const struct drm_edid *drm_edid; 588 int ret = 0; 589 590 if (!hdmi->ddc) 591 return 0; 592 593 drm_edid = drm_edid_read_ddc(connector, hdmi->ddc); 594 drm_edid_connector_update(connector, drm_edid); 595 ret = drm_edid_connector_add_modes(connector); 596 drm_edid_free(drm_edid); 597 598 return ret; 599 } 600 601 static enum drm_mode_status 602 inno_hdmi_connector_mode_valid(struct drm_connector *connector, 603 const struct drm_display_mode *mode) 604 { 605 struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector); 606 607 return inno_hdmi_display_mode_valid(hdmi, mode); 608 } 609 610 static void 611 inno_hdmi_connector_destroy_state(struct drm_connector *connector, 612 struct drm_connector_state *state) 613 { 614 struct inno_hdmi_connector_state *inno_conn_state = 615 to_inno_hdmi_conn_state(state); 616 617 __drm_atomic_helper_connector_destroy_state(&inno_conn_state->base); 618 kfree(inno_conn_state); 619 } 620 621 static void inno_hdmi_connector_reset(struct drm_connector *connector) 622 { 623 struct inno_hdmi_connector_state *inno_conn_state; 624 625 if (connector->state) { 626 inno_hdmi_connector_destroy_state(connector, connector->state); 627 connector->state = NULL; 628 } 629 630 inno_conn_state = kzalloc(sizeof(*inno_conn_state), GFP_KERNEL); 631 if (!inno_conn_state) 632 return; 633 634 __drm_atomic_helper_connector_reset(connector, &inno_conn_state->base); 635 __drm_atomic_helper_connector_hdmi_reset(connector, connector->state); 636 637 inno_conn_state->colorimetry = HDMI_COLORIMETRY_ITU_709; 638 } 639 640 static struct drm_connector_state * 641 inno_hdmi_connector_duplicate_state(struct drm_connector *connector) 642 { 643 struct inno_hdmi_connector_state *inno_conn_state; 644 645 if (WARN_ON(!connector->state)) 646 return NULL; 647 648 inno_conn_state = kmemdup(to_inno_hdmi_conn_state(connector->state), 649 sizeof(*inno_conn_state), GFP_KERNEL); 650 651 if (!inno_conn_state) 652 return NULL; 653 654 __drm_atomic_helper_connector_duplicate_state(connector, 655 &inno_conn_state->base); 656 657 return &inno_conn_state->base; 658 } 659 660 static const struct drm_connector_funcs inno_hdmi_connector_funcs = { 661 .fill_modes = drm_helper_probe_single_connector_modes, 662 .detect = inno_hdmi_connector_detect, 663 .reset = inno_hdmi_connector_reset, 664 .atomic_duplicate_state = inno_hdmi_connector_duplicate_state, 665 .atomic_destroy_state = inno_hdmi_connector_destroy_state, 666 }; 667 668 static struct drm_connector_helper_funcs inno_hdmi_connector_helper_funcs = { 669 .atomic_check = drm_atomic_helper_connector_hdmi_check, 670 .get_modes = inno_hdmi_connector_get_modes, 671 .mode_valid = inno_hdmi_connector_mode_valid, 672 }; 673 674 static int inno_hdmi_register(struct drm_device *drm, struct inno_hdmi *hdmi) 675 { 676 struct drm_encoder *encoder = &hdmi->encoder.encoder; 677 struct device *dev = hdmi->dev; 678 679 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); 680 681 /* 682 * If we failed to find the CRTC(s) which this encoder is 683 * supposed to be connected to, it's because the CRTC has 684 * not been registered yet. Defer probing, and hope that 685 * the required CRTC is added later. 686 */ 687 if (encoder->possible_crtcs == 0) 688 return -EPROBE_DEFER; 689 690 drm_encoder_helper_add(encoder, &inno_hdmi_encoder_helper_funcs); 691 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); 692 693 hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD; 694 695 drm_connector_helper_add(&hdmi->connector, 696 &inno_hdmi_connector_helper_funcs); 697 drmm_connector_hdmi_init(drm, &hdmi->connector, 698 "Rockchip", "Inno HDMI", 699 &inno_hdmi_connector_funcs, 700 &inno_hdmi_hdmi_connector_funcs, 701 DRM_MODE_CONNECTOR_HDMIA, 702 hdmi->ddc, 703 BIT(HDMI_COLORSPACE_RGB), 704 8); 705 706 drm_connector_attach_encoder(&hdmi->connector, encoder); 707 708 return 0; 709 } 710 711 static irqreturn_t inno_hdmi_i2c_irq(struct inno_hdmi *hdmi) 712 { 713 struct inno_hdmi_i2c *i2c = hdmi->i2c; 714 u8 stat; 715 716 stat = hdmi_readb(hdmi, HDMI_INTERRUPT_STATUS1); 717 if (!(stat & m_INT_EDID_READY)) 718 return IRQ_NONE; 719 720 /* Clear HDMI EDID interrupt flag */ 721 hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY); 722 723 complete(&i2c->cmp); 724 725 return IRQ_HANDLED; 726 } 727 728 static irqreturn_t inno_hdmi_hardirq(int irq, void *dev_id) 729 { 730 struct inno_hdmi *hdmi = dev_id; 731 irqreturn_t ret = IRQ_NONE; 732 u8 interrupt; 733 734 if (hdmi->i2c) 735 ret = inno_hdmi_i2c_irq(hdmi); 736 737 interrupt = hdmi_readb(hdmi, HDMI_STATUS); 738 if (interrupt & m_INT_HOTPLUG) { 739 hdmi_modb(hdmi, HDMI_STATUS, m_INT_HOTPLUG, m_INT_HOTPLUG); 740 ret = IRQ_WAKE_THREAD; 741 } 742 743 return ret; 744 } 745 746 static irqreturn_t inno_hdmi_irq(int irq, void *dev_id) 747 { 748 struct inno_hdmi *hdmi = dev_id; 749 750 drm_helper_hpd_irq_event(hdmi->connector.dev); 751 752 return IRQ_HANDLED; 753 } 754 755 static int inno_hdmi_i2c_read(struct inno_hdmi *hdmi, struct i2c_msg *msgs) 756 { 757 int length = msgs->len; 758 u8 *buf = msgs->buf; 759 int ret; 760 761 ret = wait_for_completion_timeout(&hdmi->i2c->cmp, HZ / 10); 762 if (!ret) 763 return -EAGAIN; 764 765 while (length--) 766 *buf++ = hdmi_readb(hdmi, HDMI_EDID_FIFO_ADDR); 767 768 return 0; 769 } 770 771 static int inno_hdmi_i2c_write(struct inno_hdmi *hdmi, struct i2c_msg *msgs) 772 { 773 /* 774 * The DDC module only support read EDID message, so 775 * we assume that each word write to this i2c adapter 776 * should be the offset of EDID word address. 777 */ 778 if ((msgs->len != 1) || 779 ((msgs->addr != DDC_ADDR) && (msgs->addr != DDC_SEGMENT_ADDR))) 780 return -EINVAL; 781 782 reinit_completion(&hdmi->i2c->cmp); 783 784 if (msgs->addr == DDC_SEGMENT_ADDR) 785 hdmi->i2c->segment_addr = msgs->buf[0]; 786 if (msgs->addr == DDC_ADDR) 787 hdmi->i2c->ddc_addr = msgs->buf[0]; 788 789 /* Set edid fifo first addr */ 790 hdmi_writeb(hdmi, HDMI_EDID_FIFO_OFFSET, 0x00); 791 792 /* Set edid word address 0x00/0x80 */ 793 hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr); 794 795 /* Set edid segment pointer */ 796 hdmi_writeb(hdmi, HDMI_EDID_SEGMENT_POINTER, hdmi->i2c->segment_addr); 797 798 return 0; 799 } 800 801 static int inno_hdmi_i2c_xfer(struct i2c_adapter *adap, 802 struct i2c_msg *msgs, int num) 803 { 804 struct inno_hdmi *hdmi = i2c_get_adapdata(adap); 805 struct inno_hdmi_i2c *i2c = hdmi->i2c; 806 int i, ret = 0; 807 808 mutex_lock(&i2c->lock); 809 810 /* Clear the EDID interrupt flag and unmute the interrupt */ 811 hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, m_INT_EDID_READY); 812 hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY); 813 814 for (i = 0; i < num; i++) { 815 DRM_DEV_DEBUG(hdmi->dev, 816 "xfer: num: %d/%d, len: %d, flags: %#x\n", 817 i + 1, num, msgs[i].len, msgs[i].flags); 818 819 if (msgs[i].flags & I2C_M_RD) 820 ret = inno_hdmi_i2c_read(hdmi, &msgs[i]); 821 else 822 ret = inno_hdmi_i2c_write(hdmi, &msgs[i]); 823 824 if (ret < 0) 825 break; 826 } 827 828 if (!ret) 829 ret = num; 830 831 /* Mute HDMI EDID interrupt */ 832 hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0); 833 834 mutex_unlock(&i2c->lock); 835 836 return ret; 837 } 838 839 static u32 inno_hdmi_i2c_func(struct i2c_adapter *adapter) 840 { 841 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 842 } 843 844 static const struct i2c_algorithm inno_hdmi_algorithm = { 845 .master_xfer = inno_hdmi_i2c_xfer, 846 .functionality = inno_hdmi_i2c_func, 847 }; 848 849 static struct i2c_adapter *inno_hdmi_i2c_adapter(struct inno_hdmi *hdmi) 850 { 851 struct i2c_adapter *adap; 852 struct inno_hdmi_i2c *i2c; 853 int ret; 854 855 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); 856 if (!i2c) 857 return ERR_PTR(-ENOMEM); 858 859 mutex_init(&i2c->lock); 860 init_completion(&i2c->cmp); 861 862 adap = &i2c->adap; 863 adap->owner = THIS_MODULE; 864 adap->dev.parent = hdmi->dev; 865 adap->dev.of_node = hdmi->dev->of_node; 866 adap->algo = &inno_hdmi_algorithm; 867 strscpy(adap->name, "Inno HDMI", sizeof(adap->name)); 868 i2c_set_adapdata(adap, hdmi); 869 870 ret = i2c_add_adapter(adap); 871 if (ret) { 872 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); 873 devm_kfree(hdmi->dev, i2c); 874 return ERR_PTR(ret); 875 } 876 877 hdmi->i2c = i2c; 878 879 DRM_DEV_INFO(hdmi->dev, "registered %s I2C bus driver\n", adap->name); 880 881 return adap; 882 } 883 884 static int inno_hdmi_bind(struct device *dev, struct device *master, 885 void *data) 886 { 887 struct platform_device *pdev = to_platform_device(dev); 888 struct drm_device *drm = data; 889 struct inno_hdmi *hdmi; 890 const struct inno_hdmi_variant *variant; 891 int irq; 892 int ret; 893 894 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 895 if (!hdmi) 896 return -ENOMEM; 897 898 hdmi->dev = dev; 899 900 variant = of_device_get_match_data(hdmi->dev); 901 if (!variant) 902 return -EINVAL; 903 904 hdmi->variant = variant; 905 906 hdmi->regs = devm_platform_ioremap_resource(pdev, 0); 907 if (IS_ERR(hdmi->regs)) 908 return PTR_ERR(hdmi->regs); 909 910 hdmi->pclk = devm_clk_get(hdmi->dev, "pclk"); 911 if (IS_ERR(hdmi->pclk)) 912 return dev_err_probe(dev, PTR_ERR(hdmi->pclk), "Unable to get HDMI pclk\n"); 913 914 ret = clk_prepare_enable(hdmi->pclk); 915 if (ret) 916 return dev_err_probe(dev, ret, "Cannot enable HDMI pclk: %d\n", ret); 917 918 hdmi->refclk = devm_clk_get_optional(hdmi->dev, "ref"); 919 if (IS_ERR(hdmi->refclk)) { 920 ret = dev_err_probe(dev, PTR_ERR(hdmi->refclk), "Unable to get HDMI refclk\n"); 921 goto err_disable_pclk; 922 } 923 924 ret = clk_prepare_enable(hdmi->refclk); 925 if (ret) { 926 ret = dev_err_probe(dev, ret, "Cannot enable HDMI refclk: %d\n", ret); 927 goto err_disable_pclk; 928 } 929 930 if (hdmi->variant->dev_type == RK3036_HDMI) { 931 hdmi->grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf"); 932 if (IS_ERR(hdmi->grf)) { 933 ret = dev_err_probe(dev, PTR_ERR(hdmi->grf), 934 "Unable to get rockchip,grf\n"); 935 goto err_disable_clk; 936 } 937 } 938 939 irq = platform_get_irq(pdev, 0); 940 if (irq < 0) { 941 ret = irq; 942 goto err_disable_clk; 943 } 944 945 inno_hdmi_reset(hdmi); 946 947 hdmi->ddc = inno_hdmi_i2c_adapter(hdmi); 948 if (IS_ERR(hdmi->ddc)) { 949 ret = PTR_ERR(hdmi->ddc); 950 hdmi->ddc = NULL; 951 goto err_disable_clk; 952 } 953 954 /* 955 * When the controller isn't configured to an accurate 956 * video timing and there is no reference clock available, 957 * then the TMDS clock source would be switched to PCLK_HDMI, 958 * so we need to init the TMDS rate to PCLK rate, and 959 * reconfigure the DDC clock. 960 */ 961 if (hdmi->refclk) 962 inno_hdmi_i2c_init(hdmi, clk_get_rate(hdmi->refclk)); 963 else 964 inno_hdmi_i2c_init(hdmi, clk_get_rate(hdmi->pclk)); 965 966 ret = inno_hdmi_register(drm, hdmi); 967 if (ret) 968 goto err_put_adapter; 969 970 dev_set_drvdata(dev, hdmi); 971 972 /* Unmute hotplug interrupt */ 973 hdmi_modb(hdmi, HDMI_STATUS, m_MASK_INT_HOTPLUG, v_MASK_INT_HOTPLUG(1)); 974 975 ret = devm_request_threaded_irq(dev, irq, inno_hdmi_hardirq, 976 inno_hdmi_irq, IRQF_SHARED, 977 dev_name(dev), hdmi); 978 if (ret < 0) 979 goto err_cleanup_hdmi; 980 981 return 0; 982 err_cleanup_hdmi: 983 hdmi->connector.funcs->destroy(&hdmi->connector); 984 hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); 985 err_put_adapter: 986 i2c_put_adapter(hdmi->ddc); 987 err_disable_clk: 988 clk_disable_unprepare(hdmi->refclk); 989 err_disable_pclk: 990 clk_disable_unprepare(hdmi->pclk); 991 return ret; 992 } 993 994 static void inno_hdmi_unbind(struct device *dev, struct device *master, 995 void *data) 996 { 997 struct inno_hdmi *hdmi = dev_get_drvdata(dev); 998 999 hdmi->connector.funcs->destroy(&hdmi->connector); 1000 hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); 1001 1002 i2c_put_adapter(hdmi->ddc); 1003 clk_disable_unprepare(hdmi->refclk); 1004 clk_disable_unprepare(hdmi->pclk); 1005 } 1006 1007 static const struct component_ops inno_hdmi_ops = { 1008 .bind = inno_hdmi_bind, 1009 .unbind = inno_hdmi_unbind, 1010 }; 1011 1012 static int inno_hdmi_probe(struct platform_device *pdev) 1013 { 1014 return component_add(&pdev->dev, &inno_hdmi_ops); 1015 } 1016 1017 static void inno_hdmi_remove(struct platform_device *pdev) 1018 { 1019 component_del(&pdev->dev, &inno_hdmi_ops); 1020 } 1021 1022 static const struct inno_hdmi_variant rk3036_inno_hdmi_variant = { 1023 .dev_type = RK3036_HDMI, 1024 .phy_configs = rk3036_hdmi_phy_configs, 1025 .default_phy_config = &rk3036_hdmi_phy_configs[1], 1026 }; 1027 1028 static const struct inno_hdmi_variant rk3128_inno_hdmi_variant = { 1029 .dev_type = RK3128_HDMI, 1030 .phy_configs = rk3128_hdmi_phy_configs, 1031 .default_phy_config = &rk3128_hdmi_phy_configs[1], 1032 }; 1033 1034 static const struct of_device_id inno_hdmi_dt_ids[] = { 1035 { .compatible = "rockchip,rk3036-inno-hdmi", 1036 .data = &rk3036_inno_hdmi_variant, 1037 }, 1038 { .compatible = "rockchip,rk3128-inno-hdmi", 1039 .data = &rk3128_inno_hdmi_variant, 1040 }, 1041 {}, 1042 }; 1043 MODULE_DEVICE_TABLE(of, inno_hdmi_dt_ids); 1044 1045 struct platform_driver inno_hdmi_driver = { 1046 .probe = inno_hdmi_probe, 1047 .remove = inno_hdmi_remove, 1048 .driver = { 1049 .name = "innohdmi-rockchip", 1050 .of_match_table = inno_hdmi_dt_ids, 1051 }, 1052 }; 1053