1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Christian König. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Christian König 25 */ 26 #include <linux/hdmi.h> 27 #include <linux/gcd.h> 28 29 #include <drm/radeon_drm.h> 30 #include "radeon.h" 31 #include "radeon_asic.h" 32 #include "radeon_audio.h" 33 #include "r600.h" 34 #include "r600d.h" 35 #include "atom.h" 36 37 /* 38 * HDMI color format 39 */ 40 enum r600_hdmi_color_format { 41 RGB = 0, 42 YCC_422 = 1, 43 YCC_444 = 2 44 }; 45 46 /* 47 * IEC60958 status bits 48 */ 49 enum r600_hdmi_iec_status_bits { 50 AUDIO_STATUS_DIG_ENABLE = 0x01, 51 AUDIO_STATUS_V = 0x02, 52 AUDIO_STATUS_VCFG = 0x04, 53 AUDIO_STATUS_EMPHASIS = 0x08, 54 AUDIO_STATUS_COPYRIGHT = 0x10, 55 AUDIO_STATUS_NONAUDIO = 0x20, 56 AUDIO_STATUS_PROFESSIONAL = 0x40, 57 AUDIO_STATUS_LEVEL = 0x80 58 }; 59 60 static struct r600_audio_pin r600_audio_status(struct radeon_device *rdev) 61 { 62 struct r600_audio_pin status = {}; 63 uint32_t value; 64 65 value = RREG32(R600_AUDIO_RATE_BPS_CHANNEL); 66 67 /* number of channels */ 68 status.channels = (value & 0x7) + 1; 69 70 /* bits per sample */ 71 switch ((value & 0xF0) >> 4) { 72 case 0x0: 73 status.bits_per_sample = 8; 74 break; 75 case 0x1: 76 status.bits_per_sample = 16; 77 break; 78 case 0x2: 79 status.bits_per_sample = 20; 80 break; 81 case 0x3: 82 status.bits_per_sample = 24; 83 break; 84 case 0x4: 85 status.bits_per_sample = 32; 86 break; 87 default: 88 dev_err(rdev->dev, "Unknown bits per sample 0x%x, using 16\n", 89 (int)value); 90 status.bits_per_sample = 16; 91 } 92 93 /* current sampling rate in HZ */ 94 if (value & 0x4000) 95 status.rate = 44100; 96 else 97 status.rate = 48000; 98 status.rate *= ((value >> 11) & 0x7) + 1; 99 status.rate /= ((value >> 8) & 0x7) + 1; 100 101 value = RREG32(R600_AUDIO_STATUS_BITS); 102 103 /* iec 60958 status bits */ 104 status.status_bits = value & 0xff; 105 106 /* iec 60958 category code */ 107 status.category_code = (value >> 8) & 0xff; 108 109 return status; 110 } 111 112 /* 113 * update all hdmi interfaces with current audio parameters 114 */ 115 void r600_audio_update_hdmi(struct work_struct *work) 116 { 117 struct radeon_device *rdev = container_of(work, struct radeon_device, 118 audio_work); 119 struct drm_device *dev = rdev_to_drm(rdev); 120 struct r600_audio_pin audio_status = r600_audio_status(rdev); 121 struct drm_encoder *encoder; 122 bool changed = false; 123 124 if (rdev->audio.pin[0].channels != audio_status.channels || 125 rdev->audio.pin[0].rate != audio_status.rate || 126 rdev->audio.pin[0].bits_per_sample != audio_status.bits_per_sample || 127 rdev->audio.pin[0].status_bits != audio_status.status_bits || 128 rdev->audio.pin[0].category_code != audio_status.category_code) { 129 rdev->audio.pin[0] = audio_status; 130 changed = true; 131 } 132 133 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 134 if (!radeon_encoder_is_digital(encoder)) 135 continue; 136 if (changed || r600_hdmi_buffer_status_changed(encoder)) 137 r600_hdmi_update_audio_settings(encoder); 138 } 139 } 140 141 /* enable the audio stream */ 142 void r600_audio_enable(struct radeon_device *rdev, 143 struct r600_audio_pin *pin, 144 u8 enable_mask) 145 { 146 u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL); 147 148 if (!pin) 149 return; 150 151 if (enable_mask) { 152 tmp |= AUDIO_ENABLED; 153 if (enable_mask & 1) 154 tmp |= PIN0_AUDIO_ENABLED; 155 if (enable_mask & 2) 156 tmp |= PIN1_AUDIO_ENABLED; 157 if (enable_mask & 4) 158 tmp |= PIN2_AUDIO_ENABLED; 159 if (enable_mask & 8) 160 tmp |= PIN3_AUDIO_ENABLED; 161 } else { 162 tmp &= ~(AUDIO_ENABLED | 163 PIN0_AUDIO_ENABLED | 164 PIN1_AUDIO_ENABLED | 165 PIN2_AUDIO_ENABLED | 166 PIN3_AUDIO_ENABLED); 167 } 168 169 WREG32(AZ_HOT_PLUG_CONTROL, tmp); 170 } 171 172 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev) 173 { 174 /* only one pin on 6xx-NI */ 175 return &rdev->audio.pin[0]; 176 } 177 178 void r600_hdmi_update_acr(struct drm_encoder *encoder, long offset, 179 const struct radeon_hdmi_acr *acr) 180 { 181 struct drm_device *dev = encoder->dev; 182 struct radeon_device *rdev = dev->dev_private; 183 184 /* DCE 3.0 uses register that's normally for CRC_CONTROL */ 185 uint32_t acr_ctl = ASIC_IS_DCE3(rdev) ? DCE3_HDMI0_ACR_PACKET_CONTROL : 186 HDMI0_ACR_PACKET_CONTROL; 187 WREG32_P(acr_ctl + offset, 188 HDMI0_ACR_SOURCE | /* select SW CTS value */ 189 HDMI0_ACR_AUTO_SEND, /* allow hw to sent ACR packets when required */ 190 ~(HDMI0_ACR_SOURCE | 191 HDMI0_ACR_AUTO_SEND)); 192 193 WREG32_P(HDMI0_ACR_32_0 + offset, 194 HDMI0_ACR_CTS_32(acr->cts_32khz), 195 ~HDMI0_ACR_CTS_32_MASK); 196 WREG32_P(HDMI0_ACR_32_1 + offset, 197 HDMI0_ACR_N_32(acr->n_32khz), 198 ~HDMI0_ACR_N_32_MASK); 199 200 WREG32_P(HDMI0_ACR_44_0 + offset, 201 HDMI0_ACR_CTS_44(acr->cts_44_1khz), 202 ~HDMI0_ACR_CTS_44_MASK); 203 WREG32_P(HDMI0_ACR_44_1 + offset, 204 HDMI0_ACR_N_44(acr->n_44_1khz), 205 ~HDMI0_ACR_N_44_MASK); 206 207 WREG32_P(HDMI0_ACR_48_0 + offset, 208 HDMI0_ACR_CTS_48(acr->cts_48khz), 209 ~HDMI0_ACR_CTS_48_MASK); 210 WREG32_P(HDMI0_ACR_48_1 + offset, 211 HDMI0_ACR_N_48(acr->n_48khz), 212 ~HDMI0_ACR_N_48_MASK); 213 } 214 215 /* 216 * build a HDMI Video Info Frame 217 */ 218 void r600_set_avi_packet(struct radeon_device *rdev, u32 offset, 219 unsigned char *buffer, size_t size) 220 { 221 uint8_t *frame = buffer + 3; 222 223 WREG32(HDMI0_AVI_INFO0 + offset, 224 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 225 WREG32(HDMI0_AVI_INFO1 + offset, 226 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 227 WREG32(HDMI0_AVI_INFO2 + offset, 228 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 229 WREG32(HDMI0_AVI_INFO3 + offset, 230 frame[0xC] | (frame[0xD] << 8) | (buffer[1] << 24)); 231 232 WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset, 233 HDMI0_AVI_INFO_LINE(2)); /* anything other than 0 */ 234 235 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, 236 HDMI0_AVI_INFO_SEND | /* enable AVI info frames */ 237 HDMI0_AVI_INFO_CONT); /* send AVI info frames every frame/field */ 238 239 } 240 241 /* 242 * build a Audio Info Frame 243 */ 244 static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder, 245 const void *buffer, size_t size) 246 { 247 struct drm_device *dev = encoder->dev; 248 struct radeon_device *rdev = dev->dev_private; 249 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 250 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 251 uint32_t offset = dig->afmt->offset; 252 const u8 *frame = buffer + 3; 253 254 WREG32(HDMI0_AUDIO_INFO0 + offset, 255 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 256 WREG32(HDMI0_AUDIO_INFO1 + offset, 257 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24)); 258 } 259 260 /* 261 * test if audio buffer is filled enough to start playing 262 */ 263 static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder) 264 { 265 struct drm_device *dev = encoder->dev; 266 struct radeon_device *rdev = dev->dev_private; 267 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 268 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 269 uint32_t offset = dig->afmt->offset; 270 271 return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0; 272 } 273 274 /* 275 * have buffer status changed since last call? 276 */ 277 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder) 278 { 279 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 280 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 281 int status, result; 282 283 if (!dig->afmt || !dig->afmt->enabled) 284 return 0; 285 286 status = r600_hdmi_is_audio_buffer_filled(encoder); 287 result = dig->afmt->last_buffer_filled_status != status; 288 dig->afmt->last_buffer_filled_status = status; 289 290 return result; 291 } 292 293 void r600_hdmi_audio_set_dto(struct radeon_device *rdev, 294 struct radeon_crtc *crtc, unsigned int clock) 295 { 296 struct radeon_encoder *radeon_encoder; 297 struct radeon_encoder_atom_dig *dig; 298 299 if (!crtc) 300 return; 301 302 radeon_encoder = to_radeon_encoder(crtc->encoder); 303 dig = radeon_encoder->enc_priv; 304 305 if (!dig) 306 return; 307 308 if (dig->dig_encoder == 0) { 309 WREG32(DCCG_AUDIO_DTO0_PHASE, 24000 * 100); 310 WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); 311 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ 312 } else { 313 WREG32(DCCG_AUDIO_DTO1_PHASE, 24000 * 100); 314 WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100); 315 WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */ 316 } 317 } 318 319 void r600_set_vbi_packet(struct drm_encoder *encoder, u32 offset) 320 { 321 struct drm_device *dev = encoder->dev; 322 struct radeon_device *rdev = dev->dev_private; 323 324 WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset, 325 HDMI0_NULL_SEND | /* send null packets when required */ 326 HDMI0_GC_SEND | /* send general control packets */ 327 HDMI0_GC_CONT); /* send general control packets every frame */ 328 } 329 330 void r600_set_audio_packet(struct drm_encoder *encoder, u32 offset) 331 { 332 struct drm_device *dev = encoder->dev; 333 struct radeon_device *rdev = dev->dev_private; 334 335 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, 336 HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */ 337 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ 338 HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */ 339 HDMI0_60958_CS_UPDATE, /* allow 60958 channel status fields to be updated */ 340 ~(HDMI0_AUDIO_SAMPLE_SEND | 341 HDMI0_AUDIO_DELAY_EN_MASK | 342 HDMI0_AUDIO_PACKETS_PER_LINE_MASK | 343 HDMI0_60958_CS_UPDATE)); 344 345 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, 346 HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ 347 HDMI0_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ 348 349 WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset, 350 HDMI0_AUDIO_INFO_LINE(2), /* anything other than 0 */ 351 ~HDMI0_AUDIO_INFO_LINE_MASK); 352 353 WREG32_AND(HDMI0_GENERIC_PACKET_CONTROL + offset, 354 ~(HDMI0_GENERIC0_SEND | 355 HDMI0_GENERIC0_CONT | 356 HDMI0_GENERIC0_UPDATE | 357 HDMI0_GENERIC1_SEND | 358 HDMI0_GENERIC1_CONT | 359 HDMI0_GENERIC0_LINE_MASK | 360 HDMI0_GENERIC1_LINE_MASK)); 361 362 WREG32_P(HDMI0_60958_0 + offset, 363 HDMI0_60958_CS_CHANNEL_NUMBER_L(1), 364 ~(HDMI0_60958_CS_CHANNEL_NUMBER_L_MASK | 365 HDMI0_60958_CS_CLOCK_ACCURACY_MASK)); 366 367 WREG32_P(HDMI0_60958_1 + offset, 368 HDMI0_60958_CS_CHANNEL_NUMBER_R(2), 369 ~HDMI0_60958_CS_CHANNEL_NUMBER_R_MASK); 370 } 371 372 void r600_set_mute(struct drm_encoder *encoder, u32 offset, bool mute) 373 { 374 struct drm_device *dev = encoder->dev; 375 struct radeon_device *rdev = dev->dev_private; 376 377 if (mute) 378 WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE); 379 else 380 WREG32_AND(HDMI0_GC + offset, ~HDMI0_GC_AVMUTE); 381 } 382 383 /** 384 * r600_hdmi_update_audio_settings - Update audio infoframe 385 * 386 * @encoder: drm encoder 387 * 388 * Gets info about current audio stream and updates audio infoframe. 389 */ 390 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder) 391 { 392 struct drm_device *dev = encoder->dev; 393 struct radeon_device *rdev = dev->dev_private; 394 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 395 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 396 struct r600_audio_pin audio = r600_audio_status(rdev); 397 uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE]; 398 struct hdmi_audio_infoframe frame; 399 uint32_t offset; 400 uint32_t value; 401 ssize_t err; 402 403 if (!dig->afmt || !dig->afmt->enabled) 404 return; 405 offset = dig->afmt->offset; 406 407 DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n", 408 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped", 409 audio.channels, audio.rate, audio.bits_per_sample); 410 DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n", 411 (int)audio.status_bits, (int)audio.category_code); 412 413 err = hdmi_audio_infoframe_init(&frame); 414 if (err < 0) { 415 DRM_ERROR("failed to setup audio infoframe\n"); 416 return; 417 } 418 419 frame.channels = audio.channels; 420 421 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); 422 if (err < 0) { 423 DRM_ERROR("failed to pack audio infoframe\n"); 424 return; 425 } 426 427 value = RREG32(HDMI0_AUDIO_PACKET_CONTROL + offset); 428 if (value & HDMI0_AUDIO_TEST_EN) 429 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, 430 value & ~HDMI0_AUDIO_TEST_EN); 431 432 WREG32_OR(HDMI0_CONTROL + offset, 433 HDMI0_ERROR_ACK); 434 435 WREG32_AND(HDMI0_INFOFRAME_CONTROL0 + offset, 436 ~HDMI0_AUDIO_INFO_SOURCE); 437 438 r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer)); 439 440 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, 441 HDMI0_AUDIO_INFO_CONT | 442 HDMI0_AUDIO_INFO_UPDATE); 443 } 444 445 /* 446 * enable the HDMI engine 447 */ 448 void r600_hdmi_enable(struct drm_encoder *encoder, bool enable) 449 { 450 struct drm_device *dev = encoder->dev; 451 struct radeon_device *rdev = dev->dev_private; 452 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 453 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 454 u32 hdmi = HDMI0_ERROR_ACK; 455 456 if (!dig || !dig->afmt) 457 return; 458 459 /* Older chipsets require setting HDMI and routing manually */ 460 if (!ASIC_IS_DCE3(rdev)) { 461 if (enable) 462 hdmi |= HDMI0_ENABLE; 463 switch (radeon_encoder->encoder_id) { 464 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 465 if (enable) { 466 WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN); 467 hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA); 468 } else { 469 WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN); 470 } 471 break; 472 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 473 if (enable) { 474 WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN); 475 hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA); 476 } else { 477 WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN); 478 } 479 break; 480 case ENCODER_OBJECT_ID_INTERNAL_DDI: 481 if (enable) { 482 WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN); 483 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA); 484 } else { 485 WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN); 486 } 487 break; 488 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 489 if (enable) 490 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA); 491 break; 492 default: 493 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n", 494 radeon_encoder->encoder_id); 495 break; 496 } 497 WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi); 498 } 499 500 if (rdev->irq.installed) { 501 /* if irq is available use it */ 502 /* XXX: shouldn't need this on any asics. Double check DCE2/3 */ 503 if (enable) 504 radeon_irq_kms_enable_afmt(rdev, dig->afmt->id); 505 else 506 radeon_irq_kms_disable_afmt(rdev, dig->afmt->id); 507 } 508 509 dig->afmt->enabled = enable; 510 511 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", 512 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); 513 } 514 515