1 /* SPDX-License-Identifier: MIT 2 * 3 * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. 4 */ 5 #include "gpu.h" 6 7 #include <engine/ce/priv.h> 8 #include <engine/fifo/priv.h> 9 10 #include <nvif/class.h> 11 12 const struct nvkm_rm_gpu 13 gb20x_gpu = { 14 .disp.class = { 15 .root = GB202_DISP, 16 .caps = GB202_DISP_CAPS, 17 .core = GB202_DISP_CORE_CHANNEL_DMA, 18 .wndw = GB202_DISP_WINDOW_CHANNEL_DMA, 19 .wimm = GB202_DISP_WINDOW_IMM_CHANNEL_DMA, 20 .curs = GB202_DISP_CURSOR, 21 }, 22 23 .usermode.class = BLACKWELL_USERMODE_A, 24 25 .fifo.chan = { 26 .class = BLACKWELL_CHANNEL_GPFIFO_B, 27 .doorbell_handle = gb202_chan_doorbell_handle, 28 }, 29 30 .ce = { 31 .class = BLACKWELL_DMA_COPY_B, 32 .grce_mask = gb202_ce_grce_mask, 33 }, 34 .gr.class = { 35 .i2m = BLACKWELL_INLINE_TO_MEMORY_A, 36 .twod = FERMI_TWOD_A, 37 .threed = BLACKWELL_B, 38 .compute = BLACKWELL_COMPUTE_B, 39 }, 40 .nvdec.class = NVCFB0_VIDEO_DECODER, 41 .nvenc.class = NVCFB7_VIDEO_ENCODER, 42 .nvjpg.class = NVCFD1_VIDEO_NVJPG, 43 .ofa.class = NVCFFA_VIDEO_OFA, 44 }; 45