1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "priv.h" 25 #include "acpi.h" 26 27 #include <core/option.h> 28 29 #include <subdev/bios.h> 30 #include <subdev/therm.h> 31 32 static DEFINE_MUTEX(nv_devices_mutex); 33 static LIST_HEAD(nv_devices); 34 35 static struct nvkm_device * 36 nvkm_device_find_locked(u64 handle) 37 { 38 struct nvkm_device *device; 39 list_for_each_entry(device, &nv_devices, head) { 40 if (device->handle == handle) 41 return device; 42 } 43 return NULL; 44 } 45 46 struct nvkm_device * 47 nvkm_device_find(u64 handle) 48 { 49 struct nvkm_device *device; 50 mutex_lock(&nv_devices_mutex); 51 device = nvkm_device_find_locked(handle); 52 mutex_unlock(&nv_devices_mutex); 53 return device; 54 } 55 56 static const struct nvkm_device_chip 57 nv4_chipset = { 58 .name = "NV04", 59 .bios = { 0x00000001, nvkm_bios_new }, 60 .bus = { 0x00000001, nv04_bus_new }, 61 .clk = { 0x00000001, nv04_clk_new }, 62 .devinit = { 0x00000001, nv04_devinit_new }, 63 .fb = { 0x00000001, nv04_fb_new }, 64 .i2c = { 0x00000001, nv04_i2c_new }, 65 .imem = { 0x00000001, nv04_instmem_new }, 66 .mc = { 0x00000001, nv04_mc_new }, 67 .mmu = { 0x00000001, nv04_mmu_new }, 68 .pci = { 0x00000001, nv04_pci_new }, 69 .timer = { 0x00000001, nv04_timer_new }, 70 .disp = { 0x00000001, nv04_disp_new }, 71 .dma = { 0x00000001, nv04_dma_new }, 72 .fifo = { 0x00000001, nv04_fifo_new }, 73 .gr = { 0x00000001, nv04_gr_new }, 74 .sw = { 0x00000001, nv04_sw_new }, 75 }; 76 77 static const struct nvkm_device_chip 78 nv5_chipset = { 79 .name = "NV05", 80 .bios = { 0x00000001, nvkm_bios_new }, 81 .bus = { 0x00000001, nv04_bus_new }, 82 .clk = { 0x00000001, nv04_clk_new }, 83 .devinit = { 0x00000001, nv05_devinit_new }, 84 .fb = { 0x00000001, nv04_fb_new }, 85 .i2c = { 0x00000001, nv04_i2c_new }, 86 .imem = { 0x00000001, nv04_instmem_new }, 87 .mc = { 0x00000001, nv04_mc_new }, 88 .mmu = { 0x00000001, nv04_mmu_new }, 89 .pci = { 0x00000001, nv04_pci_new }, 90 .timer = { 0x00000001, nv04_timer_new }, 91 .disp = { 0x00000001, nv04_disp_new }, 92 .dma = { 0x00000001, nv04_dma_new }, 93 .fifo = { 0x00000001, nv04_fifo_new }, 94 .gr = { 0x00000001, nv04_gr_new }, 95 .sw = { 0x00000001, nv04_sw_new }, 96 }; 97 98 static const struct nvkm_device_chip 99 nv10_chipset = { 100 .name = "NV10", 101 .bios = { 0x00000001, nvkm_bios_new }, 102 .bus = { 0x00000001, nv04_bus_new }, 103 .clk = { 0x00000001, nv04_clk_new }, 104 .devinit = { 0x00000001, nv10_devinit_new }, 105 .fb = { 0x00000001, nv10_fb_new }, 106 .gpio = { 0x00000001, nv10_gpio_new }, 107 .i2c = { 0x00000001, nv04_i2c_new }, 108 .imem = { 0x00000001, nv04_instmem_new }, 109 .mc = { 0x00000001, nv04_mc_new }, 110 .mmu = { 0x00000001, nv04_mmu_new }, 111 .pci = { 0x00000001, nv04_pci_new }, 112 .timer = { 0x00000001, nv04_timer_new }, 113 .disp = { 0x00000001, nv04_disp_new }, 114 .dma = { 0x00000001, nv04_dma_new }, 115 .gr = { 0x00000001, nv10_gr_new }, 116 }; 117 118 static const struct nvkm_device_chip 119 nv11_chipset = { 120 .name = "NV11", 121 .bios = { 0x00000001, nvkm_bios_new }, 122 .bus = { 0x00000001, nv04_bus_new }, 123 .clk = { 0x00000001, nv04_clk_new }, 124 .devinit = { 0x00000001, nv10_devinit_new }, 125 .fb = { 0x00000001, nv10_fb_new }, 126 .gpio = { 0x00000001, nv10_gpio_new }, 127 .i2c = { 0x00000001, nv04_i2c_new }, 128 .imem = { 0x00000001, nv04_instmem_new }, 129 .mc = { 0x00000001, nv11_mc_new }, 130 .mmu = { 0x00000001, nv04_mmu_new }, 131 .pci = { 0x00000001, nv04_pci_new }, 132 .timer = { 0x00000001, nv04_timer_new }, 133 .disp = { 0x00000001, nv04_disp_new }, 134 .dma = { 0x00000001, nv04_dma_new }, 135 .fifo = { 0x00000001, nv10_fifo_new }, 136 .gr = { 0x00000001, nv15_gr_new }, 137 .sw = { 0x00000001, nv10_sw_new }, 138 }; 139 140 static const struct nvkm_device_chip 141 nv15_chipset = { 142 .name = "NV15", 143 .bios = { 0x00000001, nvkm_bios_new }, 144 .bus = { 0x00000001, nv04_bus_new }, 145 .clk = { 0x00000001, nv04_clk_new }, 146 .devinit = { 0x00000001, nv10_devinit_new }, 147 .fb = { 0x00000001, nv10_fb_new }, 148 .gpio = { 0x00000001, nv10_gpio_new }, 149 .i2c = { 0x00000001, nv04_i2c_new }, 150 .imem = { 0x00000001, nv04_instmem_new }, 151 .mc = { 0x00000001, nv04_mc_new }, 152 .mmu = { 0x00000001, nv04_mmu_new }, 153 .pci = { 0x00000001, nv04_pci_new }, 154 .timer = { 0x00000001, nv04_timer_new }, 155 .disp = { 0x00000001, nv04_disp_new }, 156 .dma = { 0x00000001, nv04_dma_new }, 157 .fifo = { 0x00000001, nv10_fifo_new }, 158 .gr = { 0x00000001, nv15_gr_new }, 159 .sw = { 0x00000001, nv10_sw_new }, 160 }; 161 162 static const struct nvkm_device_chip 163 nv17_chipset = { 164 .name = "NV17", 165 .bios = { 0x00000001, nvkm_bios_new }, 166 .bus = { 0x00000001, nv04_bus_new }, 167 .clk = { 0x00000001, nv04_clk_new }, 168 .devinit = { 0x00000001, nv10_devinit_new }, 169 .fb = { 0x00000001, nv10_fb_new }, 170 .gpio = { 0x00000001, nv10_gpio_new }, 171 .i2c = { 0x00000001, nv04_i2c_new }, 172 .imem = { 0x00000001, nv04_instmem_new }, 173 .mc = { 0x00000001, nv17_mc_new }, 174 .mmu = { 0x00000001, nv04_mmu_new }, 175 .pci = { 0x00000001, nv04_pci_new }, 176 .timer = { 0x00000001, nv04_timer_new }, 177 .disp = { 0x00000001, nv04_disp_new }, 178 .dma = { 0x00000001, nv04_dma_new }, 179 .fifo = { 0x00000001, nv17_fifo_new }, 180 .gr = { 0x00000001, nv17_gr_new }, 181 .sw = { 0x00000001, nv10_sw_new }, 182 }; 183 184 static const struct nvkm_device_chip 185 nv18_chipset = { 186 .name = "NV18", 187 .bios = { 0x00000001, nvkm_bios_new }, 188 .bus = { 0x00000001, nv04_bus_new }, 189 .clk = { 0x00000001, nv04_clk_new }, 190 .devinit = { 0x00000001, nv10_devinit_new }, 191 .fb = { 0x00000001, nv10_fb_new }, 192 .gpio = { 0x00000001, nv10_gpio_new }, 193 .i2c = { 0x00000001, nv04_i2c_new }, 194 .imem = { 0x00000001, nv04_instmem_new }, 195 .mc = { 0x00000001, nv17_mc_new }, 196 .mmu = { 0x00000001, nv04_mmu_new }, 197 .pci = { 0x00000001, nv04_pci_new }, 198 .timer = { 0x00000001, nv04_timer_new }, 199 .disp = { 0x00000001, nv04_disp_new }, 200 .dma = { 0x00000001, nv04_dma_new }, 201 .fifo = { 0x00000001, nv17_fifo_new }, 202 .gr = { 0x00000001, nv17_gr_new }, 203 .sw = { 0x00000001, nv10_sw_new }, 204 }; 205 206 static const struct nvkm_device_chip 207 nv1a_chipset = { 208 .name = "nForce", 209 .bios = { 0x00000001, nvkm_bios_new }, 210 .bus = { 0x00000001, nv04_bus_new }, 211 .clk = { 0x00000001, nv04_clk_new }, 212 .devinit = { 0x00000001, nv1a_devinit_new }, 213 .fb = { 0x00000001, nv1a_fb_new }, 214 .gpio = { 0x00000001, nv10_gpio_new }, 215 .i2c = { 0x00000001, nv04_i2c_new }, 216 .imem = { 0x00000001, nv04_instmem_new }, 217 .mc = { 0x00000001, nv04_mc_new }, 218 .mmu = { 0x00000001, nv04_mmu_new }, 219 .pci = { 0x00000001, nv04_pci_new }, 220 .timer = { 0x00000001, nv04_timer_new }, 221 .disp = { 0x00000001, nv04_disp_new }, 222 .dma = { 0x00000001, nv04_dma_new }, 223 .fifo = { 0x00000001, nv10_fifo_new }, 224 .gr = { 0x00000001, nv15_gr_new }, 225 .sw = { 0x00000001, nv10_sw_new }, 226 }; 227 228 static const struct nvkm_device_chip 229 nv1f_chipset = { 230 .name = "nForce2", 231 .bios = { 0x00000001, nvkm_bios_new }, 232 .bus = { 0x00000001, nv04_bus_new }, 233 .clk = { 0x00000001, nv04_clk_new }, 234 .devinit = { 0x00000001, nv1a_devinit_new }, 235 .fb = { 0x00000001, nv1a_fb_new }, 236 .gpio = { 0x00000001, nv10_gpio_new }, 237 .i2c = { 0x00000001, nv04_i2c_new }, 238 .imem = { 0x00000001, nv04_instmem_new }, 239 .mc = { 0x00000001, nv17_mc_new }, 240 .mmu = { 0x00000001, nv04_mmu_new }, 241 .pci = { 0x00000001, nv04_pci_new }, 242 .timer = { 0x00000001, nv04_timer_new }, 243 .disp = { 0x00000001, nv04_disp_new }, 244 .dma = { 0x00000001, nv04_dma_new }, 245 .fifo = { 0x00000001, nv17_fifo_new }, 246 .gr = { 0x00000001, nv17_gr_new }, 247 .sw = { 0x00000001, nv10_sw_new }, 248 }; 249 250 static const struct nvkm_device_chip 251 nv20_chipset = { 252 .name = "NV20", 253 .bios = { 0x00000001, nvkm_bios_new }, 254 .bus = { 0x00000001, nv04_bus_new }, 255 .clk = { 0x00000001, nv04_clk_new }, 256 .devinit = { 0x00000001, nv20_devinit_new }, 257 .fb = { 0x00000001, nv20_fb_new }, 258 .gpio = { 0x00000001, nv10_gpio_new }, 259 .i2c = { 0x00000001, nv04_i2c_new }, 260 .imem = { 0x00000001, nv04_instmem_new }, 261 .mc = { 0x00000001, nv17_mc_new }, 262 .mmu = { 0x00000001, nv04_mmu_new }, 263 .pci = { 0x00000001, nv04_pci_new }, 264 .timer = { 0x00000001, nv04_timer_new }, 265 .disp = { 0x00000001, nv04_disp_new }, 266 .dma = { 0x00000001, nv04_dma_new }, 267 .fifo = { 0x00000001, nv17_fifo_new }, 268 .gr = { 0x00000001, nv20_gr_new }, 269 .sw = { 0x00000001, nv10_sw_new }, 270 }; 271 272 static const struct nvkm_device_chip 273 nv25_chipset = { 274 .name = "NV25", 275 .bios = { 0x00000001, nvkm_bios_new }, 276 .bus = { 0x00000001, nv04_bus_new }, 277 .clk = { 0x00000001, nv04_clk_new }, 278 .devinit = { 0x00000001, nv20_devinit_new }, 279 .fb = { 0x00000001, nv25_fb_new }, 280 .gpio = { 0x00000001, nv10_gpio_new }, 281 .i2c = { 0x00000001, nv04_i2c_new }, 282 .imem = { 0x00000001, nv04_instmem_new }, 283 .mc = { 0x00000001, nv17_mc_new }, 284 .mmu = { 0x00000001, nv04_mmu_new }, 285 .pci = { 0x00000001, nv04_pci_new }, 286 .timer = { 0x00000001, nv04_timer_new }, 287 .disp = { 0x00000001, nv04_disp_new }, 288 .dma = { 0x00000001, nv04_dma_new }, 289 .fifo = { 0x00000001, nv17_fifo_new }, 290 .gr = { 0x00000001, nv25_gr_new }, 291 .sw = { 0x00000001, nv10_sw_new }, 292 }; 293 294 static const struct nvkm_device_chip 295 nv28_chipset = { 296 .name = "NV28", 297 .bios = { 0x00000001, nvkm_bios_new }, 298 .bus = { 0x00000001, nv04_bus_new }, 299 .clk = { 0x00000001, nv04_clk_new }, 300 .devinit = { 0x00000001, nv20_devinit_new }, 301 .fb = { 0x00000001, nv25_fb_new }, 302 .gpio = { 0x00000001, nv10_gpio_new }, 303 .i2c = { 0x00000001, nv04_i2c_new }, 304 .imem = { 0x00000001, nv04_instmem_new }, 305 .mc = { 0x00000001, nv17_mc_new }, 306 .mmu = { 0x00000001, nv04_mmu_new }, 307 .pci = { 0x00000001, nv04_pci_new }, 308 .timer = { 0x00000001, nv04_timer_new }, 309 .disp = { 0x00000001, nv04_disp_new }, 310 .dma = { 0x00000001, nv04_dma_new }, 311 .fifo = { 0x00000001, nv17_fifo_new }, 312 .gr = { 0x00000001, nv25_gr_new }, 313 .sw = { 0x00000001, nv10_sw_new }, 314 }; 315 316 static const struct nvkm_device_chip 317 nv2a_chipset = { 318 .name = "NV2A", 319 .bios = { 0x00000001, nvkm_bios_new }, 320 .bus = { 0x00000001, nv04_bus_new }, 321 .clk = { 0x00000001, nv04_clk_new }, 322 .devinit = { 0x00000001, nv20_devinit_new }, 323 .fb = { 0x00000001, nv25_fb_new }, 324 .gpio = { 0x00000001, nv10_gpio_new }, 325 .i2c = { 0x00000001, nv04_i2c_new }, 326 .imem = { 0x00000001, nv04_instmem_new }, 327 .mc = { 0x00000001, nv17_mc_new }, 328 .mmu = { 0x00000001, nv04_mmu_new }, 329 .pci = { 0x00000001, nv04_pci_new }, 330 .timer = { 0x00000001, nv04_timer_new }, 331 .disp = { 0x00000001, nv04_disp_new }, 332 .dma = { 0x00000001, nv04_dma_new }, 333 .fifo = { 0x00000001, nv17_fifo_new }, 334 .gr = { 0x00000001, nv2a_gr_new }, 335 .sw = { 0x00000001, nv10_sw_new }, 336 }; 337 338 static const struct nvkm_device_chip 339 nv30_chipset = { 340 .name = "NV30", 341 .bios = { 0x00000001, nvkm_bios_new }, 342 .bus = { 0x00000001, nv04_bus_new }, 343 .clk = { 0x00000001, nv04_clk_new }, 344 .devinit = { 0x00000001, nv20_devinit_new }, 345 .fb = { 0x00000001, nv30_fb_new }, 346 .gpio = { 0x00000001, nv10_gpio_new }, 347 .i2c = { 0x00000001, nv04_i2c_new }, 348 .imem = { 0x00000001, nv04_instmem_new }, 349 .mc = { 0x00000001, nv17_mc_new }, 350 .mmu = { 0x00000001, nv04_mmu_new }, 351 .pci = { 0x00000001, nv04_pci_new }, 352 .timer = { 0x00000001, nv04_timer_new }, 353 .disp = { 0x00000001, nv04_disp_new }, 354 .dma = { 0x00000001, nv04_dma_new }, 355 .fifo = { 0x00000001, nv17_fifo_new }, 356 .gr = { 0x00000001, nv30_gr_new }, 357 .sw = { 0x00000001, nv10_sw_new }, 358 }; 359 360 static const struct nvkm_device_chip 361 nv31_chipset = { 362 .name = "NV31", 363 .bios = { 0x00000001, nvkm_bios_new }, 364 .bus = { 0x00000001, nv31_bus_new }, 365 .clk = { 0x00000001, nv04_clk_new }, 366 .devinit = { 0x00000001, nv20_devinit_new }, 367 .fb = { 0x00000001, nv30_fb_new }, 368 .gpio = { 0x00000001, nv10_gpio_new }, 369 .i2c = { 0x00000001, nv04_i2c_new }, 370 .imem = { 0x00000001, nv04_instmem_new }, 371 .mc = { 0x00000001, nv17_mc_new }, 372 .mmu = { 0x00000001, nv04_mmu_new }, 373 .pci = { 0x00000001, nv04_pci_new }, 374 .timer = { 0x00000001, nv04_timer_new }, 375 .disp = { 0x00000001, nv04_disp_new }, 376 .dma = { 0x00000001, nv04_dma_new }, 377 .fifo = { 0x00000001, nv17_fifo_new }, 378 .gr = { 0x00000001, nv30_gr_new }, 379 .mpeg = { 0x00000001, nv31_mpeg_new }, 380 .sw = { 0x00000001, nv10_sw_new }, 381 }; 382 383 static const struct nvkm_device_chip 384 nv34_chipset = { 385 .name = "NV34", 386 .bios = { 0x00000001, nvkm_bios_new }, 387 .bus = { 0x00000001, nv31_bus_new }, 388 .clk = { 0x00000001, nv04_clk_new }, 389 .devinit = { 0x00000001, nv10_devinit_new }, 390 .fb = { 0x00000001, nv10_fb_new }, 391 .gpio = { 0x00000001, nv10_gpio_new }, 392 .i2c = { 0x00000001, nv04_i2c_new }, 393 .imem = { 0x00000001, nv04_instmem_new }, 394 .mc = { 0x00000001, nv17_mc_new }, 395 .mmu = { 0x00000001, nv04_mmu_new }, 396 .pci = { 0x00000001, nv04_pci_new }, 397 .timer = { 0x00000001, nv04_timer_new }, 398 .disp = { 0x00000001, nv04_disp_new }, 399 .dma = { 0x00000001, nv04_dma_new }, 400 .fifo = { 0x00000001, nv17_fifo_new }, 401 .gr = { 0x00000001, nv34_gr_new }, 402 .mpeg = { 0x00000001, nv31_mpeg_new }, 403 .sw = { 0x00000001, nv10_sw_new }, 404 }; 405 406 static const struct nvkm_device_chip 407 nv35_chipset = { 408 .name = "NV35", 409 .bios = { 0x00000001, nvkm_bios_new }, 410 .bus = { 0x00000001, nv04_bus_new }, 411 .clk = { 0x00000001, nv04_clk_new }, 412 .devinit = { 0x00000001, nv20_devinit_new }, 413 .fb = { 0x00000001, nv35_fb_new }, 414 .gpio = { 0x00000001, nv10_gpio_new }, 415 .i2c = { 0x00000001, nv04_i2c_new }, 416 .imem = { 0x00000001, nv04_instmem_new }, 417 .mc = { 0x00000001, nv17_mc_new }, 418 .mmu = { 0x00000001, nv04_mmu_new }, 419 .pci = { 0x00000001, nv04_pci_new }, 420 .timer = { 0x00000001, nv04_timer_new }, 421 .disp = { 0x00000001, nv04_disp_new }, 422 .dma = { 0x00000001, nv04_dma_new }, 423 .fifo = { 0x00000001, nv17_fifo_new }, 424 .gr = { 0x00000001, nv35_gr_new }, 425 .sw = { 0x00000001, nv10_sw_new }, 426 }; 427 428 static const struct nvkm_device_chip 429 nv36_chipset = { 430 .name = "NV36", 431 .bios = { 0x00000001, nvkm_bios_new }, 432 .bus = { 0x00000001, nv31_bus_new }, 433 .clk = { 0x00000001, nv04_clk_new }, 434 .devinit = { 0x00000001, nv20_devinit_new }, 435 .fb = { 0x00000001, nv36_fb_new }, 436 .gpio = { 0x00000001, nv10_gpio_new }, 437 .i2c = { 0x00000001, nv04_i2c_new }, 438 .imem = { 0x00000001, nv04_instmem_new }, 439 .mc = { 0x00000001, nv17_mc_new }, 440 .mmu = { 0x00000001, nv04_mmu_new }, 441 .pci = { 0x00000001, nv04_pci_new }, 442 .timer = { 0x00000001, nv04_timer_new }, 443 .disp = { 0x00000001, nv04_disp_new }, 444 .dma = { 0x00000001, nv04_dma_new }, 445 .fifo = { 0x00000001, nv17_fifo_new }, 446 .gr = { 0x00000001, nv35_gr_new }, 447 .mpeg = { 0x00000001, nv31_mpeg_new }, 448 .sw = { 0x00000001, nv10_sw_new }, 449 }; 450 451 static const struct nvkm_device_chip 452 nv40_chipset = { 453 .name = "NV40", 454 .bios = { 0x00000001, nvkm_bios_new }, 455 .bus = { 0x00000001, nv31_bus_new }, 456 .clk = { 0x00000001, nv40_clk_new }, 457 .devinit = { 0x00000001, nv1a_devinit_new }, 458 .fb = { 0x00000001, nv40_fb_new }, 459 .gpio = { 0x00000001, nv10_gpio_new }, 460 .i2c = { 0x00000001, nv04_i2c_new }, 461 .imem = { 0x00000001, nv40_instmem_new }, 462 .mc = { 0x00000001, nv17_mc_new }, 463 .mmu = { 0x00000001, nv04_mmu_new }, 464 .pci = { 0x00000001, nv40_pci_new }, 465 .therm = { 0x00000001, nv40_therm_new }, 466 .timer = { 0x00000001, nv40_timer_new }, 467 .volt = { 0x00000001, nv40_volt_new }, 468 .disp = { 0x00000001, nv04_disp_new }, 469 .dma = { 0x00000001, nv04_dma_new }, 470 .fifo = { 0x00000001, nv40_fifo_new }, 471 .gr = { 0x00000001, nv40_gr_new }, 472 .mpeg = { 0x00000001, nv40_mpeg_new }, 473 .sw = { 0x00000001, nv10_sw_new }, 474 }; 475 476 static const struct nvkm_device_chip 477 nv41_chipset = { 478 .name = "NV41", 479 .bios = { 0x00000001, nvkm_bios_new }, 480 .bus = { 0x00000001, nv31_bus_new }, 481 .clk = { 0x00000001, nv40_clk_new }, 482 .devinit = { 0x00000001, nv1a_devinit_new }, 483 .fb = { 0x00000001, nv41_fb_new }, 484 .gpio = { 0x00000001, nv10_gpio_new }, 485 .i2c = { 0x00000001, nv04_i2c_new }, 486 .imem = { 0x00000001, nv40_instmem_new }, 487 .mc = { 0x00000001, nv17_mc_new }, 488 .mmu = { 0x00000001, nv41_mmu_new }, 489 .pci = { 0x00000001, nv40_pci_new }, 490 .therm = { 0x00000001, nv40_therm_new }, 491 .timer = { 0x00000001, nv41_timer_new }, 492 .volt = { 0x00000001, nv40_volt_new }, 493 .disp = { 0x00000001, nv04_disp_new }, 494 .dma = { 0x00000001, nv04_dma_new }, 495 .fifo = { 0x00000001, nv40_fifo_new }, 496 .gr = { 0x00000001, nv40_gr_new }, 497 .mpeg = { 0x00000001, nv40_mpeg_new }, 498 .sw = { 0x00000001, nv10_sw_new }, 499 }; 500 501 static const struct nvkm_device_chip 502 nv42_chipset = { 503 .name = "NV42", 504 .bios = { 0x00000001, nvkm_bios_new }, 505 .bus = { 0x00000001, nv31_bus_new }, 506 .clk = { 0x00000001, nv40_clk_new }, 507 .devinit = { 0x00000001, nv1a_devinit_new }, 508 .fb = { 0x00000001, nv41_fb_new }, 509 .gpio = { 0x00000001, nv10_gpio_new }, 510 .i2c = { 0x00000001, nv04_i2c_new }, 511 .imem = { 0x00000001, nv40_instmem_new }, 512 .mc = { 0x00000001, nv17_mc_new }, 513 .mmu = { 0x00000001, nv41_mmu_new }, 514 .pci = { 0x00000001, nv40_pci_new }, 515 .therm = { 0x00000001, nv40_therm_new }, 516 .timer = { 0x00000001, nv41_timer_new }, 517 .volt = { 0x00000001, nv40_volt_new }, 518 .disp = { 0x00000001, nv04_disp_new }, 519 .dma = { 0x00000001, nv04_dma_new }, 520 .fifo = { 0x00000001, nv40_fifo_new }, 521 .gr = { 0x00000001, nv40_gr_new }, 522 .mpeg = { 0x00000001, nv40_mpeg_new }, 523 .sw = { 0x00000001, nv10_sw_new }, 524 }; 525 526 static const struct nvkm_device_chip 527 nv43_chipset = { 528 .name = "NV43", 529 .bios = { 0x00000001, nvkm_bios_new }, 530 .bus = { 0x00000001, nv31_bus_new }, 531 .clk = { 0x00000001, nv40_clk_new }, 532 .devinit = { 0x00000001, nv1a_devinit_new }, 533 .fb = { 0x00000001, nv41_fb_new }, 534 .gpio = { 0x00000001, nv10_gpio_new }, 535 .i2c = { 0x00000001, nv04_i2c_new }, 536 .imem = { 0x00000001, nv40_instmem_new }, 537 .mc = { 0x00000001, nv17_mc_new }, 538 .mmu = { 0x00000001, nv41_mmu_new }, 539 .pci = { 0x00000001, nv40_pci_new }, 540 .therm = { 0x00000001, nv40_therm_new }, 541 .timer = { 0x00000001, nv41_timer_new }, 542 .volt = { 0x00000001, nv40_volt_new }, 543 .disp = { 0x00000001, nv04_disp_new }, 544 .dma = { 0x00000001, nv04_dma_new }, 545 .fifo = { 0x00000001, nv40_fifo_new }, 546 .gr = { 0x00000001, nv40_gr_new }, 547 .mpeg = { 0x00000001, nv40_mpeg_new }, 548 .sw = { 0x00000001, nv10_sw_new }, 549 }; 550 551 static const struct nvkm_device_chip 552 nv44_chipset = { 553 .name = "NV44", 554 .bios = { 0x00000001, nvkm_bios_new }, 555 .bus = { 0x00000001, nv31_bus_new }, 556 .clk = { 0x00000001, nv40_clk_new }, 557 .devinit = { 0x00000001, nv1a_devinit_new }, 558 .fb = { 0x00000001, nv44_fb_new }, 559 .gpio = { 0x00000001, nv10_gpio_new }, 560 .i2c = { 0x00000001, nv04_i2c_new }, 561 .imem = { 0x00000001, nv40_instmem_new }, 562 .mc = { 0x00000001, nv44_mc_new }, 563 .mmu = { 0x00000001, nv44_mmu_new }, 564 .pci = { 0x00000001, nv40_pci_new }, 565 .therm = { 0x00000001, nv40_therm_new }, 566 .timer = { 0x00000001, nv41_timer_new }, 567 .volt = { 0x00000001, nv40_volt_new }, 568 .disp = { 0x00000001, nv04_disp_new }, 569 .dma = { 0x00000001, nv04_dma_new }, 570 .fifo = { 0x00000001, nv40_fifo_new }, 571 .gr = { 0x00000001, nv44_gr_new }, 572 .mpeg = { 0x00000001, nv44_mpeg_new }, 573 .sw = { 0x00000001, nv10_sw_new }, 574 }; 575 576 static const struct nvkm_device_chip 577 nv45_chipset = { 578 .name = "NV45", 579 .bios = { 0x00000001, nvkm_bios_new }, 580 .bus = { 0x00000001, nv31_bus_new }, 581 .clk = { 0x00000001, nv40_clk_new }, 582 .devinit = { 0x00000001, nv1a_devinit_new }, 583 .fb = { 0x00000001, nv40_fb_new }, 584 .gpio = { 0x00000001, nv10_gpio_new }, 585 .i2c = { 0x00000001, nv04_i2c_new }, 586 .imem = { 0x00000001, nv40_instmem_new }, 587 .mc = { 0x00000001, nv17_mc_new }, 588 .mmu = { 0x00000001, nv04_mmu_new }, 589 .pci = { 0x00000001, nv40_pci_new }, 590 .therm = { 0x00000001, nv40_therm_new }, 591 .timer = { 0x00000001, nv41_timer_new }, 592 .volt = { 0x00000001, nv40_volt_new }, 593 .disp = { 0x00000001, nv04_disp_new }, 594 .dma = { 0x00000001, nv04_dma_new }, 595 .fifo = { 0x00000001, nv40_fifo_new }, 596 .gr = { 0x00000001, nv40_gr_new }, 597 .mpeg = { 0x00000001, nv44_mpeg_new }, 598 .sw = { 0x00000001, nv10_sw_new }, 599 }; 600 601 static const struct nvkm_device_chip 602 nv46_chipset = { 603 .name = "G72", 604 .bios = { 0x00000001, nvkm_bios_new }, 605 .bus = { 0x00000001, nv31_bus_new }, 606 .clk = { 0x00000001, nv40_clk_new }, 607 .devinit = { 0x00000001, nv1a_devinit_new }, 608 .fb = { 0x00000001, nv46_fb_new }, 609 .gpio = { 0x00000001, nv10_gpio_new }, 610 .i2c = { 0x00000001, nv04_i2c_new }, 611 .imem = { 0x00000001, nv40_instmem_new }, 612 .mc = { 0x00000001, nv44_mc_new }, 613 .mmu = { 0x00000001, nv44_mmu_new }, 614 .pci = { 0x00000001, nv46_pci_new }, 615 .therm = { 0x00000001, nv40_therm_new }, 616 .timer = { 0x00000001, nv41_timer_new }, 617 .volt = { 0x00000001, nv40_volt_new }, 618 .disp = { 0x00000001, nv04_disp_new }, 619 .dma = { 0x00000001, nv04_dma_new }, 620 .fifo = { 0x00000001, nv40_fifo_new }, 621 .gr = { 0x00000001, nv44_gr_new }, 622 .mpeg = { 0x00000001, nv44_mpeg_new }, 623 .sw = { 0x00000001, nv10_sw_new }, 624 }; 625 626 static const struct nvkm_device_chip 627 nv47_chipset = { 628 .name = "G70", 629 .bios = { 0x00000001, nvkm_bios_new }, 630 .bus = { 0x00000001, nv31_bus_new }, 631 .clk = { 0x00000001, nv40_clk_new }, 632 .devinit = { 0x00000001, nv1a_devinit_new }, 633 .fb = { 0x00000001, nv47_fb_new }, 634 .gpio = { 0x00000001, nv10_gpio_new }, 635 .i2c = { 0x00000001, nv04_i2c_new }, 636 .imem = { 0x00000001, nv40_instmem_new }, 637 .mc = { 0x00000001, nv17_mc_new }, 638 .mmu = { 0x00000001, nv41_mmu_new }, 639 .pci = { 0x00000001, nv40_pci_new }, 640 .therm = { 0x00000001, nv40_therm_new }, 641 .timer = { 0x00000001, nv41_timer_new }, 642 .volt = { 0x00000001, nv40_volt_new }, 643 .disp = { 0x00000001, nv04_disp_new }, 644 .dma = { 0x00000001, nv04_dma_new }, 645 .fifo = { 0x00000001, nv40_fifo_new }, 646 .gr = { 0x00000001, nv40_gr_new }, 647 .mpeg = { 0x00000001, nv44_mpeg_new }, 648 .sw = { 0x00000001, nv10_sw_new }, 649 }; 650 651 static const struct nvkm_device_chip 652 nv49_chipset = { 653 .name = "G71", 654 .bios = { 0x00000001, nvkm_bios_new }, 655 .bus = { 0x00000001, nv31_bus_new }, 656 .clk = { 0x00000001, nv40_clk_new }, 657 .devinit = { 0x00000001, nv1a_devinit_new }, 658 .fb = { 0x00000001, nv49_fb_new }, 659 .gpio = { 0x00000001, nv10_gpio_new }, 660 .i2c = { 0x00000001, nv04_i2c_new }, 661 .imem = { 0x00000001, nv40_instmem_new }, 662 .mc = { 0x00000001, nv17_mc_new }, 663 .mmu = { 0x00000001, nv41_mmu_new }, 664 .pci = { 0x00000001, nv40_pci_new }, 665 .therm = { 0x00000001, nv40_therm_new }, 666 .timer = { 0x00000001, nv41_timer_new }, 667 .volt = { 0x00000001, nv40_volt_new }, 668 .disp = { 0x00000001, nv04_disp_new }, 669 .dma = { 0x00000001, nv04_dma_new }, 670 .fifo = { 0x00000001, nv40_fifo_new }, 671 .gr = { 0x00000001, nv40_gr_new }, 672 .mpeg = { 0x00000001, nv44_mpeg_new }, 673 .sw = { 0x00000001, nv10_sw_new }, 674 }; 675 676 static const struct nvkm_device_chip 677 nv4a_chipset = { 678 .name = "NV44A", 679 .bios = { 0x00000001, nvkm_bios_new }, 680 .bus = { 0x00000001, nv31_bus_new }, 681 .clk = { 0x00000001, nv40_clk_new }, 682 .devinit = { 0x00000001, nv1a_devinit_new }, 683 .fb = { 0x00000001, nv44_fb_new }, 684 .gpio = { 0x00000001, nv10_gpio_new }, 685 .i2c = { 0x00000001, nv04_i2c_new }, 686 .imem = { 0x00000001, nv40_instmem_new }, 687 .mc = { 0x00000001, nv44_mc_new }, 688 .mmu = { 0x00000001, nv04_mmu_new }, 689 .pci = { 0x00000001, nv40_pci_new }, 690 .therm = { 0x00000001, nv40_therm_new }, 691 .timer = { 0x00000001, nv41_timer_new }, 692 .volt = { 0x00000001, nv40_volt_new }, 693 .disp = { 0x00000001, nv04_disp_new }, 694 .dma = { 0x00000001, nv04_dma_new }, 695 .fifo = { 0x00000001, nv40_fifo_new }, 696 .gr = { 0x00000001, nv44_gr_new }, 697 .mpeg = { 0x00000001, nv44_mpeg_new }, 698 .sw = { 0x00000001, nv10_sw_new }, 699 }; 700 701 static const struct nvkm_device_chip 702 nv4b_chipset = { 703 .name = "G73", 704 .bios = { 0x00000001, nvkm_bios_new }, 705 .bus = { 0x00000001, nv31_bus_new }, 706 .clk = { 0x00000001, nv40_clk_new }, 707 .devinit = { 0x00000001, nv1a_devinit_new }, 708 .fb = { 0x00000001, nv49_fb_new }, 709 .gpio = { 0x00000001, nv10_gpio_new }, 710 .i2c = { 0x00000001, nv04_i2c_new }, 711 .imem = { 0x00000001, nv40_instmem_new }, 712 .mc = { 0x00000001, nv17_mc_new }, 713 .mmu = { 0x00000001, nv41_mmu_new }, 714 .pci = { 0x00000001, nv40_pci_new }, 715 .therm = { 0x00000001, nv40_therm_new }, 716 .timer = { 0x00000001, nv41_timer_new }, 717 .volt = { 0x00000001, nv40_volt_new }, 718 .disp = { 0x00000001, nv04_disp_new }, 719 .dma = { 0x00000001, nv04_dma_new }, 720 .fifo = { 0x00000001, nv40_fifo_new }, 721 .gr = { 0x00000001, nv40_gr_new }, 722 .mpeg = { 0x00000001, nv44_mpeg_new }, 723 .sw = { 0x00000001, nv10_sw_new }, 724 }; 725 726 static const struct nvkm_device_chip 727 nv4c_chipset = { 728 .name = "C61", 729 .bios = { 0x00000001, nvkm_bios_new }, 730 .bus = { 0x00000001, nv31_bus_new }, 731 .clk = { 0x00000001, nv40_clk_new }, 732 .devinit = { 0x00000001, nv1a_devinit_new }, 733 .fb = { 0x00000001, nv46_fb_new }, 734 .gpio = { 0x00000001, nv10_gpio_new }, 735 .i2c = { 0x00000001, nv04_i2c_new }, 736 .imem = { 0x00000001, nv40_instmem_new }, 737 .mc = { 0x00000001, nv44_mc_new }, 738 .mmu = { 0x00000001, nv44_mmu_new }, 739 .pci = { 0x00000001, nv4c_pci_new }, 740 .therm = { 0x00000001, nv40_therm_new }, 741 .timer = { 0x00000001, nv41_timer_new }, 742 .volt = { 0x00000001, nv40_volt_new }, 743 .disp = { 0x00000001, nv04_disp_new }, 744 .dma = { 0x00000001, nv04_dma_new }, 745 .fifo = { 0x00000001, nv40_fifo_new }, 746 .gr = { 0x00000001, nv44_gr_new }, 747 .mpeg = { 0x00000001, nv44_mpeg_new }, 748 .sw = { 0x00000001, nv10_sw_new }, 749 }; 750 751 static const struct nvkm_device_chip 752 nv4e_chipset = { 753 .name = "C51", 754 .bios = { 0x00000001, nvkm_bios_new }, 755 .bus = { 0x00000001, nv31_bus_new }, 756 .clk = { 0x00000001, nv40_clk_new }, 757 .devinit = { 0x00000001, nv1a_devinit_new }, 758 .fb = { 0x00000001, nv4e_fb_new }, 759 .gpio = { 0x00000001, nv10_gpio_new }, 760 .i2c = { 0x00000001, nv4e_i2c_new }, 761 .imem = { 0x00000001, nv40_instmem_new }, 762 .mc = { 0x00000001, nv44_mc_new }, 763 .mmu = { 0x00000001, nv44_mmu_new }, 764 .pci = { 0x00000001, nv4c_pci_new }, 765 .therm = { 0x00000001, nv40_therm_new }, 766 .timer = { 0x00000001, nv41_timer_new }, 767 .volt = { 0x00000001, nv40_volt_new }, 768 .disp = { 0x00000001, nv04_disp_new }, 769 .dma = { 0x00000001, nv04_dma_new }, 770 .fifo = { 0x00000001, nv40_fifo_new }, 771 .gr = { 0x00000001, nv44_gr_new }, 772 .mpeg = { 0x00000001, nv44_mpeg_new }, 773 .sw = { 0x00000001, nv10_sw_new }, 774 }; 775 776 static const struct nvkm_device_chip 777 nv50_chipset = { 778 .name = "G80", 779 .bar = { 0x00000001, nv50_bar_new }, 780 .bios = { 0x00000001, nvkm_bios_new }, 781 .bus = { 0x00000001, nv50_bus_new }, 782 .clk = { 0x00000001, nv50_clk_new }, 783 .devinit = { 0x00000001, nv50_devinit_new }, 784 .fb = { 0x00000001, nv50_fb_new }, 785 .fuse = { 0x00000001, nv50_fuse_new }, 786 .gpio = { 0x00000001, nv50_gpio_new }, 787 .i2c = { 0x00000001, nv50_i2c_new }, 788 .imem = { 0x00000001, nv50_instmem_new }, 789 .mc = { 0x00000001, nv50_mc_new }, 790 .mmu = { 0x00000001, nv50_mmu_new }, 791 .mxm = { 0x00000001, nv50_mxm_new }, 792 .pci = { 0x00000001, nv46_pci_new }, 793 .therm = { 0x00000001, nv50_therm_new }, 794 .timer = { 0x00000001, nv41_timer_new }, 795 .volt = { 0x00000001, nv40_volt_new }, 796 .disp = { 0x00000001, nv50_disp_new }, 797 .dma = { 0x00000001, nv50_dma_new }, 798 .fifo = { 0x00000001, nv50_fifo_new }, 799 .gr = { 0x00000001, nv50_gr_new }, 800 .mpeg = { 0x00000001, nv50_mpeg_new }, 801 .sw = { 0x00000001, nv50_sw_new }, 802 }; 803 804 static const struct nvkm_device_chip 805 nv63_chipset = { 806 .name = "C73", 807 .bios = { 0x00000001, nvkm_bios_new }, 808 .bus = { 0x00000001, nv31_bus_new }, 809 .clk = { 0x00000001, nv40_clk_new }, 810 .devinit = { 0x00000001, nv1a_devinit_new }, 811 .fb = { 0x00000001, nv46_fb_new }, 812 .gpio = { 0x00000001, nv10_gpio_new }, 813 .i2c = { 0x00000001, nv04_i2c_new }, 814 .imem = { 0x00000001, nv40_instmem_new }, 815 .mc = { 0x00000001, nv44_mc_new }, 816 .mmu = { 0x00000001, nv44_mmu_new }, 817 .pci = { 0x00000001, nv4c_pci_new }, 818 .therm = { 0x00000001, nv40_therm_new }, 819 .timer = { 0x00000001, nv41_timer_new }, 820 .volt = { 0x00000001, nv40_volt_new }, 821 .disp = { 0x00000001, nv04_disp_new }, 822 .dma = { 0x00000001, nv04_dma_new }, 823 .fifo = { 0x00000001, nv40_fifo_new }, 824 .gr = { 0x00000001, nv44_gr_new }, 825 .mpeg = { 0x00000001, nv44_mpeg_new }, 826 .sw = { 0x00000001, nv10_sw_new }, 827 }; 828 829 static const struct nvkm_device_chip 830 nv67_chipset = { 831 .name = "C67", 832 .bios = { 0x00000001, nvkm_bios_new }, 833 .bus = { 0x00000001, nv31_bus_new }, 834 .clk = { 0x00000001, nv40_clk_new }, 835 .devinit = { 0x00000001, nv1a_devinit_new }, 836 .fb = { 0x00000001, nv46_fb_new }, 837 .gpio = { 0x00000001, nv10_gpio_new }, 838 .i2c = { 0x00000001, nv04_i2c_new }, 839 .imem = { 0x00000001, nv40_instmem_new }, 840 .mc = { 0x00000001, nv44_mc_new }, 841 .mmu = { 0x00000001, nv44_mmu_new }, 842 .pci = { 0x00000001, nv4c_pci_new }, 843 .therm = { 0x00000001, nv40_therm_new }, 844 .timer = { 0x00000001, nv41_timer_new }, 845 .volt = { 0x00000001, nv40_volt_new }, 846 .disp = { 0x00000001, nv04_disp_new }, 847 .dma = { 0x00000001, nv04_dma_new }, 848 .fifo = { 0x00000001, nv40_fifo_new }, 849 .gr = { 0x00000001, nv44_gr_new }, 850 .mpeg = { 0x00000001, nv44_mpeg_new }, 851 .sw = { 0x00000001, nv10_sw_new }, 852 }; 853 854 static const struct nvkm_device_chip 855 nv68_chipset = { 856 .name = "C68", 857 .bios = { 0x00000001, nvkm_bios_new }, 858 .bus = { 0x00000001, nv31_bus_new }, 859 .clk = { 0x00000001, nv40_clk_new }, 860 .devinit = { 0x00000001, nv1a_devinit_new }, 861 .fb = { 0x00000001, nv46_fb_new }, 862 .gpio = { 0x00000001, nv10_gpio_new }, 863 .i2c = { 0x00000001, nv04_i2c_new }, 864 .imem = { 0x00000001, nv40_instmem_new }, 865 .mc = { 0x00000001, nv44_mc_new }, 866 .mmu = { 0x00000001, nv44_mmu_new }, 867 .pci = { 0x00000001, nv4c_pci_new }, 868 .therm = { 0x00000001, nv40_therm_new }, 869 .timer = { 0x00000001, nv41_timer_new }, 870 .volt = { 0x00000001, nv40_volt_new }, 871 .disp = { 0x00000001, nv04_disp_new }, 872 .dma = { 0x00000001, nv04_dma_new }, 873 .fifo = { 0x00000001, nv40_fifo_new }, 874 .gr = { 0x00000001, nv44_gr_new }, 875 .mpeg = { 0x00000001, nv44_mpeg_new }, 876 .sw = { 0x00000001, nv10_sw_new }, 877 }; 878 879 static const struct nvkm_device_chip 880 nv84_chipset = { 881 .name = "G84", 882 .bar = { 0x00000001, g84_bar_new }, 883 .bios = { 0x00000001, nvkm_bios_new }, 884 .bus = { 0x00000001, nv50_bus_new }, 885 .clk = { 0x00000001, g84_clk_new }, 886 .devinit = { 0x00000001, g84_devinit_new }, 887 .fb = { 0x00000001, g84_fb_new }, 888 .fuse = { 0x00000001, nv50_fuse_new }, 889 .gpio = { 0x00000001, nv50_gpio_new }, 890 .i2c = { 0x00000001, nv50_i2c_new }, 891 .imem = { 0x00000001, nv50_instmem_new }, 892 .mc = { 0x00000001, g84_mc_new }, 893 .mmu = { 0x00000001, g84_mmu_new }, 894 .mxm = { 0x00000001, nv50_mxm_new }, 895 .pci = { 0x00000001, g84_pci_new }, 896 .therm = { 0x00000001, g84_therm_new }, 897 .timer = { 0x00000001, nv41_timer_new }, 898 .volt = { 0x00000001, nv40_volt_new }, 899 .bsp = { 0x00000001, g84_bsp_new }, 900 .cipher = { 0x00000001, g84_cipher_new }, 901 .disp = { 0x00000001, g84_disp_new }, 902 .dma = { 0x00000001, nv50_dma_new }, 903 .fifo = { 0x00000001, g84_fifo_new }, 904 .gr = { 0x00000001, g84_gr_new }, 905 .mpeg = { 0x00000001, g84_mpeg_new }, 906 .sw = { 0x00000001, nv50_sw_new }, 907 .vp = { 0x00000001, g84_vp_new }, 908 }; 909 910 static const struct nvkm_device_chip 911 nv86_chipset = { 912 .name = "G86", 913 .bar = { 0x00000001, g84_bar_new }, 914 .bios = { 0x00000001, nvkm_bios_new }, 915 .bus = { 0x00000001, nv50_bus_new }, 916 .clk = { 0x00000001, g84_clk_new }, 917 .devinit = { 0x00000001, g84_devinit_new }, 918 .fb = { 0x00000001, g84_fb_new }, 919 .fuse = { 0x00000001, nv50_fuse_new }, 920 .gpio = { 0x00000001, nv50_gpio_new }, 921 .i2c = { 0x00000001, nv50_i2c_new }, 922 .imem = { 0x00000001, nv50_instmem_new }, 923 .mc = { 0x00000001, g84_mc_new }, 924 .mmu = { 0x00000001, g84_mmu_new }, 925 .mxm = { 0x00000001, nv50_mxm_new }, 926 .pci = { 0x00000001, g84_pci_new }, 927 .therm = { 0x00000001, g84_therm_new }, 928 .timer = { 0x00000001, nv41_timer_new }, 929 .volt = { 0x00000001, nv40_volt_new }, 930 .bsp = { 0x00000001, g84_bsp_new }, 931 .cipher = { 0x00000001, g84_cipher_new }, 932 .disp = { 0x00000001, g84_disp_new }, 933 .dma = { 0x00000001, nv50_dma_new }, 934 .fifo = { 0x00000001, g84_fifo_new }, 935 .gr = { 0x00000001, g84_gr_new }, 936 .mpeg = { 0x00000001, g84_mpeg_new }, 937 .sw = { 0x00000001, nv50_sw_new }, 938 .vp = { 0x00000001, g84_vp_new }, 939 }; 940 941 static const struct nvkm_device_chip 942 nv92_chipset = { 943 .name = "G92", 944 .bar = { 0x00000001, g84_bar_new }, 945 .bios = { 0x00000001, nvkm_bios_new }, 946 .bus = { 0x00000001, nv50_bus_new }, 947 .clk = { 0x00000001, g84_clk_new }, 948 .devinit = { 0x00000001, g84_devinit_new }, 949 .fb = { 0x00000001, g84_fb_new }, 950 .fuse = { 0x00000001, nv50_fuse_new }, 951 .gpio = { 0x00000001, nv50_gpio_new }, 952 .i2c = { 0x00000001, nv50_i2c_new }, 953 .imem = { 0x00000001, nv50_instmem_new }, 954 .mc = { 0x00000001, g84_mc_new }, 955 .mmu = { 0x00000001, g84_mmu_new }, 956 .mxm = { 0x00000001, nv50_mxm_new }, 957 .pci = { 0x00000001, g92_pci_new }, 958 .therm = { 0x00000001, g84_therm_new }, 959 .timer = { 0x00000001, nv41_timer_new }, 960 .volt = { 0x00000001, nv40_volt_new }, 961 .bsp = { 0x00000001, g84_bsp_new }, 962 .cipher = { 0x00000001, g84_cipher_new }, 963 .disp = { 0x00000001, g84_disp_new }, 964 .dma = { 0x00000001, nv50_dma_new }, 965 .fifo = { 0x00000001, g84_fifo_new }, 966 .gr = { 0x00000001, g84_gr_new }, 967 .mpeg = { 0x00000001, g84_mpeg_new }, 968 .sw = { 0x00000001, nv50_sw_new }, 969 .vp = { 0x00000001, g84_vp_new }, 970 }; 971 972 static const struct nvkm_device_chip 973 nv94_chipset = { 974 .name = "G94", 975 .bar = { 0x00000001, g84_bar_new }, 976 .bios = { 0x00000001, nvkm_bios_new }, 977 .bus = { 0x00000001, g94_bus_new }, 978 .clk = { 0x00000001, g84_clk_new }, 979 .devinit = { 0x00000001, g84_devinit_new }, 980 .fb = { 0x00000001, g84_fb_new }, 981 .fuse = { 0x00000001, nv50_fuse_new }, 982 .gpio = { 0x00000001, g94_gpio_new }, 983 .i2c = { 0x00000001, g94_i2c_new }, 984 .imem = { 0x00000001, nv50_instmem_new }, 985 .mc = { 0x00000001, g84_mc_new }, 986 .mmu = { 0x00000001, g84_mmu_new }, 987 .mxm = { 0x00000001, nv50_mxm_new }, 988 .pci = { 0x00000001, g94_pci_new }, 989 .therm = { 0x00000001, g84_therm_new }, 990 .timer = { 0x00000001, nv41_timer_new }, 991 .volt = { 0x00000001, nv40_volt_new }, 992 .bsp = { 0x00000001, g84_bsp_new }, 993 .cipher = { 0x00000001, g84_cipher_new }, 994 .disp = { 0x00000001, g94_disp_new }, 995 .dma = { 0x00000001, nv50_dma_new }, 996 .fifo = { 0x00000001, g84_fifo_new }, 997 .gr = { 0x00000001, g84_gr_new }, 998 .mpeg = { 0x00000001, g84_mpeg_new }, 999 .sw = { 0x00000001, nv50_sw_new }, 1000 .vp = { 0x00000001, g84_vp_new }, 1001 }; 1002 1003 static const struct nvkm_device_chip 1004 nv96_chipset = { 1005 .name = "G96", 1006 .bar = { 0x00000001, g84_bar_new }, 1007 .bios = { 0x00000001, nvkm_bios_new }, 1008 .bus = { 0x00000001, g94_bus_new }, 1009 .clk = { 0x00000001, g84_clk_new }, 1010 .devinit = { 0x00000001, g84_devinit_new }, 1011 .fb = { 0x00000001, g84_fb_new }, 1012 .fuse = { 0x00000001, nv50_fuse_new }, 1013 .gpio = { 0x00000001, g94_gpio_new }, 1014 .i2c = { 0x00000001, g94_i2c_new }, 1015 .imem = { 0x00000001, nv50_instmem_new }, 1016 .mc = { 0x00000001, g84_mc_new }, 1017 .mmu = { 0x00000001, g84_mmu_new }, 1018 .mxm = { 0x00000001, nv50_mxm_new }, 1019 .pci = { 0x00000001, g94_pci_new }, 1020 .therm = { 0x00000001, g84_therm_new }, 1021 .timer = { 0x00000001, nv41_timer_new }, 1022 .volt = { 0x00000001, nv40_volt_new }, 1023 .bsp = { 0x00000001, g84_bsp_new }, 1024 .cipher = { 0x00000001, g84_cipher_new }, 1025 .disp = { 0x00000001, g94_disp_new }, 1026 .dma = { 0x00000001, nv50_dma_new }, 1027 .fifo = { 0x00000001, g84_fifo_new }, 1028 .gr = { 0x00000001, g84_gr_new }, 1029 .mpeg = { 0x00000001, g84_mpeg_new }, 1030 .sw = { 0x00000001, nv50_sw_new }, 1031 .vp = { 0x00000001, g84_vp_new }, 1032 }; 1033 1034 static const struct nvkm_device_chip 1035 nv98_chipset = { 1036 .name = "G98", 1037 .bar = { 0x00000001, g84_bar_new }, 1038 .bios = { 0x00000001, nvkm_bios_new }, 1039 .bus = { 0x00000001, g94_bus_new }, 1040 .clk = { 0x00000001, g84_clk_new }, 1041 .devinit = { 0x00000001, g98_devinit_new }, 1042 .fb = { 0x00000001, g84_fb_new }, 1043 .fuse = { 0x00000001, nv50_fuse_new }, 1044 .gpio = { 0x00000001, g94_gpio_new }, 1045 .i2c = { 0x00000001, g94_i2c_new }, 1046 .imem = { 0x00000001, nv50_instmem_new }, 1047 .mc = { 0x00000001, g98_mc_new }, 1048 .mmu = { 0x00000001, g84_mmu_new }, 1049 .mxm = { 0x00000001, nv50_mxm_new }, 1050 .pci = { 0x00000001, g94_pci_new }, 1051 .therm = { 0x00000001, g84_therm_new }, 1052 .timer = { 0x00000001, nv41_timer_new }, 1053 .volt = { 0x00000001, nv40_volt_new }, 1054 .disp = { 0x00000001, g94_disp_new }, 1055 .dma = { 0x00000001, nv50_dma_new }, 1056 .fifo = { 0x00000001, g98_fifo_new }, 1057 .gr = { 0x00000001, g84_gr_new }, 1058 .mspdec = { 0x00000001, g98_mspdec_new }, 1059 .msppp = { 0x00000001, g98_msppp_new }, 1060 .msvld = { 0x00000001, g98_msvld_new }, 1061 .sec = { 0x00000001, g98_sec_new }, 1062 .sw = { 0x00000001, nv50_sw_new }, 1063 }; 1064 1065 static const struct nvkm_device_chip 1066 nva0_chipset = { 1067 .name = "GT200", 1068 .bar = { 0x00000001, g84_bar_new }, 1069 .bios = { 0x00000001, nvkm_bios_new }, 1070 .bus = { 0x00000001, g94_bus_new }, 1071 .clk = { 0x00000001, g84_clk_new }, 1072 .devinit = { 0x00000001, g84_devinit_new }, 1073 .fb = { 0x00000001, g84_fb_new }, 1074 .fuse = { 0x00000001, nv50_fuse_new }, 1075 .gpio = { 0x00000001, g94_gpio_new }, 1076 .i2c = { 0x00000001, nv50_i2c_new }, 1077 .imem = { 0x00000001, nv50_instmem_new }, 1078 .mc = { 0x00000001, g84_mc_new }, 1079 .mmu = { 0x00000001, g84_mmu_new }, 1080 .mxm = { 0x00000001, nv50_mxm_new }, 1081 .pci = { 0x00000001, g94_pci_new }, 1082 .therm = { 0x00000001, g84_therm_new }, 1083 .timer = { 0x00000001, nv41_timer_new }, 1084 .volt = { 0x00000001, nv40_volt_new }, 1085 .bsp = { 0x00000001, g84_bsp_new }, 1086 .cipher = { 0x00000001, g84_cipher_new }, 1087 .disp = { 0x00000001, gt200_disp_new }, 1088 .dma = { 0x00000001, nv50_dma_new }, 1089 .fifo = { 0x00000001, g84_fifo_new }, 1090 .gr = { 0x00000001, gt200_gr_new }, 1091 .mpeg = { 0x00000001, g84_mpeg_new }, 1092 .sw = { 0x00000001, nv50_sw_new }, 1093 .vp = { 0x00000001, g84_vp_new }, 1094 }; 1095 1096 static const struct nvkm_device_chip 1097 nva3_chipset = { 1098 .name = "GT215", 1099 .bar = { 0x00000001, g84_bar_new }, 1100 .bios = { 0x00000001, nvkm_bios_new }, 1101 .bus = { 0x00000001, g94_bus_new }, 1102 .clk = { 0x00000001, gt215_clk_new }, 1103 .devinit = { 0x00000001, gt215_devinit_new }, 1104 .fb = { 0x00000001, gt215_fb_new }, 1105 .fuse = { 0x00000001, nv50_fuse_new }, 1106 .gpio = { 0x00000001, g94_gpio_new }, 1107 .i2c = { 0x00000001, g94_i2c_new }, 1108 .imem = { 0x00000001, nv50_instmem_new }, 1109 .mc = { 0x00000001, gt215_mc_new }, 1110 .mmu = { 0x00000001, g84_mmu_new }, 1111 .mxm = { 0x00000001, nv50_mxm_new }, 1112 .pci = { 0x00000001, g94_pci_new }, 1113 .pmu = { 0x00000001, gt215_pmu_new }, 1114 .therm = { 0x00000001, gt215_therm_new }, 1115 .timer = { 0x00000001, nv41_timer_new }, 1116 .volt = { 0x00000001, nv40_volt_new }, 1117 .ce = { 0x00000001, gt215_ce_new }, 1118 .disp = { 0x00000001, gt215_disp_new }, 1119 .dma = { 0x00000001, nv50_dma_new }, 1120 .fifo = { 0x00000001, g98_fifo_new }, 1121 .gr = { 0x00000001, gt215_gr_new }, 1122 .mpeg = { 0x00000001, g84_mpeg_new }, 1123 .mspdec = { 0x00000001, gt215_mspdec_new }, 1124 .msppp = { 0x00000001, gt215_msppp_new }, 1125 .msvld = { 0x00000001, gt215_msvld_new }, 1126 .sw = { 0x00000001, nv50_sw_new }, 1127 }; 1128 1129 static const struct nvkm_device_chip 1130 nva5_chipset = { 1131 .name = "GT216", 1132 .bar = { 0x00000001, g84_bar_new }, 1133 .bios = { 0x00000001, nvkm_bios_new }, 1134 .bus = { 0x00000001, g94_bus_new }, 1135 .clk = { 0x00000001, gt215_clk_new }, 1136 .devinit = { 0x00000001, gt215_devinit_new }, 1137 .fb = { 0x00000001, gt215_fb_new }, 1138 .fuse = { 0x00000001, nv50_fuse_new }, 1139 .gpio = { 0x00000001, g94_gpio_new }, 1140 .i2c = { 0x00000001, g94_i2c_new }, 1141 .imem = { 0x00000001, nv50_instmem_new }, 1142 .mc = { 0x00000001, gt215_mc_new }, 1143 .mmu = { 0x00000001, g84_mmu_new }, 1144 .mxm = { 0x00000001, nv50_mxm_new }, 1145 .pci = { 0x00000001, g94_pci_new }, 1146 .pmu = { 0x00000001, gt215_pmu_new }, 1147 .therm = { 0x00000001, gt215_therm_new }, 1148 .timer = { 0x00000001, nv41_timer_new }, 1149 .volt = { 0x00000001, nv40_volt_new }, 1150 .ce = { 0x00000001, gt215_ce_new }, 1151 .disp = { 0x00000001, gt215_disp_new }, 1152 .dma = { 0x00000001, nv50_dma_new }, 1153 .fifo = { 0x00000001, g98_fifo_new }, 1154 .gr = { 0x00000001, gt215_gr_new }, 1155 .mspdec = { 0x00000001, gt215_mspdec_new }, 1156 .msppp = { 0x00000001, gt215_msppp_new }, 1157 .msvld = { 0x00000001, gt215_msvld_new }, 1158 .sw = { 0x00000001, nv50_sw_new }, 1159 }; 1160 1161 static const struct nvkm_device_chip 1162 nva8_chipset = { 1163 .name = "GT218", 1164 .bar = { 0x00000001, g84_bar_new }, 1165 .bios = { 0x00000001, nvkm_bios_new }, 1166 .bus = { 0x00000001, g94_bus_new }, 1167 .clk = { 0x00000001, gt215_clk_new }, 1168 .devinit = { 0x00000001, gt215_devinit_new }, 1169 .fb = { 0x00000001, gt215_fb_new }, 1170 .fuse = { 0x00000001, nv50_fuse_new }, 1171 .gpio = { 0x00000001, g94_gpio_new }, 1172 .i2c = { 0x00000001, g94_i2c_new }, 1173 .imem = { 0x00000001, nv50_instmem_new }, 1174 .mc = { 0x00000001, gt215_mc_new }, 1175 .mmu = { 0x00000001, g84_mmu_new }, 1176 .mxm = { 0x00000001, nv50_mxm_new }, 1177 .pci = { 0x00000001, g94_pci_new }, 1178 .pmu = { 0x00000001, gt215_pmu_new }, 1179 .therm = { 0x00000001, gt215_therm_new }, 1180 .timer = { 0x00000001, nv41_timer_new }, 1181 .volt = { 0x00000001, nv40_volt_new }, 1182 .ce = { 0x00000001, gt215_ce_new }, 1183 .disp = { 0x00000001, gt215_disp_new }, 1184 .dma = { 0x00000001, nv50_dma_new }, 1185 .fifo = { 0x00000001, g98_fifo_new }, 1186 .gr = { 0x00000001, gt215_gr_new }, 1187 .mspdec = { 0x00000001, gt215_mspdec_new }, 1188 .msppp = { 0x00000001, gt215_msppp_new }, 1189 .msvld = { 0x00000001, gt215_msvld_new }, 1190 .sw = { 0x00000001, nv50_sw_new }, 1191 }; 1192 1193 static const struct nvkm_device_chip 1194 nvaa_chipset = { 1195 .name = "MCP77/MCP78", 1196 .bar = { 0x00000001, g84_bar_new }, 1197 .bios = { 0x00000001, nvkm_bios_new }, 1198 .bus = { 0x00000001, g94_bus_new }, 1199 .clk = { 0x00000001, mcp77_clk_new }, 1200 .devinit = { 0x00000001, g98_devinit_new }, 1201 .fb = { 0x00000001, mcp77_fb_new }, 1202 .fuse = { 0x00000001, nv50_fuse_new }, 1203 .gpio = { 0x00000001, g94_gpio_new }, 1204 .i2c = { 0x00000001, g94_i2c_new }, 1205 .imem = { 0x00000001, nv50_instmem_new }, 1206 .mc = { 0x00000001, g98_mc_new }, 1207 .mmu = { 0x00000001, mcp77_mmu_new }, 1208 .mxm = { 0x00000001, nv50_mxm_new }, 1209 .pci = { 0x00000001, g94_pci_new }, 1210 .therm = { 0x00000001, g84_therm_new }, 1211 .timer = { 0x00000001, nv41_timer_new }, 1212 .volt = { 0x00000001, nv40_volt_new }, 1213 .disp = { 0x00000001, mcp77_disp_new }, 1214 .dma = { 0x00000001, nv50_dma_new }, 1215 .fifo = { 0x00000001, g98_fifo_new }, 1216 .gr = { 0x00000001, gt200_gr_new }, 1217 .mspdec = { 0x00000001, g98_mspdec_new }, 1218 .msppp = { 0x00000001, g98_msppp_new }, 1219 .msvld = { 0x00000001, g98_msvld_new }, 1220 .sec = { 0x00000001, g98_sec_new }, 1221 .sw = { 0x00000001, nv50_sw_new }, 1222 }; 1223 1224 static const struct nvkm_device_chip 1225 nvac_chipset = { 1226 .name = "MCP79/MCP7A", 1227 .bar = { 0x00000001, g84_bar_new }, 1228 .bios = { 0x00000001, nvkm_bios_new }, 1229 .bus = { 0x00000001, g94_bus_new }, 1230 .clk = { 0x00000001, mcp77_clk_new }, 1231 .devinit = { 0x00000001, g98_devinit_new }, 1232 .fb = { 0x00000001, mcp77_fb_new }, 1233 .fuse = { 0x00000001, nv50_fuse_new }, 1234 .gpio = { 0x00000001, g94_gpio_new }, 1235 .i2c = { 0x00000001, g94_i2c_new }, 1236 .imem = { 0x00000001, nv50_instmem_new }, 1237 .mc = { 0x00000001, g98_mc_new }, 1238 .mmu = { 0x00000001, mcp77_mmu_new }, 1239 .mxm = { 0x00000001, nv50_mxm_new }, 1240 .pci = { 0x00000001, g94_pci_new }, 1241 .therm = { 0x00000001, g84_therm_new }, 1242 .timer = { 0x00000001, nv41_timer_new }, 1243 .volt = { 0x00000001, nv40_volt_new }, 1244 .disp = { 0x00000001, mcp77_disp_new }, 1245 .dma = { 0x00000001, nv50_dma_new }, 1246 .fifo = { 0x00000001, g98_fifo_new }, 1247 .gr = { 0x00000001, mcp79_gr_new }, 1248 .mspdec = { 0x00000001, g98_mspdec_new }, 1249 .msppp = { 0x00000001, g98_msppp_new }, 1250 .msvld = { 0x00000001, g98_msvld_new }, 1251 .sec = { 0x00000001, g98_sec_new }, 1252 .sw = { 0x00000001, nv50_sw_new }, 1253 }; 1254 1255 static const struct nvkm_device_chip 1256 nvaf_chipset = { 1257 .name = "MCP89", 1258 .bar = { 0x00000001, g84_bar_new }, 1259 .bios = { 0x00000001, nvkm_bios_new }, 1260 .bus = { 0x00000001, g94_bus_new }, 1261 .clk = { 0x00000001, gt215_clk_new }, 1262 .devinit = { 0x00000001, mcp89_devinit_new }, 1263 .fb = { 0x00000001, mcp89_fb_new }, 1264 .fuse = { 0x00000001, nv50_fuse_new }, 1265 .gpio = { 0x00000001, g94_gpio_new }, 1266 .i2c = { 0x00000001, g94_i2c_new }, 1267 .imem = { 0x00000001, nv50_instmem_new }, 1268 .mc = { 0x00000001, gt215_mc_new }, 1269 .mmu = { 0x00000001, mcp77_mmu_new }, 1270 .mxm = { 0x00000001, nv50_mxm_new }, 1271 .pci = { 0x00000001, g94_pci_new }, 1272 .pmu = { 0x00000001, gt215_pmu_new }, 1273 .therm = { 0x00000001, gt215_therm_new }, 1274 .timer = { 0x00000001, nv41_timer_new }, 1275 .volt = { 0x00000001, nv40_volt_new }, 1276 .ce = { 0x00000001, gt215_ce_new }, 1277 .disp = { 0x00000001, mcp89_disp_new }, 1278 .dma = { 0x00000001, nv50_dma_new }, 1279 .fifo = { 0x00000001, g98_fifo_new }, 1280 .gr = { 0x00000001, mcp89_gr_new }, 1281 .mspdec = { 0x00000001, gt215_mspdec_new }, 1282 .msppp = { 0x00000001, gt215_msppp_new }, 1283 .msvld = { 0x00000001, mcp89_msvld_new }, 1284 .sw = { 0x00000001, nv50_sw_new }, 1285 }; 1286 1287 static const struct nvkm_device_chip 1288 nvc0_chipset = { 1289 .name = "GF100", 1290 .bar = { 0x00000001, gf100_bar_new }, 1291 .bios = { 0x00000001, nvkm_bios_new }, 1292 .bus = { 0x00000001, gf100_bus_new }, 1293 .clk = { 0x00000001, gf100_clk_new }, 1294 .devinit = { 0x00000001, gf100_devinit_new }, 1295 .fb = { 0x00000001, gf100_fb_new }, 1296 .fuse = { 0x00000001, gf100_fuse_new }, 1297 .gpio = { 0x00000001, g94_gpio_new }, 1298 .i2c = { 0x00000001, g94_i2c_new }, 1299 .iccsense = { 0x00000001, gf100_iccsense_new }, 1300 .imem = { 0x00000001, nv50_instmem_new }, 1301 .ltc = { 0x00000001, gf100_ltc_new }, 1302 .mc = { 0x00000001, gf100_mc_new }, 1303 .mmu = { 0x00000001, gf100_mmu_new }, 1304 .mxm = { 0x00000001, nv50_mxm_new }, 1305 .pci = { 0x00000001, gf100_pci_new }, 1306 .pmu = { 0x00000001, gf100_pmu_new }, 1307 .privring = { 0x00000001, gf100_privring_new }, 1308 .therm = { 0x00000001, gt215_therm_new }, 1309 .timer = { 0x00000001, nv41_timer_new }, 1310 .volt = { 0x00000001, gf100_volt_new }, 1311 .ce = { 0x00000003, gf100_ce_new }, 1312 .disp = { 0x00000001, gt215_disp_new }, 1313 .dma = { 0x00000001, gf100_dma_new }, 1314 .fifo = { 0x00000001, gf100_fifo_new }, 1315 .gr = { 0x00000001, gf100_gr_new }, 1316 .mspdec = { 0x00000001, gf100_mspdec_new }, 1317 .msppp = { 0x00000001, gf100_msppp_new }, 1318 .msvld = { 0x00000001, gf100_msvld_new }, 1319 .sw = { 0x00000001, gf100_sw_new }, 1320 }; 1321 1322 static const struct nvkm_device_chip 1323 nvc1_chipset = { 1324 .name = "GF108", 1325 .bar = { 0x00000001, gf100_bar_new }, 1326 .bios = { 0x00000001, nvkm_bios_new }, 1327 .bus = { 0x00000001, gf100_bus_new }, 1328 .clk = { 0x00000001, gf100_clk_new }, 1329 .devinit = { 0x00000001, gf100_devinit_new }, 1330 .fb = { 0x00000001, gf108_fb_new }, 1331 .fuse = { 0x00000001, gf100_fuse_new }, 1332 .gpio = { 0x00000001, g94_gpio_new }, 1333 .i2c = { 0x00000001, g94_i2c_new }, 1334 .iccsense = { 0x00000001, gf100_iccsense_new }, 1335 .imem = { 0x00000001, nv50_instmem_new }, 1336 .ltc = { 0x00000001, gf100_ltc_new }, 1337 .mc = { 0x00000001, gf100_mc_new }, 1338 .mmu = { 0x00000001, gf100_mmu_new }, 1339 .mxm = { 0x00000001, nv50_mxm_new }, 1340 .pci = { 0x00000001, gf106_pci_new }, 1341 .pmu = { 0x00000001, gf100_pmu_new }, 1342 .privring = { 0x00000001, gf100_privring_new }, 1343 .therm = { 0x00000001, gt215_therm_new }, 1344 .timer = { 0x00000001, nv41_timer_new }, 1345 .volt = { 0x00000001, gf100_volt_new }, 1346 .ce = { 0x00000001, gf100_ce_new }, 1347 .disp = { 0x00000001, gt215_disp_new }, 1348 .dma = { 0x00000001, gf100_dma_new }, 1349 .fifo = { 0x00000001, gf100_fifo_new }, 1350 .gr = { 0x00000001, gf108_gr_new }, 1351 .mspdec = { 0x00000001, gf100_mspdec_new }, 1352 .msppp = { 0x00000001, gf100_msppp_new }, 1353 .msvld = { 0x00000001, gf100_msvld_new }, 1354 .sw = { 0x00000001, gf100_sw_new }, 1355 }; 1356 1357 static const struct nvkm_device_chip 1358 nvc3_chipset = { 1359 .name = "GF106", 1360 .bar = { 0x00000001, gf100_bar_new }, 1361 .bios = { 0x00000001, nvkm_bios_new }, 1362 .bus = { 0x00000001, gf100_bus_new }, 1363 .clk = { 0x00000001, gf100_clk_new }, 1364 .devinit = { 0x00000001, gf100_devinit_new }, 1365 .fb = { 0x00000001, gf100_fb_new }, 1366 .fuse = { 0x00000001, gf100_fuse_new }, 1367 .gpio = { 0x00000001, g94_gpio_new }, 1368 .i2c = { 0x00000001, g94_i2c_new }, 1369 .iccsense = { 0x00000001, gf100_iccsense_new }, 1370 .imem = { 0x00000001, nv50_instmem_new }, 1371 .ltc = { 0x00000001, gf100_ltc_new }, 1372 .mc = { 0x00000001, gf100_mc_new }, 1373 .mmu = { 0x00000001, gf100_mmu_new }, 1374 .mxm = { 0x00000001, nv50_mxm_new }, 1375 .pci = { 0x00000001, gf106_pci_new }, 1376 .pmu = { 0x00000001, gf100_pmu_new }, 1377 .privring = { 0x00000001, gf100_privring_new }, 1378 .therm = { 0x00000001, gt215_therm_new }, 1379 .timer = { 0x00000001, nv41_timer_new }, 1380 .volt = { 0x00000001, gf100_volt_new }, 1381 .ce = { 0x00000001, gf100_ce_new }, 1382 .disp = { 0x00000001, gt215_disp_new }, 1383 .dma = { 0x00000001, gf100_dma_new }, 1384 .fifo = { 0x00000001, gf100_fifo_new }, 1385 .gr = { 0x00000001, gf104_gr_new }, 1386 .mspdec = { 0x00000001, gf100_mspdec_new }, 1387 .msppp = { 0x00000001, gf100_msppp_new }, 1388 .msvld = { 0x00000001, gf100_msvld_new }, 1389 .sw = { 0x00000001, gf100_sw_new }, 1390 }; 1391 1392 static const struct nvkm_device_chip 1393 nvc4_chipset = { 1394 .name = "GF104", 1395 .bar = { 0x00000001, gf100_bar_new }, 1396 .bios = { 0x00000001, nvkm_bios_new }, 1397 .bus = { 0x00000001, gf100_bus_new }, 1398 .clk = { 0x00000001, gf100_clk_new }, 1399 .devinit = { 0x00000001, gf100_devinit_new }, 1400 .fb = { 0x00000001, gf100_fb_new }, 1401 .fuse = { 0x00000001, gf100_fuse_new }, 1402 .gpio = { 0x00000001, g94_gpio_new }, 1403 .i2c = { 0x00000001, g94_i2c_new }, 1404 .iccsense = { 0x00000001, gf100_iccsense_new }, 1405 .imem = { 0x00000001, nv50_instmem_new }, 1406 .ltc = { 0x00000001, gf100_ltc_new }, 1407 .mc = { 0x00000001, gf100_mc_new }, 1408 .mmu = { 0x00000001, gf100_mmu_new }, 1409 .mxm = { 0x00000001, nv50_mxm_new }, 1410 .pci = { 0x00000001, gf100_pci_new }, 1411 .pmu = { 0x00000001, gf100_pmu_new }, 1412 .privring = { 0x00000001, gf100_privring_new }, 1413 .therm = { 0x00000001, gt215_therm_new }, 1414 .timer = { 0x00000001, nv41_timer_new }, 1415 .volt = { 0x00000001, gf100_volt_new }, 1416 .ce = { 0x00000003, gf100_ce_new }, 1417 .disp = { 0x00000001, gt215_disp_new }, 1418 .dma = { 0x00000001, gf100_dma_new }, 1419 .fifo = { 0x00000001, gf100_fifo_new }, 1420 .gr = { 0x00000001, gf104_gr_new }, 1421 .mspdec = { 0x00000001, gf100_mspdec_new }, 1422 .msppp = { 0x00000001, gf100_msppp_new }, 1423 .msvld = { 0x00000001, gf100_msvld_new }, 1424 .sw = { 0x00000001, gf100_sw_new }, 1425 }; 1426 1427 static const struct nvkm_device_chip 1428 nvc8_chipset = { 1429 .name = "GF110", 1430 .bar = { 0x00000001, gf100_bar_new }, 1431 .bios = { 0x00000001, nvkm_bios_new }, 1432 .bus = { 0x00000001, gf100_bus_new }, 1433 .clk = { 0x00000001, gf100_clk_new }, 1434 .devinit = { 0x00000001, gf100_devinit_new }, 1435 .fb = { 0x00000001, gf100_fb_new }, 1436 .fuse = { 0x00000001, gf100_fuse_new }, 1437 .gpio = { 0x00000001, g94_gpio_new }, 1438 .i2c = { 0x00000001, g94_i2c_new }, 1439 .iccsense = { 0x00000001, gf100_iccsense_new }, 1440 .imem = { 0x00000001, nv50_instmem_new }, 1441 .ltc = { 0x00000001, gf100_ltc_new }, 1442 .mc = { 0x00000001, gf100_mc_new }, 1443 .mmu = { 0x00000001, gf100_mmu_new }, 1444 .mxm = { 0x00000001, nv50_mxm_new }, 1445 .pci = { 0x00000001, gf100_pci_new }, 1446 .pmu = { 0x00000001, gf100_pmu_new }, 1447 .privring = { 0x00000001, gf100_privring_new }, 1448 .therm = { 0x00000001, gt215_therm_new }, 1449 .timer = { 0x00000001, nv41_timer_new }, 1450 .volt = { 0x00000001, gf100_volt_new }, 1451 .ce = { 0x00000003, gf100_ce_new }, 1452 .disp = { 0x00000001, gt215_disp_new }, 1453 .dma = { 0x00000001, gf100_dma_new }, 1454 .fifo = { 0x00000001, gf100_fifo_new }, 1455 .gr = { 0x00000001, gf110_gr_new }, 1456 .mspdec = { 0x00000001, gf100_mspdec_new }, 1457 .msppp = { 0x00000001, gf100_msppp_new }, 1458 .msvld = { 0x00000001, gf100_msvld_new }, 1459 .sw = { 0x00000001, gf100_sw_new }, 1460 }; 1461 1462 static const struct nvkm_device_chip 1463 nvce_chipset = { 1464 .name = "GF114", 1465 .bar = { 0x00000001, gf100_bar_new }, 1466 .bios = { 0x00000001, nvkm_bios_new }, 1467 .bus = { 0x00000001, gf100_bus_new }, 1468 .clk = { 0x00000001, gf100_clk_new }, 1469 .devinit = { 0x00000001, gf100_devinit_new }, 1470 .fb = { 0x00000001, gf100_fb_new }, 1471 .fuse = { 0x00000001, gf100_fuse_new }, 1472 .gpio = { 0x00000001, g94_gpio_new }, 1473 .i2c = { 0x00000001, g94_i2c_new }, 1474 .iccsense = { 0x00000001, gf100_iccsense_new }, 1475 .imem = { 0x00000001, nv50_instmem_new }, 1476 .ltc = { 0x00000001, gf100_ltc_new }, 1477 .mc = { 0x00000001, gf100_mc_new }, 1478 .mmu = { 0x00000001, gf100_mmu_new }, 1479 .mxm = { 0x00000001, nv50_mxm_new }, 1480 .pci = { 0x00000001, gf100_pci_new }, 1481 .pmu = { 0x00000001, gf100_pmu_new }, 1482 .privring = { 0x00000001, gf100_privring_new }, 1483 .therm = { 0x00000001, gt215_therm_new }, 1484 .timer = { 0x00000001, nv41_timer_new }, 1485 .volt = { 0x00000001, gf100_volt_new }, 1486 .ce = { 0x00000003, gf100_ce_new }, 1487 .disp = { 0x00000001, gt215_disp_new }, 1488 .dma = { 0x00000001, gf100_dma_new }, 1489 .fifo = { 0x00000001, gf100_fifo_new }, 1490 .gr = { 0x00000001, gf104_gr_new }, 1491 .mspdec = { 0x00000001, gf100_mspdec_new }, 1492 .msppp = { 0x00000001, gf100_msppp_new }, 1493 .msvld = { 0x00000001, gf100_msvld_new }, 1494 .sw = { 0x00000001, gf100_sw_new }, 1495 }; 1496 1497 static const struct nvkm_device_chip 1498 nvcf_chipset = { 1499 .name = "GF116", 1500 .bar = { 0x00000001, gf100_bar_new }, 1501 .bios = { 0x00000001, nvkm_bios_new }, 1502 .bus = { 0x00000001, gf100_bus_new }, 1503 .clk = { 0x00000001, gf100_clk_new }, 1504 .devinit = { 0x00000001, gf100_devinit_new }, 1505 .fb = { 0x00000001, gf100_fb_new }, 1506 .fuse = { 0x00000001, gf100_fuse_new }, 1507 .gpio = { 0x00000001, g94_gpio_new }, 1508 .i2c = { 0x00000001, g94_i2c_new }, 1509 .iccsense = { 0x00000001, gf100_iccsense_new }, 1510 .imem = { 0x00000001, nv50_instmem_new }, 1511 .ltc = { 0x00000001, gf100_ltc_new }, 1512 .mc = { 0x00000001, gf100_mc_new }, 1513 .mmu = { 0x00000001, gf100_mmu_new }, 1514 .mxm = { 0x00000001, nv50_mxm_new }, 1515 .pci = { 0x00000001, gf106_pci_new }, 1516 .pmu = { 0x00000001, gf100_pmu_new }, 1517 .privring = { 0x00000001, gf100_privring_new }, 1518 .therm = { 0x00000001, gt215_therm_new }, 1519 .timer = { 0x00000001, nv41_timer_new }, 1520 .volt = { 0x00000001, gf100_volt_new }, 1521 .ce = { 0x00000001, gf100_ce_new }, 1522 .disp = { 0x00000001, gt215_disp_new }, 1523 .dma = { 0x00000001, gf100_dma_new }, 1524 .fifo = { 0x00000001, gf100_fifo_new }, 1525 .gr = { 0x00000001, gf104_gr_new }, 1526 .mspdec = { 0x00000001, gf100_mspdec_new }, 1527 .msppp = { 0x00000001, gf100_msppp_new }, 1528 .msvld = { 0x00000001, gf100_msvld_new }, 1529 .sw = { 0x00000001, gf100_sw_new }, 1530 }; 1531 1532 static const struct nvkm_device_chip 1533 nvd7_chipset = { 1534 .name = "GF117", 1535 .bar = { 0x00000001, gf100_bar_new }, 1536 .bios = { 0x00000001, nvkm_bios_new }, 1537 .bus = { 0x00000001, gf100_bus_new }, 1538 .clk = { 0x00000001, gf100_clk_new }, 1539 .devinit = { 0x00000001, gf100_devinit_new }, 1540 .fb = { 0x00000001, gf100_fb_new }, 1541 .fuse = { 0x00000001, gf100_fuse_new }, 1542 .gpio = { 0x00000001, gf119_gpio_new }, 1543 .i2c = { 0x00000001, gf117_i2c_new }, 1544 .iccsense = { 0x00000001, gf100_iccsense_new }, 1545 .imem = { 0x00000001, nv50_instmem_new }, 1546 .ltc = { 0x00000001, gf100_ltc_new }, 1547 .mc = { 0x00000001, gf100_mc_new }, 1548 .mmu = { 0x00000001, gf100_mmu_new }, 1549 .mxm = { 0x00000001, nv50_mxm_new }, 1550 .pci = { 0x00000001, gf106_pci_new }, 1551 .privring = { 0x00000001, gf117_privring_new }, 1552 .therm = { 0x00000001, gf119_therm_new }, 1553 .timer = { 0x00000001, nv41_timer_new }, 1554 .volt = { 0x00000001, gf117_volt_new }, 1555 .ce = { 0x00000001, gf100_ce_new }, 1556 .disp = { 0x00000001, gf119_disp_new }, 1557 .dma = { 0x00000001, gf119_dma_new }, 1558 .fifo = { 0x00000001, gf100_fifo_new }, 1559 .gr = { 0x00000001, gf117_gr_new }, 1560 .mspdec = { 0x00000001, gf100_mspdec_new }, 1561 .msppp = { 0x00000001, gf100_msppp_new }, 1562 .msvld = { 0x00000001, gf100_msvld_new }, 1563 .sw = { 0x00000001, gf100_sw_new }, 1564 }; 1565 1566 static const struct nvkm_device_chip 1567 nvd9_chipset = { 1568 .name = "GF119", 1569 .bar = { 0x00000001, gf100_bar_new }, 1570 .bios = { 0x00000001, nvkm_bios_new }, 1571 .bus = { 0x00000001, gf100_bus_new }, 1572 .clk = { 0x00000001, gf100_clk_new }, 1573 .devinit = { 0x00000001, gf100_devinit_new }, 1574 .fb = { 0x00000001, gf100_fb_new }, 1575 .fuse = { 0x00000001, gf100_fuse_new }, 1576 .gpio = { 0x00000001, gf119_gpio_new }, 1577 .i2c = { 0x00000001, gf119_i2c_new }, 1578 .iccsense = { 0x00000001, gf100_iccsense_new }, 1579 .imem = { 0x00000001, nv50_instmem_new }, 1580 .ltc = { 0x00000001, gf100_ltc_new }, 1581 .mc = { 0x00000001, gf100_mc_new }, 1582 .mmu = { 0x00000001, gf100_mmu_new }, 1583 .mxm = { 0x00000001, nv50_mxm_new }, 1584 .pci = { 0x00000001, gf106_pci_new }, 1585 .pmu = { 0x00000001, gf119_pmu_new }, 1586 .privring = { 0x00000001, gf117_privring_new }, 1587 .therm = { 0x00000001, gf119_therm_new }, 1588 .timer = { 0x00000001, nv41_timer_new }, 1589 .volt = { 0x00000001, gf100_volt_new }, 1590 .ce = { 0x00000001, gf100_ce_new }, 1591 .disp = { 0x00000001, gf119_disp_new }, 1592 .dma = { 0x00000001, gf119_dma_new }, 1593 .fifo = { 0x00000001, gf100_fifo_new }, 1594 .gr = { 0x00000001, gf119_gr_new }, 1595 .mspdec = { 0x00000001, gf100_mspdec_new }, 1596 .msppp = { 0x00000001, gf100_msppp_new }, 1597 .msvld = { 0x00000001, gf100_msvld_new }, 1598 .sw = { 0x00000001, gf100_sw_new }, 1599 }; 1600 1601 static const struct nvkm_device_chip 1602 nve4_chipset = { 1603 .name = "GK104", 1604 .bar = { 0x00000001, gf100_bar_new }, 1605 .bios = { 0x00000001, nvkm_bios_new }, 1606 .bus = { 0x00000001, gf100_bus_new }, 1607 .clk = { 0x00000001, gk104_clk_new }, 1608 .devinit = { 0x00000001, gf100_devinit_new }, 1609 .fb = { 0x00000001, gk104_fb_new }, 1610 .fuse = { 0x00000001, gf100_fuse_new }, 1611 .gpio = { 0x00000001, gk104_gpio_new }, 1612 .i2c = { 0x00000001, gk104_i2c_new }, 1613 .iccsense = { 0x00000001, gf100_iccsense_new }, 1614 .imem = { 0x00000001, nv50_instmem_new }, 1615 .ltc = { 0x00000001, gk104_ltc_new }, 1616 .mc = { 0x00000001, gk104_mc_new }, 1617 .mmu = { 0x00000001, gk104_mmu_new }, 1618 .mxm = { 0x00000001, nv50_mxm_new }, 1619 .pci = { 0x00000001, gk104_pci_new }, 1620 .pmu = { 0x00000001, gk104_pmu_new }, 1621 .privring = { 0x00000001, gk104_privring_new }, 1622 .therm = { 0x00000001, gk104_therm_new }, 1623 .timer = { 0x00000001, nv41_timer_new }, 1624 .top = { 0x00000001, gk104_top_new }, 1625 .volt = { 0x00000001, gk104_volt_new }, 1626 .ce = { 0x00000007, gk104_ce_new }, 1627 .disp = { 0x00000001, gk104_disp_new }, 1628 .dma = { 0x00000001, gf119_dma_new }, 1629 .fifo = { 0x00000001, gk104_fifo_new }, 1630 .gr = { 0x00000001, gk104_gr_new }, 1631 .mspdec = { 0x00000001, gk104_mspdec_new }, 1632 .msppp = { 0x00000001, gf100_msppp_new }, 1633 .msvld = { 0x00000001, gk104_msvld_new }, 1634 .sw = { 0x00000001, gf100_sw_new }, 1635 }; 1636 1637 static const struct nvkm_device_chip 1638 nve6_chipset = { 1639 .name = "GK106", 1640 .bar = { 0x00000001, gf100_bar_new }, 1641 .bios = { 0x00000001, nvkm_bios_new }, 1642 .bus = { 0x00000001, gf100_bus_new }, 1643 .clk = { 0x00000001, gk104_clk_new }, 1644 .devinit = { 0x00000001, gf100_devinit_new }, 1645 .fb = { 0x00000001, gk104_fb_new }, 1646 .fuse = { 0x00000001, gf100_fuse_new }, 1647 .gpio = { 0x00000001, gk104_gpio_new }, 1648 .i2c = { 0x00000001, gk104_i2c_new }, 1649 .iccsense = { 0x00000001, gf100_iccsense_new }, 1650 .imem = { 0x00000001, nv50_instmem_new }, 1651 .ltc = { 0x00000001, gk104_ltc_new }, 1652 .mc = { 0x00000001, gk104_mc_new }, 1653 .mmu = { 0x00000001, gk104_mmu_new }, 1654 .mxm = { 0x00000001, nv50_mxm_new }, 1655 .pci = { 0x00000001, gk104_pci_new }, 1656 .pmu = { 0x00000001, gk104_pmu_new }, 1657 .privring = { 0x00000001, gk104_privring_new }, 1658 .therm = { 0x00000001, gk104_therm_new }, 1659 .timer = { 0x00000001, nv41_timer_new }, 1660 .top = { 0x00000001, gk104_top_new }, 1661 .volt = { 0x00000001, gk104_volt_new }, 1662 .ce = { 0x00000007, gk104_ce_new }, 1663 .disp = { 0x00000001, gk104_disp_new }, 1664 .dma = { 0x00000001, gf119_dma_new }, 1665 .fifo = { 0x00000001, gk104_fifo_new }, 1666 .gr = { 0x00000001, gk104_gr_new }, 1667 .mspdec = { 0x00000001, gk104_mspdec_new }, 1668 .msppp = { 0x00000001, gf100_msppp_new }, 1669 .msvld = { 0x00000001, gk104_msvld_new }, 1670 .sw = { 0x00000001, gf100_sw_new }, 1671 }; 1672 1673 static const struct nvkm_device_chip 1674 nve7_chipset = { 1675 .name = "GK107", 1676 .bar = { 0x00000001, gf100_bar_new }, 1677 .bios = { 0x00000001, nvkm_bios_new }, 1678 .bus = { 0x00000001, gf100_bus_new }, 1679 .clk = { 0x00000001, gk104_clk_new }, 1680 .devinit = { 0x00000001, gf100_devinit_new }, 1681 .fb = { 0x00000001, gk104_fb_new }, 1682 .fuse = { 0x00000001, gf100_fuse_new }, 1683 .gpio = { 0x00000001, gk104_gpio_new }, 1684 .i2c = { 0x00000001, gk104_i2c_new }, 1685 .iccsense = { 0x00000001, gf100_iccsense_new }, 1686 .imem = { 0x00000001, nv50_instmem_new }, 1687 .ltc = { 0x00000001, gk104_ltc_new }, 1688 .mc = { 0x00000001, gk104_mc_new }, 1689 .mmu = { 0x00000001, gk104_mmu_new }, 1690 .mxm = { 0x00000001, nv50_mxm_new }, 1691 .pci = { 0x00000001, gk104_pci_new }, 1692 .pmu = { 0x00000001, gk104_pmu_new }, 1693 .privring = { 0x00000001, gk104_privring_new }, 1694 .therm = { 0x00000001, gk104_therm_new }, 1695 .timer = { 0x00000001, nv41_timer_new }, 1696 .top = { 0x00000001, gk104_top_new }, 1697 .volt = { 0x00000001, gk104_volt_new }, 1698 .ce = { 0x00000007, gk104_ce_new }, 1699 .disp = { 0x00000001, gk104_disp_new }, 1700 .dma = { 0x00000001, gf119_dma_new }, 1701 .fifo = { 0x00000001, gk104_fifo_new }, 1702 .gr = { 0x00000001, gk104_gr_new }, 1703 .mspdec = { 0x00000001, gk104_mspdec_new }, 1704 .msppp = { 0x00000001, gf100_msppp_new }, 1705 .msvld = { 0x00000001, gk104_msvld_new }, 1706 .sw = { 0x00000001, gf100_sw_new }, 1707 }; 1708 1709 static const struct nvkm_device_chip 1710 nvea_chipset = { 1711 .name = "GK20A", 1712 .bar = { 0x00000001, gk20a_bar_new }, 1713 .bus = { 0x00000001, gf100_bus_new }, 1714 .clk = { 0x00000001, gk20a_clk_new }, 1715 .fb = { 0x00000001, gk20a_fb_new }, 1716 .fuse = { 0x00000001, gf100_fuse_new }, 1717 .imem = { 0x00000001, gk20a_instmem_new }, 1718 .ltc = { 0x00000001, gk104_ltc_new }, 1719 .mc = { 0x00000001, gk20a_mc_new }, 1720 .mmu = { 0x00000001, gk20a_mmu_new }, 1721 .pmu = { 0x00000001, gk20a_pmu_new }, 1722 .privring = { 0x00000001, gk20a_privring_new }, 1723 .timer = { 0x00000001, gk20a_timer_new }, 1724 .top = { 0x00000001, gk104_top_new }, 1725 .volt = { 0x00000001, gk20a_volt_new }, 1726 .ce = { 0x00000004, gk104_ce_new }, 1727 .dma = { 0x00000001, gf119_dma_new }, 1728 .fifo = { 0x00000001, gk20a_fifo_new }, 1729 .gr = { 0x00000001, gk20a_gr_new }, 1730 .sw = { 0x00000001, gf100_sw_new }, 1731 }; 1732 1733 static const struct nvkm_device_chip 1734 nvf0_chipset = { 1735 .name = "GK110", 1736 .bar = { 0x00000001, gf100_bar_new }, 1737 .bios = { 0x00000001, nvkm_bios_new }, 1738 .bus = { 0x00000001, gf100_bus_new }, 1739 .clk = { 0x00000001, gk104_clk_new }, 1740 .devinit = { 0x00000001, gf100_devinit_new }, 1741 .fb = { 0x00000001, gk110_fb_new }, 1742 .fuse = { 0x00000001, gf100_fuse_new }, 1743 .gpio = { 0x00000001, gk104_gpio_new }, 1744 .i2c = { 0x00000001, gk110_i2c_new }, 1745 .iccsense = { 0x00000001, gf100_iccsense_new }, 1746 .imem = { 0x00000001, nv50_instmem_new }, 1747 .ltc = { 0x00000001, gk104_ltc_new }, 1748 .mc = { 0x00000001, gk104_mc_new }, 1749 .mmu = { 0x00000001, gk104_mmu_new }, 1750 .mxm = { 0x00000001, nv50_mxm_new }, 1751 .pci = { 0x00000001, gk104_pci_new }, 1752 .pmu = { 0x00000001, gk110_pmu_new }, 1753 .privring = { 0x00000001, gk104_privring_new }, 1754 .therm = { 0x00000001, gk104_therm_new }, 1755 .timer = { 0x00000001, nv41_timer_new }, 1756 .top = { 0x00000001, gk104_top_new }, 1757 .volt = { 0x00000001, gk104_volt_new }, 1758 .ce = { 0x00000007, gk104_ce_new }, 1759 .disp = { 0x00000001, gk110_disp_new }, 1760 .dma = { 0x00000001, gf119_dma_new }, 1761 .fifo = { 0x00000001, gk110_fifo_new }, 1762 .gr = { 0x00000001, gk110_gr_new }, 1763 .mspdec = { 0x00000001, gk104_mspdec_new }, 1764 .msppp = { 0x00000001, gf100_msppp_new }, 1765 .msvld = { 0x00000001, gk104_msvld_new }, 1766 .sw = { 0x00000001, gf100_sw_new }, 1767 }; 1768 1769 static const struct nvkm_device_chip 1770 nvf1_chipset = { 1771 .name = "GK110B", 1772 .bar = { 0x00000001, gf100_bar_new }, 1773 .bios = { 0x00000001, nvkm_bios_new }, 1774 .bus = { 0x00000001, gf100_bus_new }, 1775 .clk = { 0x00000001, gk104_clk_new }, 1776 .devinit = { 0x00000001, gf100_devinit_new }, 1777 .fb = { 0x00000001, gk110_fb_new }, 1778 .fuse = { 0x00000001, gf100_fuse_new }, 1779 .gpio = { 0x00000001, gk104_gpio_new }, 1780 .i2c = { 0x00000001, gk110_i2c_new }, 1781 .iccsense = { 0x00000001, gf100_iccsense_new }, 1782 .imem = { 0x00000001, nv50_instmem_new }, 1783 .ltc = { 0x00000001, gk104_ltc_new }, 1784 .mc = { 0x00000001, gk104_mc_new }, 1785 .mmu = { 0x00000001, gk104_mmu_new }, 1786 .mxm = { 0x00000001, nv50_mxm_new }, 1787 .pci = { 0x00000001, gk104_pci_new }, 1788 .pmu = { 0x00000001, gk110_pmu_new }, 1789 .privring = { 0x00000001, gk104_privring_new }, 1790 .therm = { 0x00000001, gk104_therm_new }, 1791 .timer = { 0x00000001, nv41_timer_new }, 1792 .top = { 0x00000001, gk104_top_new }, 1793 .volt = { 0x00000001, gk104_volt_new }, 1794 .ce = { 0x00000007, gk104_ce_new }, 1795 .disp = { 0x00000001, gk110_disp_new }, 1796 .dma = { 0x00000001, gf119_dma_new }, 1797 .fifo = { 0x00000001, gk110_fifo_new }, 1798 .gr = { 0x00000001, gk110b_gr_new }, 1799 .mspdec = { 0x00000001, gk104_mspdec_new }, 1800 .msppp = { 0x00000001, gf100_msppp_new }, 1801 .msvld = { 0x00000001, gk104_msvld_new }, 1802 .sw = { 0x00000001, gf100_sw_new }, 1803 }; 1804 1805 static const struct nvkm_device_chip 1806 nv106_chipset = { 1807 .name = "GK208B", 1808 .bar = { 0x00000001, gf100_bar_new }, 1809 .bios = { 0x00000001, nvkm_bios_new }, 1810 .bus = { 0x00000001, gf100_bus_new }, 1811 .clk = { 0x00000001, gk104_clk_new }, 1812 .devinit = { 0x00000001, gf100_devinit_new }, 1813 .fb = { 0x00000001, gk110_fb_new }, 1814 .fuse = { 0x00000001, gf100_fuse_new }, 1815 .gpio = { 0x00000001, gk104_gpio_new }, 1816 .i2c = { 0x00000001, gk110_i2c_new }, 1817 .iccsense = { 0x00000001, gf100_iccsense_new }, 1818 .imem = { 0x00000001, nv50_instmem_new }, 1819 .ltc = { 0x00000001, gk104_ltc_new }, 1820 .mc = { 0x00000001, gk20a_mc_new }, 1821 .mmu = { 0x00000001, gk104_mmu_new }, 1822 .mxm = { 0x00000001, nv50_mxm_new }, 1823 .pci = { 0x00000001, gk104_pci_new }, 1824 .pmu = { 0x00000001, gk208_pmu_new }, 1825 .privring = { 0x00000001, gk104_privring_new }, 1826 .therm = { 0x00000001, gk104_therm_new }, 1827 .timer = { 0x00000001, nv41_timer_new }, 1828 .top = { 0x00000001, gk104_top_new }, 1829 .volt = { 0x00000001, gk104_volt_new }, 1830 .ce = { 0x00000007, gk104_ce_new }, 1831 .disp = { 0x00000001, gk110_disp_new }, 1832 .dma = { 0x00000001, gf119_dma_new }, 1833 .fifo = { 0x00000001, gk208_fifo_new }, 1834 .gr = { 0x00000001, gk208_gr_new }, 1835 .mspdec = { 0x00000001, gk104_mspdec_new }, 1836 .msppp = { 0x00000001, gf100_msppp_new }, 1837 .msvld = { 0x00000001, gk104_msvld_new }, 1838 .sw = { 0x00000001, gf100_sw_new }, 1839 }; 1840 1841 static const struct nvkm_device_chip 1842 nv108_chipset = { 1843 .name = "GK208", 1844 .bar = { 0x00000001, gf100_bar_new }, 1845 .bios = { 0x00000001, nvkm_bios_new }, 1846 .bus = { 0x00000001, gf100_bus_new }, 1847 .clk = { 0x00000001, gk104_clk_new }, 1848 .devinit = { 0x00000001, gf100_devinit_new }, 1849 .fb = { 0x00000001, gk110_fb_new }, 1850 .fuse = { 0x00000001, gf100_fuse_new }, 1851 .gpio = { 0x00000001, gk104_gpio_new }, 1852 .i2c = { 0x00000001, gk110_i2c_new }, 1853 .iccsense = { 0x00000001, gf100_iccsense_new }, 1854 .imem = { 0x00000001, nv50_instmem_new }, 1855 .ltc = { 0x00000001, gk104_ltc_new }, 1856 .mc = { 0x00000001, gk20a_mc_new }, 1857 .mmu = { 0x00000001, gk104_mmu_new }, 1858 .mxm = { 0x00000001, nv50_mxm_new }, 1859 .pci = { 0x00000001, gk104_pci_new }, 1860 .pmu = { 0x00000001, gk208_pmu_new }, 1861 .privring = { 0x00000001, gk104_privring_new }, 1862 .therm = { 0x00000001, gk104_therm_new }, 1863 .timer = { 0x00000001, nv41_timer_new }, 1864 .top = { 0x00000001, gk104_top_new }, 1865 .volt = { 0x00000001, gk104_volt_new }, 1866 .ce = { 0x00000007, gk104_ce_new }, 1867 .disp = { 0x00000001, gk110_disp_new }, 1868 .dma = { 0x00000001, gf119_dma_new }, 1869 .fifo = { 0x00000001, gk208_fifo_new }, 1870 .gr = { 0x00000001, gk208_gr_new }, 1871 .mspdec = { 0x00000001, gk104_mspdec_new }, 1872 .msppp = { 0x00000001, gf100_msppp_new }, 1873 .msvld = { 0x00000001, gk104_msvld_new }, 1874 .sw = { 0x00000001, gf100_sw_new }, 1875 }; 1876 1877 static const struct nvkm_device_chip 1878 nv117_chipset = { 1879 .name = "GM107", 1880 .bar = { 0x00000001, gm107_bar_new }, 1881 .bios = { 0x00000001, nvkm_bios_new }, 1882 .bus = { 0x00000001, gf100_bus_new }, 1883 .clk = { 0x00000001, gk104_clk_new }, 1884 .devinit = { 0x00000001, gm107_devinit_new }, 1885 .fb = { 0x00000001, gm107_fb_new }, 1886 .fuse = { 0x00000001, gm107_fuse_new }, 1887 .gpio = { 0x00000001, gk104_gpio_new }, 1888 .i2c = { 0x00000001, gk110_i2c_new }, 1889 .iccsense = { 0x00000001, gf100_iccsense_new }, 1890 .imem = { 0x00000001, nv50_instmem_new }, 1891 .ltc = { 0x00000001, gm107_ltc_new }, 1892 .mc = { 0x00000001, gk20a_mc_new }, 1893 .mmu = { 0x00000001, gk104_mmu_new }, 1894 .mxm = { 0x00000001, nv50_mxm_new }, 1895 .pci = { 0x00000001, gk104_pci_new }, 1896 .pmu = { 0x00000001, gm107_pmu_new }, 1897 .privring = { 0x00000001, gk104_privring_new }, 1898 .therm = { 0x00000001, gm107_therm_new }, 1899 .timer = { 0x00000001, gk20a_timer_new }, 1900 .top = { 0x00000001, gk104_top_new }, 1901 .volt = { 0x00000001, gk104_volt_new }, 1902 .ce = { 0x00000005, gm107_ce_new }, 1903 .disp = { 0x00000001, gm107_disp_new }, 1904 .dma = { 0x00000001, gf119_dma_new }, 1905 .fifo = { 0x00000001, gm107_fifo_new }, 1906 .gr = { 0x00000001, gm107_gr_new }, 1907 .nvdec = { 0x00000001, gm107_nvdec_new }, 1908 .nvenc = { 0x00000001, gm107_nvenc_new }, 1909 .sw = { 0x00000001, gf100_sw_new }, 1910 }; 1911 1912 static const struct nvkm_device_chip 1913 nv118_chipset = { 1914 .name = "GM108", 1915 .bar = { 0x00000001, gm107_bar_new }, 1916 .bios = { 0x00000001, nvkm_bios_new }, 1917 .bus = { 0x00000001, gf100_bus_new }, 1918 .clk = { 0x00000001, gk104_clk_new }, 1919 .devinit = { 0x00000001, gm107_devinit_new }, 1920 .fb = { 0x00000001, gm107_fb_new }, 1921 .fuse = { 0x00000001, gm107_fuse_new }, 1922 .gpio = { 0x00000001, gk104_gpio_new }, 1923 .i2c = { 0x00000001, gk110_i2c_new }, 1924 .iccsense = { 0x00000001, gf100_iccsense_new }, 1925 .imem = { 0x00000001, nv50_instmem_new }, 1926 .ltc = { 0x00000001, gm107_ltc_new }, 1927 .mc = { 0x00000001, gk20a_mc_new }, 1928 .mmu = { 0x00000001, gk104_mmu_new }, 1929 .mxm = { 0x00000001, nv50_mxm_new }, 1930 .pci = { 0x00000001, gk104_pci_new }, 1931 .pmu = { 0x00000001, gm107_pmu_new }, 1932 .privring = { 0x00000001, gk104_privring_new }, 1933 .therm = { 0x00000001, gm107_therm_new }, 1934 .timer = { 0x00000001, gk20a_timer_new }, 1935 .top = { 0x00000001, gk104_top_new }, 1936 .volt = { 0x00000001, gk104_volt_new }, 1937 .ce = { 0x00000005, gm107_ce_new }, 1938 .disp = { 0x00000001, gm107_disp_new }, 1939 .dma = { 0x00000001, gf119_dma_new }, 1940 .fifo = { 0x00000001, gm107_fifo_new }, 1941 .gr = { 0x00000001, gm107_gr_new }, 1942 .sw = { 0x00000001, gf100_sw_new }, 1943 }; 1944 1945 static const struct nvkm_device_chip 1946 nv120_chipset = { 1947 .name = "GM200", 1948 .acr = { 0x00000001, gm200_acr_new }, 1949 .bar = { 0x00000001, gm107_bar_new }, 1950 .bios = { 0x00000001, nvkm_bios_new }, 1951 .bus = { 0x00000001, gf100_bus_new }, 1952 .devinit = { 0x00000001, gm200_devinit_new }, 1953 .fb = { 0x00000001, gm200_fb_new }, 1954 .fuse = { 0x00000001, gm107_fuse_new }, 1955 .gpio = { 0x00000001, gk104_gpio_new }, 1956 .i2c = { 0x00000001, gm200_i2c_new }, 1957 .iccsense = { 0x00000001, gf100_iccsense_new }, 1958 .imem = { 0x00000001, nv50_instmem_new }, 1959 .ltc = { 0x00000001, gm200_ltc_new }, 1960 .mc = { 0x00000001, gk20a_mc_new }, 1961 .mmu = { 0x00000001, gm200_mmu_new }, 1962 .mxm = { 0x00000001, nv50_mxm_new }, 1963 .pci = { 0x00000001, gk104_pci_new }, 1964 .pmu = { 0x00000001, gm200_pmu_new }, 1965 .privring = { 0x00000001, gm200_privring_new }, 1966 .therm = { 0x00000001, gm200_therm_new }, 1967 .timer = { 0x00000001, gk20a_timer_new }, 1968 .top = { 0x00000001, gk104_top_new }, 1969 .volt = { 0x00000001, gk104_volt_new }, 1970 .ce = { 0x00000007, gm200_ce_new }, 1971 .disp = { 0x00000001, gm200_disp_new }, 1972 .dma = { 0x00000001, gf119_dma_new }, 1973 .fifo = { 0x00000001, gm200_fifo_new }, 1974 .gr = { 0x00000001, gm200_gr_new }, 1975 .nvdec = { 0x00000001, gm107_nvdec_new }, 1976 .nvenc = { 0x00000003, gm107_nvenc_new }, 1977 .sw = { 0x00000001, gf100_sw_new }, 1978 }; 1979 1980 static const struct nvkm_device_chip 1981 nv124_chipset = { 1982 .name = "GM204", 1983 .acr = { 0x00000001, gm200_acr_new }, 1984 .bar = { 0x00000001, gm107_bar_new }, 1985 .bios = { 0x00000001, nvkm_bios_new }, 1986 .bus = { 0x00000001, gf100_bus_new }, 1987 .devinit = { 0x00000001, gm200_devinit_new }, 1988 .fb = { 0x00000001, gm200_fb_new }, 1989 .fuse = { 0x00000001, gm107_fuse_new }, 1990 .gpio = { 0x00000001, gk104_gpio_new }, 1991 .i2c = { 0x00000001, gm200_i2c_new }, 1992 .iccsense = { 0x00000001, gf100_iccsense_new }, 1993 .imem = { 0x00000001, nv50_instmem_new }, 1994 .ltc = { 0x00000001, gm200_ltc_new }, 1995 .mc = { 0x00000001, gk20a_mc_new }, 1996 .mmu = { 0x00000001, gm200_mmu_new }, 1997 .mxm = { 0x00000001, nv50_mxm_new }, 1998 .pci = { 0x00000001, gk104_pci_new }, 1999 .pmu = { 0x00000001, gm200_pmu_new }, 2000 .privring = { 0x00000001, gm200_privring_new }, 2001 .therm = { 0x00000001, gm200_therm_new }, 2002 .timer = { 0x00000001, gk20a_timer_new }, 2003 .top = { 0x00000001, gk104_top_new }, 2004 .volt = { 0x00000001, gk104_volt_new }, 2005 .ce = { 0x00000007, gm200_ce_new }, 2006 .disp = { 0x00000001, gm200_disp_new }, 2007 .dma = { 0x00000001, gf119_dma_new }, 2008 .fifo = { 0x00000001, gm200_fifo_new }, 2009 .gr = { 0x00000001, gm200_gr_new }, 2010 .nvdec = { 0x00000001, gm107_nvdec_new }, 2011 .nvenc = { 0x00000003, gm107_nvenc_new }, 2012 .sw = { 0x00000001, gf100_sw_new }, 2013 }; 2014 2015 static const struct nvkm_device_chip 2016 nv126_chipset = { 2017 .name = "GM206", 2018 .acr = { 0x00000001, gm200_acr_new }, 2019 .bar = { 0x00000001, gm107_bar_new }, 2020 .bios = { 0x00000001, nvkm_bios_new }, 2021 .bus = { 0x00000001, gf100_bus_new }, 2022 .devinit = { 0x00000001, gm200_devinit_new }, 2023 .fb = { 0x00000001, gm200_fb_new }, 2024 .fuse = { 0x00000001, gm107_fuse_new }, 2025 .gpio = { 0x00000001, gk104_gpio_new }, 2026 .i2c = { 0x00000001, gm200_i2c_new }, 2027 .iccsense = { 0x00000001, gf100_iccsense_new }, 2028 .imem = { 0x00000001, nv50_instmem_new }, 2029 .ltc = { 0x00000001, gm200_ltc_new }, 2030 .mc = { 0x00000001, gk20a_mc_new }, 2031 .mmu = { 0x00000001, gm200_mmu_new }, 2032 .mxm = { 0x00000001, nv50_mxm_new }, 2033 .pci = { 0x00000001, gk104_pci_new }, 2034 .pmu = { 0x00000001, gm200_pmu_new }, 2035 .privring = { 0x00000001, gm200_privring_new }, 2036 .therm = { 0x00000001, gm200_therm_new }, 2037 .timer = { 0x00000001, gk20a_timer_new }, 2038 .top = { 0x00000001, gk104_top_new }, 2039 .volt = { 0x00000001, gk104_volt_new }, 2040 .ce = { 0x00000007, gm200_ce_new }, 2041 .disp = { 0x00000001, gm200_disp_new }, 2042 .dma = { 0x00000001, gf119_dma_new }, 2043 .fifo = { 0x00000001, gm200_fifo_new }, 2044 .gr = { 0x00000001, gm200_gr_new }, 2045 .nvdec = { 0x00000001, gm107_nvdec_new }, 2046 .nvenc = { 0x00000001, gm107_nvenc_new }, 2047 .sw = { 0x00000001, gf100_sw_new }, 2048 }; 2049 2050 static const struct nvkm_device_chip 2051 nv12b_chipset = { 2052 .name = "GM20B", 2053 .acr = { 0x00000001, gm20b_acr_new }, 2054 .bar = { 0x00000001, gm20b_bar_new }, 2055 .bus = { 0x00000001, gf100_bus_new }, 2056 .clk = { 0x00000001, gm20b_clk_new }, 2057 .fb = { 0x00000001, gm20b_fb_new }, 2058 .fuse = { 0x00000001, gm107_fuse_new }, 2059 .imem = { 0x00000001, gk20a_instmem_new }, 2060 .ltc = { 0x00000001, gm200_ltc_new }, 2061 .mc = { 0x00000001, gk20a_mc_new }, 2062 .mmu = { 0x00000001, gm20b_mmu_new }, 2063 .pmu = { 0x00000001, gm20b_pmu_new }, 2064 .privring = { 0x00000001, gk20a_privring_new }, 2065 .timer = { 0x00000001, gk20a_timer_new }, 2066 .top = { 0x00000001, gk104_top_new }, 2067 .volt = { 0x00000001, gm20b_volt_new }, 2068 .ce = { 0x00000004, gm200_ce_new }, 2069 .dma = { 0x00000001, gf119_dma_new }, 2070 .fifo = { 0x00000001, gm200_fifo_new }, 2071 .gr = { 0x00000001, gm20b_gr_new }, 2072 .sw = { 0x00000001, gf100_sw_new }, 2073 }; 2074 2075 static const struct nvkm_device_chip 2076 nv130_chipset = { 2077 .name = "GP100", 2078 .acr = { 0x00000001, gm200_acr_new }, 2079 .bar = { 0x00000001, gm107_bar_new }, 2080 .bios = { 0x00000001, nvkm_bios_new }, 2081 .bus = { 0x00000001, gf100_bus_new }, 2082 .devinit = { 0x00000001, gm200_devinit_new }, 2083 .fault = { 0x00000001, gp100_fault_new }, 2084 .fb = { 0x00000001, gp100_fb_new }, 2085 .fuse = { 0x00000001, gm107_fuse_new }, 2086 .gpio = { 0x00000001, gk104_gpio_new }, 2087 .i2c = { 0x00000001, gm200_i2c_new }, 2088 .imem = { 0x00000001, nv50_instmem_new }, 2089 .ltc = { 0x00000001, gp100_ltc_new }, 2090 .mc = { 0x00000001, gp100_mc_new }, 2091 .mmu = { 0x00000001, gp100_mmu_new }, 2092 .therm = { 0x00000001, gp100_therm_new }, 2093 .pci = { 0x00000001, gp100_pci_new }, 2094 .pmu = { 0x00000001, gm200_pmu_new }, 2095 .privring = { 0x00000001, gm200_privring_new }, 2096 .timer = { 0x00000001, gk20a_timer_new }, 2097 .top = { 0x00000001, gk104_top_new }, 2098 .ce = { 0x0000003f, gp100_ce_new }, 2099 .dma = { 0x00000001, gf119_dma_new }, 2100 .disp = { 0x00000001, gp100_disp_new }, 2101 .fifo = { 0x00000001, gp100_fifo_new }, 2102 .gr = { 0x00000001, gp100_gr_new }, 2103 .nvdec = { 0x00000001, gm107_nvdec_new }, 2104 .nvenc = { 0x00000007, gm107_nvenc_new }, 2105 .sw = { 0x00000001, gf100_sw_new }, 2106 }; 2107 2108 static const struct nvkm_device_chip 2109 nv132_chipset = { 2110 .name = "GP102", 2111 .acr = { 0x00000001, gp102_acr_new }, 2112 .bar = { 0x00000001, gm107_bar_new }, 2113 .bios = { 0x00000001, nvkm_bios_new }, 2114 .bus = { 0x00000001, gf100_bus_new }, 2115 .devinit = { 0x00000001, gm200_devinit_new }, 2116 .fault = { 0x00000001, gp100_fault_new }, 2117 .fb = { 0x00000001, gp102_fb_new }, 2118 .fuse = { 0x00000001, gm107_fuse_new }, 2119 .gpio = { 0x00000001, gk104_gpio_new }, 2120 .i2c = { 0x00000001, gm200_i2c_new }, 2121 .imem = { 0x00000001, nv50_instmem_new }, 2122 .ltc = { 0x00000001, gp102_ltc_new }, 2123 .mc = { 0x00000001, gp100_mc_new }, 2124 .mmu = { 0x00000001, gp100_mmu_new }, 2125 .therm = { 0x00000001, gp100_therm_new }, 2126 .pci = { 0x00000001, gp100_pci_new }, 2127 .pmu = { 0x00000001, gp102_pmu_new }, 2128 .privring = { 0x00000001, gm200_privring_new }, 2129 .timer = { 0x00000001, gk20a_timer_new }, 2130 .top = { 0x00000001, gk104_top_new }, 2131 .ce = { 0x0000000f, gp102_ce_new }, 2132 .disp = { 0x00000001, gp102_disp_new }, 2133 .dma = { 0x00000001, gf119_dma_new }, 2134 .fifo = { 0x00000001, gp100_fifo_new }, 2135 .gr = { 0x00000001, gp102_gr_new }, 2136 .nvdec = { 0x00000001, gm107_nvdec_new }, 2137 .nvenc = { 0x00000003, gm107_nvenc_new }, 2138 .sec2 = { 0x00000001, gp102_sec2_new }, 2139 .sw = { 0x00000001, gf100_sw_new }, 2140 }; 2141 2142 static const struct nvkm_device_chip 2143 nv134_chipset = { 2144 .name = "GP104", 2145 .acr = { 0x00000001, gp102_acr_new }, 2146 .bar = { 0x00000001, gm107_bar_new }, 2147 .bios = { 0x00000001, nvkm_bios_new }, 2148 .bus = { 0x00000001, gf100_bus_new }, 2149 .devinit = { 0x00000001, gm200_devinit_new }, 2150 .fault = { 0x00000001, gp100_fault_new }, 2151 .fb = { 0x00000001, gp102_fb_new }, 2152 .fuse = { 0x00000001, gm107_fuse_new }, 2153 .gpio = { 0x00000001, gk104_gpio_new }, 2154 .i2c = { 0x00000001, gm200_i2c_new }, 2155 .imem = { 0x00000001, nv50_instmem_new }, 2156 .ltc = { 0x00000001, gp102_ltc_new }, 2157 .mc = { 0x00000001, gp100_mc_new }, 2158 .mmu = { 0x00000001, gp100_mmu_new }, 2159 .therm = { 0x00000001, gp100_therm_new }, 2160 .pci = { 0x00000001, gp100_pci_new }, 2161 .pmu = { 0x00000001, gp102_pmu_new }, 2162 .privring = { 0x00000001, gm200_privring_new }, 2163 .timer = { 0x00000001, gk20a_timer_new }, 2164 .top = { 0x00000001, gk104_top_new }, 2165 .ce = { 0x0000000f, gp102_ce_new }, 2166 .disp = { 0x00000001, gp102_disp_new }, 2167 .dma = { 0x00000001, gf119_dma_new }, 2168 .fifo = { 0x00000001, gp100_fifo_new }, 2169 .gr = { 0x00000001, gp104_gr_new }, 2170 .nvdec = { 0x00000001, gm107_nvdec_new }, 2171 .nvenc = { 0x00000003, gm107_nvenc_new }, 2172 .sec2 = { 0x00000001, gp102_sec2_new }, 2173 .sw = { 0x00000001, gf100_sw_new }, 2174 }; 2175 2176 static const struct nvkm_device_chip 2177 nv136_chipset = { 2178 .name = "GP106", 2179 .acr = { 0x00000001, gp102_acr_new }, 2180 .bar = { 0x00000001, gm107_bar_new }, 2181 .bios = { 0x00000001, nvkm_bios_new }, 2182 .bus = { 0x00000001, gf100_bus_new }, 2183 .devinit = { 0x00000001, gm200_devinit_new }, 2184 .fault = { 0x00000001, gp100_fault_new }, 2185 .fb = { 0x00000001, gp102_fb_new }, 2186 .fuse = { 0x00000001, gm107_fuse_new }, 2187 .gpio = { 0x00000001, gk104_gpio_new }, 2188 .i2c = { 0x00000001, gm200_i2c_new }, 2189 .imem = { 0x00000001, nv50_instmem_new }, 2190 .ltc = { 0x00000001, gp102_ltc_new }, 2191 .mc = { 0x00000001, gp100_mc_new }, 2192 .mmu = { 0x00000001, gp100_mmu_new }, 2193 .therm = { 0x00000001, gp100_therm_new }, 2194 .pci = { 0x00000001, gp100_pci_new }, 2195 .pmu = { 0x00000001, gp102_pmu_new }, 2196 .privring = { 0x00000001, gm200_privring_new }, 2197 .timer = { 0x00000001, gk20a_timer_new }, 2198 .top = { 0x00000001, gk104_top_new }, 2199 .ce = { 0x0000000f, gp102_ce_new }, 2200 .disp = { 0x00000001, gp102_disp_new }, 2201 .dma = { 0x00000001, gf119_dma_new }, 2202 .fifo = { 0x00000001, gp100_fifo_new }, 2203 .gr = { 0x00000001, gp104_gr_new }, 2204 .nvdec = { 0x00000001, gm107_nvdec_new }, 2205 .nvenc = { 0x00000001, gm107_nvenc_new }, 2206 .sec2 = { 0x00000001, gp102_sec2_new }, 2207 .sw = { 0x00000001, gf100_sw_new }, 2208 }; 2209 2210 static const struct nvkm_device_chip 2211 nv137_chipset = { 2212 .name = "GP107", 2213 .acr = { 0x00000001, gp102_acr_new }, 2214 .bar = { 0x00000001, gm107_bar_new }, 2215 .bios = { 0x00000001, nvkm_bios_new }, 2216 .bus = { 0x00000001, gf100_bus_new }, 2217 .devinit = { 0x00000001, gm200_devinit_new }, 2218 .fault = { 0x00000001, gp100_fault_new }, 2219 .fb = { 0x00000001, gp102_fb_new }, 2220 .fuse = { 0x00000001, gm107_fuse_new }, 2221 .gpio = { 0x00000001, gk104_gpio_new }, 2222 .i2c = { 0x00000001, gm200_i2c_new }, 2223 .imem = { 0x00000001, nv50_instmem_new }, 2224 .ltc = { 0x00000001, gp102_ltc_new }, 2225 .mc = { 0x00000001, gp100_mc_new }, 2226 .mmu = { 0x00000001, gp100_mmu_new }, 2227 .therm = { 0x00000001, gp100_therm_new }, 2228 .pci = { 0x00000001, gp100_pci_new }, 2229 .pmu = { 0x00000001, gp102_pmu_new }, 2230 .privring = { 0x00000001, gm200_privring_new }, 2231 .timer = { 0x00000001, gk20a_timer_new }, 2232 .top = { 0x00000001, gk104_top_new }, 2233 .ce = { 0x0000000f, gp102_ce_new }, 2234 .disp = { 0x00000001, gp102_disp_new }, 2235 .dma = { 0x00000001, gf119_dma_new }, 2236 .fifo = { 0x00000001, gp100_fifo_new }, 2237 .gr = { 0x00000001, gp107_gr_new }, 2238 .nvdec = { 0x00000001, gm107_nvdec_new }, 2239 .nvenc = { 0x00000003, gm107_nvenc_new }, 2240 .sec2 = { 0x00000001, gp102_sec2_new }, 2241 .sw = { 0x00000001, gf100_sw_new }, 2242 }; 2243 2244 static const struct nvkm_device_chip 2245 nv138_chipset = { 2246 .name = "GP108", 2247 .acr = { 0x00000001, gp108_acr_new }, 2248 .bar = { 0x00000001, gm107_bar_new }, 2249 .bios = { 0x00000001, nvkm_bios_new }, 2250 .bus = { 0x00000001, gf100_bus_new }, 2251 .devinit = { 0x00000001, gm200_devinit_new }, 2252 .fault = { 0x00000001, gp100_fault_new }, 2253 .fb = { 0x00000001, gp102_fb_new }, 2254 .fuse = { 0x00000001, gm107_fuse_new }, 2255 .gpio = { 0x00000001, gk104_gpio_new }, 2256 .i2c = { 0x00000001, gm200_i2c_new }, 2257 .imem = { 0x00000001, nv50_instmem_new }, 2258 .ltc = { 0x00000001, gp102_ltc_new }, 2259 .mc = { 0x00000001, gp100_mc_new }, 2260 .mmu = { 0x00000001, gp100_mmu_new }, 2261 .therm = { 0x00000001, gp100_therm_new }, 2262 .pci = { 0x00000001, gp100_pci_new }, 2263 .pmu = { 0x00000001, gp102_pmu_new }, 2264 .privring = { 0x00000001, gm200_privring_new }, 2265 .timer = { 0x00000001, gk20a_timer_new }, 2266 .top = { 0x00000001, gk104_top_new }, 2267 .ce = { 0x0000000f, gp102_ce_new }, 2268 .disp = { 0x00000001, gp102_disp_new }, 2269 .dma = { 0x00000001, gf119_dma_new }, 2270 .fifo = { 0x00000001, gp100_fifo_new }, 2271 .gr = { 0x00000001, gp108_gr_new }, 2272 .nvdec = { 0x00000001, gm107_nvdec_new }, 2273 .sec2 = { 0x00000001, gp108_sec2_new }, 2274 .sw = { 0x00000001, gf100_sw_new }, 2275 }; 2276 2277 static const struct nvkm_device_chip 2278 nv13b_chipset = { 2279 .name = "GP10B", 2280 .acr = { 0x00000001, gp10b_acr_new }, 2281 .bar = { 0x00000001, gm20b_bar_new }, 2282 .bus = { 0x00000001, gf100_bus_new }, 2283 .fault = { 0x00000001, gp10b_fault_new }, 2284 .fb = { 0x00000001, gp10b_fb_new }, 2285 .fuse = { 0x00000001, gm107_fuse_new }, 2286 .imem = { 0x00000001, gk20a_instmem_new }, 2287 .ltc = { 0x00000001, gp10b_ltc_new }, 2288 .mc = { 0x00000001, gp10b_mc_new }, 2289 .mmu = { 0x00000001, gp10b_mmu_new }, 2290 .pmu = { 0x00000001, gp10b_pmu_new }, 2291 .privring = { 0x00000001, gp10b_privring_new }, 2292 .timer = { 0x00000001, gk20a_timer_new }, 2293 .top = { 0x00000001, gk104_top_new }, 2294 .ce = { 0x00000001, gp100_ce_new }, 2295 .dma = { 0x00000001, gf119_dma_new }, 2296 .fifo = { 0x00000001, gp100_fifo_new }, 2297 .gr = { 0x00000001, gp10b_gr_new }, 2298 .sw = { 0x00000001, gf100_sw_new }, 2299 }; 2300 2301 static const struct nvkm_device_chip 2302 nv140_chipset = { 2303 .name = "GV100", 2304 .acr = { 0x00000001, gv100_acr_new }, 2305 .bar = { 0x00000001, gm107_bar_new }, 2306 .bios = { 0x00000001, nvkm_bios_new }, 2307 .bus = { 0x00000001, gf100_bus_new }, 2308 .devinit = { 0x00000001, gv100_devinit_new }, 2309 .fault = { 0x00000001, gv100_fault_new }, 2310 .fb = { 0x00000001, gv100_fb_new }, 2311 .fuse = { 0x00000001, gm107_fuse_new }, 2312 .gpio = { 0x00000001, gk104_gpio_new }, 2313 .gsp = { 0x00000001, gv100_gsp_new }, 2314 .i2c = { 0x00000001, gm200_i2c_new }, 2315 .imem = { 0x00000001, nv50_instmem_new }, 2316 .ltc = { 0x00000001, gp102_ltc_new }, 2317 .mc = { 0x00000001, gp100_mc_new }, 2318 .mmu = { 0x00000001, gv100_mmu_new }, 2319 .pci = { 0x00000001, gp100_pci_new }, 2320 .pmu = { 0x00000001, gp102_pmu_new }, 2321 .privring = { 0x00000001, gm200_privring_new }, 2322 .therm = { 0x00000001, gp100_therm_new }, 2323 .timer = { 0x00000001, gk20a_timer_new }, 2324 .top = { 0x00000001, gk104_top_new }, 2325 .vfn = { 0x00000001, gv100_vfn_new }, 2326 .ce = { 0x000001ff, gv100_ce_new }, 2327 .disp = { 0x00000001, gv100_disp_new }, 2328 .dma = { 0x00000001, gv100_dma_new }, 2329 .fifo = { 0x00000001, gv100_fifo_new }, 2330 .gr = { 0x00000001, gv100_gr_new }, 2331 .nvdec = { 0x00000001, gm107_nvdec_new }, 2332 .nvenc = { 0x00000007, gm107_nvenc_new }, 2333 .sec2 = { 0x00000001, gp108_sec2_new }, 2334 }; 2335 2336 static const struct nvkm_device_chip 2337 nv162_chipset = { 2338 .name = "TU102", 2339 .acr = { 0x00000001, tu102_acr_new }, 2340 .bar = { 0x00000001, tu102_bar_new }, 2341 .bios = { 0x00000001, nvkm_bios_new }, 2342 .bus = { 0x00000001, gf100_bus_new }, 2343 .devinit = { 0x00000001, tu102_devinit_new }, 2344 .fault = { 0x00000001, tu102_fault_new }, 2345 .fb = { 0x00000001, tu102_fb_new }, 2346 .fuse = { 0x00000001, gm107_fuse_new }, 2347 .gpio = { 0x00000001, gk104_gpio_new }, 2348 .gsp = { 0x00000001, tu102_gsp_new }, 2349 .i2c = { 0x00000001, gm200_i2c_new }, 2350 .imem = { 0x00000001, nv50_instmem_new }, 2351 .ltc = { 0x00000001, gp102_ltc_new }, 2352 .mc = { 0x00000001, gp100_mc_new }, 2353 .mmu = { 0x00000001, tu102_mmu_new }, 2354 .pci = { 0x00000001, gp100_pci_new }, 2355 .pmu = { 0x00000001, gp102_pmu_new }, 2356 .privring = { 0x00000001, gm200_privring_new }, 2357 .therm = { 0x00000001, gp100_therm_new }, 2358 .timer = { 0x00000001, gk20a_timer_new }, 2359 .top = { 0x00000001, gk104_top_new }, 2360 .vfn = { 0x00000001, tu102_vfn_new }, 2361 .ce = { 0x0000001f, tu102_ce_new }, 2362 .disp = { 0x00000001, tu102_disp_new }, 2363 .dma = { 0x00000001, gv100_dma_new }, 2364 .fifo = { 0x00000001, tu102_fifo_new }, 2365 .gr = { 0x00000001, tu102_gr_new }, 2366 .nvdec = { 0x00000001, tu102_nvdec_new }, 2367 .nvenc = { 0x00000001, tu102_nvenc_new }, 2368 .sec2 = { 0x00000001, tu102_sec2_new }, 2369 }; 2370 2371 static const struct nvkm_device_chip 2372 nv164_chipset = { 2373 .name = "TU104", 2374 .acr = { 0x00000001, tu102_acr_new }, 2375 .bar = { 0x00000001, tu102_bar_new }, 2376 .bios = { 0x00000001, nvkm_bios_new }, 2377 .bus = { 0x00000001, gf100_bus_new }, 2378 .devinit = { 0x00000001, tu102_devinit_new }, 2379 .fault = { 0x00000001, tu102_fault_new }, 2380 .fb = { 0x00000001, tu102_fb_new }, 2381 .fuse = { 0x00000001, gm107_fuse_new }, 2382 .gpio = { 0x00000001, gk104_gpio_new }, 2383 .gsp = { 0x00000001, tu102_gsp_new }, 2384 .i2c = { 0x00000001, gm200_i2c_new }, 2385 .imem = { 0x00000001, nv50_instmem_new }, 2386 .ltc = { 0x00000001, gp102_ltc_new }, 2387 .mc = { 0x00000001, gp100_mc_new }, 2388 .mmu = { 0x00000001, tu102_mmu_new }, 2389 .pci = { 0x00000001, gp100_pci_new }, 2390 .pmu = { 0x00000001, gp102_pmu_new }, 2391 .privring = { 0x00000001, gm200_privring_new }, 2392 .therm = { 0x00000001, gp100_therm_new }, 2393 .timer = { 0x00000001, gk20a_timer_new }, 2394 .top = { 0x00000001, gk104_top_new }, 2395 .vfn = { 0x00000001, tu102_vfn_new }, 2396 .ce = { 0x0000001f, tu102_ce_new }, 2397 .disp = { 0x00000001, tu102_disp_new }, 2398 .dma = { 0x00000001, gv100_dma_new }, 2399 .fifo = { 0x00000001, tu102_fifo_new }, 2400 .gr = { 0x00000001, tu102_gr_new }, 2401 .nvdec = { 0x00000003, tu102_nvdec_new }, 2402 .nvenc = { 0x00000001, tu102_nvenc_new }, 2403 .sec2 = { 0x00000001, tu102_sec2_new }, 2404 }; 2405 2406 static const struct nvkm_device_chip 2407 nv166_chipset = { 2408 .name = "TU106", 2409 .acr = { 0x00000001, tu102_acr_new }, 2410 .bar = { 0x00000001, tu102_bar_new }, 2411 .bios = { 0x00000001, nvkm_bios_new }, 2412 .bus = { 0x00000001, gf100_bus_new }, 2413 .devinit = { 0x00000001, tu102_devinit_new }, 2414 .fault = { 0x00000001, tu102_fault_new }, 2415 .fb = { 0x00000001, tu102_fb_new }, 2416 .fuse = { 0x00000001, gm107_fuse_new }, 2417 .gpio = { 0x00000001, gk104_gpio_new }, 2418 .gsp = { 0x00000001, tu102_gsp_new }, 2419 .i2c = { 0x00000001, gm200_i2c_new }, 2420 .imem = { 0x00000001, nv50_instmem_new }, 2421 .ltc = { 0x00000001, gp102_ltc_new }, 2422 .mc = { 0x00000001, gp100_mc_new }, 2423 .mmu = { 0x00000001, tu102_mmu_new }, 2424 .pci = { 0x00000001, gp100_pci_new }, 2425 .pmu = { 0x00000001, gp102_pmu_new }, 2426 .privring = { 0x00000001, gm200_privring_new }, 2427 .therm = { 0x00000001, gp100_therm_new }, 2428 .timer = { 0x00000001, gk20a_timer_new }, 2429 .top = { 0x00000001, gk104_top_new }, 2430 .vfn = { 0x00000001, tu102_vfn_new }, 2431 .ce = { 0x0000001f, tu102_ce_new }, 2432 .disp = { 0x00000001, tu102_disp_new }, 2433 .dma = { 0x00000001, gv100_dma_new }, 2434 .fifo = { 0x00000001, tu102_fifo_new }, 2435 .gr = { 0x00000001, tu102_gr_new }, 2436 .nvdec = { 0x00000007, tu102_nvdec_new }, 2437 .nvenc = { 0x00000001, tu102_nvenc_new }, 2438 .sec2 = { 0x00000001, tu102_sec2_new }, 2439 }; 2440 2441 static const struct nvkm_device_chip 2442 nv167_chipset = { 2443 .name = "TU117", 2444 .acr = { 0x00000001, tu102_acr_new }, 2445 .bar = { 0x00000001, tu102_bar_new }, 2446 .bios = { 0x00000001, nvkm_bios_new }, 2447 .bus = { 0x00000001, gf100_bus_new }, 2448 .devinit = { 0x00000001, tu102_devinit_new }, 2449 .fault = { 0x00000001, tu102_fault_new }, 2450 .fb = { 0x00000001, tu102_fb_new }, 2451 .fuse = { 0x00000001, gm107_fuse_new }, 2452 .gpio = { 0x00000001, gk104_gpio_new }, 2453 .gsp = { 0x00000001, tu116_gsp_new }, 2454 .i2c = { 0x00000001, gm200_i2c_new }, 2455 .imem = { 0x00000001, nv50_instmem_new }, 2456 .ltc = { 0x00000001, gp102_ltc_new }, 2457 .mc = { 0x00000001, gp100_mc_new }, 2458 .mmu = { 0x00000001, tu102_mmu_new }, 2459 .pci = { 0x00000001, gp100_pci_new }, 2460 .pmu = { 0x00000001, gp102_pmu_new }, 2461 .privring = { 0x00000001, gm200_privring_new }, 2462 .therm = { 0x00000001, gp100_therm_new }, 2463 .timer = { 0x00000001, gk20a_timer_new }, 2464 .top = { 0x00000001, gk104_top_new }, 2465 .vfn = { 0x00000001, tu102_vfn_new }, 2466 .ce = { 0x0000001f, tu102_ce_new }, 2467 .disp = { 0x00000001, tu102_disp_new }, 2468 .dma = { 0x00000001, gv100_dma_new }, 2469 .fifo = { 0x00000001, tu102_fifo_new }, 2470 .gr = { 0x00000001, tu102_gr_new }, 2471 .nvdec = { 0x00000001, tu102_nvdec_new }, 2472 .nvenc = { 0x00000001, tu102_nvenc_new }, 2473 .sec2 = { 0x00000001, tu102_sec2_new }, 2474 }; 2475 2476 static const struct nvkm_device_chip 2477 nv168_chipset = { 2478 .name = "TU116", 2479 .acr = { 0x00000001, tu102_acr_new }, 2480 .bar = { 0x00000001, tu102_bar_new }, 2481 .bios = { 0x00000001, nvkm_bios_new }, 2482 .bus = { 0x00000001, gf100_bus_new }, 2483 .devinit = { 0x00000001, tu102_devinit_new }, 2484 .fault = { 0x00000001, tu102_fault_new }, 2485 .fb = { 0x00000001, tu102_fb_new }, 2486 .fuse = { 0x00000001, gm107_fuse_new }, 2487 .gpio = { 0x00000001, gk104_gpio_new }, 2488 .gsp = { 0x00000001, tu116_gsp_new }, 2489 .i2c = { 0x00000001, gm200_i2c_new }, 2490 .imem = { 0x00000001, nv50_instmem_new }, 2491 .ltc = { 0x00000001, gp102_ltc_new }, 2492 .mc = { 0x00000001, gp100_mc_new }, 2493 .mmu = { 0x00000001, tu102_mmu_new }, 2494 .pci = { 0x00000001, gp100_pci_new }, 2495 .pmu = { 0x00000001, gp102_pmu_new }, 2496 .privring = { 0x00000001, gm200_privring_new }, 2497 .therm = { 0x00000001, gp100_therm_new }, 2498 .timer = { 0x00000001, gk20a_timer_new }, 2499 .top = { 0x00000001, gk104_top_new }, 2500 .vfn = { 0x00000001, tu102_vfn_new }, 2501 .ce = { 0x0000001f, tu102_ce_new }, 2502 .disp = { 0x00000001, tu102_disp_new }, 2503 .dma = { 0x00000001, gv100_dma_new }, 2504 .fifo = { 0x00000001, tu102_fifo_new }, 2505 .gr = { 0x00000001, tu102_gr_new }, 2506 .nvdec = { 0x00000001, tu102_nvdec_new }, 2507 .nvenc = { 0x00000001, tu102_nvenc_new }, 2508 .sec2 = { 0x00000001, tu102_sec2_new }, 2509 }; 2510 2511 static const struct nvkm_device_chip 2512 nv170_chipset = { 2513 .name = "GA100", 2514 .bar = { 0x00000001, tu102_bar_new }, 2515 .bios = { 0x00000001, nvkm_bios_new }, 2516 .devinit = { 0x00000001, ga100_devinit_new }, 2517 .fault = { 0x00000001, tu102_fault_new }, 2518 .fb = { 0x00000001, ga100_fb_new }, 2519 .gpio = { 0x00000001, gk104_gpio_new }, 2520 .gsp = { 0x00000001, ga100_gsp_new }, 2521 .i2c = { 0x00000001, gm200_i2c_new }, 2522 .imem = { 0x00000001, nv50_instmem_new }, 2523 .mc = { 0x00000001, ga100_mc_new }, 2524 .mmu = { 0x00000001, tu102_mmu_new }, 2525 .pci = { 0x00000001, gp100_pci_new }, 2526 .privring = { 0x00000001, gm200_privring_new }, 2527 .timer = { 0x00000001, gk20a_timer_new }, 2528 .top = { 0x00000001, ga100_top_new }, 2529 .vfn = { 0x00000001, ga100_vfn_new }, 2530 .ce = { 0x000003ff, ga100_ce_new }, 2531 .fifo = { 0x00000001, ga100_fifo_new }, 2532 }; 2533 2534 static const struct nvkm_device_chip 2535 nv172_chipset = { 2536 .name = "GA102", 2537 .acr = { 0x00000001, ga102_acr_new }, 2538 .bar = { 0x00000001, tu102_bar_new }, 2539 .bios = { 0x00000001, nvkm_bios_new }, 2540 .devinit = { 0x00000001, ga100_devinit_new }, 2541 .fault = { 0x00000001, tu102_fault_new }, 2542 .fb = { 0x00000001, ga102_fb_new }, 2543 .gpio = { 0x00000001, ga102_gpio_new }, 2544 .gsp = { 0x00000001, ga102_gsp_new }, 2545 .i2c = { 0x00000001, gm200_i2c_new }, 2546 .imem = { 0x00000001, nv50_instmem_new }, 2547 .ltc = { 0x00000001, ga102_ltc_new }, 2548 .mc = { 0x00000001, ga100_mc_new }, 2549 .mmu = { 0x00000001, tu102_mmu_new }, 2550 .pci = { 0x00000001, gp100_pci_new }, 2551 .privring = { 0x00000001, gm200_privring_new }, 2552 .timer = { 0x00000001, gk20a_timer_new }, 2553 .top = { 0x00000001, ga100_top_new }, 2554 .vfn = { 0x00000001, ga100_vfn_new }, 2555 .ce = { 0x0000001f, ga102_ce_new }, 2556 .disp = { 0x00000001, ga102_disp_new }, 2557 .dma = { 0x00000001, gv100_dma_new }, 2558 .fifo = { 0x00000001, ga102_fifo_new }, 2559 .gr = { 0x00000001, ga102_gr_new }, 2560 .nvdec = { 0x00000003, ga102_nvdec_new }, 2561 .sec2 = { 0x00000001, ga102_sec2_new }, 2562 }; 2563 2564 static const struct nvkm_device_chip 2565 nv173_chipset = { 2566 .name = "GA103", 2567 .acr = { 0x00000001, ga102_acr_new }, 2568 .bar = { 0x00000001, tu102_bar_new }, 2569 .bios = { 0x00000001, nvkm_bios_new }, 2570 .devinit = { 0x00000001, ga100_devinit_new }, 2571 .fault = { 0x00000001, tu102_fault_new }, 2572 .fb = { 0x00000001, ga102_fb_new }, 2573 .gpio = { 0x00000001, ga102_gpio_new }, 2574 .gsp = { 0x00000001, ga102_gsp_new }, 2575 .i2c = { 0x00000001, gm200_i2c_new }, 2576 .imem = { 0x00000001, nv50_instmem_new }, 2577 .ltc = { 0x00000001, ga102_ltc_new }, 2578 .mc = { 0x00000001, ga100_mc_new }, 2579 .mmu = { 0x00000001, tu102_mmu_new }, 2580 .pci = { 0x00000001, gp100_pci_new }, 2581 .privring = { 0x00000001, gm200_privring_new }, 2582 .timer = { 0x00000001, gk20a_timer_new }, 2583 .top = { 0x00000001, ga100_top_new }, 2584 .vfn = { 0x00000001, ga100_vfn_new }, 2585 .ce = { 0x0000001f, ga102_ce_new }, 2586 .disp = { 0x00000001, ga102_disp_new }, 2587 .dma = { 0x00000001, gv100_dma_new }, 2588 .fifo = { 0x00000001, ga102_fifo_new }, 2589 .gr = { 0x00000001, ga102_gr_new }, 2590 .nvdec = { 0x00000003, ga102_nvdec_new }, 2591 .sec2 = { 0x00000001, ga102_sec2_new }, 2592 }; 2593 2594 static const struct nvkm_device_chip 2595 nv174_chipset = { 2596 .name = "GA104", 2597 .acr = { 0x00000001, ga102_acr_new }, 2598 .bar = { 0x00000001, tu102_bar_new }, 2599 .bios = { 0x00000001, nvkm_bios_new }, 2600 .devinit = { 0x00000001, ga100_devinit_new }, 2601 .fault = { 0x00000001, tu102_fault_new }, 2602 .fb = { 0x00000001, ga102_fb_new }, 2603 .gpio = { 0x00000001, ga102_gpio_new }, 2604 .gsp = { 0x00000001, ga102_gsp_new }, 2605 .i2c = { 0x00000001, gm200_i2c_new }, 2606 .imem = { 0x00000001, nv50_instmem_new }, 2607 .ltc = { 0x00000001, ga102_ltc_new }, 2608 .mc = { 0x00000001, ga100_mc_new }, 2609 .mmu = { 0x00000001, tu102_mmu_new }, 2610 .pci = { 0x00000001, gp100_pci_new }, 2611 .privring = { 0x00000001, gm200_privring_new }, 2612 .timer = { 0x00000001, gk20a_timer_new }, 2613 .top = { 0x00000001, ga100_top_new }, 2614 .vfn = { 0x00000001, ga100_vfn_new }, 2615 .ce = { 0x0000001f, ga102_ce_new }, 2616 .disp = { 0x00000001, ga102_disp_new }, 2617 .dma = { 0x00000001, gv100_dma_new }, 2618 .fifo = { 0x00000001, ga102_fifo_new }, 2619 .gr = { 0x00000001, ga102_gr_new }, 2620 .nvdec = { 0x00000003, ga102_nvdec_new }, 2621 .sec2 = { 0x00000001, ga102_sec2_new }, 2622 }; 2623 2624 static const struct nvkm_device_chip 2625 nv176_chipset = { 2626 .name = "GA106", 2627 .acr = { 0x00000001, ga102_acr_new }, 2628 .bar = { 0x00000001, tu102_bar_new }, 2629 .bios = { 0x00000001, nvkm_bios_new }, 2630 .devinit = { 0x00000001, ga100_devinit_new }, 2631 .fault = { 0x00000001, tu102_fault_new }, 2632 .fb = { 0x00000001, ga102_fb_new }, 2633 .gpio = { 0x00000001, ga102_gpio_new }, 2634 .gsp = { 0x00000001, ga102_gsp_new }, 2635 .i2c = { 0x00000001, gm200_i2c_new }, 2636 .imem = { 0x00000001, nv50_instmem_new }, 2637 .ltc = { 0x00000001, ga102_ltc_new }, 2638 .mc = { 0x00000001, ga100_mc_new }, 2639 .mmu = { 0x00000001, tu102_mmu_new }, 2640 .pci = { 0x00000001, gp100_pci_new }, 2641 .privring = { 0x00000001, gm200_privring_new }, 2642 .timer = { 0x00000001, gk20a_timer_new }, 2643 .top = { 0x00000001, ga100_top_new }, 2644 .vfn = { 0x00000001, ga100_vfn_new }, 2645 .ce = { 0x0000001f, ga102_ce_new }, 2646 .disp = { 0x00000001, ga102_disp_new }, 2647 .dma = { 0x00000001, gv100_dma_new }, 2648 .fifo = { 0x00000001, ga102_fifo_new }, 2649 .gr = { 0x00000001, ga102_gr_new }, 2650 .nvdec = { 0x00000003, ga102_nvdec_new }, 2651 .sec2 = { 0x00000001, ga102_sec2_new }, 2652 }; 2653 2654 static const struct nvkm_device_chip 2655 nv177_chipset = { 2656 .name = "GA107", 2657 .acr = { 0x00000001, ga102_acr_new }, 2658 .bar = { 0x00000001, tu102_bar_new }, 2659 .bios = { 0x00000001, nvkm_bios_new }, 2660 .devinit = { 0x00000001, ga100_devinit_new }, 2661 .fault = { 0x00000001, tu102_fault_new }, 2662 .fb = { 0x00000001, ga102_fb_new }, 2663 .gpio = { 0x00000001, ga102_gpio_new }, 2664 .gsp = { 0x00000001, ga102_gsp_new }, 2665 .i2c = { 0x00000001, gm200_i2c_new }, 2666 .imem = { 0x00000001, nv50_instmem_new }, 2667 .ltc = { 0x00000001, ga102_ltc_new }, 2668 .mc = { 0x00000001, ga100_mc_new }, 2669 .mmu = { 0x00000001, tu102_mmu_new }, 2670 .pci = { 0x00000001, gp100_pci_new }, 2671 .privring = { 0x00000001, gm200_privring_new }, 2672 .timer = { 0x00000001, gk20a_timer_new }, 2673 .top = { 0x00000001, ga100_top_new }, 2674 .vfn = { 0x00000001, ga100_vfn_new }, 2675 .ce = { 0x0000001f, ga102_ce_new }, 2676 .disp = { 0x00000001, ga102_disp_new }, 2677 .dma = { 0x00000001, gv100_dma_new }, 2678 .fifo = { 0x00000001, ga102_fifo_new }, 2679 .gr = { 0x00000001, ga102_gr_new }, 2680 .nvdec = { 0x00000003, ga102_nvdec_new }, 2681 .sec2 = { 0x00000001, ga102_sec2_new }, 2682 }; 2683 2684 static const struct nvkm_device_chip 2685 nv180_chipset = { 2686 .name = "GH100", 2687 .bar = { 0x00000001, tu102_bar_new }, 2688 .fault = { 0x00000001, tu102_fault_new }, 2689 .fb = { 0x00000001, gh100_fb_new }, 2690 .fsp = { 0x00000001, gh100_fsp_new }, 2691 .gsp = { 0x00000001, gh100_gsp_new }, 2692 .imem = { 0x00000001, gh100_instmem_new }, 2693 .mmu = { 0x00000001, gh100_mmu_new }, 2694 .pci = { 0x00000001, gh100_pci_new }, 2695 .timer = { 0x00000001, gk20a_timer_new }, 2696 .vfn = { 0x00000001, ga100_vfn_new }, 2697 .fifo = { 0x00000001, ga102_fifo_new }, 2698 }; 2699 2700 static const struct nvkm_device_chip 2701 nv192_chipset = { 2702 .name = "AD102", 2703 .bar = { 0x00000001, tu102_bar_new }, 2704 .bios = { 0x00000001, nvkm_bios_new }, 2705 .devinit = { 0x00000001, ga100_devinit_new }, 2706 .fault = { 0x00000001, tu102_fault_new }, 2707 .fb = { 0x00000001, ga102_fb_new }, 2708 .gsp = { 0x00000001, ad102_gsp_new }, 2709 .imem = { 0x00000001, nv50_instmem_new }, 2710 .mmu = { 0x00000001, tu102_mmu_new }, 2711 .pci = { 0x00000001, gp100_pci_new }, 2712 .timer = { 0x00000001, gk20a_timer_new }, 2713 .vfn = { 0x00000001, ga100_vfn_new }, 2714 .ce = { 0x0000001f, ga102_ce_new }, 2715 .disp = { 0x00000001, ga102_disp_new }, 2716 .dma = { 0x00000001, gv100_dma_new }, 2717 .fifo = { 0x00000001, ga102_fifo_new }, 2718 .sec2 = { 0x00000001, ga102_sec2_new }, 2719 }; 2720 2721 static const struct nvkm_device_chip 2722 nv193_chipset = { 2723 .name = "AD103", 2724 .bar = { 0x00000001, tu102_bar_new }, 2725 .bios = { 0x00000001, nvkm_bios_new }, 2726 .devinit = { 0x00000001, ga100_devinit_new }, 2727 .fault = { 0x00000001, tu102_fault_new }, 2728 .fb = { 0x00000001, ga102_fb_new }, 2729 .gsp = { 0x00000001, ad102_gsp_new }, 2730 .imem = { 0x00000001, nv50_instmem_new }, 2731 .mmu = { 0x00000001, tu102_mmu_new }, 2732 .pci = { 0x00000001, gp100_pci_new }, 2733 .timer = { 0x00000001, gk20a_timer_new }, 2734 .vfn = { 0x00000001, ga100_vfn_new }, 2735 .ce = { 0x0000001f, ga102_ce_new }, 2736 .disp = { 0x00000001, ga102_disp_new }, 2737 .dma = { 0x00000001, gv100_dma_new }, 2738 .fifo = { 0x00000001, ga102_fifo_new }, 2739 .sec2 = { 0x00000001, ga102_sec2_new }, 2740 }; 2741 2742 static const struct nvkm_device_chip 2743 nv194_chipset = { 2744 .name = "AD104", 2745 .bar = { 0x00000001, tu102_bar_new }, 2746 .bios = { 0x00000001, nvkm_bios_new }, 2747 .devinit = { 0x00000001, ga100_devinit_new }, 2748 .fault = { 0x00000001, tu102_fault_new }, 2749 .fb = { 0x00000001, ga102_fb_new }, 2750 .gsp = { 0x00000001, ad102_gsp_new }, 2751 .imem = { 0x00000001, nv50_instmem_new }, 2752 .mmu = { 0x00000001, tu102_mmu_new }, 2753 .pci = { 0x00000001, gp100_pci_new }, 2754 .timer = { 0x00000001, gk20a_timer_new }, 2755 .vfn = { 0x00000001, ga100_vfn_new }, 2756 .ce = { 0x0000001f, ga102_ce_new }, 2757 .disp = { 0x00000001, ga102_disp_new }, 2758 .dma = { 0x00000001, gv100_dma_new }, 2759 .fifo = { 0x00000001, ga102_fifo_new }, 2760 .sec2 = { 0x00000001, ga102_sec2_new }, 2761 }; 2762 2763 static const struct nvkm_device_chip 2764 nv196_chipset = { 2765 .name = "AD106", 2766 .bar = { 0x00000001, tu102_bar_new }, 2767 .bios = { 0x00000001, nvkm_bios_new }, 2768 .devinit = { 0x00000001, ga100_devinit_new }, 2769 .fault = { 0x00000001, tu102_fault_new }, 2770 .fb = { 0x00000001, ga102_fb_new }, 2771 .gsp = { 0x00000001, ad102_gsp_new }, 2772 .imem = { 0x00000001, nv50_instmem_new }, 2773 .mmu = { 0x00000001, tu102_mmu_new }, 2774 .pci = { 0x00000001, gp100_pci_new }, 2775 .timer = { 0x00000001, gk20a_timer_new }, 2776 .vfn = { 0x00000001, ga100_vfn_new }, 2777 .ce = { 0x0000001f, ga102_ce_new }, 2778 .disp = { 0x00000001, ga102_disp_new }, 2779 .dma = { 0x00000001, gv100_dma_new }, 2780 .fifo = { 0x00000001, ga102_fifo_new }, 2781 .sec2 = { 0x00000001, ga102_sec2_new }, 2782 }; 2783 2784 static const struct nvkm_device_chip 2785 nv197_chipset = { 2786 .name = "AD107", 2787 .bar = { 0x00000001, tu102_bar_new }, 2788 .bios = { 0x00000001, nvkm_bios_new }, 2789 .devinit = { 0x00000001, ga100_devinit_new }, 2790 .fault = { 0x00000001, tu102_fault_new }, 2791 .fb = { 0x00000001, ga102_fb_new }, 2792 .gsp = { 0x00000001, ad102_gsp_new }, 2793 .imem = { 0x00000001, nv50_instmem_new }, 2794 .mmu = { 0x00000001, tu102_mmu_new }, 2795 .pci = { 0x00000001, gp100_pci_new }, 2796 .timer = { 0x00000001, gk20a_timer_new }, 2797 .vfn = { 0x00000001, ga100_vfn_new }, 2798 .ce = { 0x0000001f, ga102_ce_new }, 2799 .disp = { 0x00000001, ga102_disp_new }, 2800 .dma = { 0x00000001, gv100_dma_new }, 2801 .fifo = { 0x00000001, ga102_fifo_new }, 2802 .sec2 = { 0x00000001, ga102_sec2_new }, 2803 }; 2804 2805 static const struct nvkm_device_chip 2806 nv1a0_chipset = { 2807 .name = "GB100", 2808 .bar = { 0x00000001, tu102_bar_new }, 2809 .fb = { 0x00000001, gb100_fb_new }, 2810 .fsp = { 0x00000001, gb100_fsp_new }, 2811 .gsp = { 0x00000001, gb100_gsp_new }, 2812 .imem = { 0x00000001, gh100_instmem_new }, 2813 .mmu = { 0x00000001, gh100_mmu_new }, 2814 .pci = { 0x00000001, gh100_pci_new }, 2815 .timer = { 0x00000001, gk20a_timer_new }, 2816 .vfn = { 0x00000001, ga100_vfn_new }, 2817 .fifo = { 0x00000001, ga102_fifo_new }, 2818 }; 2819 2820 static const struct nvkm_device_chip 2821 nv1a2_chipset = { 2822 .name = "GB102", 2823 .bar = { 0x00000001, tu102_bar_new }, 2824 .fb = { 0x00000001, gb100_fb_new }, 2825 .fsp = { 0x00000001, gb100_fsp_new }, 2826 .gsp = { 0x00000001, gb100_gsp_new }, 2827 .imem = { 0x00000001, gh100_instmem_new }, 2828 .mmu = { 0x00000001, gh100_mmu_new }, 2829 .pci = { 0x00000001, gh100_pci_new }, 2830 .timer = { 0x00000001, gk20a_timer_new }, 2831 .vfn = { 0x00000001, ga100_vfn_new }, 2832 .fifo = { 0x00000001, ga102_fifo_new }, 2833 }; 2834 2835 static const struct nvkm_device_chip 2836 nv1b2_chipset = { 2837 .name = "GB202", 2838 .bar = { 0x00000001, tu102_bar_new }, 2839 .fb = { 0x00000001, gb202_fb_new }, 2840 .fsp = { 0x00000001, gb202_fsp_new }, 2841 .gsp = { 0x00000001, gb202_gsp_new }, 2842 .imem = { 0x00000001, gh100_instmem_new }, 2843 .mmu = { 0x00000001, gh100_mmu_new }, 2844 .pci = { 0x00000001, gh100_pci_new }, 2845 .timer = { 0x00000001, gk20a_timer_new }, 2846 .vfn = { 0x00000001, ga100_vfn_new }, 2847 .disp = { 0x00000001, ga102_disp_new }, 2848 .fifo = { 0x00000001, ga102_fifo_new }, 2849 }; 2850 2851 static const struct nvkm_device_chip 2852 nv1b3_chipset = { 2853 .name = "GB203", 2854 .bar = { 0x00000001, tu102_bar_new }, 2855 .fb = { 0x00000001, gb202_fb_new }, 2856 .fsp = { 0x00000001, gb202_fsp_new }, 2857 .gsp = { 0x00000001, gb202_gsp_new }, 2858 .imem = { 0x00000001, gh100_instmem_new }, 2859 .mmu = { 0x00000001, gh100_mmu_new }, 2860 .pci = { 0x00000001, gh100_pci_new }, 2861 .timer = { 0x00000001, gk20a_timer_new }, 2862 .vfn = { 0x00000001, ga100_vfn_new }, 2863 .disp = { 0x00000001, ga102_disp_new }, 2864 .fifo = { 0x00000001, ga102_fifo_new }, 2865 }; 2866 2867 static const struct nvkm_device_chip 2868 nv1b5_chipset = { 2869 .name = "GB205", 2870 .bar = { 0x00000001, tu102_bar_new }, 2871 .fb = { 0x00000001, gb202_fb_new }, 2872 .fsp = { 0x00000001, gb202_fsp_new }, 2873 .gsp = { 0x00000001, gb202_gsp_new }, 2874 .imem = { 0x00000001, gh100_instmem_new }, 2875 .mmu = { 0x00000001, gh100_mmu_new }, 2876 .pci = { 0x00000001, gh100_pci_new }, 2877 .timer = { 0x00000001, gk20a_timer_new }, 2878 .vfn = { 0x00000001, ga100_vfn_new }, 2879 .disp = { 0x00000001, ga102_disp_new }, 2880 .fifo = { 0x00000001, ga102_fifo_new }, 2881 }; 2882 2883 static const struct nvkm_device_chip 2884 nv1b6_chipset = { 2885 .name = "GB206", 2886 .bar = { 0x00000001, tu102_bar_new }, 2887 .fb = { 0x00000001, gb202_fb_new }, 2888 .fsp = { 0x00000001, gb202_fsp_new }, 2889 .gsp = { 0x00000001, gb202_gsp_new }, 2890 .imem = { 0x00000001, gh100_instmem_new }, 2891 .mmu = { 0x00000001, gh100_mmu_new }, 2892 .pci = { 0x00000001, gh100_pci_new }, 2893 .timer = { 0x00000001, gk20a_timer_new }, 2894 .vfn = { 0x00000001, ga100_vfn_new }, 2895 .disp = { 0x00000001, ga102_disp_new }, 2896 .fifo = { 0x00000001, ga102_fifo_new }, 2897 }; 2898 2899 static const struct nvkm_device_chip 2900 nv1b7_chipset = { 2901 .name = "GB207", 2902 .bar = { 0x00000001, tu102_bar_new }, 2903 .fb = { 0x00000001, gb202_fb_new }, 2904 .fsp = { 0x00000001, gb202_fsp_new }, 2905 .gsp = { 0x00000001, gb202_gsp_new }, 2906 .imem = { 0x00000001, gh100_instmem_new }, 2907 .mmu = { 0x00000001, gh100_mmu_new }, 2908 .pci = { 0x00000001, gh100_pci_new }, 2909 .timer = { 0x00000001, gk20a_timer_new }, 2910 .vfn = { 0x00000001, ga100_vfn_new }, 2911 .disp = { 0x00000001, ga102_disp_new }, 2912 .fifo = { 0x00000001, ga102_fifo_new }, 2913 }; 2914 2915 struct nvkm_subdev * 2916 nvkm_device_subdev(struct nvkm_device *device, int type, int inst) 2917 { 2918 struct nvkm_subdev *subdev; 2919 2920 list_for_each_entry(subdev, &device->subdev, head) { 2921 if (subdev->type == type && subdev->inst == inst) 2922 return subdev; 2923 } 2924 2925 return NULL; 2926 } 2927 2928 struct nvkm_engine * 2929 nvkm_device_engine(struct nvkm_device *device, int type, int inst) 2930 { 2931 struct nvkm_subdev *subdev = nvkm_device_subdev(device, type, inst); 2932 if (subdev && subdev->func == &nvkm_engine) 2933 return container_of(subdev, struct nvkm_engine, subdev); 2934 return NULL; 2935 } 2936 2937 int 2938 nvkm_device_fini(struct nvkm_device *device, bool suspend) 2939 { 2940 const char *action = suspend ? "suspend" : "fini"; 2941 struct nvkm_subdev *subdev; 2942 int ret; 2943 s64 time; 2944 2945 nvdev_trace(device, "%s running...\n", action); 2946 time = ktime_to_us(ktime_get()); 2947 2948 nvkm_acpi_fini(device); 2949 2950 list_for_each_entry_reverse(subdev, &device->subdev, head) { 2951 ret = nvkm_subdev_fini(subdev, suspend); 2952 if (ret && suspend) 2953 goto fail; 2954 } 2955 2956 nvkm_therm_clkgate_fini(device->therm, suspend); 2957 2958 if (device->func->fini) 2959 device->func->fini(device, suspend); 2960 2961 nvkm_intr_unarm(device); 2962 2963 time = ktime_to_us(ktime_get()) - time; 2964 nvdev_trace(device, "%s completed in %lldus...\n", action, time); 2965 return 0; 2966 2967 fail: 2968 list_for_each_entry_from(subdev, &device->subdev, head) { 2969 int rret = nvkm_subdev_init(subdev); 2970 if (rret) 2971 nvkm_fatal(subdev, "failed restart, %d\n", ret); 2972 } 2973 2974 nvdev_trace(device, "%s failed with %d\n", action, ret); 2975 return ret; 2976 } 2977 2978 static int 2979 nvkm_device_preinit(struct nvkm_device *device) 2980 { 2981 struct nvkm_subdev *subdev; 2982 int ret; 2983 s64 time; 2984 2985 nvdev_trace(device, "preinit running...\n"); 2986 time = ktime_to_us(ktime_get()); 2987 2988 nvkm_intr_unarm(device); 2989 2990 if (device->func->preinit) { 2991 ret = device->func->preinit(device); 2992 if (ret) 2993 goto fail; 2994 } 2995 2996 list_for_each_entry(subdev, &device->subdev, head) { 2997 ret = nvkm_subdev_preinit(subdev); 2998 if (ret) 2999 goto fail; 3000 } 3001 3002 ret = nvkm_devinit_post(device->devinit); 3003 if (ret) 3004 goto fail; 3005 3006 ret = nvkm_top_parse(device); 3007 if (ret) 3008 goto fail; 3009 3010 ret = nvkm_fb_mem_unlock(device->fb); 3011 if (ret) 3012 goto fail; 3013 3014 time = ktime_to_us(ktime_get()) - time; 3015 nvdev_trace(device, "preinit completed in %lldus\n", time); 3016 return 0; 3017 3018 fail: 3019 nvdev_error(device, "preinit failed with %d\n", ret); 3020 return ret; 3021 } 3022 3023 int 3024 nvkm_device_init(struct nvkm_device *device) 3025 { 3026 struct nvkm_subdev *subdev; 3027 int ret; 3028 s64 time; 3029 3030 ret = nvkm_device_preinit(device); 3031 if (ret) 3032 return ret; 3033 3034 nvkm_device_fini(device, false); 3035 3036 nvdev_trace(device, "init running...\n"); 3037 time = ktime_to_us(ktime_get()); 3038 3039 nvkm_intr_rearm(device); 3040 3041 if (device->func->init) { 3042 ret = device->func->init(device); 3043 if (ret) 3044 goto fail; 3045 } 3046 3047 list_for_each_entry(subdev, &device->subdev, head) { 3048 ret = nvkm_subdev_init(subdev); 3049 if (ret) 3050 goto fail_subdev; 3051 } 3052 3053 nvkm_acpi_init(device); 3054 nvkm_therm_clkgate_enable(device->therm); 3055 3056 time = ktime_to_us(ktime_get()) - time; 3057 nvdev_trace(device, "init completed in %lldus\n", time); 3058 return 0; 3059 3060 fail_subdev: 3061 list_for_each_entry_from(subdev, &device->subdev, head) 3062 nvkm_subdev_fini(subdev, false); 3063 fail: 3064 nvkm_device_fini(device, false); 3065 3066 nvdev_error(device, "init failed with %d\n", ret); 3067 return ret; 3068 } 3069 3070 void 3071 nvkm_device_del(struct nvkm_device **pdevice) 3072 { 3073 struct nvkm_device *device = *pdevice; 3074 struct nvkm_subdev *subdev, *subtmp; 3075 if (device) { 3076 mutex_lock(&nv_devices_mutex); 3077 3078 nvkm_intr_dtor(device); 3079 3080 list_for_each_entry_safe_reverse(subdev, subtmp, &device->subdev, head) 3081 nvkm_subdev_del(&subdev); 3082 3083 if (device->pri) 3084 iounmap(device->pri); 3085 list_del(&device->head); 3086 3087 if (device->func->dtor) 3088 *pdevice = device->func->dtor(device); 3089 mutex_unlock(&nv_devices_mutex); 3090 3091 kfree(*pdevice); 3092 *pdevice = NULL; 3093 } 3094 } 3095 3096 /* returns true if the GPU is in the CPU native byte order */ 3097 static inline bool 3098 nvkm_device_endianness(struct nvkm_device *device) 3099 { 3100 #ifdef __BIG_ENDIAN 3101 const bool big_endian = true; 3102 #else 3103 const bool big_endian = false; 3104 #endif 3105 3106 /* Read NV_PMC_BOOT_1, and assume non-functional endian switch if it 3107 * doesn't contain the expected values. 3108 */ 3109 u32 pmc_boot_1 = nvkm_rd32(device, 0x000004); 3110 if (pmc_boot_1 && pmc_boot_1 != 0x01000001) 3111 return !big_endian; /* Assume GPU is LE in this case. */ 3112 3113 /* 0 means LE and 0x01000001 means BE GPU. Condition is true when 3114 * GPU/CPU endianness don't match. 3115 */ 3116 if (big_endian == !pmc_boot_1) { 3117 nvkm_wr32(device, 0x000004, 0x01000001); 3118 nvkm_rd32(device, 0x000000); 3119 if (nvkm_rd32(device, 0x000004) != (big_endian ? 0x01000001 : 0x00000000)) 3120 return !big_endian; /* Assume GPU is LE on any unexpected read-back. */ 3121 } 3122 3123 /* CPU/GPU endianness should (hopefully) match. */ 3124 return true; 3125 } 3126 3127 int 3128 nvkm_device_ctor(const struct nvkm_device_func *func, 3129 const struct nvkm_device_quirk *quirk, 3130 struct device *dev, enum nvkm_device_type type, u64 handle, 3131 const char *name, const char *cfg, const char *dbg, 3132 struct nvkm_device *device) 3133 { 3134 struct nvkm_subdev *subdev; 3135 u64 mmio_base, mmio_size; 3136 u32 boot0, boot1, strap; 3137 int ret = -EEXIST, j; 3138 unsigned chipset; 3139 3140 mutex_lock(&nv_devices_mutex); 3141 if (nvkm_device_find_locked(handle)) 3142 goto done; 3143 3144 device->func = func; 3145 device->quirk = quirk; 3146 device->dev = dev; 3147 device->type = type; 3148 device->handle = handle; 3149 device->cfgopt = cfg; 3150 device->dbgopt = dbg; 3151 device->name = name; 3152 list_add_tail(&device->head, &nv_devices); 3153 device->debug = nvkm_dbgopt(device->dbgopt, "device"); 3154 INIT_LIST_HEAD(&device->subdev); 3155 3156 mmio_base = device->func->resource_addr(device, NVKM_BAR0_PRI); 3157 mmio_size = device->func->resource_size(device, NVKM_BAR0_PRI); 3158 3159 device->pri = ioremap(mmio_base, mmio_size); 3160 if (device->pri == NULL) { 3161 nvdev_error(device, "unable to map PRI\n"); 3162 ret = -ENOMEM; 3163 goto done; 3164 } 3165 3166 /* identify the chipset, and determine classes of subdev/engines */ 3167 3168 /* switch mmio to cpu's native endianness */ 3169 if (!nvkm_device_endianness(device)) { 3170 nvdev_error(device, 3171 "Couldn't switch GPU to CPUs endianness\n"); 3172 ret = -ENOSYS; 3173 goto done; 3174 } 3175 3176 boot0 = nvkm_rd32(device, 0x000000); 3177 3178 /* chipset can be overridden for devel/testing purposes */ 3179 chipset = nvkm_longopt(device->cfgopt, "NvChipset", 0); 3180 if (chipset) { 3181 u32 override_boot0; 3182 3183 if (chipset >= 0x10) { 3184 override_boot0 = ((chipset & 0x1ff) << 20); 3185 override_boot0 |= 0x000000a1; 3186 } else { 3187 if (chipset != 0x04) 3188 override_boot0 = 0x20104000; 3189 else 3190 override_boot0 = 0x20004000; 3191 } 3192 3193 nvdev_warn(device, "CHIPSET OVERRIDE: %08x -> %08x\n", 3194 boot0, override_boot0); 3195 boot0 = override_boot0; 3196 } 3197 3198 /* determine chipset and derive architecture from it */ 3199 if ((boot0 & 0x1f000000) > 0) { 3200 device->chipset = (boot0 & 0x1ff00000) >> 20; 3201 device->chiprev = (boot0 & 0x000000ff); 3202 switch (device->chipset & 0x1f0) { 3203 case 0x010: { 3204 if (0x461 & (1 << (device->chipset & 0xf))) 3205 device->card_type = NV_10; 3206 else 3207 device->card_type = NV_11; 3208 device->chiprev = 0x00; 3209 break; 3210 } 3211 case 0x020: device->card_type = NV_20; break; 3212 case 0x030: device->card_type = NV_30; break; 3213 case 0x040: 3214 case 0x060: device->card_type = NV_40; break; 3215 case 0x050: 3216 case 0x080: 3217 case 0x090: 3218 case 0x0a0: device->card_type = NV_50; break; 3219 case 0x0c0: 3220 case 0x0d0: device->card_type = NV_C0; break; 3221 case 0x0e0: 3222 case 0x0f0: 3223 case 0x100: device->card_type = NV_E0; break; 3224 case 0x110: 3225 case 0x120: device->card_type = GM100; break; 3226 case 0x130: device->card_type = GP100; break; 3227 case 0x140: device->card_type = GV100; break; 3228 case 0x160: device->card_type = TU100; break; 3229 case 0x170: device->card_type = GA100; break; 3230 case 0x180: device->card_type = GH100; break; 3231 case 0x190: device->card_type = AD100; break; 3232 case 0x1a0: device->card_type = GB10x; break; 3233 case 0x1b0: device->card_type = GB20x; break; 3234 default: 3235 break; 3236 } 3237 } else 3238 if ((boot0 & 0xff00fff0) == 0x20004000) { 3239 if (boot0 & 0x00f00000) 3240 device->chipset = 0x05; 3241 else 3242 device->chipset = 0x04; 3243 device->card_type = NV_04; 3244 } 3245 3246 switch (device->chipset) { 3247 case 0x004: device->chip = &nv4_chipset; break; 3248 case 0x005: device->chip = &nv5_chipset; break; 3249 case 0x010: device->chip = &nv10_chipset; break; 3250 case 0x011: device->chip = &nv11_chipset; break; 3251 case 0x015: device->chip = &nv15_chipset; break; 3252 case 0x017: device->chip = &nv17_chipset; break; 3253 case 0x018: device->chip = &nv18_chipset; break; 3254 case 0x01a: device->chip = &nv1a_chipset; break; 3255 case 0x01f: device->chip = &nv1f_chipset; break; 3256 case 0x020: device->chip = &nv20_chipset; break; 3257 case 0x025: device->chip = &nv25_chipset; break; 3258 case 0x028: device->chip = &nv28_chipset; break; 3259 case 0x02a: device->chip = &nv2a_chipset; break; 3260 case 0x030: device->chip = &nv30_chipset; break; 3261 case 0x031: device->chip = &nv31_chipset; break; 3262 case 0x034: device->chip = &nv34_chipset; break; 3263 case 0x035: device->chip = &nv35_chipset; break; 3264 case 0x036: device->chip = &nv36_chipset; break; 3265 case 0x040: device->chip = &nv40_chipset; break; 3266 case 0x041: device->chip = &nv41_chipset; break; 3267 case 0x042: device->chip = &nv42_chipset; break; 3268 case 0x043: device->chip = &nv43_chipset; break; 3269 case 0x044: device->chip = &nv44_chipset; break; 3270 case 0x045: device->chip = &nv45_chipset; break; 3271 case 0x046: device->chip = &nv46_chipset; break; 3272 case 0x047: device->chip = &nv47_chipset; break; 3273 case 0x049: device->chip = &nv49_chipset; break; 3274 case 0x04a: device->chip = &nv4a_chipset; break; 3275 case 0x04b: device->chip = &nv4b_chipset; break; 3276 case 0x04c: device->chip = &nv4c_chipset; break; 3277 case 0x04e: device->chip = &nv4e_chipset; break; 3278 case 0x050: device->chip = &nv50_chipset; break; 3279 case 0x063: device->chip = &nv63_chipset; break; 3280 case 0x067: device->chip = &nv67_chipset; break; 3281 case 0x068: device->chip = &nv68_chipset; break; 3282 case 0x084: device->chip = &nv84_chipset; break; 3283 case 0x086: device->chip = &nv86_chipset; break; 3284 case 0x092: device->chip = &nv92_chipset; break; 3285 case 0x094: device->chip = &nv94_chipset; break; 3286 case 0x096: device->chip = &nv96_chipset; break; 3287 case 0x098: device->chip = &nv98_chipset; break; 3288 case 0x0a0: device->chip = &nva0_chipset; break; 3289 case 0x0a3: device->chip = &nva3_chipset; break; 3290 case 0x0a5: device->chip = &nva5_chipset; break; 3291 case 0x0a8: device->chip = &nva8_chipset; break; 3292 case 0x0aa: device->chip = &nvaa_chipset; break; 3293 case 0x0ac: device->chip = &nvac_chipset; break; 3294 case 0x0af: device->chip = &nvaf_chipset; break; 3295 case 0x0c0: device->chip = &nvc0_chipset; break; 3296 case 0x0c1: device->chip = &nvc1_chipset; break; 3297 case 0x0c3: device->chip = &nvc3_chipset; break; 3298 case 0x0c4: device->chip = &nvc4_chipset; break; 3299 case 0x0c8: device->chip = &nvc8_chipset; break; 3300 case 0x0ce: device->chip = &nvce_chipset; break; 3301 case 0x0cf: device->chip = &nvcf_chipset; break; 3302 case 0x0d7: device->chip = &nvd7_chipset; break; 3303 case 0x0d9: device->chip = &nvd9_chipset; break; 3304 case 0x0e4: device->chip = &nve4_chipset; break; 3305 case 0x0e6: device->chip = &nve6_chipset; break; 3306 case 0x0e7: device->chip = &nve7_chipset; break; 3307 case 0x0ea: device->chip = &nvea_chipset; break; 3308 case 0x0f0: device->chip = &nvf0_chipset; break; 3309 case 0x0f1: device->chip = &nvf1_chipset; break; 3310 case 0x106: device->chip = &nv106_chipset; break; 3311 case 0x108: device->chip = &nv108_chipset; break; 3312 case 0x117: device->chip = &nv117_chipset; break; 3313 case 0x118: device->chip = &nv118_chipset; break; 3314 case 0x120: device->chip = &nv120_chipset; break; 3315 case 0x124: device->chip = &nv124_chipset; break; 3316 case 0x126: device->chip = &nv126_chipset; break; 3317 case 0x12b: device->chip = &nv12b_chipset; break; 3318 case 0x130: device->chip = &nv130_chipset; break; 3319 case 0x132: device->chip = &nv132_chipset; break; 3320 case 0x134: device->chip = &nv134_chipset; break; 3321 case 0x136: device->chip = &nv136_chipset; break; 3322 case 0x137: device->chip = &nv137_chipset; break; 3323 case 0x138: device->chip = &nv138_chipset; break; 3324 case 0x13b: device->chip = &nv13b_chipset; break; 3325 case 0x140: device->chip = &nv140_chipset; break; 3326 case 0x162: device->chip = &nv162_chipset; break; 3327 case 0x164: device->chip = &nv164_chipset; break; 3328 case 0x166: device->chip = &nv166_chipset; break; 3329 case 0x167: device->chip = &nv167_chipset; break; 3330 case 0x168: device->chip = &nv168_chipset; break; 3331 case 0x172: device->chip = &nv172_chipset; break; 3332 case 0x173: device->chip = &nv173_chipset; break; 3333 case 0x174: device->chip = &nv174_chipset; break; 3334 case 0x176: device->chip = &nv176_chipset; break; 3335 case 0x177: device->chip = &nv177_chipset; break; 3336 case 0x180: device->chip = &nv180_chipset; break; 3337 case 0x192: device->chip = &nv192_chipset; break; 3338 case 0x193: device->chip = &nv193_chipset; break; 3339 case 0x194: device->chip = &nv194_chipset; break; 3340 case 0x196: device->chip = &nv196_chipset; break; 3341 case 0x197: device->chip = &nv197_chipset; break; 3342 case 0x1a0: device->chip = &nv1a0_chipset; break; 3343 case 0x1a2: device->chip = &nv1a2_chipset; break; 3344 case 0x1b2: device->chip = &nv1b2_chipset; break; 3345 case 0x1b3: device->chip = &nv1b3_chipset; break; 3346 case 0x1b5: device->chip = &nv1b5_chipset; break; 3347 case 0x1b6: device->chip = &nv1b6_chipset; break; 3348 case 0x1b7: device->chip = &nv1b7_chipset; break; 3349 default: 3350 if (nvkm_boolopt(device->cfgopt, "NvEnableUnsupportedChipsets", false)) { 3351 switch (device->chipset) { 3352 case 0x170: device->chip = &nv170_chipset; break; 3353 default: 3354 break; 3355 } 3356 } 3357 3358 if (!device->chip) { 3359 nvdev_error(device, "unknown chipset (%08x)\n", boot0); 3360 ret = -ENODEV; 3361 goto done; 3362 } 3363 break; 3364 } 3365 3366 nvdev_info(device, "NVIDIA %s (%08x)\n", 3367 device->chip->name, boot0); 3368 3369 /* vGPU detection */ 3370 boot1 = nvkm_rd32(device, 0x0000004); 3371 if (device->card_type >= TU100 && (boot1 & 0x00030000)) { 3372 nvdev_info(device, "vGPUs are not supported\n"); 3373 ret = -ENODEV; 3374 goto done; 3375 } 3376 3377 /* read strapping information */ 3378 strap = nvkm_rd32(device, 0x101000); 3379 3380 /* determine frequency of timing crystal */ 3381 if ( device->card_type <= NV_10 || device->chipset < 0x17 || 3382 (device->chipset >= 0x20 && device->chipset < 0x25)) 3383 strap &= 0x00000040; 3384 else 3385 strap &= 0x00400040; 3386 3387 switch (strap) { 3388 case 0x00000000: device->crystal = 13500; break; 3389 case 0x00000040: device->crystal = 14318; break; 3390 case 0x00400000: device->crystal = 27000; break; 3391 case 0x00400040: device->crystal = 25000; break; 3392 } 3393 3394 if (!device->name) 3395 device->name = device->chip->name; 3396 3397 mutex_init(&device->mutex); 3398 nvkm_intr_ctor(device); 3399 3400 #define NVKM_LAYOUT_ONCE(type,data,ptr) \ 3401 if (device->chip->ptr.inst) { \ 3402 WARN_ON(device->chip->ptr.inst != 0x00000001); \ 3403 ret = device->chip->ptr.ctor(device, (type), -1, &device->ptr); \ 3404 subdev = nvkm_device_subdev(device, (type), 0); \ 3405 if (ret) { \ 3406 nvkm_subdev_del(&subdev); \ 3407 device->ptr = NULL; \ 3408 if (ret != -ENODEV) { \ 3409 nvdev_error(device, "%s ctor failed: %d\n", \ 3410 nvkm_subdev_type[(type)], ret); \ 3411 goto done; \ 3412 } \ 3413 } else { \ 3414 subdev->pself = (void **)&device->ptr; \ 3415 } \ 3416 } 3417 #define NVKM_LAYOUT_INST(type,data,ptr,cnt) \ 3418 WARN_ON(device->chip->ptr.inst & ~((1 << ARRAY_SIZE(device->ptr)) - 1)); \ 3419 for (j = 0; device->chip->ptr.inst && j < ARRAY_SIZE(device->ptr); j++) { \ 3420 if (device->chip->ptr.inst & BIT(j)) { \ 3421 ret = device->chip->ptr.ctor(device, (type), (j), &device->ptr[j]); \ 3422 subdev = nvkm_device_subdev(device, (type), (j)); \ 3423 if (ret) { \ 3424 nvkm_subdev_del(&subdev); \ 3425 device->ptr[j] = NULL; \ 3426 if (ret != -ENODEV) { \ 3427 nvdev_error(device, "%s%d ctor failed: %d\n", \ 3428 nvkm_subdev_type[(type)], (j), ret); \ 3429 goto done; \ 3430 } \ 3431 } else { \ 3432 subdev->pself = (void **)&device->ptr[j]; \ 3433 } \ 3434 } \ 3435 } 3436 #include <core/layout.h> 3437 #undef NVKM_LAYOUT_INST 3438 #undef NVKM_LAYOUT_ONCE 3439 3440 ret = nvkm_intr_install(device); 3441 done: 3442 if (ret && device->pri) { 3443 iounmap(device->pri); 3444 device->pri = NULL; 3445 } 3446 mutex_unlock(&nv_devices_mutex); 3447 return ret; 3448 } 3449