1 /* SPDX-License-Identifier: MIT 2 * 3 * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. 4 */ 5 #ifndef _clc36f_h_ 6 #define _clc36f_h_ 7 8 #define NVC36F_NON_STALL_INTERRUPT (0x00000020) 9 #define NVC36F_NON_STALL_INTERRUPT_HANDLE 31:0 10 #define NVC36F_SEM_ADDR_LO (0x0000005c) 11 #define NVC36F_SEM_ADDR_LO_OFFSET 31:2 12 #define NVC36F_SEM_ADDR_HI (0x00000060) 13 #define NVC36F_SEM_ADDR_HI_OFFSET 7:0 14 #define NVC36F_SEM_PAYLOAD_LO (0x00000064) 15 #define NVC36F_SEM_PAYLOAD_LO_PAYLOAD 31:0 16 #define NVC36F_SEM_PAYLOAD_HI (0x00000068) 17 #define NVC36F_SEM_PAYLOAD_HI_PAYLOAD 31:0 18 #define NVC36F_SEM_EXECUTE (0x0000006c) 19 #define NVC36F_SEM_EXECUTE_OPERATION 2:0 20 #define NVC36F_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000 21 #define NVC36F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001 22 #define NVC36F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ 0x00000002 23 #define NVC36F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ 0x00000003 24 #define NVC36F_SEM_EXECUTE_OPERATION_ACQ_AND 0x00000004 25 #define NVC36F_SEM_EXECUTE_OPERATION_ACQ_NOR 0x00000005 26 #define NVC36F_SEM_EXECUTE_OPERATION_REDUCTION 0x00000006 27 #define NVC36F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG 12:12 28 #define NVC36F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS 0x00000000 29 #define NVC36F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN 0x00000001 30 #define NVC36F_SEM_EXECUTE_RELEASE_WFI 20:20 31 #define NVC36F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000 32 #define NVC36F_SEM_EXECUTE_RELEASE_WFI_EN 0x00000001 33 #define NVC36F_SEM_EXECUTE_PAYLOAD_SIZE 24:24 34 #define NVC36F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000 35 #define NVC36F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT 0x00000001 36 #define NVC36F_SEM_EXECUTE_RELEASE_TIMESTAMP 25:25 37 #define NVC36F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS 0x00000000 38 #define NVC36F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN 0x00000001 39 #define NVC36F_SEM_EXECUTE_REDUCTION 30:27 40 #define NVC36F_SEM_EXECUTE_REDUCTION_IMIN 0x00000000 41 #define NVC36F_SEM_EXECUTE_REDUCTION_IMAX 0x00000001 42 #define NVC36F_SEM_EXECUTE_REDUCTION_IXOR 0x00000002 43 #define NVC36F_SEM_EXECUTE_REDUCTION_IAND 0x00000003 44 #define NVC36F_SEM_EXECUTE_REDUCTION_IOR 0x00000004 45 #define NVC36F_SEM_EXECUTE_REDUCTION_IADD 0x00000005 46 #define NVC36F_SEM_EXECUTE_REDUCTION_INC 0x00000006 47 #define NVC36F_SEM_EXECUTE_REDUCTION_DEC 0x00000007 48 #define NVC36F_SEM_EXECUTE_REDUCTION_FORMAT 31:31 49 #define NVC36F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000000 50 #define NVC36F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000001 51 52 #endif 53