1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 */ 6 7 #include "msm_ringbuffer.h" 8 #include "msm_gpu.h" 9 10 static uint num_hw_submissions = 8; 11 MODULE_PARM_DESC(num_hw_submissions, "The max # of jobs to write into ringbuffer (default 8)"); 12 module_param(num_hw_submissions, uint, 0600); 13 14 static struct dma_fence *msm_job_run(struct drm_sched_job *job) 15 { 16 struct msm_gem_submit *submit = to_msm_submit(job); 17 struct msm_fence_context *fctx = submit->ring->fctx; 18 struct msm_gpu *gpu = submit->gpu; 19 struct msm_drm_private *priv = gpu->dev->dev_private; 20 int i; 21 22 msm_fence_init(submit->hw_fence, fctx); 23 24 mutex_lock(&priv->lru.lock); 25 26 for (i = 0; i < submit->nr_bos; i++) { 27 struct drm_gem_object *obj = submit->bos[i].obj; 28 29 msm_gem_unpin_active(obj); 30 } 31 32 submit->bos_pinned = false; 33 34 mutex_unlock(&priv->lru.lock); 35 36 /* TODO move submit path over to using a per-ring lock.. */ 37 mutex_lock(&gpu->lock); 38 39 msm_gpu_submit(gpu, submit); 40 41 mutex_unlock(&gpu->lock); 42 43 return dma_fence_get(submit->hw_fence); 44 } 45 46 static void msm_job_free(struct drm_sched_job *job) 47 { 48 struct msm_gem_submit *submit = to_msm_submit(job); 49 50 drm_sched_job_cleanup(job); 51 msm_gem_submit_put(submit); 52 } 53 54 static const struct drm_sched_backend_ops msm_sched_ops = { 55 .run_job = msm_job_run, 56 .free_job = msm_job_free 57 }; 58 59 struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id, 60 void *memptrs, uint64_t memptrs_iova) 61 { 62 struct drm_sched_init_args args = { 63 .ops = &msm_sched_ops, 64 .num_rqs = DRM_SCHED_PRIORITY_COUNT, 65 .credit_limit = num_hw_submissions, 66 .timeout = MAX_SCHEDULE_TIMEOUT, 67 .dev = gpu->dev->dev, 68 }; 69 struct msm_ringbuffer *ring; 70 char name[32]; 71 int ret; 72 73 /* We assume everywhere that MSM_GPU_RINGBUFFER_SZ is a power of 2 */ 74 BUILD_BUG_ON(!is_power_of_2(MSM_GPU_RINGBUFFER_SZ)); 75 76 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 77 if (!ring) { 78 ret = -ENOMEM; 79 goto fail; 80 } 81 82 ring->gpu = gpu; 83 ring->id = id; 84 85 ring->start = msm_gem_kernel_new(gpu->dev, MSM_GPU_RINGBUFFER_SZ, 86 check_apriv(gpu, MSM_BO_WC | MSM_BO_GPU_READONLY), 87 gpu->aspace, &ring->bo, &ring->iova); 88 89 if (IS_ERR(ring->start)) { 90 ret = PTR_ERR(ring->start); 91 ring->start = NULL; 92 goto fail; 93 } 94 95 msm_gem_object_set_name(ring->bo, "ring%d", id); 96 args.name = to_msm_bo(ring->bo)->name; 97 98 ring->end = ring->start + (MSM_GPU_RINGBUFFER_SZ >> 2); 99 ring->next = ring->start; 100 ring->cur = ring->start; 101 102 ring->memptrs = memptrs; 103 ring->memptrs_iova = memptrs_iova; 104 105 ret = drm_sched_init(&ring->sched, &args); 106 if (ret) { 107 goto fail; 108 } 109 110 INIT_LIST_HEAD(&ring->submits); 111 spin_lock_init(&ring->submit_lock); 112 spin_lock_init(&ring->preempt_lock); 113 114 snprintf(name, sizeof(name), "gpu-ring-%d", ring->id); 115 116 ring->fctx = msm_fence_context_alloc(gpu->dev, &ring->memptrs->fence, name); 117 118 return ring; 119 120 fail: 121 msm_ringbuffer_destroy(ring); 122 return ERR_PTR(ret); 123 } 124 125 void msm_ringbuffer_destroy(struct msm_ringbuffer *ring) 126 { 127 if (IS_ERR_OR_NULL(ring)) 128 return; 129 130 drm_sched_fini(&ring->sched); 131 132 msm_fence_context_free(ring->fctx); 133 134 msm_gem_kernel_put(ring->bo, ring->gpu->aspace); 135 136 kfree(ring); 137 } 138