1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #include <linux/limits.h> 4 #include <linux/pci.h> 5 #include <linux/units.h> 6 7 #include <drm/drm_atomic.h> 8 #include <drm/drm_atomic_helper.h> 9 #include <drm/drm_drv.h> 10 #include <drm/drm_gem_atomic_helper.h> 11 #include <drm/drm_probe_helper.h> 12 13 #include "mgag200_drv.h" 14 15 /* 16 * PIXPLLC 17 */ 18 19 static int mgag200_g200eh5_pixpllc_atomic_check(struct drm_crtc *crtc, 20 struct drm_atomic_state *new_state) 21 { 22 const unsigned long long VCO_MAX = 10 * GIGA; // Hz 23 const unsigned long long VCO_MIN = 2500 * MEGA; // Hz 24 const unsigned long long PLL_FREQ_REF = 25 * MEGA; // Hz 25 26 struct drm_crtc_state *new_crtc_state = drm_atomic_get_new_crtc_state(new_state, crtc); 27 struct mgag200_crtc_state *new_mgag200_crtc_state = to_mgag200_crtc_state(new_crtc_state); 28 long clock = new_crtc_state->mode.clock; 29 struct mgag200_pll_values *pixpllc = &new_mgag200_crtc_state->pixpllc; 30 31 unsigned long long fdelta = ULLONG_MAX; 32 33 u16 mult_max = (u16)(VCO_MAX / PLL_FREQ_REF); // 400 (0x190) 34 u16 mult_min = (u16)(VCO_MIN / PLL_FREQ_REF); // 100 (0x64) 35 36 u64 ftmp_delta; 37 u64 computed_fo; 38 39 u16 test_m; 40 u8 test_div_a; 41 u8 test_div_b; 42 u64 fo_hz; 43 44 u8 uc_m = 0; 45 u8 uc_n = 0; 46 u8 uc_p = 0; 47 48 fo_hz = (u64)clock * HZ_PER_KHZ; 49 50 for (test_m = mult_min; test_m <= mult_max; test_m++) { // This gives 100 <= M <= 400 51 for (test_div_a = 8; test_div_a > 0; test_div_a--) { // This gives 1 <= A <= 8 52 for (test_div_b = 1; test_div_b <= test_div_a; test_div_b++) { 53 // This gives 1 <= B <= A 54 computed_fo = (PLL_FREQ_REF * test_m) / 55 (4 * test_div_a * test_div_b); 56 57 if (computed_fo > fo_hz) 58 ftmp_delta = computed_fo - fo_hz; 59 else 60 ftmp_delta = fo_hz - computed_fo; 61 62 if (ftmp_delta < fdelta) { 63 fdelta = ftmp_delta; 64 uc_m = (u8)(0xFF & test_m); 65 uc_n = (u8)((0x7 & (test_div_a - 1)) 66 | (0x70 & (0x7 & (test_div_b - 1)) << 4)); 67 uc_p = (u8)(1 & (test_m >> 8)); 68 } 69 if (fdelta == 0) 70 break; 71 } 72 if (fdelta == 0) 73 break; 74 } 75 if (fdelta == 0) 76 break; 77 } 78 79 pixpllc->m = uc_m + 1; 80 pixpllc->n = uc_n + 1; 81 pixpllc->p = uc_p + 1; 82 pixpllc->s = 0; 83 84 return 0; 85 } 86 87 /* 88 * Mode-setting pipeline 89 */ 90 91 static const struct drm_plane_helper_funcs mgag200_g200eh5_primary_plane_helper_funcs = { 92 MGAG200_PRIMARY_PLANE_HELPER_FUNCS, 93 }; 94 95 static const struct drm_plane_funcs mgag200_g200eh5_primary_plane_funcs = { 96 MGAG200_PRIMARY_PLANE_FUNCS, 97 }; 98 99 static const struct drm_crtc_helper_funcs mgag200_g200eh5_crtc_helper_funcs = { 100 MGAG200_CRTC_HELPER_FUNCS, 101 }; 102 103 static const struct drm_crtc_funcs mgag200_g200eh5_crtc_funcs = { 104 MGAG200_CRTC_FUNCS, 105 }; 106 107 static int mgag200_g200eh5_pipeline_init(struct mga_device *mdev) 108 { 109 struct drm_device *dev = &mdev->base; 110 struct drm_plane *primary_plane = &mdev->primary_plane; 111 struct drm_crtc *crtc = &mdev->crtc; 112 int ret; 113 114 ret = drm_universal_plane_init(dev, primary_plane, 0, 115 &mgag200_g200eh5_primary_plane_funcs, 116 mgag200_primary_plane_formats, 117 mgag200_primary_plane_formats_size, 118 mgag200_primary_plane_fmtmods, 119 DRM_PLANE_TYPE_PRIMARY, NULL); 120 if (ret) { 121 drm_err(dev, "drm_universal_plane_init() failed: %d\n", ret); 122 return ret; 123 } 124 drm_plane_helper_add(primary_plane, &mgag200_g200eh5_primary_plane_helper_funcs); 125 drm_plane_enable_fb_damage_clips(primary_plane); 126 127 ret = drm_crtc_init_with_planes(dev, crtc, primary_plane, NULL, 128 &mgag200_g200eh5_crtc_funcs, NULL); 129 if (ret) { 130 drm_err(dev, "drm_crtc_init_with_planes() failed: %d\n", ret); 131 return ret; 132 } 133 134 drm_crtc_helper_add(crtc, &mgag200_g200eh5_crtc_helper_funcs); 135 136 /* FIXME: legacy gamma tables, but atomic gamma doesn't work without */ 137 drm_mode_crtc_set_gamma_size(crtc, MGAG200_LUT_SIZE); 138 drm_crtc_enable_color_mgmt(crtc, 0, false, MGAG200_LUT_SIZE); 139 ret = mgag200_vga_bmc_output_init(mdev); 140 141 if (ret) 142 return ret; 143 144 return 0; 145 } 146 147 /* 148 * DRM device 149 */ 150 151 static const struct mgag200_device_info mgag200_g200eh5_device_info = 152 MGAG200_DEVICE_INFO_INIT(2048, 2048, 0, false, 1, 0, false); 153 154 static const struct mgag200_device_funcs mgag200_g200eh5_device_funcs = { 155 .pixpllc_atomic_check = mgag200_g200eh5_pixpllc_atomic_check, 156 .pixpllc_atomic_update = mgag200_g200eh_pixpllc_atomic_update, // same as G200EH 157 }; 158 159 struct mga_device *mgag200_g200eh5_device_create(struct pci_dev *pdev, 160 const struct drm_driver *drv) 161 { 162 struct mga_device *mdev; 163 struct drm_device *dev; 164 resource_size_t vram_available; 165 int ret; 166 167 mdev = devm_drm_dev_alloc(&pdev->dev, drv, struct mga_device, base); 168 169 if (IS_ERR(mdev)) 170 return mdev; 171 dev = &mdev->base; 172 173 pci_set_drvdata(pdev, dev); 174 175 ret = mgag200_init_pci_options(pdev, 0x00000120, 0x0000b000); 176 if (ret) 177 return ERR_PTR(ret); 178 179 ret = mgag200_device_preinit(mdev); 180 if (ret) 181 return ERR_PTR(ret); 182 183 ret = mgag200_device_init(mdev, &mgag200_g200eh5_device_info, 184 &mgag200_g200eh5_device_funcs); 185 186 if (ret) 187 return ERR_PTR(ret); 188 189 mgag200_g200eh_init_registers(mdev); // same as G200EH 190 vram_available = mgag200_device_probe_vram(mdev); 191 192 ret = mgag200_mode_config_init(mdev, vram_available); 193 if (ret) 194 return ERR_PTR(ret); 195 196 ret = mgag200_g200eh5_pipeline_init(mdev); 197 if (ret) 198 return ERR_PTR(ret); 199 200 drm_mode_config_reset(dev); 201 drm_kms_helper_poll_init(dev); 202 203 return mdev; 204 } 205