1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: YT SHEN <yt.shen@mediatek.com> 5 */ 6 7 #include <linux/component.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/of_platform.h> 11 #include <linux/platform_device.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/dma-mapping.h> 14 15 #include <drm/clients/drm_client_setup.h> 16 #include <drm/drm_atomic.h> 17 #include <drm/drm_atomic_helper.h> 18 #include <drm/drm_drv.h> 19 #include <drm/drm_fbdev_dma.h> 20 #include <drm/drm_fourcc.h> 21 #include <drm/drm_gem.h> 22 #include <drm/drm_gem_framebuffer_helper.h> 23 #include <drm/drm_ioctl.h> 24 #include <drm/drm_of.h> 25 #include <drm/drm_probe_helper.h> 26 #include <drm/drm_vblank.h> 27 28 #include "mtk_crtc.h" 29 #include "mtk_ddp_comp.h" 30 #include "mtk_disp_drv.h" 31 #include "mtk_drm_drv.h" 32 #include "mtk_gem.h" 33 34 #define DRIVER_NAME "mediatek" 35 #define DRIVER_DESC "Mediatek SoC DRM" 36 #define DRIVER_MAJOR 1 37 #define DRIVER_MINOR 0 38 39 static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = { 40 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, 41 }; 42 43 static struct drm_framebuffer * 44 mtk_drm_mode_fb_create(struct drm_device *dev, 45 struct drm_file *file, 46 const struct drm_mode_fb_cmd2 *cmd) 47 { 48 const struct drm_format_info *info = drm_get_format_info(dev, cmd); 49 50 if (info->num_planes != 1) 51 return ERR_PTR(-EINVAL); 52 53 return drm_gem_fb_create(dev, file, cmd); 54 } 55 56 static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = { 57 .fb_create = mtk_drm_mode_fb_create, 58 .atomic_check = drm_atomic_helper_check, 59 .atomic_commit = drm_atomic_helper_commit, 60 }; 61 62 static const unsigned int mt2701_mtk_ddp_main[] = { 63 DDP_COMPONENT_OVL0, 64 DDP_COMPONENT_RDMA0, 65 DDP_COMPONENT_COLOR0, 66 DDP_COMPONENT_BLS, 67 DDP_COMPONENT_DSI0, 68 }; 69 70 static const unsigned int mt2701_mtk_ddp_ext[] = { 71 DDP_COMPONENT_RDMA1, 72 DDP_COMPONENT_DPI0, 73 }; 74 75 static const unsigned int mt7623_mtk_ddp_main[] = { 76 DDP_COMPONENT_OVL0, 77 DDP_COMPONENT_RDMA0, 78 DDP_COMPONENT_COLOR0, 79 DDP_COMPONENT_BLS, 80 DDP_COMPONENT_DPI0, 81 }; 82 83 static const unsigned int mt7623_mtk_ddp_ext[] = { 84 DDP_COMPONENT_RDMA1, 85 DDP_COMPONENT_DSI0, 86 }; 87 88 static const unsigned int mt2712_mtk_ddp_main[] = { 89 DDP_COMPONENT_OVL0, 90 DDP_COMPONENT_COLOR0, 91 DDP_COMPONENT_AAL0, 92 DDP_COMPONENT_OD0, 93 DDP_COMPONENT_RDMA0, 94 DDP_COMPONENT_DPI0, 95 DDP_COMPONENT_PWM0, 96 }; 97 98 static const unsigned int mt2712_mtk_ddp_ext[] = { 99 DDP_COMPONENT_OVL1, 100 DDP_COMPONENT_COLOR1, 101 DDP_COMPONENT_AAL1, 102 DDP_COMPONENT_OD1, 103 DDP_COMPONENT_RDMA1, 104 DDP_COMPONENT_DPI1, 105 DDP_COMPONENT_PWM1, 106 }; 107 108 static const unsigned int mt2712_mtk_ddp_third[] = { 109 DDP_COMPONENT_RDMA2, 110 DDP_COMPONENT_DSI3, 111 DDP_COMPONENT_PWM2, 112 }; 113 114 static unsigned int mt8167_mtk_ddp_main[] = { 115 DDP_COMPONENT_OVL0, 116 DDP_COMPONENT_COLOR0, 117 DDP_COMPONENT_CCORR, 118 DDP_COMPONENT_AAL0, 119 DDP_COMPONENT_GAMMA, 120 DDP_COMPONENT_DITHER0, 121 DDP_COMPONENT_RDMA0, 122 DDP_COMPONENT_DSI0, 123 }; 124 125 static const unsigned int mt8173_mtk_ddp_main[] = { 126 DDP_COMPONENT_OVL0, 127 DDP_COMPONENT_COLOR0, 128 DDP_COMPONENT_AAL0, 129 DDP_COMPONENT_OD0, 130 DDP_COMPONENT_RDMA0, 131 DDP_COMPONENT_UFOE, 132 DDP_COMPONENT_DSI0, 133 DDP_COMPONENT_PWM0, 134 }; 135 136 static const unsigned int mt8173_mtk_ddp_ext[] = { 137 DDP_COMPONENT_OVL1, 138 DDP_COMPONENT_COLOR1, 139 DDP_COMPONENT_GAMMA, 140 DDP_COMPONENT_RDMA1, 141 DDP_COMPONENT_DPI0, 142 }; 143 144 static const unsigned int mt8183_mtk_ddp_main[] = { 145 DDP_COMPONENT_OVL0, 146 DDP_COMPONENT_OVL_2L0, 147 DDP_COMPONENT_RDMA0, 148 DDP_COMPONENT_COLOR0, 149 DDP_COMPONENT_CCORR, 150 DDP_COMPONENT_AAL0, 151 DDP_COMPONENT_GAMMA, 152 DDP_COMPONENT_DITHER0, 153 DDP_COMPONENT_DSI0, 154 }; 155 156 static const unsigned int mt8183_mtk_ddp_ext[] = { 157 DDP_COMPONENT_OVL_2L1, 158 DDP_COMPONENT_RDMA1, 159 DDP_COMPONENT_DPI0, 160 }; 161 162 static const unsigned int mt8186_mtk_ddp_main[] = { 163 DDP_COMPONENT_OVL0, 164 DDP_COMPONENT_RDMA0, 165 DDP_COMPONENT_COLOR0, 166 DDP_COMPONENT_CCORR, 167 DDP_COMPONENT_AAL0, 168 DDP_COMPONENT_GAMMA, 169 DDP_COMPONENT_POSTMASK0, 170 DDP_COMPONENT_DITHER0, 171 DDP_COMPONENT_DSI0, 172 }; 173 174 static const unsigned int mt8186_mtk_ddp_ext[] = { 175 DDP_COMPONENT_OVL_2L0, 176 DDP_COMPONENT_RDMA1, 177 DDP_COMPONENT_DPI0, 178 }; 179 180 static const unsigned int mt8188_mtk_ddp_main[] = { 181 DDP_COMPONENT_OVL0, 182 DDP_COMPONENT_RDMA0, 183 DDP_COMPONENT_COLOR0, 184 DDP_COMPONENT_CCORR, 185 DDP_COMPONENT_AAL0, 186 DDP_COMPONENT_GAMMA, 187 DDP_COMPONENT_POSTMASK0, 188 DDP_COMPONENT_DITHER0, 189 }; 190 191 static const struct mtk_drm_route mt8188_mtk_ddp_main_routes[] = { 192 {0, DDP_COMPONENT_DP_INTF0}, 193 {0, DDP_COMPONENT_DSI0}, 194 }; 195 196 static const unsigned int mt8192_mtk_ddp_main[] = { 197 DDP_COMPONENT_OVL0, 198 DDP_COMPONENT_OVL_2L0, 199 DDP_COMPONENT_RDMA0, 200 DDP_COMPONENT_COLOR0, 201 DDP_COMPONENT_CCORR, 202 DDP_COMPONENT_AAL0, 203 DDP_COMPONENT_GAMMA, 204 DDP_COMPONENT_POSTMASK0, 205 DDP_COMPONENT_DITHER0, 206 DDP_COMPONENT_DSI0, 207 }; 208 209 static const unsigned int mt8192_mtk_ddp_ext[] = { 210 DDP_COMPONENT_OVL_2L2, 211 DDP_COMPONENT_RDMA4, 212 DDP_COMPONENT_DPI0, 213 }; 214 215 static const unsigned int mt8195_mtk_ddp_main[] = { 216 DDP_COMPONENT_OVL0, 217 DDP_COMPONENT_RDMA0, 218 DDP_COMPONENT_COLOR0, 219 DDP_COMPONENT_CCORR, 220 DDP_COMPONENT_AAL0, 221 DDP_COMPONENT_GAMMA, 222 DDP_COMPONENT_DITHER0, 223 DDP_COMPONENT_DSC0, 224 DDP_COMPONENT_MERGE0, 225 DDP_COMPONENT_DP_INTF0, 226 }; 227 228 static const unsigned int mt8195_mtk_ddp_ext[] = { 229 DDP_COMPONENT_DRM_OVL_ADAPTOR, 230 DDP_COMPONENT_MERGE5, 231 DDP_COMPONENT_DP_INTF1, 232 }; 233 234 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { 235 .main_path = mt2701_mtk_ddp_main, 236 .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), 237 .ext_path = mt2701_mtk_ddp_ext, 238 .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext), 239 .shadow_register = true, 240 .mmsys_dev_num = 1, 241 }; 242 243 static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = { 244 .main_path = mt7623_mtk_ddp_main, 245 .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main), 246 .ext_path = mt7623_mtk_ddp_ext, 247 .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext), 248 .shadow_register = true, 249 .mmsys_dev_num = 1, 250 }; 251 252 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { 253 .main_path = mt2712_mtk_ddp_main, 254 .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), 255 .ext_path = mt2712_mtk_ddp_ext, 256 .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), 257 .third_path = mt2712_mtk_ddp_third, 258 .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), 259 .mmsys_dev_num = 1, 260 }; 261 262 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { 263 .main_path = mt8167_mtk_ddp_main, 264 .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main), 265 .mmsys_dev_num = 1, 266 }; 267 268 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { 269 .main_path = mt8173_mtk_ddp_main, 270 .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), 271 .ext_path = mt8173_mtk_ddp_ext, 272 .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), 273 .mmsys_dev_num = 1, 274 }; 275 276 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { 277 .main_path = mt8183_mtk_ddp_main, 278 .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), 279 .ext_path = mt8183_mtk_ddp_ext, 280 .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), 281 .mmsys_dev_num = 1, 282 }; 283 284 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { 285 .main_path = mt8186_mtk_ddp_main, 286 .main_len = ARRAY_SIZE(mt8186_mtk_ddp_main), 287 .ext_path = mt8186_mtk_ddp_ext, 288 .ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext), 289 .mmsys_dev_num = 1, 290 }; 291 292 static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = { 293 .main_path = mt8188_mtk_ddp_main, 294 .main_len = ARRAY_SIZE(mt8188_mtk_ddp_main), 295 .conn_routes = mt8188_mtk_ddp_main_routes, 296 .num_conn_routes = ARRAY_SIZE(mt8188_mtk_ddp_main_routes), 297 .mmsys_dev_num = 2, 298 .max_width = 8191, 299 .min_width = 1, 300 .min_height = 1, 301 }; 302 303 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { 304 .main_path = mt8192_mtk_ddp_main, 305 .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main), 306 .ext_path = mt8192_mtk_ddp_ext, 307 .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext), 308 .mmsys_dev_num = 1, 309 }; 310 311 static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { 312 .main_path = mt8195_mtk_ddp_main, 313 .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main), 314 .mmsys_dev_num = 2, 315 .max_width = 8191, 316 .min_width = 1, 317 .min_height = 1, 318 }; 319 320 static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { 321 .ext_path = mt8195_mtk_ddp_ext, 322 .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext), 323 .mmsys_id = 1, 324 .mmsys_dev_num = 2, 325 .max_width = 8191, 326 .min_width = 2, /* 2-pixel align when ethdr is bypassed */ 327 .min_height = 1, 328 }; 329 330 static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { 331 .mmsys_dev_num = 1, 332 }; 333 334 static const struct of_device_id mtk_drm_of_ids[] = { 335 { .compatible = "mediatek,mt2701-mmsys", 336 .data = &mt2701_mmsys_driver_data}, 337 { .compatible = "mediatek,mt7623-mmsys", 338 .data = &mt7623_mmsys_driver_data}, 339 { .compatible = "mediatek,mt2712-mmsys", 340 .data = &mt2712_mmsys_driver_data}, 341 { .compatible = "mediatek,mt8167-mmsys", 342 .data = &mt8167_mmsys_driver_data}, 343 { .compatible = "mediatek,mt8173-mmsys", 344 .data = &mt8173_mmsys_driver_data}, 345 { .compatible = "mediatek,mt8183-mmsys", 346 .data = &mt8183_mmsys_driver_data}, 347 { .compatible = "mediatek,mt8186-mmsys", 348 .data = &mt8186_mmsys_driver_data}, 349 { .compatible = "mediatek,mt8188-vdosys0", 350 .data = &mt8188_vdosys0_driver_data}, 351 { .compatible = "mediatek,mt8188-vdosys1", 352 .data = &mt8195_vdosys1_driver_data}, 353 { .compatible = "mediatek,mt8192-mmsys", 354 .data = &mt8192_mmsys_driver_data}, 355 { .compatible = "mediatek,mt8195-mmsys", 356 .data = &mt8195_vdosys0_driver_data}, 357 { .compatible = "mediatek,mt8195-vdosys0", 358 .data = &mt8195_vdosys0_driver_data}, 359 { .compatible = "mediatek,mt8195-vdosys1", 360 .data = &mt8195_vdosys1_driver_data}, 361 { .compatible = "mediatek,mt8365-mmsys", 362 .data = &mt8365_mmsys_driver_data}, 363 { } 364 }; 365 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids); 366 367 static int mtk_drm_match(struct device *dev, const void *data) 368 { 369 if (!strncmp(dev_name(dev), "mediatek-drm", sizeof("mediatek-drm") - 1)) 370 return true; 371 return false; 372 } 373 374 static bool mtk_drm_get_all_drm_priv(struct device *dev) 375 { 376 struct mtk_drm_private *drm_priv = dev_get_drvdata(dev); 377 struct mtk_drm_private *all_drm_priv[MAX_CRTC]; 378 struct mtk_drm_private *temp_drm_priv; 379 struct device_node *phandle = dev->parent->of_node; 380 const struct of_device_id *of_id; 381 struct device_node *node; 382 struct device *drm_dev; 383 unsigned int cnt = 0; 384 int i, j; 385 386 for_each_child_of_node(phandle->parent, node) { 387 struct platform_device *pdev; 388 389 of_id = of_match_node(mtk_drm_of_ids, node); 390 if (!of_id) 391 continue; 392 393 pdev = of_find_device_by_node(node); 394 if (!pdev) 395 continue; 396 397 drm_dev = device_find_child(&pdev->dev, NULL, mtk_drm_match); 398 if (!drm_dev) 399 continue; 400 401 temp_drm_priv = dev_get_drvdata(drm_dev); 402 if (!temp_drm_priv) 403 continue; 404 405 if (temp_drm_priv->data->main_len) 406 all_drm_priv[CRTC_MAIN] = temp_drm_priv; 407 else if (temp_drm_priv->data->ext_len) 408 all_drm_priv[CRTC_EXT] = temp_drm_priv; 409 else if (temp_drm_priv->data->third_len) 410 all_drm_priv[CRTC_THIRD] = temp_drm_priv; 411 412 if (temp_drm_priv->mtk_drm_bound) 413 cnt++; 414 415 if (cnt == MAX_CRTC) { 416 of_node_put(node); 417 break; 418 } 419 } 420 421 if (drm_priv->data->mmsys_dev_num == cnt) { 422 for (i = 0; i < cnt; i++) 423 for (j = 0; j < cnt; j++) 424 all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i]; 425 426 return true; 427 } 428 429 return false; 430 } 431 432 static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id) 433 { 434 const struct mtk_mmsys_driver_data *drv_data = private->data; 435 int i; 436 437 if (drv_data->main_path) 438 for (i = 0; i < drv_data->main_len; i++) 439 if (drv_data->main_path[i] == comp_id) 440 return true; 441 442 if (drv_data->ext_path) 443 for (i = 0; i < drv_data->ext_len; i++) 444 if (drv_data->ext_path[i] == comp_id) 445 return true; 446 447 if (drv_data->third_path) 448 for (i = 0; i < drv_data->third_len; i++) 449 if (drv_data->third_path[i] == comp_id) 450 return true; 451 452 if (drv_data->num_conn_routes) 453 for (i = 0; i < drv_data->num_conn_routes; i++) 454 if (drv_data->conn_routes[i].route_ddp == comp_id) 455 return true; 456 457 return false; 458 } 459 460 static int mtk_drm_kms_init(struct drm_device *drm) 461 { 462 struct mtk_drm_private *private = drm->dev_private; 463 struct mtk_drm_private *priv_n; 464 struct device *dma_dev = NULL; 465 struct drm_crtc *crtc; 466 int ret, i, j; 467 468 if (drm_firmware_drivers_only()) 469 return -ENODEV; 470 471 ret = drmm_mode_config_init(drm); 472 if (ret) 473 return ret; 474 475 drm->mode_config.min_width = 64; 476 drm->mode_config.min_height = 64; 477 478 /* 479 * set max width and height as default value(4096x4096). 480 * this value would be used to check framebuffer size limitation 481 * at drm_mode_addfb(). 482 */ 483 drm->mode_config.max_width = 4096; 484 drm->mode_config.max_height = 4096; 485 drm->mode_config.funcs = &mtk_drm_mode_config_funcs; 486 drm->mode_config.helper_private = &mtk_drm_mode_config_helpers; 487 488 for (i = 0; i < private->data->mmsys_dev_num; i++) { 489 drm->dev_private = private->all_drm_private[i]; 490 ret = component_bind_all(private->all_drm_private[i]->dev, drm); 491 if (ret) { 492 while (--i >= 0) 493 component_unbind_all(private->all_drm_private[i]->dev, drm); 494 return ret; 495 } 496 } 497 498 /* 499 * Ensure internal panels are at the top of the connector list before 500 * crtc creation. 501 */ 502 drm_helper_move_panel_connectors_to_head(drm); 503 504 /* 505 * 1. We currently support two fixed data streams, each optional, 506 * and each statically assigned to a crtc: 507 * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ... 508 * 2. For multi mmsys architecture, crtc path data are located in 509 * different drm private data structures. Loop through crtc index to 510 * create crtc from the main path and then ext_path and finally the 511 * third path. 512 */ 513 for (i = 0; i < MAX_CRTC; i++) { 514 for (j = 0; j < private->data->mmsys_dev_num; j++) { 515 priv_n = private->all_drm_private[j]; 516 517 if (priv_n->data->max_width) 518 drm->mode_config.max_width = priv_n->data->max_width; 519 520 if (priv_n->data->min_width) 521 drm->mode_config.min_width = priv_n->data->min_width; 522 523 if (priv_n->data->min_height) 524 drm->mode_config.min_height = priv_n->data->min_height; 525 526 if (i == CRTC_MAIN && priv_n->data->main_len) { 527 ret = mtk_crtc_create(drm, priv_n->data->main_path, 528 priv_n->data->main_len, j, 529 priv_n->data->conn_routes, 530 priv_n->data->num_conn_routes); 531 if (ret) 532 goto err_component_unbind; 533 534 continue; 535 } else if (i == CRTC_EXT && priv_n->data->ext_len) { 536 ret = mtk_crtc_create(drm, priv_n->data->ext_path, 537 priv_n->data->ext_len, j, NULL, 0); 538 if (ret) 539 goto err_component_unbind; 540 541 continue; 542 } else if (i == CRTC_THIRD && priv_n->data->third_len) { 543 ret = mtk_crtc_create(drm, priv_n->data->third_path, 544 priv_n->data->third_len, j, NULL, 0); 545 if (ret) 546 goto err_component_unbind; 547 548 continue; 549 } 550 } 551 } 552 553 /* IGT will check if the cursor size is configured */ 554 drm->mode_config.cursor_width = 512; 555 drm->mode_config.cursor_height = 512; 556 557 /* Use OVL device for all DMA memory allocations */ 558 crtc = drm_crtc_from_index(drm, 0); 559 if (crtc) 560 dma_dev = mtk_crtc_dma_dev_get(crtc); 561 if (!dma_dev) { 562 ret = -ENODEV; 563 dev_err(drm->dev, "Need at least one OVL device\n"); 564 goto err_component_unbind; 565 } 566 567 for (i = 0; i < private->data->mmsys_dev_num; i++) 568 private->all_drm_private[i]->dma_dev = dma_dev; 569 570 /* 571 * Configure the DMA segment size to make sure we get contiguous IOVA 572 * when importing PRIME buffers. 573 */ 574 dma_set_max_seg_size(dma_dev, UINT_MAX); 575 576 ret = drm_vblank_init(drm, MAX_CRTC); 577 if (ret < 0) 578 goto err_component_unbind; 579 580 drm_kms_helper_poll_init(drm); 581 drm_mode_config_reset(drm); 582 583 return 0; 584 585 err_component_unbind: 586 for (i = 0; i < private->data->mmsys_dev_num; i++) 587 component_unbind_all(private->all_drm_private[i]->dev, drm); 588 589 return ret; 590 } 591 592 static void mtk_drm_kms_deinit(struct drm_device *drm) 593 { 594 drm_kms_helper_poll_fini(drm); 595 drm_atomic_helper_shutdown(drm); 596 597 component_unbind_all(drm->dev, drm); 598 } 599 600 DEFINE_DRM_GEM_FOPS(mtk_drm_fops); 601 602 /* 603 * We need to override this because the device used to import the memory is 604 * not dev->dev, as drm_gem_prime_import() expects. 605 */ 606 static struct drm_gem_object *mtk_gem_prime_import(struct drm_device *dev, 607 struct dma_buf *dma_buf) 608 { 609 struct mtk_drm_private *private = dev->dev_private; 610 611 return drm_gem_prime_import_dev(dev, dma_buf, private->dma_dev); 612 } 613 614 static const struct drm_driver mtk_drm_driver = { 615 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 616 617 .dumb_create = mtk_gem_dumb_create, 618 DRM_FBDEV_DMA_DRIVER_OPS, 619 620 .gem_prime_import = mtk_gem_prime_import, 621 .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table, 622 .fops = &mtk_drm_fops, 623 624 .name = DRIVER_NAME, 625 .desc = DRIVER_DESC, 626 .major = DRIVER_MAJOR, 627 .minor = DRIVER_MINOR, 628 }; 629 630 static int compare_dev(struct device *dev, void *data) 631 { 632 return dev == (struct device *)data; 633 } 634 635 static int mtk_drm_bind(struct device *dev) 636 { 637 struct mtk_drm_private *private = dev_get_drvdata(dev); 638 struct platform_device *pdev; 639 struct drm_device *drm; 640 int ret, i; 641 642 pdev = of_find_device_by_node(private->mutex_node); 643 if (!pdev) { 644 dev_err(dev, "Waiting for disp-mutex device %pOF\n", 645 private->mutex_node); 646 of_node_put(private->mutex_node); 647 return -EPROBE_DEFER; 648 } 649 650 private->mutex_dev = &pdev->dev; 651 private->mtk_drm_bound = true; 652 private->dev = dev; 653 654 if (!mtk_drm_get_all_drm_priv(dev)) 655 return 0; 656 657 drm = drm_dev_alloc(&mtk_drm_driver, dev); 658 if (IS_ERR(drm)) { 659 ret = PTR_ERR(drm); 660 goto err_put_dev; 661 } 662 663 private->drm_master = true; 664 drm->dev_private = private; 665 for (i = 0; i < private->data->mmsys_dev_num; i++) 666 private->all_drm_private[i]->drm = drm; 667 668 ret = mtk_drm_kms_init(drm); 669 if (ret < 0) 670 goto err_free; 671 672 ret = drm_dev_register(drm, 0); 673 if (ret < 0) 674 goto err_deinit; 675 676 drm_client_setup(drm, NULL); 677 678 return 0; 679 680 err_deinit: 681 mtk_drm_kms_deinit(drm); 682 err_free: 683 private->drm = NULL; 684 drm_dev_put(drm); 685 for (i = 0; i < private->data->mmsys_dev_num; i++) 686 private->all_drm_private[i]->drm = NULL; 687 err_put_dev: 688 for (i = 0; i < private->data->mmsys_dev_num; i++) { 689 /* For device_find_child in mtk_drm_get_all_priv() */ 690 put_device(private->all_drm_private[i]->dev); 691 } 692 put_device(private->mutex_dev); 693 return ret; 694 } 695 696 static void mtk_drm_unbind(struct device *dev) 697 { 698 struct mtk_drm_private *private = dev_get_drvdata(dev); 699 int i; 700 701 /* for multi mmsys dev, unregister drm dev in mmsys master */ 702 if (private->drm_master) { 703 drm_dev_unregister(private->drm); 704 mtk_drm_kms_deinit(private->drm); 705 drm_dev_put(private->drm); 706 707 for (i = 0; i < private->data->mmsys_dev_num; i++) { 708 /* For device_find_child in mtk_drm_get_all_priv() */ 709 put_device(private->all_drm_private[i]->dev); 710 } 711 put_device(private->mutex_dev); 712 } 713 private->mtk_drm_bound = false; 714 private->drm_master = false; 715 private->drm = NULL; 716 } 717 718 static const struct component_master_ops mtk_drm_ops = { 719 .bind = mtk_drm_bind, 720 .unbind = mtk_drm_unbind, 721 }; 722 723 static const struct of_device_id mtk_ddp_comp_dt_ids[] = { 724 { .compatible = "mediatek,mt8167-disp-aal", 725 .data = (void *)MTK_DISP_AAL}, 726 { .compatible = "mediatek,mt8173-disp-aal", 727 .data = (void *)MTK_DISP_AAL}, 728 { .compatible = "mediatek,mt8183-disp-aal", 729 .data = (void *)MTK_DISP_AAL}, 730 { .compatible = "mediatek,mt8192-disp-aal", 731 .data = (void *)MTK_DISP_AAL}, 732 { .compatible = "mediatek,mt8167-disp-ccorr", 733 .data = (void *)MTK_DISP_CCORR }, 734 { .compatible = "mediatek,mt8183-disp-ccorr", 735 .data = (void *)MTK_DISP_CCORR }, 736 { .compatible = "mediatek,mt8192-disp-ccorr", 737 .data = (void *)MTK_DISP_CCORR }, 738 { .compatible = "mediatek,mt2701-disp-color", 739 .data = (void *)MTK_DISP_COLOR }, 740 { .compatible = "mediatek,mt8167-disp-color", 741 .data = (void *)MTK_DISP_COLOR }, 742 { .compatible = "mediatek,mt8173-disp-color", 743 .data = (void *)MTK_DISP_COLOR }, 744 { .compatible = "mediatek,mt8167-disp-dither", 745 .data = (void *)MTK_DISP_DITHER }, 746 { .compatible = "mediatek,mt8183-disp-dither", 747 .data = (void *)MTK_DISP_DITHER }, 748 { .compatible = "mediatek,mt8195-disp-dsc", 749 .data = (void *)MTK_DISP_DSC }, 750 { .compatible = "mediatek,mt8167-disp-gamma", 751 .data = (void *)MTK_DISP_GAMMA, }, 752 { .compatible = "mediatek,mt8173-disp-gamma", 753 .data = (void *)MTK_DISP_GAMMA, }, 754 { .compatible = "mediatek,mt8183-disp-gamma", 755 .data = (void *)MTK_DISP_GAMMA, }, 756 { .compatible = "mediatek,mt8195-disp-gamma", 757 .data = (void *)MTK_DISP_GAMMA, }, 758 { .compatible = "mediatek,mt8195-disp-merge", 759 .data = (void *)MTK_DISP_MERGE }, 760 { .compatible = "mediatek,mt2701-disp-mutex", 761 .data = (void *)MTK_DISP_MUTEX }, 762 { .compatible = "mediatek,mt2712-disp-mutex", 763 .data = (void *)MTK_DISP_MUTEX }, 764 { .compatible = "mediatek,mt8167-disp-mutex", 765 .data = (void *)MTK_DISP_MUTEX }, 766 { .compatible = "mediatek,mt8173-disp-mutex", 767 .data = (void *)MTK_DISP_MUTEX }, 768 { .compatible = "mediatek,mt8183-disp-mutex", 769 .data = (void *)MTK_DISP_MUTEX }, 770 { .compatible = "mediatek,mt8186-disp-mutex", 771 .data = (void *)MTK_DISP_MUTEX }, 772 { .compatible = "mediatek,mt8188-disp-mutex", 773 .data = (void *)MTK_DISP_MUTEX }, 774 { .compatible = "mediatek,mt8192-disp-mutex", 775 .data = (void *)MTK_DISP_MUTEX }, 776 { .compatible = "mediatek,mt8195-disp-mutex", 777 .data = (void *)MTK_DISP_MUTEX }, 778 { .compatible = "mediatek,mt8365-disp-mutex", 779 .data = (void *)MTK_DISP_MUTEX }, 780 { .compatible = "mediatek,mt8173-disp-od", 781 .data = (void *)MTK_DISP_OD }, 782 { .compatible = "mediatek,mt2701-disp-ovl", 783 .data = (void *)MTK_DISP_OVL }, 784 { .compatible = "mediatek,mt8167-disp-ovl", 785 .data = (void *)MTK_DISP_OVL }, 786 { .compatible = "mediatek,mt8173-disp-ovl", 787 .data = (void *)MTK_DISP_OVL }, 788 { .compatible = "mediatek,mt8183-disp-ovl", 789 .data = (void *)MTK_DISP_OVL }, 790 { .compatible = "mediatek,mt8192-disp-ovl", 791 .data = (void *)MTK_DISP_OVL }, 792 { .compatible = "mediatek,mt8195-disp-ovl", 793 .data = (void *)MTK_DISP_OVL }, 794 { .compatible = "mediatek,mt8183-disp-ovl-2l", 795 .data = (void *)MTK_DISP_OVL_2L }, 796 { .compatible = "mediatek,mt8192-disp-ovl-2l", 797 .data = (void *)MTK_DISP_OVL_2L }, 798 { .compatible = "mediatek,mt8192-disp-postmask", 799 .data = (void *)MTK_DISP_POSTMASK }, 800 { .compatible = "mediatek,mt2701-disp-pwm", 801 .data = (void *)MTK_DISP_BLS }, 802 { .compatible = "mediatek,mt8167-disp-pwm", 803 .data = (void *)MTK_DISP_PWM }, 804 { .compatible = "mediatek,mt8173-disp-pwm", 805 .data = (void *)MTK_DISP_PWM }, 806 { .compatible = "mediatek,mt2701-disp-rdma", 807 .data = (void *)MTK_DISP_RDMA }, 808 { .compatible = "mediatek,mt8167-disp-rdma", 809 .data = (void *)MTK_DISP_RDMA }, 810 { .compatible = "mediatek,mt8173-disp-rdma", 811 .data = (void *)MTK_DISP_RDMA }, 812 { .compatible = "mediatek,mt8183-disp-rdma", 813 .data = (void *)MTK_DISP_RDMA }, 814 { .compatible = "mediatek,mt8195-disp-rdma", 815 .data = (void *)MTK_DISP_RDMA }, 816 { .compatible = "mediatek,mt8173-disp-ufoe", 817 .data = (void *)MTK_DISP_UFOE }, 818 { .compatible = "mediatek,mt8173-disp-wdma", 819 .data = (void *)MTK_DISP_WDMA }, 820 { .compatible = "mediatek,mt2701-dpi", 821 .data = (void *)MTK_DPI }, 822 { .compatible = "mediatek,mt8167-dsi", 823 .data = (void *)MTK_DSI }, 824 { .compatible = "mediatek,mt8173-dpi", 825 .data = (void *)MTK_DPI }, 826 { .compatible = "mediatek,mt8183-dpi", 827 .data = (void *)MTK_DPI }, 828 { .compatible = "mediatek,mt8186-dpi", 829 .data = (void *)MTK_DPI }, 830 { .compatible = "mediatek,mt8188-dp-intf", 831 .data = (void *)MTK_DP_INTF }, 832 { .compatible = "mediatek,mt8192-dpi", 833 .data = (void *)MTK_DPI }, 834 { .compatible = "mediatek,mt8195-dp-intf", 835 .data = (void *)MTK_DP_INTF }, 836 { .compatible = "mediatek,mt8195-dpi", 837 .data = (void *)MTK_DPI }, 838 { .compatible = "mediatek,mt2701-dsi", 839 .data = (void *)MTK_DSI }, 840 { .compatible = "mediatek,mt8173-dsi", 841 .data = (void *)MTK_DSI }, 842 { .compatible = "mediatek,mt8183-dsi", 843 .data = (void *)MTK_DSI }, 844 { .compatible = "mediatek,mt8186-dsi", 845 .data = (void *)MTK_DSI }, 846 { .compatible = "mediatek,mt8188-dsi", 847 .data = (void *)MTK_DSI }, 848 { } 849 }; 850 851 static int mtk_drm_of_get_ddp_comp_type(struct device_node *node, enum mtk_ddp_comp_type *ctype) 852 { 853 const struct of_device_id *of_id = of_match_node(mtk_ddp_comp_dt_ids, node); 854 855 if (!of_id) 856 return -EINVAL; 857 858 *ctype = (enum mtk_ddp_comp_type)((uintptr_t)of_id->data); 859 860 return 0; 861 } 862 863 static int mtk_drm_of_get_ddp_ep_cid(struct device_node *node, 864 int output_port, enum mtk_crtc_path crtc_path, 865 struct device_node **next, unsigned int *cid) 866 { 867 struct device_node *ep_dev_node, *ep_out; 868 enum mtk_ddp_comp_type comp_type; 869 int ret; 870 871 ep_out = of_graph_get_endpoint_by_regs(node, output_port, crtc_path); 872 if (!ep_out) 873 return -ENOENT; 874 875 ep_dev_node = of_graph_get_remote_port_parent(ep_out); 876 of_node_put(ep_out); 877 if (!ep_dev_node) 878 return -EINVAL; 879 880 /* 881 * Pass the next node pointer regardless of failures in the later code 882 * so that if this function is called in a loop it will walk through all 883 * of the subsequent endpoints anyway. 884 */ 885 *next = ep_dev_node; 886 887 if (!of_device_is_available(ep_dev_node)) 888 return -ENODEV; 889 890 ret = mtk_drm_of_get_ddp_comp_type(ep_dev_node, &comp_type); 891 if (ret) { 892 if (mtk_ovl_adaptor_is_comp_present(ep_dev_node)) { 893 *cid = (unsigned int)DDP_COMPONENT_DRM_OVL_ADAPTOR; 894 return 0; 895 } 896 return ret; 897 } 898 899 ret = mtk_ddp_comp_get_id(ep_dev_node, comp_type); 900 if (ret < 0) 901 return ret; 902 903 /* All ok! Pass the Component ID to the caller. */ 904 *cid = (unsigned int)ret; 905 906 return 0; 907 } 908 909 /** 910 * mtk_drm_of_ddp_path_build_one - Build a Display HW Pipeline for a CRTC Path 911 * @dev: The mediatek-drm device 912 * @cpath: CRTC Path relative to a VDO or MMSYS 913 * @out_path: Pointer to an array that will contain the new pipeline 914 * @out_path_len: Number of entries in the pipeline array 915 * 916 * MediaTek SoCs can use different DDP hardware pipelines (or paths) depending 917 * on the board-specific desired display configuration; this function walks 918 * through all of the output endpoints starting from a VDO or MMSYS hardware 919 * instance and builds the right pipeline as specified in device trees. 920 * 921 * Return: 922 * * %0 - Display HW Pipeline successfully built and validated 923 * * %-ENOENT - Display pipeline was not specified in device tree 924 * * %-EINVAL - Display pipeline built but validation failed 925 * * %-ENOMEM - Failure to allocate pipeline array to pass to the caller 926 */ 927 static int mtk_drm_of_ddp_path_build_one(struct device *dev, enum mtk_crtc_path cpath, 928 const unsigned int **out_path, 929 unsigned int *out_path_len) 930 { 931 struct device_node *next = NULL, *prev, *vdo = dev->parent->of_node; 932 unsigned int temp_path[DDP_COMPONENT_DRM_ID_MAX] = { 0 }; 933 unsigned int *final_ddp_path; 934 unsigned short int idx = 0; 935 bool ovl_adaptor_comp_added = false; 936 int ret; 937 938 /* Get the first entry for the temp_path array */ 939 ret = mtk_drm_of_get_ddp_ep_cid(vdo, 0, cpath, &next, &temp_path[idx]); 940 if (ret) { 941 if (next && temp_path[idx] == DDP_COMPONENT_DRM_OVL_ADAPTOR) { 942 dev_dbg(dev, "Adding OVL Adaptor for %pOF\n", next); 943 ovl_adaptor_comp_added = true; 944 } else { 945 if (next) 946 dev_err(dev, "Invalid component %pOF\n", next); 947 else 948 dev_err(dev, "Cannot find first endpoint for path %d\n", cpath); 949 950 return ret; 951 } 952 } 953 idx++; 954 955 /* 956 * Walk through port outputs until we reach the last valid mediatek-drm component. 957 * To be valid, this must end with an "invalid" component that is a display node. 958 */ 959 do { 960 prev = next; 961 ret = mtk_drm_of_get_ddp_ep_cid(next, 1, cpath, &next, &temp_path[idx]); 962 of_node_put(prev); 963 if (ret) { 964 of_node_put(next); 965 break; 966 } 967 968 /* 969 * If this is an OVL adaptor exclusive component and one of those 970 * was already added, don't add another instance of the generic 971 * DDP_COMPONENT_OVL_ADAPTOR, as this is used only to decide whether 972 * to probe that component master driver of which only one instance 973 * is needed and possible. 974 */ 975 if (temp_path[idx] == DDP_COMPONENT_DRM_OVL_ADAPTOR) { 976 if (!ovl_adaptor_comp_added) 977 ovl_adaptor_comp_added = true; 978 else 979 idx--; 980 } 981 } while (++idx < DDP_COMPONENT_DRM_ID_MAX); 982 983 /* 984 * The device component might not be enabled: in that case, don't 985 * check the last entry and just report that the device is missing. 986 */ 987 if (ret == -ENODEV) 988 return ret; 989 990 /* If the last entry is not a final display output, the configuration is wrong */ 991 switch (temp_path[idx - 1]) { 992 case DDP_COMPONENT_DP_INTF0: 993 case DDP_COMPONENT_DP_INTF1: 994 case DDP_COMPONENT_DPI0: 995 case DDP_COMPONENT_DPI1: 996 case DDP_COMPONENT_DSI0: 997 case DDP_COMPONENT_DSI1: 998 case DDP_COMPONENT_DSI2: 999 case DDP_COMPONENT_DSI3: 1000 break; 1001 default: 1002 dev_err(dev, "Invalid display hw pipeline. Last component: %d (ret=%d)\n", 1003 temp_path[idx - 1], ret); 1004 return -EINVAL; 1005 } 1006 1007 final_ddp_path = devm_kmemdup(dev, temp_path, idx * sizeof(temp_path[0]), GFP_KERNEL); 1008 if (!final_ddp_path) 1009 return -ENOMEM; 1010 1011 dev_dbg(dev, "Display HW Pipeline built with %d components.\n", idx); 1012 1013 /* Pipeline built! */ 1014 *out_path = final_ddp_path; 1015 *out_path_len = idx; 1016 1017 return 0; 1018 } 1019 1020 static int mtk_drm_of_ddp_path_build(struct device *dev, struct device_node *node, 1021 struct mtk_mmsys_driver_data *data) 1022 { 1023 struct device_node *ep_node; 1024 struct of_endpoint of_ep; 1025 bool output_present[MAX_CRTC] = { false }; 1026 int ret; 1027 1028 for_each_endpoint_of_node(node, ep_node) { 1029 ret = of_graph_parse_endpoint(ep_node, &of_ep); 1030 if (ret) { 1031 dev_err_probe(dev, ret, "Cannot parse endpoint\n"); 1032 break; 1033 } 1034 1035 if (of_ep.id >= MAX_CRTC) { 1036 ret = dev_err_probe(dev, -EINVAL, 1037 "Invalid endpoint%u number\n", of_ep.port); 1038 break; 1039 } 1040 1041 output_present[of_ep.id] = true; 1042 } 1043 1044 if (ret) { 1045 of_node_put(ep_node); 1046 return ret; 1047 } 1048 1049 if (output_present[CRTC_MAIN]) { 1050 ret = mtk_drm_of_ddp_path_build_one(dev, CRTC_MAIN, 1051 &data->main_path, &data->main_len); 1052 if (ret && ret != -ENODEV) 1053 return ret; 1054 } 1055 1056 if (output_present[CRTC_EXT]) { 1057 ret = mtk_drm_of_ddp_path_build_one(dev, CRTC_EXT, 1058 &data->ext_path, &data->ext_len); 1059 if (ret && ret != -ENODEV) 1060 return ret; 1061 } 1062 1063 if (output_present[CRTC_THIRD]) { 1064 ret = mtk_drm_of_ddp_path_build_one(dev, CRTC_THIRD, 1065 &data->third_path, &data->third_len); 1066 if (ret && ret != -ENODEV) 1067 return ret; 1068 } 1069 1070 return 0; 1071 } 1072 1073 static int mtk_drm_probe(struct platform_device *pdev) 1074 { 1075 struct device *dev = &pdev->dev; 1076 struct device_node *phandle = dev->parent->of_node; 1077 const struct of_device_id *of_id; 1078 struct mtk_drm_private *private; 1079 struct mtk_mmsys_driver_data *mtk_drm_data; 1080 struct device_node *node; 1081 struct component_match *match = NULL; 1082 struct platform_device *ovl_adaptor; 1083 int ret; 1084 int i; 1085 1086 private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); 1087 if (!private) 1088 return -ENOMEM; 1089 1090 private->mmsys_dev = dev->parent; 1091 if (!private->mmsys_dev) { 1092 dev_err(dev, "Failed to get MMSYS device\n"); 1093 return -ENODEV; 1094 } 1095 1096 of_id = of_match_node(mtk_drm_of_ids, phandle); 1097 if (!of_id) 1098 return -ENODEV; 1099 1100 mtk_drm_data = (struct mtk_mmsys_driver_data *)of_id->data; 1101 if (!mtk_drm_data) 1102 return -EINVAL; 1103 1104 /* Try to build the display pipeline from devicetree graphs */ 1105 if (of_graph_is_present(phandle)) { 1106 dev_dbg(dev, "Building display pipeline for MMSYS %u\n", 1107 mtk_drm_data->mmsys_id); 1108 private->data = devm_kmemdup(dev, mtk_drm_data, 1109 sizeof(*mtk_drm_data), GFP_KERNEL); 1110 if (!private->data) 1111 return -ENOMEM; 1112 1113 ret = mtk_drm_of_ddp_path_build(dev, phandle, private->data); 1114 if (ret) 1115 return ret; 1116 } else { 1117 /* No devicetree graphs support: go with hardcoded paths if present */ 1118 dev_dbg(dev, "Using hardcoded paths for MMSYS %u\n", mtk_drm_data->mmsys_id); 1119 private->data = mtk_drm_data; 1120 } 1121 1122 private->all_drm_private = devm_kmalloc_array(dev, private->data->mmsys_dev_num, 1123 sizeof(*private->all_drm_private), 1124 GFP_KERNEL); 1125 if (!private->all_drm_private) 1126 return -ENOMEM; 1127 1128 /* Bringup ovl_adaptor */ 1129 if (mtk_drm_find_mmsys_comp(private, DDP_COMPONENT_DRM_OVL_ADAPTOR)) { 1130 ovl_adaptor = platform_device_register_data(dev, "mediatek-disp-ovl-adaptor", 1131 PLATFORM_DEVID_AUTO, 1132 (void *)private->mmsys_dev, 1133 sizeof(*private->mmsys_dev)); 1134 private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR].dev = &ovl_adaptor->dev; 1135 mtk_ddp_comp_init(NULL, &private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR], 1136 DDP_COMPONENT_DRM_OVL_ADAPTOR); 1137 component_match_add(dev, &match, compare_dev, &ovl_adaptor->dev); 1138 } 1139 1140 /* Iterate over sibling DISP function blocks */ 1141 for_each_child_of_node(phandle->parent, node) { 1142 enum mtk_ddp_comp_type comp_type; 1143 int comp_id; 1144 1145 ret = mtk_drm_of_get_ddp_comp_type(node, &comp_type); 1146 if (ret) 1147 continue; 1148 1149 if (!of_device_is_available(node)) { 1150 dev_dbg(dev, "Skipping disabled component %pOF\n", 1151 node); 1152 continue; 1153 } 1154 1155 if (comp_type == MTK_DISP_MUTEX) { 1156 int id; 1157 1158 id = of_alias_get_id(node, "mutex"); 1159 if (id < 0 || id == private->data->mmsys_id) { 1160 private->mutex_node = of_node_get(node); 1161 dev_dbg(dev, "get mutex for mmsys %d", private->data->mmsys_id); 1162 } 1163 continue; 1164 } 1165 1166 comp_id = mtk_ddp_comp_get_id(node, comp_type); 1167 if (comp_id < 0) { 1168 dev_warn(dev, "Skipping unknown component %pOF\n", 1169 node); 1170 continue; 1171 } 1172 1173 if (!mtk_drm_find_mmsys_comp(private, comp_id)) 1174 continue; 1175 1176 private->comp_node[comp_id] = of_node_get(node); 1177 1178 /* 1179 * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI 1180 * blocks have separate component platform drivers and initialize their own 1181 * DDP component structure. The others are initialized here. 1182 */ 1183 if (comp_type == MTK_DISP_AAL || 1184 comp_type == MTK_DISP_CCORR || 1185 comp_type == MTK_DISP_COLOR || 1186 comp_type == MTK_DISP_GAMMA || 1187 comp_type == MTK_DISP_MERGE || 1188 comp_type == MTK_DISP_OVL || 1189 comp_type == MTK_DISP_OVL_2L || 1190 comp_type == MTK_DISP_OVL_ADAPTOR || 1191 comp_type == MTK_DISP_RDMA || 1192 comp_type == MTK_DP_INTF || 1193 comp_type == MTK_DPI || 1194 comp_type == MTK_DSI) { 1195 dev_info(dev, "Adding component match for %pOF\n", 1196 node); 1197 drm_of_component_match_add(dev, &match, component_compare_of, 1198 node); 1199 } 1200 1201 ret = mtk_ddp_comp_init(node, &private->ddp_comp[comp_id], comp_id); 1202 if (ret) { 1203 of_node_put(node); 1204 goto err_node; 1205 } 1206 } 1207 1208 if (!private->mutex_node) { 1209 dev_err(dev, "Failed to find disp-mutex node\n"); 1210 ret = -ENODEV; 1211 goto err_node; 1212 } 1213 1214 pm_runtime_enable(dev); 1215 1216 platform_set_drvdata(pdev, private); 1217 1218 ret = component_master_add_with_match(dev, &mtk_drm_ops, match); 1219 if (ret) 1220 goto err_pm; 1221 1222 return 0; 1223 1224 err_pm: 1225 pm_runtime_disable(dev); 1226 err_node: 1227 of_node_put(private->mutex_node); 1228 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++) 1229 of_node_put(private->comp_node[i]); 1230 return ret; 1231 } 1232 1233 static void mtk_drm_remove(struct platform_device *pdev) 1234 { 1235 struct mtk_drm_private *private = platform_get_drvdata(pdev); 1236 int i; 1237 1238 component_master_del(&pdev->dev, &mtk_drm_ops); 1239 pm_runtime_disable(&pdev->dev); 1240 of_node_put(private->mutex_node); 1241 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++) 1242 of_node_put(private->comp_node[i]); 1243 } 1244 1245 static void mtk_drm_shutdown(struct platform_device *pdev) 1246 { 1247 struct mtk_drm_private *private = platform_get_drvdata(pdev); 1248 1249 drm_atomic_helper_shutdown(private->drm); 1250 } 1251 1252 static int mtk_drm_sys_prepare(struct device *dev) 1253 { 1254 struct mtk_drm_private *private = dev_get_drvdata(dev); 1255 struct drm_device *drm = private->drm; 1256 1257 if (private->drm_master) 1258 return drm_mode_config_helper_suspend(drm); 1259 else 1260 return 0; 1261 } 1262 1263 static void mtk_drm_sys_complete(struct device *dev) 1264 { 1265 struct mtk_drm_private *private = dev_get_drvdata(dev); 1266 struct drm_device *drm = private->drm; 1267 int ret = 0; 1268 1269 if (private->drm_master) 1270 ret = drm_mode_config_helper_resume(drm); 1271 if (ret) 1272 dev_err(dev, "Failed to resume\n"); 1273 } 1274 1275 static const struct dev_pm_ops mtk_drm_pm_ops = { 1276 .prepare = mtk_drm_sys_prepare, 1277 .complete = mtk_drm_sys_complete, 1278 }; 1279 1280 static struct platform_driver mtk_drm_platform_driver = { 1281 .probe = mtk_drm_probe, 1282 .remove = mtk_drm_remove, 1283 .shutdown = mtk_drm_shutdown, 1284 .driver = { 1285 .name = "mediatek-drm", 1286 .pm = &mtk_drm_pm_ops, 1287 }, 1288 }; 1289 1290 static struct platform_driver * const mtk_drm_drivers[] = { 1291 &mtk_disp_aal_driver, 1292 &mtk_disp_ccorr_driver, 1293 &mtk_disp_color_driver, 1294 &mtk_disp_gamma_driver, 1295 &mtk_disp_merge_driver, 1296 &mtk_disp_ovl_adaptor_driver, 1297 &mtk_disp_ovl_driver, 1298 &mtk_disp_rdma_driver, 1299 &mtk_dpi_driver, 1300 &mtk_drm_platform_driver, 1301 &mtk_dsi_driver, 1302 &mtk_ethdr_driver, 1303 &mtk_mdp_rdma_driver, 1304 &mtk_padding_driver, 1305 }; 1306 1307 static int __init mtk_drm_init(void) 1308 { 1309 return platform_register_drivers(mtk_drm_drivers, 1310 ARRAY_SIZE(mtk_drm_drivers)); 1311 } 1312 1313 static void __exit mtk_drm_exit(void) 1314 { 1315 platform_unregister_drivers(mtk_drm_drivers, 1316 ARRAY_SIZE(mtk_drm_drivers)); 1317 } 1318 1319 module_init(mtk_drm_init); 1320 module_exit(mtk_drm_exit); 1321 1322 MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>"); 1323 MODULE_DESCRIPTION("Mediatek SoC DRM driver"); 1324 MODULE_LICENSE("GPL v2"); 1325