1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * Zhiyuan Lv <zhiyuan.lv@intel.com> 27 * 28 * Contributors: 29 * Min He <min.he@intel.com> 30 * Tina Zhang <tina.zhang@intel.com> 31 * Pei Zhang <pei.zhang@intel.com> 32 * Niu Bing <bing.niu@intel.com> 33 * Ping Gao <ping.a.gao@intel.com> 34 * Zhi Wang <zhi.a.wang@intel.com> 35 * 36 37 */ 38 39 #include <drm/display/drm_dp.h> 40 41 #include "i915_drv.h" 42 #include "i915_reg.h" 43 #include "gvt.h" 44 #include "i915_pvinfo.h" 45 #include "intel_mchbar_regs.h" 46 #include "display/bxt_dpio_phy_regs.h" 47 #include "display/i9xx_plane_regs.h" 48 #include "display/intel_crt_regs.h" 49 #include "display/intel_cursor_regs.h" 50 #include "display/intel_display_types.h" 51 #include "display/intel_dmc_regs.h" 52 #include "display/intel_dp_aux_regs.h" 53 #include "display/intel_dpio_phy.h" 54 #include "display/intel_fbc.h" 55 #include "display/intel_fdi_regs.h" 56 #include "display/intel_pps_regs.h" 57 #include "display/intel_psr_regs.h" 58 #include "display/intel_sprite_regs.h" 59 #include "display/intel_vga_regs.h" 60 #include "display/skl_universal_plane_regs.h" 61 #include "display/skl_watermark_regs.h" 62 #include "display/vlv_dsi_pll_regs.h" 63 #include "gt/intel_gt_regs.h" 64 #include <linux/vmalloc.h> 65 66 /* XXX FIXME i915 has changed PP_XXX definition */ 67 #define PCH_PP_STATUS _MMIO(0xc7200) 68 #define PCH_PP_CONTROL _MMIO(0xc7204) 69 #define PCH_PP_ON_DELAYS _MMIO(0xc7208) 70 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) 71 #define PCH_PP_DIVISOR _MMIO(0xc7210) 72 73 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) 74 { 75 struct drm_i915_private *i915 = gvt->gt->i915; 76 77 if (IS_BROADWELL(i915)) 78 return D_BDW; 79 else if (IS_SKYLAKE(i915)) 80 return D_SKL; 81 else if (IS_KABYLAKE(i915)) 82 return D_KBL; 83 else if (IS_BROXTON(i915)) 84 return D_BXT; 85 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 86 return D_CFL; 87 88 return 0; 89 } 90 91 static bool intel_gvt_match_device(struct intel_gvt *gvt, 92 unsigned long device) 93 { 94 return intel_gvt_get_device_type(gvt) & device; 95 } 96 97 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset, 98 void *p_data, unsigned int bytes) 99 { 100 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 101 } 102 103 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset, 104 void *p_data, unsigned int bytes) 105 { 106 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); 107 } 108 109 struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt, 110 unsigned int offset) 111 { 112 struct intel_gvt_mmio_info *e; 113 114 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { 115 if (e->offset == offset) 116 return e; 117 } 118 return NULL; 119 } 120 121 static int setup_mmio_info(struct intel_gvt *gvt, u32 offset, u32 size, 122 u16 flags, u32 addr_mask, u32 ro_mask, u32 device, 123 gvt_mmio_func read, gvt_mmio_func write) 124 { 125 struct intel_gvt_mmio_info *p; 126 u32 start, end, i; 127 128 if (!intel_gvt_match_device(gvt, device)) 129 return 0; 130 131 if (WARN_ON(!IS_ALIGNED(offset, 4))) 132 return -EINVAL; 133 134 start = offset; 135 end = offset + size; 136 137 for (i = start; i < end; i += 4) { 138 p = intel_gvt_find_mmio_info(gvt, i); 139 if (!p) { 140 WARN(1, "assign a handler to a non-tracked mmio %x\n", 141 i); 142 return -ENODEV; 143 } 144 p->ro_mask = ro_mask; 145 gvt->mmio.mmio_attribute[i / 4] = flags; 146 if (read) 147 p->read = read; 148 if (write) 149 p->write = write; 150 } 151 return 0; 152 } 153 154 /** 155 * intel_gvt_render_mmio_to_engine - convert a mmio offset into the engine 156 * @gvt: a GVT device 157 * @offset: register offset 158 * 159 * Returns: 160 * The engine containing the offset within its mmio page. 161 */ 162 const struct intel_engine_cs * 163 intel_gvt_render_mmio_to_engine(struct intel_gvt *gvt, unsigned int offset) 164 { 165 struct intel_engine_cs *engine; 166 enum intel_engine_id id; 167 168 offset &= ~GENMASK(11, 0); 169 for_each_engine(engine, gvt->gt, id) 170 if (engine->mmio_base == offset) 171 return engine; 172 173 return NULL; 174 } 175 176 #define offset_to_fence_num(offset) \ 177 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3) 178 179 #define fence_num_to_offset(num) \ 180 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) 181 182 183 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason) 184 { 185 switch (reason) { 186 case GVT_FAILSAFE_UNSUPPORTED_GUEST: 187 pr_err("Detected your guest driver doesn't support GVT-g.\n"); 188 break; 189 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE: 190 pr_err("Graphics resource is not enough for the guest\n"); 191 break; 192 case GVT_FAILSAFE_GUEST_ERR: 193 pr_err("GVT Internal error for the guest\n"); 194 break; 195 default: 196 break; 197 } 198 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id); 199 vgpu->failsafe = true; 200 } 201 202 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, 203 unsigned int fence_num, void *p_data, unsigned int bytes) 204 { 205 unsigned int max_fence = vgpu_fence_sz(vgpu); 206 207 if (fence_num >= max_fence) { 208 gvt_vgpu_err("access oob fence reg %d/%d\n", 209 fence_num, max_fence); 210 211 /* When guest access oob fence regs without access 212 * pv_info first, we treat guest not supporting GVT, 213 * and we will let vgpu enter failsafe mode. 214 */ 215 if (!vgpu->pv_notified) 216 enter_failsafe_mode(vgpu, 217 GVT_FAILSAFE_UNSUPPORTED_GUEST); 218 219 memset(p_data, 0, bytes); 220 return -EINVAL; 221 } 222 return 0; 223 } 224 225 static int gamw_echo_dev_rw_ia_write(struct intel_vgpu *vgpu, 226 unsigned int offset, void *p_data, unsigned int bytes) 227 { 228 u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD; 229 230 if (GRAPHICS_VER(vgpu->gvt->gt->i915) <= 10) { 231 if (ips == GAMW_ECO_ENABLE_64K_IPS_FIELD) 232 gvt_dbg_core("vgpu%d: ips enabled\n", vgpu->id); 233 else if (!ips) 234 gvt_dbg_core("vgpu%d: ips disabled\n", vgpu->id); 235 else { 236 /* All engines must be enabled together for vGPU, 237 * since we don't know which engine the ppgtt will 238 * bind to when shadowing. 239 */ 240 gvt_vgpu_err("Unsupported IPS setting %x, cannot enable 64K gtt.\n", 241 ips); 242 return -EINVAL; 243 } 244 } 245 246 write_vreg(vgpu, offset, p_data, bytes); 247 return 0; 248 } 249 250 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off, 251 void *p_data, unsigned int bytes) 252 { 253 int ret; 254 255 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off), 256 p_data, bytes); 257 if (ret) 258 return ret; 259 read_vreg(vgpu, off, p_data, bytes); 260 return 0; 261 } 262 263 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 264 void *p_data, unsigned int bytes) 265 { 266 struct intel_gvt *gvt = vgpu->gvt; 267 unsigned int fence_num = offset_to_fence_num(off); 268 intel_wakeref_t wakeref; 269 int ret; 270 271 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes); 272 if (ret) 273 return ret; 274 write_vreg(vgpu, off, p_data, bytes); 275 276 wakeref = mmio_hw_access_pre(gvt->gt); 277 intel_vgpu_write_fence(vgpu, fence_num, 278 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num))); 279 mmio_hw_access_post(gvt->gt, wakeref); 280 return 0; 281 } 282 283 #define CALC_MODE_MASK_REG(old, new) \ 284 (((new) & GENMASK(31, 16)) \ 285 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \ 286 | ((new) & ((new) >> 16)))) 287 288 static int mul_force_wake_write(struct intel_vgpu *vgpu, 289 unsigned int offset, void *p_data, unsigned int bytes) 290 { 291 u32 old, new; 292 u32 ack_reg_offset; 293 294 old = vgpu_vreg(vgpu, offset); 295 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data); 296 297 if (GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9) { 298 switch (offset) { 299 case FORCEWAKE_RENDER_GEN9_REG: 300 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG; 301 break; 302 case FORCEWAKE_GT_GEN9_REG: 303 ack_reg_offset = FORCEWAKE_ACK_GT_GEN9_REG; 304 break; 305 case FORCEWAKE_MEDIA_GEN9_REG: 306 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG; 307 break; 308 default: 309 /*should not hit here*/ 310 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset); 311 return -EINVAL; 312 } 313 } else { 314 ack_reg_offset = FORCEWAKE_ACK_HSW_REG; 315 } 316 317 vgpu_vreg(vgpu, offset) = new; 318 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); 319 return 0; 320 } 321 322 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 323 void *p_data, unsigned int bytes) 324 { 325 intel_engine_mask_t engine_mask = 0; 326 u32 data; 327 328 write_vreg(vgpu, offset, p_data, bytes); 329 data = vgpu_vreg(vgpu, offset); 330 331 if (data & GEN6_GRDOM_FULL) { 332 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id); 333 engine_mask = ALL_ENGINES; 334 } else { 335 if (data & GEN6_GRDOM_RENDER) { 336 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id); 337 engine_mask |= BIT(RCS0); 338 } 339 if (data & GEN6_GRDOM_MEDIA) { 340 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id); 341 engine_mask |= BIT(VCS0); 342 } 343 if (data & GEN6_GRDOM_BLT) { 344 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id); 345 engine_mask |= BIT(BCS0); 346 } 347 if (data & GEN6_GRDOM_VECS) { 348 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id); 349 engine_mask |= BIT(VECS0); 350 } 351 if (data & GEN8_GRDOM_MEDIA2) { 352 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id); 353 engine_mask |= BIT(VCS1); 354 } 355 if (data & GEN9_GRDOM_GUC) { 356 gvt_dbg_mmio("vgpu%d: request GUC Reset\n", vgpu->id); 357 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET; 358 } 359 engine_mask &= vgpu->gvt->gt->info.engine_mask; 360 } 361 362 /* vgpu_lock already hold by emulate mmio r/w */ 363 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask); 364 365 /* sw will wait for the device to ack the reset request */ 366 vgpu_vreg(vgpu, offset) = 0; 367 368 return 0; 369 } 370 371 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 372 void *p_data, unsigned int bytes) 373 { 374 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes); 375 } 376 377 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 378 void *p_data, unsigned int bytes) 379 { 380 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes); 381 } 382 383 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu, 384 unsigned int offset, void *p_data, unsigned int bytes) 385 { 386 write_vreg(vgpu, offset, p_data, bytes); 387 388 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { 389 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON; 390 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; 391 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; 392 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; 393 394 } else 395 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= 396 ~(PP_ON | PP_SEQUENCE_POWER_DOWN 397 | PP_CYCLE_DELAY_ACTIVE); 398 return 0; 399 } 400 401 static int transconf_mmio_write(struct intel_vgpu *vgpu, 402 unsigned int offset, void *p_data, unsigned int bytes) 403 { 404 write_vreg(vgpu, offset, p_data, bytes); 405 406 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) 407 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; 408 else 409 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE; 410 return 0; 411 } 412 413 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 414 void *p_data, unsigned int bytes) 415 { 416 write_vreg(vgpu, offset, p_data, bytes); 417 418 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE) 419 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK; 420 else 421 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK; 422 423 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK) 424 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE; 425 else 426 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE; 427 428 return 0; 429 } 430 431 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 432 void *p_data, unsigned int bytes) 433 { 434 switch (offset) { 435 case 0xe651c: 436 case 0xe661c: 437 case 0xe671c: 438 case 0xe681c: 439 vgpu_vreg(vgpu, offset) = 1 << 17; 440 break; 441 case 0xe6c04: 442 vgpu_vreg(vgpu, offset) = 0x3; 443 break; 444 case 0xe6e1c: 445 vgpu_vreg(vgpu, offset) = 0x2f << 16; 446 break; 447 default: 448 return -EINVAL; 449 } 450 451 read_vreg(vgpu, offset, p_data, bytes); 452 return 0; 453 } 454 455 /* 456 * Only PIPE_A is enabled in current vGPU display and PIPE_A is tied to 457 * TRANSCODER_A in HW. DDI/PORT could be PORT_x depends on 458 * setup_virtual_dp_monitor(). 459 * emulate_monitor_status_change() set up PLL for PORT_x as the initial enabled 460 * DPLL. Later guest driver may setup a different DPLLx when setting mode. 461 * So the correct sequence to find DP stream clock is: 462 * Check TRANS_DDI_FUNC_CTL on TRANSCODER_A to get PORT_x. 463 * Check correct PLLx for PORT_x to get PLL frequency and DP bitrate. 464 * Then Refresh rate then can be calculated based on follow equations: 465 * Pixel clock = h_total * v_total * refresh_rate 466 * stream clock = Pixel clock 467 * ls_clk = DP bitrate 468 * Link M/N = strm_clk / ls_clk 469 */ 470 471 static u32 bdw_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) 472 { 473 u32 dp_br = 0; 474 u32 ddi_pll_sel = vgpu_vreg_t(vgpu, PORT_CLK_SEL(port)); 475 476 switch (ddi_pll_sel) { 477 case PORT_CLK_SEL_LCPLL_2700: 478 dp_br = 270000 * 2; 479 break; 480 case PORT_CLK_SEL_LCPLL_1350: 481 dp_br = 135000 * 2; 482 break; 483 case PORT_CLK_SEL_LCPLL_810: 484 dp_br = 81000 * 2; 485 break; 486 case PORT_CLK_SEL_SPLL: 487 { 488 switch (vgpu_vreg_t(vgpu, SPLL_CTL) & SPLL_FREQ_MASK) { 489 case SPLL_FREQ_810MHz: 490 dp_br = 81000 * 2; 491 break; 492 case SPLL_FREQ_1350MHz: 493 dp_br = 135000 * 2; 494 break; 495 case SPLL_FREQ_2700MHz: 496 dp_br = 270000 * 2; 497 break; 498 default: 499 gvt_dbg_dpy("vgpu-%d PORT_%c can't get freq from SPLL 0x%08x\n", 500 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, SPLL_CTL)); 501 break; 502 } 503 break; 504 } 505 case PORT_CLK_SEL_WRPLL1: 506 case PORT_CLK_SEL_WRPLL2: 507 { 508 u32 wrpll_ctl; 509 int refclk, n, p, r; 510 511 if (ddi_pll_sel == PORT_CLK_SEL_WRPLL1) 512 wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL1)); 513 else 514 wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL2)); 515 516 switch (wrpll_ctl & WRPLL_REF_MASK) { 517 case WRPLL_REF_PCH_SSC: 518 refclk = 135000; 519 break; 520 case WRPLL_REF_LCPLL: 521 refclk = 2700000; 522 break; 523 default: 524 gvt_dbg_dpy("vgpu-%d PORT_%c WRPLL can't get refclk 0x%08x\n", 525 vgpu->id, port_name(port), wrpll_ctl); 526 goto out; 527 } 528 529 r = wrpll_ctl & WRPLL_DIVIDER_REF_MASK; 530 p = (wrpll_ctl & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; 531 n = (wrpll_ctl & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; 532 533 dp_br = (refclk * n / 10) / (p * r) * 2; 534 break; 535 } 536 default: 537 gvt_dbg_dpy("vgpu-%d PORT_%c has invalid clock select 0x%08x\n", 538 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, PORT_CLK_SEL(port))); 539 break; 540 } 541 542 out: 543 return dp_br; 544 } 545 546 static u32 bxt_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) 547 { 548 u32 dp_br = 0; 549 int refclk = 100000; 550 enum dpio_phy phy = DPIO_PHY0; 551 enum dpio_channel ch = DPIO_CH0; 552 struct dpll clock = {}; 553 u32 temp; 554 555 /* Port to PHY mapping is fixed, see bxt_ddi_phy_info{} */ 556 switch (port) { 557 case PORT_A: 558 phy = DPIO_PHY1; 559 ch = DPIO_CH0; 560 break; 561 case PORT_B: 562 phy = DPIO_PHY0; 563 ch = DPIO_CH0; 564 break; 565 case PORT_C: 566 phy = DPIO_PHY0; 567 ch = DPIO_CH1; 568 break; 569 default: 570 gvt_dbg_dpy("vgpu-%d no PHY for PORT_%c\n", vgpu->id, port_name(port)); 571 goto out; 572 } 573 574 temp = vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)); 575 if (!(temp & PORT_PLL_ENABLE) || !(temp & PORT_PLL_LOCK)) { 576 gvt_dbg_dpy("vgpu-%d PORT_%c PLL_ENABLE 0x%08x isn't enabled or locked\n", 577 vgpu->id, port_name(port), temp); 578 goto out; 579 } 580 581 clock.m1 = 2; 582 clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, 583 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 0))) << 22; 584 if (vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 3)) & PORT_PLL_M2_FRAC_ENABLE) 585 clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK, 586 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 2))); 587 clock.n = REG_FIELD_GET(PORT_PLL_N_MASK, 588 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 1))); 589 clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, 590 vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch))); 591 clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, 592 vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch))); 593 clock.m = clock.m1 * clock.m2; 594 clock.p = clock.p1 * clock.p2 * 5; 595 596 if (clock.n == 0 || clock.p == 0) { 597 gvt_dbg_dpy("vgpu-%d PORT_%c PLL has invalid divider\n", vgpu->id, port_name(port)); 598 goto out; 599 } 600 601 clock.vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock.m), clock.n << 22); 602 clock.dot = DIV_ROUND_CLOSEST(clock.vco, clock.p); 603 604 dp_br = clock.dot; 605 606 out: 607 return dp_br; 608 } 609 610 static u32 skl_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) 611 { 612 u32 dp_br = 0; 613 enum intel_dpll_id dpll_id = DPLL_ID_SKL_DPLL0; 614 615 /* Find the enabled DPLL for the DDI/PORT */ 616 if (!(vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)) && 617 (vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_SEL_OVERRIDE(port))) { 618 dpll_id += (vgpu_vreg_t(vgpu, DPLL_CTRL2) & 619 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 620 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 621 } else { 622 gvt_dbg_dpy("vgpu-%d DPLL for PORT_%c isn't turned on\n", 623 vgpu->id, port_name(port)); 624 return dp_br; 625 } 626 627 /* Find PLL output frequency from correct DPLL, and get bir rate */ 628 switch ((vgpu_vreg_t(vgpu, DPLL_CTRL1) & 629 DPLL_CTRL1_LINK_RATE_MASK(dpll_id)) >> 630 DPLL_CTRL1_LINK_RATE_SHIFT(dpll_id)) { 631 case DPLL_CTRL1_LINK_RATE_810: 632 dp_br = 81000 * 2; 633 break; 634 case DPLL_CTRL1_LINK_RATE_1080: 635 dp_br = 108000 * 2; 636 break; 637 case DPLL_CTRL1_LINK_RATE_1350: 638 dp_br = 135000 * 2; 639 break; 640 case DPLL_CTRL1_LINK_RATE_1620: 641 dp_br = 162000 * 2; 642 break; 643 case DPLL_CTRL1_LINK_RATE_2160: 644 dp_br = 216000 * 2; 645 break; 646 case DPLL_CTRL1_LINK_RATE_2700: 647 dp_br = 270000 * 2; 648 break; 649 default: 650 dp_br = 0; 651 gvt_dbg_dpy("vgpu-%d PORT_%c fail to get DPLL-%d freq\n", 652 vgpu->id, port_name(port), dpll_id); 653 } 654 655 return dp_br; 656 } 657 658 static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu) 659 { 660 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 661 struct intel_display *display = &dev_priv->display; 662 enum port port; 663 u32 dp_br, link_m, link_n, htotal, vtotal; 664 665 /* Find DDI/PORT assigned to TRANSCODER_A, expect B or D */ 666 port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) & 667 TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; 668 if (port != PORT_B && port != PORT_D) { 669 gvt_dbg_dpy("vgpu-%d unsupported PORT_%c\n", vgpu->id, port_name(port)); 670 return; 671 } 672 673 /* Calculate DP bitrate from PLL */ 674 if (IS_BROADWELL(dev_priv)) 675 dp_br = bdw_vgpu_get_dp_bitrate(vgpu, port); 676 else if (IS_BROXTON(dev_priv)) 677 dp_br = bxt_vgpu_get_dp_bitrate(vgpu, port); 678 else 679 dp_br = skl_vgpu_get_dp_bitrate(vgpu, port); 680 681 /* Get DP link symbol clock M/N */ 682 link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)); 683 link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)); 684 685 /* Get H/V total from transcoder timing */ 686 htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(display, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT); 687 vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(display, TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT); 688 689 if (dp_br && link_n && htotal && vtotal) { 690 u64 pixel_clk = 0; 691 u32 new_rate = 0; 692 u32 *old_rate = &(intel_vgpu_port(vgpu, vgpu->display.port_num)->vrefresh_k); 693 694 /* Calculate pixel clock by (ls_clk * M / N) */ 695 pixel_clk = div_u64(mul_u32_u32(link_m, dp_br), link_n); 696 pixel_clk *= MSEC_PER_SEC; 697 698 /* Calculate refresh rate by (pixel_clk / (h_total * v_total)) */ 699 new_rate = DIV64_U64_ROUND_CLOSEST(mul_u64_u32_shr(pixel_clk, MSEC_PER_SEC, 0), mul_u32_u32(htotal + 1, vtotal + 1)); 700 701 if (*old_rate != new_rate) 702 *old_rate = new_rate; 703 704 gvt_dbg_dpy("vgpu-%d PIPE_%c refresh rate updated to %d\n", 705 vgpu->id, pipe_name(PIPE_A), new_rate); 706 } 707 } 708 709 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 710 void *p_data, unsigned int bytes) 711 { 712 u32 data; 713 714 write_vreg(vgpu, offset, p_data, bytes); 715 data = vgpu_vreg(vgpu, offset); 716 717 if (data & TRANSCONF_ENABLE) { 718 vgpu_vreg(vgpu, offset) |= TRANSCONF_STATE_ENABLE; 719 vgpu_update_refresh_rate(vgpu); 720 vgpu_update_vblank_emulation(vgpu, true); 721 } else { 722 vgpu_vreg(vgpu, offset) &= ~TRANSCONF_STATE_ENABLE; 723 vgpu_update_vblank_emulation(vgpu, false); 724 } 725 return 0; 726 } 727 728 /* sorted in ascending order */ 729 static i915_reg_t force_nonpriv_white_list[] = { 730 _MMIO(0xd80), 731 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec) 732 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248) 733 CL_PRIMITIVES_COUNT, //_MMIO(0x2340) 734 PS_INVOCATION_COUNT, //_MMIO(0x2348) 735 PS_DEPTH_COUNT, //_MMIO(0x2350) 736 GEN8_CS_CHICKEN1,//_MMIO(0x2580) 737 _MMIO(0x2690), 738 _MMIO(0x2694), 739 _MMIO(0x2698), 740 _MMIO(0x2754), 741 _MMIO(0x28a0), 742 _MMIO(0x4de0), 743 _MMIO(0x4de4), 744 _MMIO(0x4dfc), 745 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010) 746 _MMIO(0x7014), 747 HDC_CHICKEN0,//_MMIO(0x7300) 748 GEN8_HDC_CHICKEN1,//_MMIO(0x7304) 749 _MMIO(0x7700), 750 _MMIO(0x7704), 751 _MMIO(0x7708), 752 _MMIO(0x770c), 753 _MMIO(0x83a8), 754 _MMIO(0xb110), 755 _MMIO(0xb118), 756 _MMIO(0xe100), 757 _MMIO(0xe18c), 758 _MMIO(0xe48c), 759 _MMIO(0xe5f4), 760 _MMIO(0x64844), 761 }; 762 763 /* a simple bsearch */ 764 static inline bool in_whitelist(u32 reg) 765 { 766 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list); 767 i915_reg_t *array = force_nonpriv_white_list; 768 769 while (left < right) { 770 int mid = (left + right)/2; 771 772 if (reg > array[mid].reg) 773 left = mid + 1; 774 else if (reg < array[mid].reg) 775 right = mid; 776 else 777 return true; 778 } 779 return false; 780 } 781 782 static int force_nonpriv_write(struct intel_vgpu *vgpu, 783 unsigned int offset, void *p_data, unsigned int bytes) 784 { 785 u32 reg_nonpriv = (*(u32 *)p_data) & REG_GENMASK(25, 2); 786 const struct intel_engine_cs *engine = 787 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 788 789 if (bytes != 4 || !IS_ALIGNED(offset, bytes) || !engine) { 790 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n", 791 vgpu->id, offset, bytes); 792 return -EINVAL; 793 } 794 795 if (!in_whitelist(reg_nonpriv) && 796 reg_nonpriv != i915_mmio_reg_offset(RING_NOPID(engine->mmio_base))) { 797 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n", 798 vgpu->id, reg_nonpriv, offset); 799 } else 800 intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 801 802 return 0; 803 } 804 805 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 806 void *p_data, unsigned int bytes) 807 { 808 write_vreg(vgpu, offset, p_data, bytes); 809 810 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { 811 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE; 812 } else { 813 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; 814 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) 815 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) 816 &= ~DP_TP_STATUS_AUTOTRAIN_DONE; 817 } 818 return 0; 819 } 820 821 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu, 822 unsigned int offset, void *p_data, unsigned int bytes) 823 { 824 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data; 825 return 0; 826 } 827 828 #define FDI_LINK_TRAIN_PATTERN1 0 829 #define FDI_LINK_TRAIN_PATTERN2 1 830 831 static int fdi_auto_training_started(struct intel_vgpu *vgpu) 832 { 833 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E)); 834 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); 835 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E)); 836 837 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) && 838 (rx_ctl & FDI_RX_ENABLE) && 839 (rx_ctl & FDI_AUTO_TRAINING) && 840 (tx_ctl & DP_TP_CTL_ENABLE) && 841 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN)) 842 return 1; 843 else 844 return 0; 845 } 846 847 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, 848 enum pipe pipe, unsigned int train_pattern) 849 { 850 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl; 851 unsigned int fdi_rx_check_bits, fdi_tx_check_bits; 852 unsigned int fdi_rx_train_bits, fdi_tx_train_bits; 853 unsigned int fdi_iir_check_bits; 854 855 fdi_rx_imr = FDI_RX_IMR(pipe); 856 fdi_tx_ctl = FDI_TX_CTL(pipe); 857 fdi_rx_ctl = FDI_RX_CTL(pipe); 858 859 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) { 860 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT; 861 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1; 862 fdi_iir_check_bits = FDI_RX_BIT_LOCK; 863 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) { 864 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT; 865 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2; 866 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK; 867 } else { 868 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern); 869 return -EINVAL; 870 } 871 872 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits; 873 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits; 874 875 /* If imr bit has been masked */ 876 if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits) 877 return 0; 878 879 if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits) 880 == fdi_tx_check_bits) 881 && ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits) 882 == fdi_rx_check_bits)) 883 return 1; 884 else 885 return 0; 886 } 887 888 #define INVALID_INDEX (~0U) 889 890 static unsigned int calc_index(unsigned int offset, i915_reg_t _start, 891 i915_reg_t _next, i915_reg_t _end) 892 { 893 u32 start = i915_mmio_reg_offset(_start); 894 u32 next = i915_mmio_reg_offset(_next); 895 u32 end = i915_mmio_reg_offset(_end); 896 u32 stride = next - start; 897 898 if (offset < start || offset > end) 899 return INVALID_INDEX; 900 offset -= start; 901 return offset / stride; 902 } 903 904 #define FDI_RX_CTL_TO_PIPE(offset) \ 905 calc_index(offset, FDI_RX_CTL(PIPE_A), FDI_RX_CTL(PIPE_B), FDI_RX_CTL(PIPE_C)) 906 907 #define FDI_TX_CTL_TO_PIPE(offset) \ 908 calc_index(offset, FDI_TX_CTL(PIPE_A), FDI_TX_CTL(PIPE_B), FDI_TX_CTL(PIPE_C)) 909 910 #define FDI_RX_IMR_TO_PIPE(offset) \ 911 calc_index(offset, FDI_RX_IMR(PIPE_A), FDI_RX_IMR(PIPE_B), FDI_RX_IMR(PIPE_C)) 912 913 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, 914 unsigned int offset, void *p_data, unsigned int bytes) 915 { 916 i915_reg_t fdi_rx_iir; 917 unsigned int index; 918 int ret; 919 920 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX) 921 index = FDI_RX_CTL_TO_PIPE(offset); 922 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX) 923 index = FDI_TX_CTL_TO_PIPE(offset); 924 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX) 925 index = FDI_RX_IMR_TO_PIPE(offset); 926 else { 927 gvt_vgpu_err("Unsupported registers %x\n", offset); 928 return -EINVAL; 929 } 930 931 write_vreg(vgpu, offset, p_data, bytes); 932 933 fdi_rx_iir = FDI_RX_IIR(index); 934 935 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1); 936 if (ret < 0) 937 return ret; 938 if (ret) 939 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK; 940 941 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2); 942 if (ret < 0) 943 return ret; 944 if (ret) 945 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK; 946 947 if (offset == _FDI_RXA_CTL) 948 if (fdi_auto_training_started(vgpu)) 949 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |= 950 DP_TP_STATUS_AUTOTRAIN_DONE; 951 return 0; 952 } 953 954 #define DP_TP_CTL_TO_PORT(offset) \ 955 calc_index(offset, DP_TP_CTL(PORT_A), DP_TP_CTL(PORT_B), DP_TP_CTL(PORT_E)) 956 957 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 958 void *p_data, unsigned int bytes) 959 { 960 i915_reg_t status_reg; 961 unsigned int index; 962 u32 data; 963 964 write_vreg(vgpu, offset, p_data, bytes); 965 966 index = DP_TP_CTL_TO_PORT(offset); 967 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8; 968 if (data == 0x2) { 969 status_reg = DP_TP_STATUS(index); 970 vgpu_vreg_t(vgpu, status_reg) |= (1 << 25); 971 } 972 return 0; 973 } 974 975 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu, 976 unsigned int offset, void *p_data, unsigned int bytes) 977 { 978 u32 reg_val; 979 u32 sticky_mask; 980 981 reg_val = *((u32 *)p_data); 982 sticky_mask = GENMASK(27, 26) | (1 << 24); 983 984 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) | 985 (vgpu_vreg(vgpu, offset) & sticky_mask); 986 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask); 987 return 0; 988 } 989 990 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu, 991 unsigned int offset, void *p_data, unsigned int bytes) 992 { 993 u32 data; 994 995 write_vreg(vgpu, offset, p_data, bytes); 996 data = vgpu_vreg(vgpu, offset); 997 998 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) 999 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 1000 return 0; 1001 } 1002 1003 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, 1004 unsigned int offset, void *p_data, unsigned int bytes) 1005 { 1006 u32 data; 1007 1008 write_vreg(vgpu, offset, p_data, bytes); 1009 data = vgpu_vreg(vgpu, offset); 1010 1011 if (data & FDI_MPHY_IOSFSB_RESET_CTL) 1012 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS; 1013 else 1014 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS; 1015 return 0; 1016 } 1017 1018 #define DSPSURF_TO_PIPE(display, offset) \ 1019 calc_index(offset, DSPSURF(display, PIPE_A), DSPSURF(display, PIPE_B), DSPSURF(display, PIPE_C)) 1020 1021 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1022 void *p_data, unsigned int bytes) 1023 { 1024 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 1025 struct intel_display *display = &dev_priv->display; 1026 u32 pipe = DSPSURF_TO_PIPE(display, offset); 1027 int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY); 1028 1029 write_vreg(vgpu, offset, p_data, bytes); 1030 vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset); 1031 1032 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, pipe))++; 1033 1034 if (vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) & PLANE_CTL_ASYNC_FLIP) 1035 intel_vgpu_trigger_virtual_event(vgpu, event); 1036 else 1037 set_bit(event, vgpu->irq.flip_done_event[pipe]); 1038 1039 return 0; 1040 } 1041 1042 #define SPRSURF_TO_PIPE(offset) \ 1043 calc_index(offset, SPRSURF(PIPE_A), SPRSURF(PIPE_B), SPRSURF(PIPE_C)) 1044 1045 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1046 void *p_data, unsigned int bytes) 1047 { 1048 u32 pipe = SPRSURF_TO_PIPE(offset); 1049 int event = SKL_FLIP_EVENT(pipe, PLANE_SPRITE0); 1050 1051 write_vreg(vgpu, offset, p_data, bytes); 1052 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 1053 1054 if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP) 1055 intel_vgpu_trigger_virtual_event(vgpu, event); 1056 else 1057 set_bit(event, vgpu->irq.flip_done_event[pipe]); 1058 1059 return 0; 1060 } 1061 1062 static int reg50080_mmio_write(struct intel_vgpu *vgpu, 1063 unsigned int offset, void *p_data, 1064 unsigned int bytes) 1065 { 1066 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 1067 struct intel_display *display = &dev_priv->display; 1068 enum pipe pipe = REG_50080_TO_PIPE(offset); 1069 enum plane_id plane = REG_50080_TO_PLANE(offset); 1070 int event = SKL_FLIP_EVENT(pipe, plane); 1071 1072 write_vreg(vgpu, offset, p_data, bytes); 1073 if (plane == PLANE_PRIMARY) { 1074 vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset); 1075 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, pipe))++; 1076 } else { 1077 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 1078 } 1079 1080 if ((vgpu_vreg(vgpu, offset) & REG50080_FLIP_TYPE_MASK) == REG50080_FLIP_TYPE_ASYNC) 1081 intel_vgpu_trigger_virtual_event(vgpu, event); 1082 else 1083 set_bit(event, vgpu->irq.flip_done_event[pipe]); 1084 1085 return 0; 1086 } 1087 1088 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu, 1089 unsigned int reg) 1090 { 1091 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 1092 enum intel_gvt_event_type event; 1093 1094 if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A))) 1095 event = AUX_CHANNEL_A; 1096 else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_B)) || 1097 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B))) 1098 event = AUX_CHANNEL_B; 1099 else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_C)) || 1100 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C))) 1101 event = AUX_CHANNEL_C; 1102 else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_D)) || 1103 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D))) 1104 event = AUX_CHANNEL_D; 1105 else { 1106 drm_WARN_ON(&dev_priv->drm, true); 1107 return -EINVAL; 1108 } 1109 1110 intel_vgpu_trigger_virtual_event(vgpu, event); 1111 return 0; 1112 } 1113 1114 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value, 1115 unsigned int reg, int len, bool data_valid) 1116 { 1117 /* mark transaction done */ 1118 value |= DP_AUX_CH_CTL_DONE; 1119 value &= ~DP_AUX_CH_CTL_SEND_BUSY; 1120 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR; 1121 1122 if (data_valid) 1123 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR; 1124 else 1125 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR; 1126 1127 /* message size */ 1128 value &= ~(0xf << 20); 1129 value |= (len << 20); 1130 vgpu_vreg(vgpu, reg) = value; 1131 1132 if (value & DP_AUX_CH_CTL_INTERRUPT) 1133 return trigger_aux_channel_interrupt(vgpu, reg); 1134 return 0; 1135 } 1136 1137 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, 1138 u8 t) 1139 { 1140 if ((t & DP_TRAINING_PATTERN_MASK) == DP_TRAINING_PATTERN_1) { 1141 /* training pattern 1 for CR */ 1142 /* set LANE0_CR_DONE, LANE1_CR_DONE */ 1143 dpcd->data[DP_LANE0_1_STATUS] |= DP_LANE_CR_DONE | 1144 DP_LANE_CR_DONE << 4; 1145 /* set LANE2_CR_DONE, LANE3_CR_DONE */ 1146 dpcd->data[DP_LANE2_3_STATUS] |= DP_LANE_CR_DONE | 1147 DP_LANE_CR_DONE << 4; 1148 } else if ((t & DP_TRAINING_PATTERN_MASK) == 1149 DP_TRAINING_PATTERN_2) { 1150 /* training pattern 2 for EQ */ 1151 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */ 1152 dpcd->data[DP_LANE0_1_STATUS] |= DP_LANE_CHANNEL_EQ_DONE | 1153 DP_LANE_CHANNEL_EQ_DONE << 4; 1154 dpcd->data[DP_LANE0_1_STATUS] |= DP_LANE_SYMBOL_LOCKED | 1155 DP_LANE_SYMBOL_LOCKED << 4; 1156 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */ 1157 dpcd->data[DP_LANE2_3_STATUS] |= DP_LANE_CHANNEL_EQ_DONE | 1158 DP_LANE_CHANNEL_EQ_DONE << 4; 1159 dpcd->data[DP_LANE2_3_STATUS] |= DP_LANE_SYMBOL_LOCKED | 1160 DP_LANE_SYMBOL_LOCKED << 4; 1161 /* set INTERLANE_ALIGN_DONE */ 1162 dpcd->data[DP_LANE_ALIGN_STATUS_UPDATED] |= 1163 DP_INTERLANE_ALIGN_DONE; 1164 } else if ((t & DP_TRAINING_PATTERN_MASK) == 1165 DP_TRAINING_PATTERN_DISABLE) { 1166 /* finish link training */ 1167 /* set sink status as synchronized */ 1168 dpcd->data[DP_SINK_STATUS] = DP_RECEIVE_PORT_0_STATUS | 1169 DP_RECEIVE_PORT_1_STATUS; 1170 } 1171 } 1172 1173 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8) 1174 1175 #define dpy_is_valid_port(port) \ 1176 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS)) 1177 1178 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, 1179 unsigned int offset, void *p_data, unsigned int bytes) 1180 { 1181 struct intel_vgpu_display *display = &vgpu->display; 1182 int msg, addr, ctrl, op, len; 1183 int port_index = OFFSET_TO_DP_AUX_PORT(offset); 1184 struct intel_vgpu_dpcd_data *dpcd = NULL; 1185 struct intel_vgpu_port *port = NULL; 1186 u32 data; 1187 1188 if (!dpy_is_valid_port(port_index)) { 1189 gvt_vgpu_err("Unsupported DP port access!\n"); 1190 return 0; 1191 } 1192 1193 write_vreg(vgpu, offset, p_data, bytes); 1194 data = vgpu_vreg(vgpu, offset); 1195 1196 if (GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9 && 1197 offset != i915_mmio_reg_offset(DP_AUX_CH_CTL(port_index))) { 1198 /* SKL DPB/C/D aux ctl register changed */ 1199 return 0; 1200 } else if (IS_BROADWELL(vgpu->gvt->gt->i915) && 1201 offset != i915_mmio_reg_offset(port_index ? 1202 PCH_DP_AUX_CH_CTL(port_index) : 1203 DP_AUX_CH_CTL(port_index))) { 1204 /* write to the data registers */ 1205 return 0; 1206 } 1207 1208 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) { 1209 /* just want to clear the sticky bits */ 1210 vgpu_vreg(vgpu, offset) = 0; 1211 return 0; 1212 } 1213 1214 port = &display->ports[port_index]; 1215 dpcd = port->dpcd; 1216 1217 /* read out message from DATA1 register */ 1218 msg = vgpu_vreg(vgpu, offset + 4); 1219 addr = (msg >> 8) & 0xffff; 1220 ctrl = (msg >> 24) & 0xff; 1221 len = msg & 0xff; 1222 op = ctrl >> 4; 1223 1224 if (op == DP_AUX_NATIVE_WRITE) { 1225 int t; 1226 u8 buf[16]; 1227 1228 if ((addr + len + 1) >= DPCD_SIZE) { 1229 /* 1230 * Write request exceeds what we supported, 1231 * DCPD spec: When a Source Device is writing a DPCD 1232 * address not supported by the Sink Device, the Sink 1233 * Device shall reply with AUX NACK and “M” equal to 1234 * zero. 1235 */ 1236 1237 /* NAK the write */ 1238 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK; 1239 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true); 1240 return 0; 1241 } 1242 1243 /* 1244 * Write request format: Headr (command + address + size) occupies 1245 * 4 bytes, followed by (len + 1) bytes of data. See details at 1246 * intel_dp_aux_transfer(). 1247 */ 1248 if ((len + 1 + 4) > AUX_BURST_SIZE) { 1249 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); 1250 return -EINVAL; 1251 } 1252 1253 /* unpack data from vreg to buf */ 1254 for (t = 0; t < 4; t++) { 1255 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4); 1256 1257 buf[t * 4] = (r >> 24) & 0xff; 1258 buf[t * 4 + 1] = (r >> 16) & 0xff; 1259 buf[t * 4 + 2] = (r >> 8) & 0xff; 1260 buf[t * 4 + 3] = r & 0xff; 1261 } 1262 1263 /* write to virtual DPCD */ 1264 if (dpcd && dpcd->data_valid) { 1265 for (t = 0; t <= len; t++) { 1266 int p = addr + t; 1267 1268 dpcd->data[p] = buf[t]; 1269 /* check for link training */ 1270 if (p == DP_TRAINING_PATTERN_SET) 1271 dp_aux_ch_ctl_link_training(dpcd, 1272 buf[t]); 1273 } 1274 } 1275 1276 /* ACK the write */ 1277 vgpu_vreg(vgpu, offset + 4) = 0; 1278 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1, 1279 dpcd && dpcd->data_valid); 1280 return 0; 1281 } 1282 1283 if (op == DP_AUX_NATIVE_READ) { 1284 int idx, i, ret = 0; 1285 1286 if ((addr + len + 1) >= DPCD_SIZE) { 1287 /* 1288 * read request exceeds what we supported 1289 * DPCD spec: A Sink Device receiving a Native AUX CH 1290 * read request for an unsupported DPCD address must 1291 * reply with an AUX ACK and read data set equal to 1292 * zero instead of replying with AUX NACK. 1293 */ 1294 1295 /* ACK the READ*/ 1296 vgpu_vreg(vgpu, offset + 4) = 0; 1297 vgpu_vreg(vgpu, offset + 8) = 0; 1298 vgpu_vreg(vgpu, offset + 12) = 0; 1299 vgpu_vreg(vgpu, offset + 16) = 0; 1300 vgpu_vreg(vgpu, offset + 20) = 0; 1301 1302 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 1303 true); 1304 return 0; 1305 } 1306 1307 for (idx = 1; idx <= 5; idx++) { 1308 /* clear the data registers */ 1309 vgpu_vreg(vgpu, offset + 4 * idx) = 0; 1310 } 1311 1312 /* 1313 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data. 1314 */ 1315 if ((len + 2) > AUX_BURST_SIZE) { 1316 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); 1317 return -EINVAL; 1318 } 1319 1320 /* read from virtual DPCD to vreg */ 1321 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */ 1322 if (dpcd && dpcd->data_valid) { 1323 for (i = 1; i <= (len + 1); i++) { 1324 int t; 1325 1326 t = dpcd->data[addr + i - 1]; 1327 t <<= (24 - 8 * (i % 4)); 1328 ret |= t; 1329 1330 if ((i % 4 == 3) || (i == (len + 1))) { 1331 vgpu_vreg(vgpu, offset + 1332 (i / 4 + 1) * 4) = ret; 1333 ret = 0; 1334 } 1335 } 1336 } 1337 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 1338 dpcd && dpcd->data_valid); 1339 return 0; 1340 } 1341 1342 /* i2c transaction starts */ 1343 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data); 1344 1345 if (data & DP_AUX_CH_CTL_INTERRUPT) 1346 trigger_aux_channel_interrupt(vgpu, offset); 1347 return 0; 1348 } 1349 1350 static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset, 1351 void *p_data, unsigned int bytes) 1352 { 1353 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH); 1354 write_vreg(vgpu, offset, p_data, bytes); 1355 return 0; 1356 } 1357 1358 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1359 void *p_data, unsigned int bytes) 1360 { 1361 bool vga_disable; 1362 1363 write_vreg(vgpu, offset, p_data, bytes); 1364 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE; 1365 1366 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id, 1367 vga_disable ? "Disable" : "Enable"); 1368 return 0; 1369 } 1370 1371 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu, 1372 unsigned int sbi_offset) 1373 { 1374 struct intel_vgpu_display *display = &vgpu->display; 1375 int num = display->sbi.number; 1376 int i; 1377 1378 for (i = 0; i < num; ++i) 1379 if (display->sbi.registers[i].offset == sbi_offset) 1380 break; 1381 1382 if (i == num) 1383 return 0; 1384 1385 return display->sbi.registers[i].value; 1386 } 1387 1388 static void write_virtual_sbi_register(struct intel_vgpu *vgpu, 1389 unsigned int offset, u32 value) 1390 { 1391 struct intel_vgpu_display *display = &vgpu->display; 1392 int num = display->sbi.number; 1393 int i; 1394 1395 for (i = 0; i < num; ++i) { 1396 if (display->sbi.registers[i].offset == offset) 1397 break; 1398 } 1399 1400 if (i == num) { 1401 if (num == SBI_REG_MAX) { 1402 gvt_vgpu_err("SBI caching meets maximum limits\n"); 1403 return; 1404 } 1405 display->sbi.number++; 1406 } 1407 1408 display->sbi.registers[i].offset = offset; 1409 display->sbi.registers[i].value = value; 1410 } 1411 1412 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1413 void *p_data, unsigned int bytes) 1414 { 1415 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1416 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) { 1417 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & 1418 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1419 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, 1420 sbi_offset); 1421 } 1422 read_vreg(vgpu, offset, p_data, bytes); 1423 return 0; 1424 } 1425 1426 static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1427 void *p_data, unsigned int bytes) 1428 { 1429 u32 data; 1430 1431 write_vreg(vgpu, offset, p_data, bytes); 1432 data = vgpu_vreg(vgpu, offset); 1433 1434 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT); 1435 data |= SBI_READY; 1436 1437 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT); 1438 data |= SBI_RESPONSE_SUCCESS; 1439 1440 vgpu_vreg(vgpu, offset) = data; 1441 1442 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1443 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) { 1444 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & 1445 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1446 1447 write_virtual_sbi_register(vgpu, sbi_offset, 1448 vgpu_vreg_t(vgpu, SBI_DATA)); 1449 } 1450 return 0; 1451 } 1452 1453 #define _vgtif_reg(x) \ 1454 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)) 1455 1456 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1457 void *p_data, unsigned int bytes) 1458 { 1459 bool invalid_read = false; 1460 1461 read_vreg(vgpu, offset, p_data, bytes); 1462 1463 switch (offset) { 1464 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id): 1465 if (offset + bytes > _vgtif_reg(vgt_id) + 4) 1466 invalid_read = true; 1467 break; 1468 case _vgtif_reg(avail_rs.mappable_gmadr.base) ... 1469 _vgtif_reg(avail_rs.fence_num): 1470 if (offset + bytes > 1471 _vgtif_reg(avail_rs.fence_num) + 4) 1472 invalid_read = true; 1473 break; 1474 case 0x78010: /* vgt_caps */ 1475 case 0x7881c: 1476 break; 1477 default: 1478 invalid_read = true; 1479 break; 1480 } 1481 if (invalid_read) 1482 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n", 1483 offset, bytes, *(u32 *)p_data); 1484 vgpu->pv_notified = true; 1485 return 0; 1486 } 1487 1488 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) 1489 { 1490 enum intel_gvt_gtt_type root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY; 1491 struct intel_vgpu_mm *mm; 1492 u64 *pdps; 1493 1494 pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0])); 1495 1496 switch (notification) { 1497 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE: 1498 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY; 1499 fallthrough; 1500 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE: 1501 mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps); 1502 return PTR_ERR_OR_ZERO(mm); 1503 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY: 1504 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY: 1505 return intel_vgpu_put_ppgtt_mm(vgpu, pdps); 1506 case VGT_G2V_EXECLIST_CONTEXT_CREATE: 1507 case VGT_G2V_EXECLIST_CONTEXT_DESTROY: 1508 case 1: /* Remove this in guest driver. */ 1509 break; 1510 default: 1511 gvt_vgpu_err("Invalid PV notification %d\n", notification); 1512 } 1513 return 0; 1514 } 1515 1516 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready) 1517 { 1518 struct kobject *kobj = &vgpu->gvt->gt->i915->drm.primary->kdev->kobj; 1519 char *env[3] = {NULL, NULL, NULL}; 1520 char vmid_str[20]; 1521 char display_ready_str[20]; 1522 1523 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready); 1524 env[0] = display_ready_str; 1525 1526 snprintf(vmid_str, 20, "VMID=%d", vgpu->id); 1527 env[1] = vmid_str; 1528 1529 return kobject_uevent_env(kobj, KOBJ_ADD, env); 1530 } 1531 1532 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1533 void *p_data, unsigned int bytes) 1534 { 1535 u32 data = *(u32 *)p_data; 1536 bool invalid_write = false; 1537 1538 switch (offset) { 1539 case _vgtif_reg(display_ready): 1540 send_display_ready_uevent(vgpu, data ? 1 : 0); 1541 break; 1542 case _vgtif_reg(g2v_notify): 1543 handle_g2v_notification(vgpu, data); 1544 break; 1545 /* add xhot and yhot to handled list to avoid error log */ 1546 case _vgtif_reg(cursor_x_hot): 1547 case _vgtif_reg(cursor_y_hot): 1548 case _vgtif_reg(pdp[0].lo): 1549 case _vgtif_reg(pdp[0].hi): 1550 case _vgtif_reg(pdp[1].lo): 1551 case _vgtif_reg(pdp[1].hi): 1552 case _vgtif_reg(pdp[2].lo): 1553 case _vgtif_reg(pdp[2].hi): 1554 case _vgtif_reg(pdp[3].lo): 1555 case _vgtif_reg(pdp[3].hi): 1556 case _vgtif_reg(execlist_context_descriptor_lo): 1557 case _vgtif_reg(execlist_context_descriptor_hi): 1558 break; 1559 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]): 1560 invalid_write = true; 1561 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE); 1562 break; 1563 default: 1564 invalid_write = true; 1565 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n", 1566 offset, bytes, data); 1567 break; 1568 } 1569 1570 if (!invalid_write) 1571 write_vreg(vgpu, offset, p_data, bytes); 1572 1573 return 0; 1574 } 1575 1576 static int pf_write(struct intel_vgpu *vgpu, 1577 unsigned int offset, void *p_data, unsigned int bytes) 1578 { 1579 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1580 u32 val = *(u32 *)p_data; 1581 1582 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL || 1583 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL || 1584 offset == _PS_1C_CTRL) && (val & PS_BINDING_MASK) != PS_BINDING_PIPE) { 1585 drm_WARN_ONCE(&i915->drm, true, 1586 "VM(%d): guest is trying to scaling a plane\n", 1587 vgpu->id); 1588 return 0; 1589 } 1590 1591 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 1592 } 1593 1594 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, 1595 unsigned int offset, void *p_data, unsigned int bytes) 1596 { 1597 write_vreg(vgpu, offset, p_data, bytes); 1598 1599 if (vgpu_vreg(vgpu, offset) & 1600 HSW_PWR_WELL_CTL_REQ(HSW_PW_CTL_IDX_GLOBAL)) 1601 vgpu_vreg(vgpu, offset) |= 1602 HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL); 1603 else 1604 vgpu_vreg(vgpu, offset) &= 1605 ~HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL); 1606 return 0; 1607 } 1608 1609 static int gen9_dbuf_ctl_mmio_write(struct intel_vgpu *vgpu, 1610 unsigned int offset, void *p_data, unsigned int bytes) 1611 { 1612 write_vreg(vgpu, offset, p_data, bytes); 1613 1614 if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST) 1615 vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE; 1616 else 1617 vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE; 1618 1619 return 0; 1620 } 1621 1622 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, 1623 unsigned int offset, void *p_data, unsigned int bytes) 1624 { 1625 write_vreg(vgpu, offset, p_data, bytes); 1626 1627 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM) 1628 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM; 1629 return 0; 1630 } 1631 1632 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, 1633 void *p_data, unsigned int bytes) 1634 { 1635 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1636 u32 mode; 1637 1638 write_vreg(vgpu, offset, p_data, bytes); 1639 mode = vgpu_vreg(vgpu, offset); 1640 1641 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) { 1642 drm_WARN_ONCE(&i915->drm, 1, 1643 "VM(%d): iGVT-g doesn't support GuC\n", 1644 vgpu->id); 1645 return 0; 1646 } 1647 1648 return 0; 1649 } 1650 1651 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset, 1652 void *p_data, unsigned int bytes) 1653 { 1654 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1655 u32 trtte = *(u32 *)p_data; 1656 1657 if ((trtte & 1) && (trtte & (1 << 1)) == 0) { 1658 drm_WARN(&i915->drm, 1, 1659 "VM(%d): Use physical address for TRTT!\n", 1660 vgpu->id); 1661 return -EINVAL; 1662 } 1663 write_vreg(vgpu, offset, p_data, bytes); 1664 1665 return 0; 1666 } 1667 1668 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset, 1669 void *p_data, unsigned int bytes) 1670 { 1671 write_vreg(vgpu, offset, p_data, bytes); 1672 return 0; 1673 } 1674 1675 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset, 1676 void *p_data, unsigned int bytes) 1677 { 1678 u32 v = 0; 1679 1680 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) 1681 v |= (1 << 0); 1682 1683 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) 1684 v |= (1 << 8); 1685 1686 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) 1687 v |= (1 << 16); 1688 1689 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) 1690 v |= (1 << 24); 1691 1692 vgpu_vreg(vgpu, offset) = v; 1693 1694 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1695 } 1696 1697 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, 1698 void *p_data, unsigned int bytes) 1699 { 1700 u32 value = *(u32 *)p_data; 1701 u32 cmd = value & 0xff; 1702 u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA); 1703 1704 switch (cmd) { 1705 case GEN9_PCODE_READ_MEM_LATENCY: 1706 if (IS_SKYLAKE(vgpu->gvt->gt->i915) || 1707 IS_KABYLAKE(vgpu->gvt->gt->i915) || 1708 IS_COFFEELAKE(vgpu->gvt->gt->i915) || 1709 IS_COMETLAKE(vgpu->gvt->gt->i915)) { 1710 /** 1711 * "Read memory latency" command on gen9. 1712 * Below memory latency values are read 1713 * from skylake platform. 1714 */ 1715 if (!*data0) 1716 *data0 = 0x1e1a1100; 1717 else 1718 *data0 = 0x61514b3d; 1719 } else if (IS_BROXTON(vgpu->gvt->gt->i915)) { 1720 /** 1721 * "Read memory latency" command on gen9. 1722 * Below memory latency values are read 1723 * from Broxton MRB. 1724 */ 1725 if (!*data0) 1726 *data0 = 0x16080707; 1727 else 1728 *data0 = 0x16161616; 1729 } 1730 break; 1731 case SKL_PCODE_CDCLK_CONTROL: 1732 if (IS_SKYLAKE(vgpu->gvt->gt->i915) || 1733 IS_KABYLAKE(vgpu->gvt->gt->i915) || 1734 IS_COFFEELAKE(vgpu->gvt->gt->i915) || 1735 IS_COMETLAKE(vgpu->gvt->gt->i915)) 1736 *data0 = SKL_CDCLK_READY_FOR_CHANGE; 1737 break; 1738 case GEN6_PCODE_READ_RC6VIDS: 1739 *data0 |= 0x1; 1740 break; 1741 } 1742 1743 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n", 1744 vgpu->id, value, *data0); 1745 /** 1746 * PCODE_READY clear means ready for pcode read/write, 1747 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we 1748 * always emulate as pcode read/write success and ready for access 1749 * anytime, since we don't touch real physical registers here. 1750 */ 1751 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK); 1752 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1753 } 1754 1755 static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset, 1756 void *p_data, unsigned int bytes) 1757 { 1758 u32 value = *(u32 *)p_data; 1759 const struct intel_engine_cs *engine = 1760 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 1761 1762 if (value != 0 && 1763 !intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) { 1764 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n", 1765 offset, value); 1766 return -EINVAL; 1767 } 1768 1769 /* 1770 * Need to emulate all the HWSP register write to ensure host can 1771 * update the VM CSB status correctly. Here listed registers can 1772 * support BDW, SKL or other platforms with same HWSP registers. 1773 */ 1774 if (unlikely(!engine)) { 1775 gvt_vgpu_err("access unknown hardware status page register:0x%x\n", 1776 offset); 1777 return -EINVAL; 1778 } 1779 vgpu->hws_pga[engine->id] = value; 1780 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n", 1781 vgpu->id, value, offset); 1782 1783 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1784 } 1785 1786 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu, 1787 unsigned int offset, void *p_data, unsigned int bytes) 1788 { 1789 u32 v = *(u32 *)p_data; 1790 1791 if (IS_BROXTON(vgpu->gvt->gt->i915)) 1792 v &= (1 << 31) | (1 << 29); 1793 else 1794 v &= (1 << 31) | (1 << 29) | (1 << 9) | 1795 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1); 1796 v |= (v >> 1); 1797 1798 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes); 1799 } 1800 1801 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset, 1802 void *p_data, unsigned int bytes) 1803 { 1804 u32 v = *(u32 *)p_data; 1805 1806 /* other bits are MBZ. */ 1807 v &= (1 << 31) | (1 << 30); 1808 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30)); 1809 1810 vgpu_vreg(vgpu, offset) = v; 1811 1812 return 0; 1813 } 1814 1815 static int bxt_de_pll_enable_write(struct intel_vgpu *vgpu, 1816 unsigned int offset, void *p_data, unsigned int bytes) 1817 { 1818 u32 v = *(u32 *)p_data; 1819 1820 if (v & BXT_DE_PLL_PLL_ENABLE) 1821 v |= BXT_DE_PLL_LOCK; 1822 1823 vgpu_vreg(vgpu, offset) = v; 1824 1825 return 0; 1826 } 1827 1828 static int bxt_port_pll_enable_write(struct intel_vgpu *vgpu, 1829 unsigned int offset, void *p_data, unsigned int bytes) 1830 { 1831 u32 v = *(u32 *)p_data; 1832 1833 if (v & PORT_PLL_ENABLE) 1834 v |= PORT_PLL_LOCK; 1835 1836 vgpu_vreg(vgpu, offset) = v; 1837 1838 return 0; 1839 } 1840 1841 static int bxt_phy_ctl_family_write(struct intel_vgpu *vgpu, 1842 unsigned int offset, void *p_data, unsigned int bytes) 1843 { 1844 u32 v = *(u32 *)p_data; 1845 u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0; 1846 1847 switch (offset) { 1848 case _PHY_CTL_FAMILY_EDP: 1849 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data; 1850 break; 1851 case _PHY_CTL_FAMILY_DDI: 1852 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data; 1853 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data; 1854 break; 1855 } 1856 1857 vgpu_vreg(vgpu, offset) = v; 1858 1859 return 0; 1860 } 1861 1862 static int bxt_port_tx_dw3_read(struct intel_vgpu *vgpu, 1863 unsigned int offset, void *p_data, unsigned int bytes) 1864 { 1865 u32 v = vgpu_vreg(vgpu, offset); 1866 1867 v &= ~UNIQUE_TRANGE_EN_METHOD; 1868 1869 vgpu_vreg(vgpu, offset) = v; 1870 1871 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1872 } 1873 1874 static int bxt_pcs_dw12_grp_write(struct intel_vgpu *vgpu, 1875 unsigned int offset, void *p_data, unsigned int bytes) 1876 { 1877 u32 v = *(u32 *)p_data; 1878 1879 if (offset == _PORT_PCS_DW12_GRP_A || offset == _PORT_PCS_DW12_GRP_B) { 1880 vgpu_vreg(vgpu, offset - 0x600) = v; 1881 vgpu_vreg(vgpu, offset - 0x800) = v; 1882 } else { 1883 vgpu_vreg(vgpu, offset - 0x400) = v; 1884 vgpu_vreg(vgpu, offset - 0x600) = v; 1885 } 1886 1887 vgpu_vreg(vgpu, offset) = v; 1888 1889 return 0; 1890 } 1891 1892 static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu, 1893 unsigned int offset, void *p_data, unsigned int bytes) 1894 { 1895 u32 v = *(u32 *)p_data; 1896 1897 if (v & BIT(0)) { 1898 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= 1899 ~PHY_RESERVED; 1900 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= 1901 PHY_POWER_GOOD; 1902 } 1903 1904 if (v & BIT(1)) { 1905 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= 1906 ~PHY_RESERVED; 1907 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= 1908 PHY_POWER_GOOD; 1909 } 1910 1911 1912 vgpu_vreg(vgpu, offset) = v; 1913 1914 return 0; 1915 } 1916 1917 static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu, 1918 unsigned int offset, void *p_data, unsigned int bytes) 1919 { 1920 vgpu_vreg(vgpu, offset) = 0; 1921 return 0; 1922 } 1923 1924 /* 1925 * FixMe: 1926 * If guest fills non-priv batch buffer on ApolloLake/Broxton as Mesa i965 did: 1927 * 717e7539124d (i965: Use a WC map and memcpy for the batch instead of pwrite.) 1928 * Due to the missing flush of bb filled by VM vCPU, host GPU hangs on executing 1929 * these MI_BATCH_BUFFER. 1930 * Temporarily workaround this by setting SNOOP bit for PAT3 used by PPGTT 1931 * PML4 PTE: PAT(0) PCD(1) PWT(1). 1932 * The performance is still expected to be low, will need further improvement. 1933 */ 1934 static int bxt_ppat_low_write(struct intel_vgpu *vgpu, unsigned int offset, 1935 void *p_data, unsigned int bytes) 1936 { 1937 u64 pat = 1938 GEN8_PPAT(0, CHV_PPAT_SNOOP) | 1939 GEN8_PPAT(1, 0) | 1940 GEN8_PPAT(2, 0) | 1941 GEN8_PPAT(3, CHV_PPAT_SNOOP) | 1942 GEN8_PPAT(4, CHV_PPAT_SNOOP) | 1943 GEN8_PPAT(5, CHV_PPAT_SNOOP) | 1944 GEN8_PPAT(6, CHV_PPAT_SNOOP) | 1945 GEN8_PPAT(7, CHV_PPAT_SNOOP); 1946 1947 vgpu_vreg(vgpu, offset) = lower_32_bits(pat); 1948 1949 return 0; 1950 } 1951 1952 static int guc_status_read(struct intel_vgpu *vgpu, 1953 unsigned int offset, void *p_data, 1954 unsigned int bytes) 1955 { 1956 /* keep MIA_IN_RESET before clearing */ 1957 read_vreg(vgpu, offset, p_data, bytes); 1958 vgpu_vreg(vgpu, offset) &= ~GS_MIA_IN_RESET; 1959 return 0; 1960 } 1961 1962 static int mmio_read_from_hw(struct intel_vgpu *vgpu, 1963 unsigned int offset, void *p_data, unsigned int bytes) 1964 { 1965 struct intel_gvt *gvt = vgpu->gvt; 1966 const struct intel_engine_cs *engine = 1967 intel_gvt_render_mmio_to_engine(gvt, offset); 1968 1969 /** 1970 * Read HW reg in following case 1971 * a. the offset isn't a ring mmio 1972 * b. the offset's ring is running on hw. 1973 * c. the offset is ring time stamp mmio 1974 */ 1975 1976 if (!engine || 1977 vgpu == gvt->scheduler.engine_owner[engine->id] || 1978 offset == i915_mmio_reg_offset(RING_TIMESTAMP(engine->mmio_base)) || 1979 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(engine->mmio_base))) { 1980 intel_wakeref_t wakeref; 1981 1982 wakeref = mmio_hw_access_pre(gvt->gt); 1983 vgpu_vreg(vgpu, offset) = 1984 intel_uncore_read(gvt->gt->uncore, _MMIO(offset)); 1985 mmio_hw_access_post(gvt->gt, wakeref); 1986 } 1987 1988 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1989 } 1990 1991 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1992 void *p_data, unsigned int bytes) 1993 { 1994 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1995 const struct intel_engine_cs *engine = intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 1996 struct intel_vgpu_execlist *execlist; 1997 u32 data = *(u32 *)p_data; 1998 int ret = 0; 1999 2000 if (drm_WARN_ON(&i915->drm, !engine)) 2001 return -EINVAL; 2002 2003 /* 2004 * Due to d3_entered is used to indicate skipping PPGTT invalidation on 2005 * vGPU reset, it's set on D0->D3 on PCI config write, and cleared after 2006 * vGPU reset if in resuming. 2007 * In S0ix exit, the device power state also transite from D3 to D0 as 2008 * S3 resume, but no vGPU reset (triggered by QEMU device model). After 2009 * S0ix exit, all engines continue to work. However the d3_entered 2010 * remains set which will break next vGPU reset logic (miss the expected 2011 * PPGTT invalidation). 2012 * Engines can only work in D0. Thus the 1st elsp write gives GVT a 2013 * chance to clear d3_entered. 2014 */ 2015 if (vgpu->d3_entered) 2016 vgpu->d3_entered = false; 2017 2018 execlist = &vgpu->submission.execlist[engine->id]; 2019 2020 execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data; 2021 if (execlist->elsp_dwords.index == 3) { 2022 ret = intel_vgpu_submit_execlist(vgpu, engine); 2023 if(ret) 2024 gvt_vgpu_err("fail submit workload on ring %s\n", 2025 engine->name); 2026 } 2027 2028 ++execlist->elsp_dwords.index; 2029 execlist->elsp_dwords.index &= 0x3; 2030 return ret; 2031 } 2032 2033 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 2034 void *p_data, unsigned int bytes) 2035 { 2036 u32 data = *(u32 *)p_data; 2037 const struct intel_engine_cs *engine = 2038 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 2039 bool enable_execlist; 2040 int ret; 2041 2042 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1); 2043 if (IS_COFFEELAKE(vgpu->gvt->gt->i915) || 2044 IS_COMETLAKE(vgpu->gvt->gt->i915)) 2045 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2); 2046 write_vreg(vgpu, offset, p_data, bytes); 2047 2048 if (IS_MASKED_BITS_ENABLED(data, 1)) { 2049 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2050 return 0; 2051 } 2052 2053 if ((IS_COFFEELAKE(vgpu->gvt->gt->i915) || 2054 IS_COMETLAKE(vgpu->gvt->gt->i915)) && 2055 IS_MASKED_BITS_ENABLED(data, 2)) { 2056 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2057 return 0; 2058 } 2059 2060 /* when PPGTT mode enabled, we will check if guest has called 2061 * pvinfo, if not, we will treat this guest as non-gvtg-aware 2062 * guest, and stop emulating its cfg space, mmio, gtt, etc. 2063 */ 2064 if ((IS_MASKED_BITS_ENABLED(data, GFX_PPGTT_ENABLE) || 2065 IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE)) && 2066 !vgpu->pv_notified) { 2067 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2068 return 0; 2069 } 2070 if (IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE) || 2071 IS_MASKED_BITS_DISABLED(data, GFX_RUN_LIST_ENABLE)) { 2072 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE); 2073 2074 gvt_dbg_core("EXECLIST %s on ring %s\n", 2075 (enable_execlist ? "enabling" : "disabling"), 2076 engine->name); 2077 2078 if (!enable_execlist) 2079 return 0; 2080 2081 ret = intel_vgpu_select_submission_ops(vgpu, 2082 engine->mask, 2083 INTEL_VGPU_EXECLIST_SUBMISSION); 2084 if (ret) 2085 return ret; 2086 2087 intel_vgpu_start_schedule(vgpu); 2088 } 2089 return 0; 2090 } 2091 2092 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu, 2093 unsigned int offset, void *p_data, unsigned int bytes) 2094 { 2095 unsigned int id = 0; 2096 2097 write_vreg(vgpu, offset, p_data, bytes); 2098 vgpu_vreg(vgpu, offset) = 0; 2099 2100 switch (offset) { 2101 case 0x4260: 2102 id = RCS0; 2103 break; 2104 case 0x4264: 2105 id = VCS0; 2106 break; 2107 case 0x4268: 2108 id = VCS1; 2109 break; 2110 case 0x426c: 2111 id = BCS0; 2112 break; 2113 case 0x4270: 2114 id = VECS0; 2115 break; 2116 default: 2117 return -EINVAL; 2118 } 2119 set_bit(id, (void *)vgpu->submission.tlb_handle_pending); 2120 2121 return 0; 2122 } 2123 2124 static int ring_reset_ctl_write(struct intel_vgpu *vgpu, 2125 unsigned int offset, void *p_data, unsigned int bytes) 2126 { 2127 u32 data; 2128 2129 write_vreg(vgpu, offset, p_data, bytes); 2130 data = vgpu_vreg(vgpu, offset); 2131 2132 if (IS_MASKED_BITS_ENABLED(data, RESET_CTL_REQUEST_RESET)) 2133 data |= RESET_CTL_READY_TO_RESET; 2134 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)) 2135 data &= ~RESET_CTL_READY_TO_RESET; 2136 2137 vgpu_vreg(vgpu, offset) = data; 2138 return 0; 2139 } 2140 2141 static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu, 2142 unsigned int offset, void *p_data, 2143 unsigned int bytes) 2144 { 2145 u32 data = *(u32 *)p_data; 2146 2147 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18); 2148 write_vreg(vgpu, offset, p_data, bytes); 2149 2150 if (IS_MASKED_BITS_ENABLED(data, 0x10) || 2151 IS_MASKED_BITS_ENABLED(data, 0x8)) 2152 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2153 2154 return 0; 2155 } 2156 2157 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ 2158 ret = setup_mmio_info(gvt, i915_mmio_reg_offset(reg), \ 2159 s, f, am, rm, d, r, w); \ 2160 if (ret) \ 2161 return ret; \ 2162 } while (0) 2163 2164 #define MMIO_DH(reg, d, r, w) \ 2165 MMIO_F(reg, 4, 0, 0, 0, d, r, w) 2166 2167 #define MMIO_DFH(reg, d, f, r, w) \ 2168 MMIO_F(reg, 4, f, 0, 0, d, r, w) 2169 2170 #define MMIO_GM(reg, d, r, w) \ 2171 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w) 2172 2173 #define MMIO_GM_RDR(reg, d, r, w) \ 2174 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w) 2175 2176 #define MMIO_RO(reg, d, f, rm, r, w) \ 2177 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w) 2178 2179 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \ 2180 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \ 2181 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ 2182 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ 2183 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ 2184 if (HAS_ENGINE(gvt->gt, VCS1)) \ 2185 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \ 2186 } while (0) 2187 2188 #define MMIO_RING_DFH(prefix, d, f, r, w) \ 2189 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w) 2190 2191 #define MMIO_RING_GM(prefix, d, r, w) \ 2192 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w) 2193 2194 #define MMIO_RING_GM_RDR(prefix, d, r, w) \ 2195 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w) 2196 2197 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \ 2198 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w) 2199 2200 static int init_generic_mmio_info(struct intel_gvt *gvt) 2201 { 2202 struct drm_i915_private *dev_priv = gvt->gt->i915; 2203 struct intel_display *display = &dev_priv->display; 2204 int ret; 2205 2206 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL, 2207 intel_vgpu_reg_imr_handler); 2208 2209 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 2210 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); 2211 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); 2212 2213 MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL); 2214 2215 2216 MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL, 2217 gamw_echo_dev_rw_ia_write); 2218 2219 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL); 2220 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL); 2221 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL); 2222 2223 #define RING_REG(base) _MMIO((base) + 0x28) 2224 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2225 #undef RING_REG 2226 2227 #define RING_REG(base) _MMIO((base) + 0x134) 2228 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2229 #undef RING_REG 2230 2231 #define RING_REG(base) _MMIO((base) + 0x6c) 2232 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL); 2233 #undef RING_REG 2234 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL); 2235 2236 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL); 2237 MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL); 2238 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL); 2239 2240 MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL); 2241 MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL); 2242 MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL); 2243 MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL); 2244 MMIO_RING_GM(RING_START, D_ALL, NULL, NULL); 2245 2246 /* RING MODE */ 2247 #define RING_REG(base) _MMIO((base) + 0x29c) 2248 MMIO_RING_DFH(RING_REG, D_ALL, 2249 F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL, 2250 ring_mode_mmio_write); 2251 #undef RING_REG 2252 2253 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2254 NULL, NULL); 2255 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2256 NULL, NULL); 2257 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, 2258 mmio_read_from_hw, NULL); 2259 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, 2260 mmio_read_from_hw, NULL); 2261 2262 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2263 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2264 NULL, NULL); 2265 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2266 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2267 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2268 2269 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2270 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2271 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2272 MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL, 2273 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2274 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2275 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL); 2276 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2277 NULL, NULL); 2278 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2279 NULL, NULL); 2280 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL); 2281 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL); 2282 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL); 2283 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL); 2284 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL); 2285 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL); 2286 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2287 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2288 MMIO_DFH(HSW_HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2289 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2290 2291 /* display */ 2292 MMIO_DH(TRANSCONF(display, TRANSCODER_A), D_ALL, NULL, 2293 pipeconf_mmio_write); 2294 MMIO_DH(TRANSCONF(display, TRANSCODER_B), D_ALL, NULL, 2295 pipeconf_mmio_write); 2296 MMIO_DH(TRANSCONF(display, TRANSCODER_C), D_ALL, NULL, 2297 pipeconf_mmio_write); 2298 MMIO_DH(TRANSCONF(display, TRANSCODER_EDP), D_ALL, NULL, 2299 pipeconf_mmio_write); 2300 MMIO_DH(DSPSURF(display, PIPE_A), D_ALL, NULL, pri_surf_mmio_write); 2301 MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL, 2302 reg50080_mmio_write); 2303 MMIO_DH(DSPSURF(display, PIPE_B), D_ALL, NULL, pri_surf_mmio_write); 2304 MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL, 2305 reg50080_mmio_write); 2306 MMIO_DH(DSPSURF(display, PIPE_C), D_ALL, NULL, pri_surf_mmio_write); 2307 MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL, 2308 reg50080_mmio_write); 2309 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); 2310 MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL, 2311 reg50080_mmio_write); 2312 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); 2313 MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL, 2314 reg50080_mmio_write); 2315 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); 2316 MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL, 2317 reg50080_mmio_write); 2318 2319 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, 2320 gmbus_mmio_write); 2321 MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); 2322 2323 MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2324 dp_aux_ch_ctl_mmio_write); 2325 MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2326 dp_aux_ch_ctl_mmio_write); 2327 MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2328 dp_aux_ch_ctl_mmio_write); 2329 2330 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write); 2331 2332 MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write); 2333 MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write); 2334 2335 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); 2336 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); 2337 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write); 2338 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 2339 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 2340 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 2341 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 2342 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 2343 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 2344 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write); 2345 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL); 2346 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL); 2347 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL); 2348 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL); 2349 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL); 2350 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL); 2351 2352 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, 2353 PORTA_HOTPLUG_STATUS_MASK 2354 | PORTB_HOTPLUG_STATUS_MASK 2355 | PORTC_HOTPLUG_STATUS_MASK 2356 | PORTD_HOTPLUG_STATUS_MASK, 2357 NULL, NULL); 2358 2359 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write); 2360 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write); 2361 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL); 2362 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); 2363 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); 2364 2365 MMIO_F(DP_AUX_CH_CTL(AUX_CH_A), 6 * 4, 0, 0, 0, D_ALL, NULL, 2366 dp_aux_ch_ctl_mmio_write); 2367 2368 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2369 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2370 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2371 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2372 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2373 2374 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); 2375 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); 2376 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); 2377 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); 2378 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); 2379 2380 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); 2381 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); 2382 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write); 2383 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); 2384 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); 2385 2386 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL); 2387 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL); 2388 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL); 2389 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL); 2390 2391 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); 2392 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2393 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2394 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write); 2395 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL); 2396 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL); 2397 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL); 2398 MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write); 2399 MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write); 2400 MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write); 2401 MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write); 2402 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write); 2403 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write); 2404 2405 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write); 2406 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); 2407 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write); 2408 2409 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); 2410 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); 2411 2412 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write); 2413 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL); 2414 2415 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); 2416 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2417 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL); 2418 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2419 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL); 2420 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2421 2422 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); 2423 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2424 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2425 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2426 2427 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2428 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2429 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2430 2431 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2432 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2433 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2434 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2435 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2436 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2437 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2438 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2439 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2440 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2441 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2442 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2443 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2444 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2445 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2446 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2447 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2448 2449 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2450 MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL); 2451 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2452 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2453 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2454 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL); 2455 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL); 2456 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2457 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2458 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2459 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2460 2461 MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write); 2462 MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write); 2463 MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL); 2464 2465 return 0; 2466 } 2467 2468 static int init_bdw_mmio_info(struct intel_gvt *gvt) 2469 { 2470 int ret; 2471 2472 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2473 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2474 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2475 2476 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2477 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2478 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2479 2480 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2481 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2482 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2483 2484 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2485 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2486 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2487 2488 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, 2489 intel_vgpu_reg_imr_handler); 2490 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, 2491 intel_vgpu_reg_ier_handler); 2492 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, 2493 intel_vgpu_reg_iir_handler); 2494 2495 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, 2496 intel_vgpu_reg_imr_handler); 2497 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, 2498 intel_vgpu_reg_ier_handler); 2499 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, 2500 intel_vgpu_reg_iir_handler); 2501 2502 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL, 2503 intel_vgpu_reg_imr_handler); 2504 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL, 2505 intel_vgpu_reg_ier_handler); 2506 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL, 2507 intel_vgpu_reg_iir_handler); 2508 2509 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2510 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2511 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2512 2513 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2514 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2515 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2516 2517 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2518 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2519 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2520 2521 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, 2522 intel_vgpu_reg_master_irq_handler); 2523 2524 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0, 2525 mmio_read_from_hw, NULL); 2526 2527 #define RING_REG(base) _MMIO((base) + 0xd0) 2528 MMIO_RING_F(RING_REG, 4, F_RO, 0, 2529 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, 2530 ring_reset_ctl_write); 2531 #undef RING_REG 2532 2533 #define RING_REG(base) _MMIO((base) + 0x230) 2534 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); 2535 #undef RING_REG 2536 2537 #define RING_REG(base) _MMIO((base) + 0x234) 2538 MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS, 2539 NULL, NULL); 2540 #undef RING_REG 2541 2542 #define RING_REG(base) _MMIO((base) + 0x244) 2543 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2544 #undef RING_REG 2545 2546 #define RING_REG(base) _MMIO((base) + 0x370) 2547 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2548 #undef RING_REG 2549 2550 #define RING_REG(base) _MMIO((base) + 0x3a0) 2551 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2552 #undef RING_REG 2553 2554 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write); 2555 2556 #define RING_REG(base) _MMIO((base) + 0x270) 2557 MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); 2558 #undef RING_REG 2559 2560 MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write); 2561 2562 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2563 2564 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2565 NULL, NULL); 2566 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2567 NULL, NULL); 2568 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2569 2570 MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL); 2571 MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL); 2572 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2573 MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL); 2574 MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL); 2575 2576 MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0, 2577 D_BDW_PLUS, NULL, force_nonpriv_write); 2578 2579 MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL); 2580 2581 MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL); 2582 2583 MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2584 MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2585 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2586 MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2587 2588 MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL); 2589 2590 MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2591 MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2592 MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2593 MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2594 MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2595 MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2596 MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2597 MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2598 MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2599 MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2600 return 0; 2601 } 2602 2603 static int init_skl_mmio_info(struct intel_gvt *gvt) 2604 { 2605 int ret; 2606 2607 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2608 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); 2609 MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2610 MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL); 2611 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2612 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); 2613 2614 MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2615 dp_aux_ch_ctl_mmio_write); 2616 MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2617 dp_aux_ch_ctl_mmio_write); 2618 MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2619 dp_aux_ch_ctl_mmio_write); 2620 2621 MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write); 2622 2623 MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write); 2624 2625 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2626 MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2627 MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL); 2628 MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write); 2629 MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write); 2630 MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL); 2631 2632 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2633 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2634 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2635 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2636 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2637 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2638 2639 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2640 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2641 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2642 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2643 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2644 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2645 2646 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2647 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2648 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2649 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2650 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2651 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2652 2653 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2654 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2655 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2656 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2657 2658 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2659 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2660 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2661 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2662 2663 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2664 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2665 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2666 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2667 2668 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL); 2669 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL); 2670 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL); 2671 2672 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2673 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2674 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2675 2676 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2677 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2678 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2679 2680 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2681 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2682 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2683 2684 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL); 2685 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL); 2686 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL); 2687 2688 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2689 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2690 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2691 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2692 2693 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2694 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2695 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2696 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2697 2698 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2699 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2700 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2701 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2702 2703 MMIO_DH(PLANE_AUX_DIST(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2704 MMIO_DH(PLANE_AUX_DIST(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2705 MMIO_DH(PLANE_AUX_DIST(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2706 MMIO_DH(PLANE_AUX_DIST(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2707 2708 MMIO_DH(PLANE_AUX_DIST(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2709 MMIO_DH(PLANE_AUX_DIST(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2710 MMIO_DH(PLANE_AUX_DIST(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2711 MMIO_DH(PLANE_AUX_DIST(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2712 2713 MMIO_DH(PLANE_AUX_DIST(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2714 MMIO_DH(PLANE_AUX_DIST(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2715 MMIO_DH(PLANE_AUX_DIST(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2716 MMIO_DH(PLANE_AUX_DIST(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2717 2718 MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2719 MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2720 MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2721 MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2722 2723 MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2724 MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2725 MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2726 MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2727 2728 MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2729 MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2730 MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2731 MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2732 2733 MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2734 2735 MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, 2736 NULL, NULL); 2737 MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, 2738 NULL, NULL); 2739 2740 MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS, 2741 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2742 MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2743 NULL, NULL); 2744 2745 /* TRTT */ 2746 MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2747 MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2748 MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2749 MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2750 MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2751 MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE, 2752 NULL, gen9_trtte_write); 2753 MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE, 2754 NULL, gen9_trtt_chicken_write); 2755 2756 MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2757 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); 2758 2759 #define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4) 2760 MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2761 NULL, csfe_chicken1_mmio_write); 2762 #undef CSFE_CHICKEN1_REG 2763 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2764 NULL, NULL); 2765 MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2766 NULL, NULL); 2767 2768 MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL); 2769 MMIO_DFH(_MMIO(0xe4cc), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2770 2771 return 0; 2772 } 2773 2774 static int init_bxt_mmio_info(struct intel_gvt *gvt) 2775 { 2776 int ret; 2777 2778 MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write); 2779 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT, 2780 NULL, bxt_phy_ctl_family_write); 2781 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT, 2782 NULL, bxt_phy_ctl_family_write); 2783 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT, 2784 NULL, bxt_port_pll_enable_write); 2785 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT, 2786 NULL, bxt_port_pll_enable_write); 2787 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL, 2788 bxt_port_pll_enable_write); 2789 2790 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT, 2791 NULL, bxt_pcs_dw12_grp_write); 2792 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT, 2793 bxt_port_tx_dw3_read, NULL); 2794 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT, 2795 NULL, bxt_pcs_dw12_grp_write); 2796 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT, 2797 bxt_port_tx_dw3_read, NULL); 2798 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT, 2799 NULL, bxt_pcs_dw12_grp_write); 2800 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT, 2801 bxt_port_tx_dw3_read, NULL); 2802 MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write); 2803 MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL); 2804 MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL); 2805 MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL); 2806 MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS, 2807 0, 0, D_BXT, NULL, NULL); 2808 MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS, 2809 0, 0, D_BXT, NULL, NULL); 2810 MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS, 2811 0, 0, D_BXT, NULL, NULL); 2812 MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS, 2813 0, 0, D_BXT, NULL, NULL); 2814 2815 MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL); 2816 2817 MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write); 2818 2819 return 0; 2820 } 2821 2822 static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt, 2823 unsigned int offset) 2824 { 2825 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 2826 int num = gvt->mmio.num_mmio_block; 2827 int i; 2828 2829 for (i = 0; i < num; i++, block++) { 2830 if (offset >= i915_mmio_reg_offset(block->offset) && 2831 offset < i915_mmio_reg_offset(block->offset) + block->size) 2832 return block; 2833 } 2834 return NULL; 2835 } 2836 2837 /** 2838 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device 2839 * @gvt: GVT device 2840 * 2841 * This function is called at the driver unloading stage, to clean up the MMIO 2842 * information table of GVT device 2843 * 2844 */ 2845 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) 2846 { 2847 struct hlist_node *tmp; 2848 struct intel_gvt_mmio_info *e; 2849 int i; 2850 2851 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node) 2852 kfree(e); 2853 2854 kfree(gvt->mmio.mmio_block); 2855 gvt->mmio.mmio_block = NULL; 2856 gvt->mmio.num_mmio_block = 0; 2857 2858 vfree(gvt->mmio.mmio_attribute); 2859 gvt->mmio.mmio_attribute = NULL; 2860 } 2861 2862 static int handle_mmio(struct intel_gvt_mmio_table_iter *iter, u32 offset, 2863 u32 size) 2864 { 2865 struct intel_gvt *gvt = iter->data; 2866 struct intel_gvt_mmio_info *info, *p; 2867 u32 start, end, i; 2868 2869 if (WARN_ON(!IS_ALIGNED(offset, 4))) 2870 return -EINVAL; 2871 2872 start = offset; 2873 end = offset + size; 2874 2875 for (i = start; i < end; i += 4) { 2876 p = intel_gvt_find_mmio_info(gvt, i); 2877 if (p) { 2878 WARN(1, "dup mmio definition offset %x\n", i); 2879 2880 /* We return -EEXIST here to make GVT-g load fail. 2881 * So duplicated MMIO can be found as soon as 2882 * possible. 2883 */ 2884 return -EEXIST; 2885 } 2886 2887 info = kzalloc(sizeof(*info), GFP_KERNEL); 2888 if (!info) 2889 return -ENOMEM; 2890 2891 info->offset = i; 2892 info->read = intel_vgpu_default_mmio_read; 2893 info->write = intel_vgpu_default_mmio_write; 2894 INIT_HLIST_NODE(&info->node); 2895 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset); 2896 gvt->mmio.num_tracked_mmio++; 2897 } 2898 return 0; 2899 } 2900 2901 static int handle_mmio_block(struct intel_gvt_mmio_table_iter *iter, 2902 u32 offset, u32 size) 2903 { 2904 struct intel_gvt *gvt = iter->data; 2905 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 2906 void *ret; 2907 2908 ret = krealloc(block, 2909 (gvt->mmio.num_mmio_block + 1) * sizeof(*block), 2910 GFP_KERNEL); 2911 if (!ret) 2912 return -ENOMEM; 2913 2914 gvt->mmio.mmio_block = block = ret; 2915 2916 block += gvt->mmio.num_mmio_block; 2917 2918 memset(block, 0, sizeof(*block)); 2919 2920 block->offset = _MMIO(offset); 2921 block->size = size; 2922 2923 gvt->mmio.num_mmio_block++; 2924 2925 return 0; 2926 } 2927 2928 static int handle_mmio_cb(struct intel_gvt_mmio_table_iter *iter, u32 offset, 2929 u32 size) 2930 { 2931 if (size < 1024 || offset == i915_mmio_reg_offset(GEN9_GFX_MOCS(0))) 2932 return handle_mmio(iter, offset, size); 2933 else 2934 return handle_mmio_block(iter, offset, size); 2935 } 2936 2937 static int init_mmio_info(struct intel_gvt *gvt) 2938 { 2939 struct intel_gvt_mmio_table_iter iter = { 2940 .i915 = gvt->gt->i915, 2941 .data = gvt, 2942 .handle_mmio_cb = handle_mmio_cb, 2943 }; 2944 2945 return intel_gvt_iterate_mmio_table(&iter); 2946 } 2947 2948 static int init_mmio_block_handlers(struct intel_gvt *gvt) 2949 { 2950 struct gvt_mmio_block *block; 2951 2952 block = find_mmio_block(gvt, VGT_PVINFO_PAGE); 2953 if (!block) { 2954 WARN(1, "fail to assign handlers to mmio block %x\n", 2955 i915_mmio_reg_offset(gvt->mmio.mmio_block->offset)); 2956 return -ENODEV; 2957 } 2958 2959 block->read = pvinfo_mmio_read; 2960 block->write = pvinfo_mmio_write; 2961 2962 return 0; 2963 } 2964 2965 /** 2966 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device 2967 * @gvt: GVT device 2968 * 2969 * This function is called at the initialization stage, to setup the MMIO 2970 * information table for GVT device 2971 * 2972 * Returns: 2973 * zero on success, negative if failed. 2974 */ 2975 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) 2976 { 2977 struct intel_gvt_device_info *info = &gvt->device_info; 2978 struct drm_i915_private *i915 = gvt->gt->i915; 2979 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute); 2980 int ret; 2981 2982 gvt->mmio.mmio_attribute = vzalloc(size); 2983 if (!gvt->mmio.mmio_attribute) 2984 return -ENOMEM; 2985 2986 ret = init_mmio_info(gvt); 2987 if (ret) 2988 goto err; 2989 2990 ret = init_mmio_block_handlers(gvt); 2991 if (ret) 2992 goto err; 2993 2994 ret = init_generic_mmio_info(gvt); 2995 if (ret) 2996 goto err; 2997 2998 if (IS_BROADWELL(i915)) { 2999 ret = init_bdw_mmio_info(gvt); 3000 if (ret) 3001 goto err; 3002 } else if (IS_SKYLAKE(i915) || 3003 IS_KABYLAKE(i915) || 3004 IS_COFFEELAKE(i915) || 3005 IS_COMETLAKE(i915)) { 3006 ret = init_bdw_mmio_info(gvt); 3007 if (ret) 3008 goto err; 3009 ret = init_skl_mmio_info(gvt); 3010 if (ret) 3011 goto err; 3012 } else if (IS_BROXTON(i915)) { 3013 ret = init_bdw_mmio_info(gvt); 3014 if (ret) 3015 goto err; 3016 ret = init_skl_mmio_info(gvt); 3017 if (ret) 3018 goto err; 3019 ret = init_bxt_mmio_info(gvt); 3020 if (ret) 3021 goto err; 3022 } 3023 3024 return 0; 3025 err: 3026 intel_gvt_clean_mmio_info(gvt); 3027 return ret; 3028 } 3029 3030 /** 3031 * intel_gvt_for_each_tracked_mmio - iterate each tracked mmio 3032 * @gvt: a GVT device 3033 * @handler: the handler 3034 * @data: private data given to handler 3035 * 3036 * Returns: 3037 * Zero on success, negative error code if failed. 3038 */ 3039 int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt, 3040 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data), 3041 void *data) 3042 { 3043 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 3044 struct intel_gvt_mmio_info *e; 3045 int i, j, ret; 3046 3047 hash_for_each(gvt->mmio.mmio_info_table, i, e, node) { 3048 ret = handler(gvt, e->offset, data); 3049 if (ret) 3050 return ret; 3051 } 3052 3053 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) { 3054 /* pvinfo data doesn't come from hw mmio */ 3055 if (i915_mmio_reg_offset(block->offset) == VGT_PVINFO_PAGE) 3056 continue; 3057 3058 for (j = 0; j < block->size; j += 4) { 3059 ret = handler(gvt, i915_mmio_reg_offset(block->offset) + j, data); 3060 if (ret) 3061 return ret; 3062 } 3063 } 3064 return 0; 3065 } 3066 3067 /** 3068 * intel_vgpu_default_mmio_read - default MMIO read handler 3069 * @vgpu: a vGPU 3070 * @offset: access offset 3071 * @p_data: data return buffer 3072 * @bytes: access data length 3073 * 3074 * Returns: 3075 * Zero on success, negative error code if failed. 3076 */ 3077 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 3078 void *p_data, unsigned int bytes) 3079 { 3080 read_vreg(vgpu, offset, p_data, bytes); 3081 return 0; 3082 } 3083 3084 /** 3085 * intel_vgpu_default_mmio_write() - default MMIO write handler 3086 * @vgpu: a vGPU 3087 * @offset: access offset 3088 * @p_data: write data buffer 3089 * @bytes: access data length 3090 * 3091 * Returns: 3092 * Zero on success, negative error code if failed. 3093 */ 3094 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 3095 void *p_data, unsigned int bytes) 3096 { 3097 write_vreg(vgpu, offset, p_data, bytes); 3098 return 0; 3099 } 3100 3101 /** 3102 * intel_vgpu_mask_mmio_write - write mask register 3103 * @vgpu: a vGPU 3104 * @offset: access offset 3105 * @p_data: write data buffer 3106 * @bytes: access data length 3107 * 3108 * Returns: 3109 * Zero on success, negative error code if failed. 3110 */ 3111 int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 3112 void *p_data, unsigned int bytes) 3113 { 3114 u32 mask, old_vreg; 3115 3116 old_vreg = vgpu_vreg(vgpu, offset); 3117 write_vreg(vgpu, offset, p_data, bytes); 3118 mask = vgpu_vreg(vgpu, offset) >> 16; 3119 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) | 3120 (vgpu_vreg(vgpu, offset) & mask); 3121 3122 return 0; 3123 } 3124 3125 /** 3126 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers 3127 * @vgpu: a vGPU 3128 * @offset: register offset 3129 * @pdata: data buffer 3130 * @bytes: data length 3131 * @is_read: read or write 3132 * 3133 * Returns: 3134 * Zero on success, negative error code if failed. 3135 */ 3136 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset, 3137 void *pdata, unsigned int bytes, bool is_read) 3138 { 3139 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 3140 struct intel_gvt *gvt = vgpu->gvt; 3141 struct intel_gvt_mmio_info *mmio_info; 3142 struct gvt_mmio_block *mmio_block; 3143 gvt_mmio_func func; 3144 int ret; 3145 3146 if (drm_WARN_ON(&i915->drm, bytes > 8)) 3147 return -EINVAL; 3148 3149 /* 3150 * Handle special MMIO blocks. 3151 */ 3152 mmio_block = find_mmio_block(gvt, offset); 3153 if (mmio_block) { 3154 func = is_read ? mmio_block->read : mmio_block->write; 3155 if (func) 3156 return func(vgpu, offset, pdata, bytes); 3157 goto default_rw; 3158 } 3159 3160 /* 3161 * Normal tracked MMIOs. 3162 */ 3163 mmio_info = intel_gvt_find_mmio_info(gvt, offset); 3164 if (!mmio_info) { 3165 gvt_dbg_mmio("untracked MMIO %08x len %d\n", offset, bytes); 3166 goto default_rw; 3167 } 3168 3169 if (is_read) 3170 return mmio_info->read(vgpu, offset, pdata, bytes); 3171 else { 3172 u64 ro_mask = mmio_info->ro_mask; 3173 u32 old_vreg = 0; 3174 u64 data = 0; 3175 3176 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3177 old_vreg = vgpu_vreg(vgpu, offset); 3178 } 3179 3180 if (likely(!ro_mask)) 3181 ret = mmio_info->write(vgpu, offset, pdata, bytes); 3182 else if (!~ro_mask) { 3183 gvt_vgpu_err("try to write RO reg %x\n", offset); 3184 return 0; 3185 } else { 3186 /* keep the RO bits in the virtual register */ 3187 memcpy(&data, pdata, bytes); 3188 data &= ~ro_mask; 3189 data |= vgpu_vreg(vgpu, offset) & ro_mask; 3190 ret = mmio_info->write(vgpu, offset, &data, bytes); 3191 } 3192 3193 /* higher 16bits of mode ctl regs are mask bits for change */ 3194 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3195 u32 mask = vgpu_vreg(vgpu, offset) >> 16; 3196 3197 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) 3198 | (vgpu_vreg(vgpu, offset) & mask); 3199 } 3200 } 3201 3202 return ret; 3203 3204 default_rw: 3205 return is_read ? 3206 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) : 3207 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes); 3208 } 3209 3210 void intel_gvt_restore_fence(struct intel_gvt *gvt) 3211 { 3212 struct intel_vgpu *vgpu; 3213 int i, id; 3214 3215 idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) { 3216 intel_wakeref_t wakeref; 3217 3218 wakeref = mmio_hw_access_pre(gvt->gt); 3219 for (i = 0; i < vgpu_fence_sz(vgpu); i++) 3220 intel_vgpu_write_fence(vgpu, i, vgpu_vreg64(vgpu, fence_num_to_offset(i))); 3221 mmio_hw_access_post(gvt->gt, wakeref); 3222 } 3223 } 3224 3225 static int mmio_pm_restore_handler(struct intel_gvt *gvt, u32 offset, void *data) 3226 { 3227 struct intel_vgpu *vgpu = data; 3228 struct drm_i915_private *dev_priv = gvt->gt->i915; 3229 3230 if (gvt->mmio.mmio_attribute[offset >> 2] & F_PM_SAVE) 3231 intel_uncore_write(&dev_priv->uncore, _MMIO(offset), vgpu_vreg(vgpu, offset)); 3232 3233 return 0; 3234 } 3235 3236 void intel_gvt_restore_mmio(struct intel_gvt *gvt) 3237 { 3238 struct intel_vgpu *vgpu; 3239 int id; 3240 3241 idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) { 3242 intel_wakeref_t wakeref; 3243 3244 wakeref = mmio_hw_access_pre(gvt->gt); 3245 intel_gvt_for_each_tracked_mmio(gvt, mmio_pm_restore_handler, vgpu); 3246 mmio_hw_access_post(gvt->gt, wakeref); 3247 } 3248 } 3249