1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <linux/pm_runtime.h> 7 #include <linux/string_helpers.h> 8 9 #include "gem/i915_gem_region.h" 10 #include "i915_drv.h" 11 #include "i915_reg.h" 12 #include "i915_vgpu.h" 13 #include "intel_engine_regs.h" 14 #include "intel_gt.h" 15 #include "intel_gt_pm.h" 16 #include "intel_gt_regs.h" 17 #include "intel_pcode.h" 18 #include "intel_rc6.h" 19 20 /** 21 * DOC: RC6 22 * 23 * RC6 is a special power stage which allows the GPU to enter an very 24 * low-voltage mode when idle, using down to 0V while at this stage. This 25 * stage is entered automatically when the GPU is idle when RC6 support is 26 * enabled, and as soon as new workload arises GPU wakes up automatically as 27 * well. 28 * 29 * There are different RC6 modes available in Intel GPU, which differentiate 30 * among each other with the latency required to enter and leave RC6 and 31 * voltage consumed by the GPU in different states. 32 * 33 * The combination of the following flags define which states GPU is allowed 34 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 35 * RC6pp is deepest RC6. Their support by hardware varies according to the 36 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 37 * which brings the most power savings; deeper states save more power, but 38 * require higher latency to switch to and wake up. 39 */ 40 41 static struct intel_gt *rc6_to_gt(struct intel_rc6 *rc6) 42 { 43 return container_of(rc6, struct intel_gt, rc6); 44 } 45 46 static struct intel_uncore *rc6_to_uncore(struct intel_rc6 *rc) 47 { 48 return rc6_to_gt(rc)->uncore; 49 } 50 51 static struct drm_i915_private *rc6_to_i915(struct intel_rc6 *rc) 52 { 53 return rc6_to_gt(rc)->i915; 54 } 55 56 static void gen11_rc6_enable(struct intel_rc6 *rc6) 57 { 58 struct intel_gt *gt = rc6_to_gt(rc6); 59 struct intel_uncore *uncore = gt->uncore; 60 struct intel_engine_cs *engine; 61 enum intel_engine_id id; 62 u32 pg_enable; 63 int i; 64 65 /* 66 * With GuCRC, these parameters are set by GuC 67 */ 68 if (!intel_uc_uses_guc_rc(>->uc)) { 69 /* 2b: Program RC6 thresholds.*/ 70 intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85); 71 intel_uncore_write_fw(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150); 72 73 intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 74 intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 75 for_each_engine(engine, rc6_to_gt(rc6), id) 76 intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 77 78 intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA); 79 80 intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0); 81 82 intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ 83 } 84 85 /* 86 * 2c: Program Coarse Power Gating Policies. 87 * 88 * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we 89 * use instead is a more conservative estimate for the maximum time 90 * it takes us to service a CS interrupt and submit a new ELSP - that 91 * is the time which the GPU is idle waiting for the CPU to select the 92 * next request to execute. If the idle hysteresis is less than that 93 * interrupt service latency, the hardware will automatically gate 94 * the power well and we will then incur the wake up cost on top of 95 * the service latency. A similar guide from plane_state is that we 96 * do not want the enable hysteresis to less than the wakeup latency. 97 * 98 * igt/gem_exec_nop/sequential provides a rough estimate for the 99 * service latency, and puts it under 10us for Icelake, similar to 100 * Broadwell+, To be conservative, we want to factor in a context 101 * switch on top (due to ksoftirqd). 102 */ 103 intel_uncore_write_fw(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60); 104 intel_uncore_write_fw(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60); 105 106 /* 3a: Enable RC6 107 * 108 * With GuCRC, we do not enable bit 31 of RC_CTL, 109 * thus allowing GuC to control RC6 entry/exit fully instead. 110 * We will not set the HW ENABLE and EI bits 111 */ 112 if (!intel_guc_rc_enable(gt_to_guc(gt))) 113 rc6->ctl_enable = GEN6_RC_CTL_RC6_ENABLE; 114 else 115 rc6->ctl_enable = 116 GEN6_RC_CTL_HW_ENABLE | 117 GEN6_RC_CTL_RC6_ENABLE | 118 GEN6_RC_CTL_EI_MODE(1); 119 120 pg_enable = 121 GEN9_RENDER_PG_ENABLE | 122 GEN9_MEDIA_PG_ENABLE | 123 GEN11_MEDIA_SAMPLER_PG_ENABLE; 124 125 if (GRAPHICS_VER(gt->i915) >= 12 && !IS_DG1(gt->i915)) { 126 for (i = 0; i < I915_MAX_VCS; i++) 127 if (HAS_ENGINE(gt, _VCS(i))) 128 pg_enable |= (VDN_HCP_POWERGATE_ENABLE(i) | 129 VDN_MFX_POWERGATE_ENABLE(i)); 130 } 131 132 intel_uncore_write_fw(uncore, GEN9_PG_ENABLE, pg_enable); 133 } 134 135 static void gen9_rc6_enable(struct intel_rc6 *rc6) 136 { 137 struct intel_uncore *uncore = rc6_to_uncore(rc6); 138 struct intel_engine_cs *engine; 139 enum intel_engine_id id; 140 141 /* 2b: Program RC6 thresholds.*/ 142 if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 11) { 143 intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85); 144 intel_uncore_write_fw(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150); 145 } else if (IS_SKYLAKE(rc6_to_i915(rc6))) { 146 /* 147 * WaRsDoubleRc6WrlWithCoarsePowerGating:skl Doubling WRL only 148 * when CPG is enabled 149 */ 150 intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16); 151 } else { 152 intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); 153 } 154 155 intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 156 intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 157 for_each_engine(engine, rc6_to_gt(rc6), id) 158 intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 159 160 intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA); 161 162 intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0); 163 164 /* 165 * 2c: Program Coarse Power Gating Policies. 166 * 167 * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we 168 * use instead is a more conservative estimate for the maximum time 169 * it takes us to service a CS interrupt and submit a new ELSP - that 170 * is the time which the GPU is idle waiting for the CPU to select the 171 * next request to execute. If the idle hysteresis is less than that 172 * interrupt service latency, the hardware will automatically gate 173 * the power well and we will then incur the wake up cost on top of 174 * the service latency. A similar guide from plane_state is that we 175 * do not want the enable hysteresis to less than the wakeup latency. 176 * 177 * igt/gem_exec_nop/sequential provides a rough estimate for the 178 * service latency, and puts it around 10us for Broadwell (and other 179 * big core) and around 40us for Broxton (and other low power cores). 180 * [Note that for legacy ringbuffer submission, this is less than 1us!] 181 * However, the wakeup latency on Broxton is closer to 100us. To be 182 * conservative, we have to factor in a context switch on top (due 183 * to ksoftirqd). 184 */ 185 intel_uncore_write_fw(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250); 186 intel_uncore_write_fw(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 250); 187 188 /* 3a: Enable RC6 */ 189 intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ 190 191 rc6->ctl_enable = 192 GEN6_RC_CTL_HW_ENABLE | 193 GEN6_RC_CTL_RC6_ENABLE | 194 GEN6_RC_CTL_EI_MODE(1); 195 196 /* 197 * WaRsDisableCoarsePowerGating:skl,cnl 198 * - Render/Media PG need to be disabled with RC6. 199 */ 200 if (!NEEDS_WaRsDisableCoarsePowerGating(rc6_to_i915(rc6))) 201 intel_uncore_write_fw(uncore, GEN9_PG_ENABLE, 202 GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE); 203 } 204 205 static void gen8_rc6_enable(struct intel_rc6 *rc6) 206 { 207 struct intel_uncore *uncore = rc6_to_uncore(rc6); 208 struct intel_engine_cs *engine; 209 enum intel_engine_id id; 210 211 /* 2b: Program RC6 thresholds.*/ 212 intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); 213 intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 214 intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 215 for_each_engine(engine, rc6_to_gt(rc6), id) 216 intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 217 intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0); 218 intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ 219 220 /* 3: Enable RC6 */ 221 rc6->ctl_enable = 222 GEN6_RC_CTL_HW_ENABLE | 223 GEN7_RC_CTL_TO_MODE | 224 GEN6_RC_CTL_RC6_ENABLE; 225 } 226 227 static void gen6_rc6_enable(struct intel_rc6 *rc6) 228 { 229 struct intel_uncore *uncore = rc6_to_uncore(rc6); 230 struct drm_i915_private *i915 = rc6_to_i915(rc6); 231 struct intel_engine_cs *engine; 232 enum intel_engine_id id; 233 u32 rc6vids, rc6_mask; 234 int ret; 235 236 intel_uncore_write_fw(uncore, GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); 237 intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); 238 intel_uncore_write_fw(uncore, GEN6_RC6pp_WAKE_RATE_LIMIT, 30); 239 intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); 240 intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); 241 242 for_each_engine(engine, rc6_to_gt(rc6), id) 243 intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 244 245 intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0); 246 intel_uncore_write_fw(uncore, GEN6_RC1e_THRESHOLD, 1000); 247 intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 50000); 248 intel_uncore_write_fw(uncore, GEN6_RC6p_THRESHOLD, 150000); 249 intel_uncore_write_fw(uncore, GEN6_RC6pp_THRESHOLD, 64000); /* unused */ 250 251 /* We don't use those on Haswell */ 252 rc6_mask = GEN6_RC_CTL_RC6_ENABLE; 253 if (HAS_RC6p(i915)) 254 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; 255 if (HAS_RC6pp(i915)) 256 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; 257 rc6->ctl_enable = 258 rc6_mask | 259 GEN6_RC_CTL_EI_MODE(1) | 260 GEN6_RC_CTL_HW_ENABLE; 261 262 rc6vids = 0; 263 ret = snb_pcode_read(rc6_to_gt(rc6)->uncore, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL); 264 if (GRAPHICS_VER(i915) == 6 && ret) { 265 drm_dbg(&i915->drm, "Couldn't check for BIOS workaround\n"); 266 } else if (GRAPHICS_VER(i915) == 6 && 267 (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { 268 drm_dbg(&i915->drm, 269 "You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", 270 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); 271 rc6vids &= 0xffff00; 272 rc6vids |= GEN6_ENCODE_RC6_VID(450); 273 ret = snb_pcode_write(rc6_to_gt(rc6)->uncore, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); 274 if (ret) 275 drm_err(&i915->drm, 276 "Couldn't fix incorrect rc6 voltage\n"); 277 } 278 } 279 280 /* Check that the pcbr address is not empty. */ 281 static int chv_rc6_init(struct intel_rc6 *rc6) 282 { 283 struct intel_uncore *uncore = rc6_to_uncore(rc6); 284 struct drm_i915_private *i915 = rc6_to_i915(rc6); 285 resource_size_t pctx_paddr, paddr; 286 resource_size_t pctx_size = 32 * SZ_1K; 287 u32 pcbr; 288 289 pcbr = intel_uncore_read(uncore, VLV_PCBR); 290 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { 291 drm_dbg(&i915->drm, "BIOS didn't set up PCBR, fixing up\n"); 292 paddr = i915->dsm.stolen.end + 1 - pctx_size; 293 GEM_BUG_ON(paddr > U32_MAX); 294 295 pctx_paddr = (paddr & ~4095); 296 intel_uncore_write(uncore, VLV_PCBR, pctx_paddr); 297 } 298 299 return 0; 300 } 301 302 static int vlv_rc6_init(struct intel_rc6 *rc6) 303 { 304 struct drm_i915_private *i915 = rc6_to_i915(rc6); 305 struct intel_uncore *uncore = rc6_to_uncore(rc6); 306 struct drm_i915_gem_object *pctx; 307 resource_size_t pctx_paddr; 308 resource_size_t pctx_size = 24 * SZ_1K; 309 u32 pcbr; 310 311 pcbr = intel_uncore_read(uncore, VLV_PCBR); 312 if (pcbr) { 313 /* BIOS set it up already, grab the pre-alloc'd space */ 314 resource_size_t pcbr_offset; 315 316 pcbr_offset = (pcbr & ~4095) - i915->dsm.stolen.start; 317 pctx = i915_gem_object_create_region_at(i915->mm.stolen_region, 318 pcbr_offset, 319 pctx_size, 320 0); 321 if (IS_ERR(pctx)) 322 return PTR_ERR(pctx); 323 324 goto out; 325 } 326 327 drm_dbg(&i915->drm, "BIOS didn't set up PCBR, fixing up\n"); 328 329 /* 330 * From the Gunit register HAS: 331 * The Gfx driver is expected to program this register and ensure 332 * proper allocation within Gfx stolen memory. For example, this 333 * register should be programmed such than the PCBR range does not 334 * overlap with other ranges, such as the frame buffer, protected 335 * memory, or any other relevant ranges. 336 */ 337 pctx = i915_gem_object_create_stolen(i915, pctx_size); 338 if (IS_ERR(pctx)) { 339 drm_dbg(&i915->drm, 340 "not enough stolen space for PCTX, disabling\n"); 341 return PTR_ERR(pctx); 342 } 343 344 GEM_BUG_ON(range_overflows_end_t(u64, 345 i915->dsm.stolen.start, 346 pctx->stolen->start, 347 U32_MAX)); 348 pctx_paddr = i915->dsm.stolen.start + pctx->stolen->start; 349 intel_uncore_write(uncore, VLV_PCBR, pctx_paddr); 350 351 out: 352 rc6->pctx = pctx; 353 return 0; 354 } 355 356 static void chv_rc6_enable(struct intel_rc6 *rc6) 357 { 358 struct intel_uncore *uncore = rc6_to_uncore(rc6); 359 struct intel_engine_cs *engine; 360 enum intel_engine_id id; 361 362 /* 2a: Program RC6 thresholds.*/ 363 intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); 364 intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 365 intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 366 367 for_each_engine(engine, rc6_to_gt(rc6), id) 368 intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 369 intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0); 370 371 /* TO threshold set to 500 us (0x186 * 1.28 us) */ 372 intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 0x186); 373 374 /* Allows RC6 residency counter to work */ 375 intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL, 376 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | 377 VLV_MEDIA_RC6_COUNT_EN | 378 VLV_RENDER_RC6_COUNT_EN)); 379 380 /* 3: Enable RC6 */ 381 rc6->ctl_enable = GEN7_RC_CTL_TO_MODE; 382 } 383 384 static void vlv_rc6_enable(struct intel_rc6 *rc6) 385 { 386 struct intel_uncore *uncore = rc6_to_uncore(rc6); 387 struct intel_engine_cs *engine; 388 enum intel_engine_id id; 389 390 intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); 391 intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); 392 intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); 393 394 for_each_engine(engine, rc6_to_gt(rc6), id) 395 intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10); 396 397 intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 0x557); 398 399 /* Allows RC6 residency counter to work */ 400 intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL, 401 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | 402 VLV_MEDIA_RC0_COUNT_EN | 403 VLV_RENDER_RC0_COUNT_EN | 404 VLV_MEDIA_RC6_COUNT_EN | 405 VLV_RENDER_RC6_COUNT_EN)); 406 407 rc6->ctl_enable = 408 GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; 409 } 410 411 bool intel_check_bios_c6_setup(struct intel_rc6 *rc6) 412 { 413 if (!rc6->bios_state_captured) { 414 struct intel_uncore *uncore = rc6_to_uncore(rc6); 415 intel_wakeref_t wakeref; 416 417 with_intel_runtime_pm(uncore->rpm, wakeref) 418 rc6->bios_rc_state = intel_uncore_read(uncore, GEN6_RC_STATE); 419 420 rc6->bios_state_captured = true; 421 } 422 423 return rc6->bios_rc_state & RC_SW_TARGET_STATE_MASK; 424 } 425 426 static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6) 427 { 428 struct intel_uncore *uncore = rc6_to_uncore(rc6); 429 struct drm_i915_private *i915 = rc6_to_i915(rc6); 430 u32 rc6_ctx_base, rc_ctl, rc_sw_target; 431 bool enable_rc6 = true; 432 433 rc_ctl = intel_uncore_read(uncore, GEN6_RC_CONTROL); 434 rc_sw_target = intel_uncore_read(uncore, GEN6_RC_STATE); 435 rc_sw_target &= RC_SW_TARGET_STATE_MASK; 436 rc_sw_target >>= RC_SW_TARGET_STATE_SHIFT; 437 drm_dbg(&i915->drm, "BIOS enabled RC states: " 438 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n", 439 str_on_off(rc_ctl & GEN6_RC_CTL_HW_ENABLE), 440 str_on_off(rc_ctl & GEN6_RC_CTL_RC6_ENABLE), 441 rc_sw_target); 442 443 if (!(intel_uncore_read(uncore, RC6_LOCATION) & RC6_CTX_IN_DRAM)) { 444 drm_dbg(&i915->drm, "RC6 Base location not set properly.\n"); 445 enable_rc6 = false; 446 } 447 448 /* 449 * The exact context size is not known for BXT, so assume a page size 450 * for this check. 451 */ 452 rc6_ctx_base = 453 intel_uncore_read(uncore, RC6_CTX_BASE) & RC6_CTX_BASE_MASK; 454 if (!(rc6_ctx_base >= i915->dsm.reserved.start && 455 rc6_ctx_base + PAGE_SIZE < i915->dsm.reserved.end)) { 456 drm_dbg(&i915->drm, "RC6 Base address not as expected.\n"); 457 enable_rc6 = false; 458 } 459 460 if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT(RENDER_RING_BASE)) & IDLE_TIME_MASK) > 1 && 461 (intel_uncore_read(uncore, PWRCTX_MAXCNT(GEN6_BSD_RING_BASE)) & IDLE_TIME_MASK) > 1 && 462 (intel_uncore_read(uncore, PWRCTX_MAXCNT(BLT_RING_BASE)) & IDLE_TIME_MASK) > 1 && 463 (intel_uncore_read(uncore, PWRCTX_MAXCNT(VEBOX_RING_BASE)) & IDLE_TIME_MASK) > 1)) { 464 drm_dbg(&i915->drm, 465 "Engine Idle wait time not set properly.\n"); 466 enable_rc6 = false; 467 } 468 469 if (!intel_uncore_read(uncore, GEN8_PUSHBUS_CONTROL) || 470 !intel_uncore_read(uncore, GEN8_PUSHBUS_ENABLE) || 471 !intel_uncore_read(uncore, GEN8_PUSHBUS_SHIFT)) { 472 drm_dbg(&i915->drm, "Pushbus not setup properly.\n"); 473 enable_rc6 = false; 474 } 475 476 if (!intel_uncore_read(uncore, GEN6_GFXPAUSE)) { 477 drm_dbg(&i915->drm, "GFX pause not setup properly.\n"); 478 enable_rc6 = false; 479 } 480 481 if (!intel_uncore_read(uncore, GEN8_MISC_CTRL0)) { 482 drm_dbg(&i915->drm, "GPM control not setup properly.\n"); 483 enable_rc6 = false; 484 } 485 486 return enable_rc6; 487 } 488 489 static bool rc6_supported(struct intel_rc6 *rc6) 490 { 491 struct drm_i915_private *i915 = rc6_to_i915(rc6); 492 struct intel_gt *gt = rc6_to_gt(rc6); 493 494 if (!HAS_RC6(i915)) 495 return false; 496 497 if (intel_vgpu_active(i915)) 498 return false; 499 500 if (is_mock_gt(rc6_to_gt(rc6))) 501 return false; 502 503 if (IS_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(rc6)) { 504 drm_notice(&i915->drm, 505 "RC6 and powersaving disabled by BIOS\n"); 506 return false; 507 } 508 509 if (IS_METEORLAKE(gt->i915) && 510 !intel_check_bios_c6_setup(rc6)) { 511 drm_notice(&i915->drm, 512 "C6 disabled by BIOS\n"); 513 return false; 514 } 515 516 if (IS_MEDIA_GT_IP_STEP(gt, IP_VER(13, 0), STEP_A0, STEP_B0)) { 517 drm_notice(&i915->drm, 518 "Media RC6 disabled on A step\n"); 519 return false; 520 } 521 522 return true; 523 } 524 525 static void rpm_get(struct intel_rc6 *rc6) 526 { 527 GEM_BUG_ON(rc6->wakeref); 528 pm_runtime_get_sync(rc6_to_i915(rc6)->drm.dev); 529 rc6->wakeref = true; 530 } 531 532 static void rpm_put(struct intel_rc6 *rc6) 533 { 534 GEM_BUG_ON(!rc6->wakeref); 535 pm_runtime_put(rc6_to_i915(rc6)->drm.dev); 536 rc6->wakeref = false; 537 } 538 539 static bool pctx_corrupted(struct intel_rc6 *rc6) 540 { 541 struct drm_i915_private *i915 = rc6_to_i915(rc6); 542 543 if (!NEEDS_RC6_CTX_CORRUPTION_WA(i915)) 544 return false; 545 546 if (intel_uncore_read(rc6_to_uncore(rc6), GEN8_RC6_CTX_INFO)) 547 return false; 548 549 drm_notice(&i915->drm, 550 "RC6 context corruption, disabling runtime power management\n"); 551 return true; 552 } 553 554 static void __intel_rc6_disable(struct intel_rc6 *rc6) 555 { 556 struct drm_i915_private *i915 = rc6_to_i915(rc6); 557 struct intel_uncore *uncore = rc6_to_uncore(rc6); 558 struct intel_gt *gt = rc6_to_gt(rc6); 559 560 /* Take control of RC6 back from GuC */ 561 intel_guc_rc_disable(gt_to_guc(gt)); 562 563 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 564 if (GRAPHICS_VER(i915) >= 9) 565 intel_uncore_write_fw(uncore, GEN9_PG_ENABLE, 0); 566 intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, 0); 567 intel_uncore_write_fw(uncore, GEN6_RC_STATE, 0); 568 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 569 } 570 571 static void rc6_res_reg_init(struct intel_rc6 *rc6) 572 { 573 i915_reg_t res_reg[INTEL_RC6_RES_MAX] = { 574 [0 ... INTEL_RC6_RES_MAX - 1] = INVALID_MMIO_REG, 575 }; 576 577 switch (rc6_to_gt(rc6)->type) { 578 case GT_MEDIA: 579 res_reg[INTEL_RC6_RES_RC6] = MTL_MEDIA_MC6; 580 break; 581 default: 582 res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED; 583 res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6; 584 res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p; 585 res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp; 586 break; 587 } 588 589 memcpy(rc6->res_reg, res_reg, sizeof(res_reg)); 590 } 591 592 void intel_rc6_init(struct intel_rc6 *rc6) 593 { 594 struct drm_i915_private *i915 = rc6_to_i915(rc6); 595 int err; 596 597 /* Disable runtime-pm until we can save the GPU state with rc6 pctx */ 598 rpm_get(rc6); 599 600 if (!rc6_supported(rc6)) 601 return; 602 603 rc6_res_reg_init(rc6); 604 605 if (IS_CHERRYVIEW(i915)) 606 err = chv_rc6_init(rc6); 607 else if (IS_VALLEYVIEW(i915)) 608 err = vlv_rc6_init(rc6); 609 else 610 err = 0; 611 612 /* Sanitize rc6, ensure it is disabled before we are ready. */ 613 __intel_rc6_disable(rc6); 614 615 rc6->supported = err == 0; 616 } 617 618 void intel_rc6_sanitize(struct intel_rc6 *rc6) 619 { 620 memset(rc6->prev_hw_residency, 0, sizeof(rc6->prev_hw_residency)); 621 622 if (rc6->enabled) { /* unbalanced suspend/resume */ 623 rpm_get(rc6); 624 rc6->enabled = false; 625 } 626 627 if (rc6->supported) 628 __intel_rc6_disable(rc6); 629 } 630 631 void intel_rc6_enable(struct intel_rc6 *rc6) 632 { 633 struct drm_i915_private *i915 = rc6_to_i915(rc6); 634 struct intel_uncore *uncore = rc6_to_uncore(rc6); 635 636 if (!rc6->supported) 637 return; 638 639 GEM_BUG_ON(rc6->enabled); 640 641 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 642 643 if (IS_CHERRYVIEW(i915)) 644 chv_rc6_enable(rc6); 645 else if (IS_VALLEYVIEW(i915)) 646 vlv_rc6_enable(rc6); 647 else if (GRAPHICS_VER(i915) >= 11) 648 gen11_rc6_enable(rc6); 649 else if (GRAPHICS_VER(i915) >= 9) 650 gen9_rc6_enable(rc6); 651 else if (IS_BROADWELL(i915)) 652 gen8_rc6_enable(rc6); 653 else if (GRAPHICS_VER(i915) >= 6) 654 gen6_rc6_enable(rc6); 655 656 rc6->manual = rc6->ctl_enable & GEN6_RC_CTL_RC6_ENABLE; 657 if (NEEDS_RC6_CTX_CORRUPTION_WA(i915)) 658 rc6->ctl_enable = 0; 659 660 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 661 662 if (unlikely(pctx_corrupted(rc6))) 663 return; 664 665 /* rc6 is ready, runtime-pm is go! */ 666 rpm_put(rc6); 667 rc6->enabled = true; 668 } 669 670 void intel_rc6_unpark(struct intel_rc6 *rc6) 671 { 672 struct intel_uncore *uncore = rc6_to_uncore(rc6); 673 674 if (!rc6->enabled) 675 return; 676 677 /* Restore HW timers for automatic RC6 entry while busy */ 678 intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, rc6->ctl_enable); 679 } 680 681 void intel_rc6_park(struct intel_rc6 *rc6) 682 { 683 struct intel_uncore *uncore = rc6_to_uncore(rc6); 684 unsigned int target; 685 686 if (!rc6->enabled) 687 return; 688 689 if (unlikely(pctx_corrupted(rc6))) { 690 intel_rc6_disable(rc6); 691 return; 692 } 693 694 if (!rc6->manual) 695 return; 696 697 /* Turn off the HW timers and go directly to rc6 */ 698 intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, GEN6_RC_CTL_RC6_ENABLE); 699 700 if (HAS_RC6pp(rc6_to_i915(rc6))) 701 target = 0x6; /* deepest rc6 */ 702 else if (HAS_RC6p(rc6_to_i915(rc6))) 703 target = 0x5; /* deep rc6 */ 704 else 705 target = 0x4; /* normal rc6 */ 706 intel_uncore_write_fw(uncore, GEN6_RC_STATE, target << RC_SW_TARGET_STATE_SHIFT); 707 } 708 709 void intel_rc6_disable(struct intel_rc6 *rc6) 710 { 711 if (!rc6->enabled) 712 return; 713 714 rpm_get(rc6); 715 rc6->enabled = false; 716 717 __intel_rc6_disable(rc6); 718 } 719 720 void intel_rc6_fini(struct intel_rc6 *rc6) 721 { 722 struct drm_i915_gem_object *pctx; 723 struct intel_uncore *uncore = rc6_to_uncore(rc6); 724 725 intel_rc6_disable(rc6); 726 727 /* We want the BIOS C6 state preserved across loads for MTL */ 728 if (IS_METEORLAKE(rc6_to_i915(rc6)) && rc6->bios_state_captured) 729 intel_uncore_write_fw(uncore, GEN6_RC_STATE, rc6->bios_rc_state); 730 731 pctx = fetch_and_zero(&rc6->pctx); 732 if (pctx) 733 i915_gem_object_put(pctx); 734 735 if (rc6->wakeref) 736 rpm_put(rc6); 737 } 738 739 static u64 vlv_residency_raw(struct intel_uncore *uncore, const i915_reg_t reg) 740 { 741 u32 lower, upper, tmp; 742 int loop = 2; 743 744 /* 745 * The register accessed do not need forcewake. We borrow 746 * uncore lock to prevent concurrent access to range reg. 747 */ 748 lockdep_assert_held(&uncore->lock); 749 750 /* 751 * vlv and chv residency counters are 40 bits in width. 752 * With a control bit, we can choose between upper or lower 753 * 32bit window into this counter. 754 * 755 * Although we always use the counter in high-range mode elsewhere, 756 * userspace may attempt to read the value before rc6 is initialised, 757 * before we have set the default VLV_COUNTER_CONTROL value. So always 758 * set the high bit to be safe. 759 */ 760 intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL, 761 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); 762 upper = intel_uncore_read_fw(uncore, reg); 763 do { 764 tmp = upper; 765 766 intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL, 767 _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH)); 768 lower = intel_uncore_read_fw(uncore, reg); 769 770 intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL, 771 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); 772 upper = intel_uncore_read_fw(uncore, reg); 773 } while (upper != tmp && --loop); 774 775 /* 776 * Everywhere else we always use VLV_COUNTER_CONTROL with the 777 * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set 778 * now. 779 */ 780 781 return lower | (u64)upper << 8; 782 } 783 784 u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, enum intel_rc6_res_type id) 785 { 786 struct drm_i915_private *i915 = rc6_to_i915(rc6); 787 struct intel_uncore *uncore = rc6_to_uncore(rc6); 788 u64 time_hw, prev_hw, overflow_hw; 789 i915_reg_t reg = rc6->res_reg[id]; 790 unsigned int fw_domains; 791 unsigned long flags; 792 u32 mul, div; 793 794 if (!rc6->supported) 795 return 0; 796 797 fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ); 798 799 spin_lock_irqsave(&uncore->lock, flags); 800 intel_uncore_forcewake_get__locked(uncore, fw_domains); 801 802 /* On VLV and CHV, residency time is in CZ units rather than 1.28us */ 803 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 804 mul = 1000000; 805 div = i915->czclk_freq; 806 overflow_hw = BIT_ULL(40); 807 time_hw = vlv_residency_raw(uncore, reg); 808 } else { 809 /* 833.33ns units on Gen9LP, 1.28us elsewhere. */ 810 if (IS_GEN9_LP(i915)) { 811 mul = 10000; 812 div = 12; 813 } else { 814 mul = 1280; 815 div = 1; 816 } 817 818 overflow_hw = BIT_ULL(32); 819 time_hw = intel_uncore_read_fw(uncore, reg); 820 } 821 822 /* 823 * Counter wrap handling. 824 * 825 * Store previous hw counter values for counter wrap-around handling. But 826 * relying on a sufficient frequency of queries otherwise counters can still wrap. 827 */ 828 prev_hw = rc6->prev_hw_residency[id]; 829 rc6->prev_hw_residency[id] = time_hw; 830 831 /* RC6 delta from last sample. */ 832 if (time_hw >= prev_hw) 833 time_hw -= prev_hw; 834 else 835 time_hw += overflow_hw - prev_hw; 836 837 /* Add delta to RC6 extended raw driver copy. */ 838 time_hw += rc6->cur_residency[id]; 839 rc6->cur_residency[id] = time_hw; 840 841 intel_uncore_forcewake_put__locked(uncore, fw_domains); 842 spin_unlock_irqrestore(&uncore->lock, flags); 843 844 return mul_u64_u32_div(time_hw, mul, div); 845 } 846 847 u64 intel_rc6_residency_us(struct intel_rc6 *rc6, enum intel_rc6_res_type id) 848 { 849 return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, id), 1000); 850 } 851 852 void intel_rc6_print_residency(struct seq_file *m, const char *title, 853 enum intel_rc6_res_type id) 854 { 855 struct intel_gt *gt = m->private; 856 i915_reg_t reg = gt->rc6.res_reg[id]; 857 intel_wakeref_t wakeref; 858 859 with_intel_runtime_pm(gt->uncore->rpm, wakeref) 860 seq_printf(m, "%s %u (%llu us)\n", title, 861 intel_uncore_read(gt->uncore, reg), 862 intel_rc6_residency_us(>->rc6, id)); 863 } 864 865 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 866 #include "selftest_rc6.c" 867 #endif 868