1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2018 Intel Corporation 4 * 5 * Author: Gaurav K Singh <gaurav.k.singh@intel.com> 6 * Manasi Navare <manasi.d.navare@intel.com> 7 */ 8 #include <linux/limits.h> 9 10 #include <drm/display/drm_dsc_helper.h> 11 #include <drm/drm_fixed.h> 12 #include <drm/drm_print.h> 13 14 #include "i915_utils.h" 15 #include "intel_crtc.h" 16 #include "intel_de.h" 17 #include "intel_display_types.h" 18 #include "intel_dp.h" 19 #include "intel_dsi.h" 20 #include "intel_qp_tables.h" 21 #include "intel_vdsc.h" 22 #include "intel_vdsc_regs.h" 23 24 bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state) 25 { 26 struct intel_display *display = to_intel_display(crtc_state); 27 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 28 29 if (!HAS_DSC(display)) 30 return false; 31 32 if (DISPLAY_VER(display) == 11 && cpu_transcoder == TRANSCODER_A) 33 return false; 34 35 return true; 36 } 37 38 static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder) 39 { 40 struct intel_display *display = to_intel_display(crtc); 41 42 if (DISPLAY_VER(display) >= 12) 43 return true; 44 45 if (cpu_transcoder == TRANSCODER_EDP || 46 cpu_transcoder == TRANSCODER_DSI_0 || 47 cpu_transcoder == TRANSCODER_DSI_1) 48 return false; 49 50 /* There's no pipe A DSC engine on ICL */ 51 drm_WARN_ON(display->drm, crtc->pipe == PIPE_A); 52 53 return true; 54 } 55 56 static void 57 intel_vdsc_set_min_max_qp(struct drm_dsc_config *vdsc_cfg, int buf, 58 int bpp) 59 { 60 int bpc = vdsc_cfg->bits_per_component; 61 62 /* Read range_minqp and range_max_qp from qp tables */ 63 vdsc_cfg->rc_range_params[buf].range_min_qp = 64 intel_lookup_range_min_qp(bpc, buf, bpp, vdsc_cfg->native_420); 65 vdsc_cfg->rc_range_params[buf].range_max_qp = 66 intel_lookup_range_max_qp(bpc, buf, bpp, vdsc_cfg->native_420); 67 } 68 69 static int 70 get_range_bpg_offset(int bpp_low, int offset_low, int bpp_high, int offset_high, int bpp) 71 { 72 return offset_low + DIV_ROUND_UP((offset_high - offset_low) * (bpp - bpp_low), 73 (bpp_low - bpp_high)); 74 } 75 76 /* 77 * We are using the method provided in DSC 1.2a C-Model in codec_main.c 78 * Above method use a common formula to derive values for any combination of DSC 79 * variables. The formula approach may yield slight differences in the derived PPS 80 * parameters from the original parameter sets. These differences are not consequential 81 * to the coding performance because all parameter sets have been shown to produce 82 * visually lossless quality (provides the same PPS values as 83 * DSCParameterValuesVESA V1-2 spreadsheet). 84 */ 85 static void 86 calculate_rc_params(struct drm_dsc_config *vdsc_cfg) 87 { 88 int bpp = fxp_q4_to_int(vdsc_cfg->bits_per_pixel); 89 int bpc = vdsc_cfg->bits_per_component; 90 int qp_bpc_modifier = (bpc - 8) * 2; 91 int uncompressed_bpg_rate; 92 int first_line_bpg_offset; 93 u32 buf_i, bpp_i; 94 95 if (vdsc_cfg->slice_height >= 8) 96 first_line_bpg_offset = 97 12 + (9 * min(34, vdsc_cfg->slice_height - 8)) / 100; 98 else 99 first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1); 100 101 uncompressed_bpg_rate = (3 * bpc + (vdsc_cfg->convert_rgb ? 0 : 2)) * 3; 102 vdsc_cfg->first_line_bpg_offset = clamp(first_line_bpg_offset, 0, 103 uncompressed_bpg_rate - 3 * bpp); 104 105 /* 106 * According to DSC 1.2 spec in Section 4.1 if native_420 is set: 107 * -second_line_bpg_offset is 12 in general and equal to 2*(slice_height-1) if slice 108 * height < 8. 109 * -second_line_offset_adj is 512 as shown by empirical values to yield best chroma 110 * preservation in second line. 111 * -nsl_bpg_offset is calculated as second_line_offset/slice_height -1 then rounded 112 * up to 16 fractional bits, we left shift second line offset by 11 to preserve 11 113 * fractional bits. 114 */ 115 if (vdsc_cfg->native_420) { 116 if (vdsc_cfg->slice_height >= 8) 117 vdsc_cfg->second_line_bpg_offset = 12; 118 else 119 vdsc_cfg->second_line_bpg_offset = 120 2 * (vdsc_cfg->slice_height - 1); 121 122 vdsc_cfg->second_line_offset_adj = 512; 123 vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP(vdsc_cfg->second_line_bpg_offset << 11, 124 vdsc_cfg->slice_height - 1); 125 } 126 127 if (bpp >= 12) 128 vdsc_cfg->initial_offset = 2048; 129 else if (bpp >= 10) 130 vdsc_cfg->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2); 131 else if (bpp >= 8) 132 vdsc_cfg->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2); 133 else 134 vdsc_cfg->initial_offset = 6144; 135 136 /* initial_xmit_delay = rc_model_size/2/compression_bpp */ 137 vdsc_cfg->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp); 138 139 vdsc_cfg->flatness_min_qp = 3 + qp_bpc_modifier; 140 vdsc_cfg->flatness_max_qp = 12 + qp_bpc_modifier; 141 142 vdsc_cfg->rc_quant_incr_limit0 = 11 + qp_bpc_modifier; 143 vdsc_cfg->rc_quant_incr_limit1 = 11 + qp_bpc_modifier; 144 145 if (vdsc_cfg->native_420) { 146 static const s8 ofs_und4[] = { 147 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 148 }; 149 static const s8 ofs_und5[] = { 150 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 151 }; 152 static const s8 ofs_und6[] = { 153 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 154 }; 155 static const s8 ofs_und8[] = { 156 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 157 }; 158 /* 159 * For 420 format since bits_per_pixel (bpp) is set to target bpp * 2, 160 * QP table values for target bpp 4.0 to 4.4375 (rounded to 4.0) are 161 * actually for bpp 8 to 8.875 (rounded to 4.0 * 2 i.e 8). 162 * Similarly values for target bpp 4.5 to 4.8375 (rounded to 4.5) 163 * are for bpp 9 to 9.875 (rounded to 4.5 * 2 i.e 9), and so on. 164 */ 165 bpp_i = bpp - 8; 166 for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) { 167 u8 range_bpg_offset; 168 169 intel_vdsc_set_min_max_qp(vdsc_cfg, buf_i, bpp_i); 170 171 /* Calculate range_bpg_offset */ 172 if (bpp <= 8) 173 range_bpg_offset = ofs_und4[buf_i]; 174 else if (bpp <= 10) 175 range_bpg_offset = get_range_bpg_offset(8, ofs_und4[buf_i], 176 10, ofs_und5[buf_i], bpp); 177 else if (bpp <= 12) 178 range_bpg_offset = get_range_bpg_offset(10, ofs_und5[buf_i], 179 12, ofs_und6[buf_i], bpp); 180 else if (bpp <= 16) 181 range_bpg_offset = get_range_bpg_offset(12, ofs_und6[buf_i], 182 16, ofs_und8[buf_i], bpp); 183 else 184 range_bpg_offset = ofs_und8[buf_i]; 185 186 vdsc_cfg->rc_range_params[buf_i].range_bpg_offset = 187 range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK; 188 } 189 } else { 190 /* fractional bpp part * 10000 (for precision up to 4 decimal places) */ 191 int fractional_bits = fxp_q4_to_frac(vdsc_cfg->bits_per_pixel); 192 193 static const s8 ofs_und6[] = { 194 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 195 }; 196 static const s8 ofs_und8[] = { 197 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 198 }; 199 static const s8 ofs_und12[] = { 200 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 201 }; 202 static const s8 ofs_und15[] = { 203 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 204 }; 205 206 /* 207 * QP table rows have values in increment of 0.5. 208 * So 6.0 bpp to 6.4375 will have index 0, 6.5 to 6.9375 will have index 1, 209 * and so on. 210 * 0.5 fractional part with 4 decimal precision becomes 5000 211 */ 212 bpp_i = ((bpp - 6) + (fractional_bits < 5000 ? 0 : 1)); 213 214 for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) { 215 u8 range_bpg_offset; 216 217 intel_vdsc_set_min_max_qp(vdsc_cfg, buf_i, bpp_i); 218 219 /* Calculate range_bpg_offset */ 220 if (bpp <= 6) 221 range_bpg_offset = ofs_und6[buf_i]; 222 else if (bpp <= 8) 223 range_bpg_offset = get_range_bpg_offset(6, ofs_und6[buf_i], 224 8, ofs_und8[buf_i], bpp); 225 else if (bpp <= 12) 226 range_bpg_offset = get_range_bpg_offset(8, ofs_und8[buf_i], 227 12, ofs_und12[buf_i], bpp); 228 else if (bpp <= 15) 229 range_bpg_offset = get_range_bpg_offset(12, ofs_und12[buf_i], 230 15, ofs_und15[buf_i], bpp); 231 else 232 range_bpg_offset = ofs_und15[buf_i]; 233 234 vdsc_cfg->rc_range_params[buf_i].range_bpg_offset = 235 range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK; 236 } 237 } 238 } 239 240 static int intel_dsc_slice_dimensions_valid(struct intel_crtc_state *pipe_config, 241 struct drm_dsc_config *vdsc_cfg) 242 { 243 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_RGB || 244 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) { 245 if (vdsc_cfg->slice_height > 4095) 246 return -EINVAL; 247 if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 15000) 248 return -EINVAL; 249 } else if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 250 if (vdsc_cfg->slice_width % 2) 251 return -EINVAL; 252 if (vdsc_cfg->slice_height % 2) 253 return -EINVAL; 254 if (vdsc_cfg->slice_height > 4094) 255 return -EINVAL; 256 if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 30000) 257 return -EINVAL; 258 } 259 260 return 0; 261 } 262 263 static bool is_dsi_dsc_1_1(struct intel_crtc_state *crtc_state) 264 { 265 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 266 267 return vdsc_cfg->dsc_version_major == 1 && 268 vdsc_cfg->dsc_version_minor == 1 && 269 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI); 270 } 271 272 int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) 273 { 274 struct intel_display *display = to_intel_display(pipe_config); 275 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; 276 u16 compressed_bpp = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16); 277 int err; 278 int ret; 279 280 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; 281 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, 282 pipe_config->dsc.slice_count); 283 284 err = intel_dsc_slice_dimensions_valid(pipe_config, vdsc_cfg); 285 286 if (err) { 287 drm_dbg_kms(display->drm, "Slice dimension requirements not met\n"); 288 return err; 289 } 290 291 /* 292 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0 293 * else 1 294 */ 295 vdsc_cfg->convert_rgb = pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR420 && 296 pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR444; 297 298 if (DISPLAY_VER(display) >= 14 && 299 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 300 vdsc_cfg->native_420 = true; 301 /* We do not support YcBCr422 as of now */ 302 vdsc_cfg->native_422 = false; 303 vdsc_cfg->simple_422 = false; 304 /* Gen 11 does not support VBR */ 305 vdsc_cfg->vbr_enable = false; 306 307 vdsc_cfg->bits_per_pixel = pipe_config->dsc.compressed_bpp_x16; 308 309 /* 310 * According to DSC 1.2 specs in Section 4.1 if native_420 is set 311 * we need to double the current bpp. 312 */ 313 if (vdsc_cfg->native_420) 314 vdsc_cfg->bits_per_pixel <<= 1; 315 316 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; 317 318 if (vdsc_cfg->bits_per_component < 8) { 319 drm_dbg_kms(display->drm, "DSC bpc requirements not met bpc: %d\n", 320 vdsc_cfg->bits_per_component); 321 return -EINVAL; 322 } 323 324 drm_dsc_set_rc_buf_thresh(vdsc_cfg); 325 326 /* 327 * From XE_LPD onwards we supports compression bpps in steps of 1 328 * upto uncompressed bpp-1, hence add calculations for all the rc 329 * parameters 330 * 331 * We don't want to calculate all rc parameters when the panel 332 * is MIPI DSI and it's using DSC 1.1. The reason being that some 333 * DSI panels vendors have hardcoded PPS params in the VBT causing 334 * the parameters sent from the source which are derived through 335 * interpolation to differ from the params the panel expects. 336 * This causes a noise in the display. 337 * Furthermore for DSI panels we are currently using bits_per_pixel 338 * (compressed bpp) hardcoded from VBT, (unlike other encoders where we 339 * find the optimum compressed bpp) so dont need to rely on interpolation, 340 * as we can get the required rc parameters from the tables. 341 */ 342 if (DISPLAY_VER(display) >= 13 && !is_dsi_dsc_1_1(pipe_config)) { 343 calculate_rc_params(vdsc_cfg); 344 } else { 345 if ((compressed_bpp == 8 || 346 compressed_bpp == 12) && 347 (vdsc_cfg->bits_per_component == 8 || 348 vdsc_cfg->bits_per_component == 10 || 349 vdsc_cfg->bits_per_component == 12)) 350 ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_1_PRE_SCR); 351 else 352 ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_2_444); 353 354 if (ret) 355 return ret; 356 } 357 358 /* 359 * BitsPerComponent value determines mux_word_size: 360 * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to 361 * 48 bits otherwise 64 362 */ 363 if (vdsc_cfg->bits_per_component <= 10) 364 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; 365 else 366 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; 367 368 /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */ 369 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / 370 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); 371 372 return 0; 373 } 374 375 enum intel_display_power_domain 376 intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder) 377 { 378 struct intel_display *display = to_intel_display(crtc); 379 enum pipe pipe = crtc->pipe; 380 381 /* 382 * VDSC/joining uses a separate power well, PW2, and requires 383 * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases: 384 * 385 * - ICL eDP/DSI transcoder 386 * - Display version 12 (except RKL) pipe A 387 * 388 * For any other pipe, VDSC/joining uses the power well associated with 389 * the pipe in use. Hence another reference on the pipe power domain 390 * will suffice. (Except no VDSC/joining on ICL pipe A.) 391 */ 392 if (DISPLAY_VER(display) == 12 && !display->platform.rocketlake && 393 pipe == PIPE_A) 394 return POWER_DOMAIN_TRANSCODER_VDSC_PW2; 395 else if (is_pipe_dsc(crtc, cpu_transcoder)) 396 return POWER_DOMAIN_PIPE(pipe); 397 else 398 return POWER_DOMAIN_TRANSCODER_VDSC_PW2; 399 } 400 401 static int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state) 402 { 403 return crtc_state->dsc.num_streams; 404 } 405 406 int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state) 407 { 408 int num_vdsc_instances = intel_dsc_get_vdsc_per_pipe(crtc_state); 409 int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state); 410 411 num_vdsc_instances *= num_joined_pipes; 412 413 return num_vdsc_instances; 414 } 415 416 static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int pps, 417 i915_reg_t *dsc_reg, int dsc_reg_num) 418 { 419 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 420 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 421 enum pipe pipe = crtc->pipe; 422 bool pipe_dsc; 423 424 pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder); 425 426 if (dsc_reg_num >= 4) 427 MISSING_CASE(dsc_reg_num); 428 if (dsc_reg_num >= 3) 429 dsc_reg[2] = BMG_DSC2_PPS(pipe, pps); 430 if (dsc_reg_num >= 2) 431 dsc_reg[1] = pipe_dsc ? ICL_DSC1_PPS(pipe, pps) : DSCC_PPS(pps); 432 if (dsc_reg_num >= 1) 433 dsc_reg[0] = pipe_dsc ? ICL_DSC0_PPS(pipe, pps) : DSCA_PPS(pps); 434 } 435 436 static void intel_dsc_pps_write(const struct intel_crtc_state *crtc_state, 437 int pps, u32 pps_val) 438 { 439 struct intel_display *display = to_intel_display(crtc_state); 440 i915_reg_t dsc_reg[3]; 441 int i, vdsc_per_pipe, dsc_reg_num; 442 443 vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); 444 dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe); 445 446 drm_WARN_ON_ONCE(display->drm, dsc_reg_num < vdsc_per_pipe); 447 448 intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num); 449 450 for (i = 0; i < dsc_reg_num; i++) 451 intel_de_write(display, dsc_reg[i], pps_val); 452 } 453 454 static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) 455 { 456 struct intel_display *display = to_intel_display(crtc_state); 457 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 458 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 459 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 460 enum pipe pipe = crtc->pipe; 461 u32 pps_val; 462 u32 rc_buf_thresh_dword[4]; 463 u32 rc_range_params_dword[8]; 464 int i = 0; 465 int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state); 466 int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); 467 468 /* PPS 0 */ 469 pps_val = DSC_PPS0_VER_MAJOR(1) | 470 DSC_PPS0_VER_MINOR(vdsc_cfg->dsc_version_minor) | 471 DSC_PPS0_BPC(vdsc_cfg->bits_per_component) | 472 DSC_PPS0_LINE_BUF_DEPTH(vdsc_cfg->line_buf_depth); 473 if (vdsc_cfg->dsc_version_minor == 2) { 474 pps_val |= DSC_PPS0_ALT_ICH_SEL; 475 if (vdsc_cfg->native_420) 476 pps_val |= DSC_PPS0_NATIVE_420_ENABLE; 477 if (vdsc_cfg->native_422) 478 pps_val |= DSC_PPS0_NATIVE_422_ENABLE; 479 } 480 if (vdsc_cfg->block_pred_enable) 481 pps_val |= DSC_PPS0_BLOCK_PREDICTION; 482 if (vdsc_cfg->convert_rgb) 483 pps_val |= DSC_PPS0_COLOR_SPACE_CONVERSION; 484 if (vdsc_cfg->simple_422) 485 pps_val |= DSC_PPS0_422_ENABLE; 486 if (vdsc_cfg->vbr_enable) 487 pps_val |= DSC_PPS0_VBR_ENABLE; 488 intel_dsc_pps_write(crtc_state, 0, pps_val); 489 490 /* PPS 1 */ 491 pps_val = DSC_PPS1_BPP(vdsc_cfg->bits_per_pixel); 492 intel_dsc_pps_write(crtc_state, 1, pps_val); 493 494 /* PPS 2 */ 495 pps_val = DSC_PPS2_PIC_HEIGHT(vdsc_cfg->pic_height) | 496 DSC_PPS2_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); 497 intel_dsc_pps_write(crtc_state, 2, pps_val); 498 499 /* PPS 3 */ 500 pps_val = DSC_PPS3_SLICE_HEIGHT(vdsc_cfg->slice_height) | 501 DSC_PPS3_SLICE_WIDTH(vdsc_cfg->slice_width); 502 intel_dsc_pps_write(crtc_state, 3, pps_val); 503 504 /* PPS 4 */ 505 pps_val = DSC_PPS4_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | 506 DSC_PPS4_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); 507 intel_dsc_pps_write(crtc_state, 4, pps_val); 508 509 /* PPS 5 */ 510 pps_val = DSC_PPS5_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | 511 DSC_PPS5_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); 512 intel_dsc_pps_write(crtc_state, 5, pps_val); 513 514 /* PPS 6 */ 515 pps_val = DSC_PPS6_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | 516 DSC_PPS6_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) | 517 DSC_PPS6_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | 518 DSC_PPS6_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); 519 intel_dsc_pps_write(crtc_state, 6, pps_val); 520 521 /* PPS 7 */ 522 pps_val = DSC_PPS7_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | 523 DSC_PPS7_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); 524 intel_dsc_pps_write(crtc_state, 7, pps_val); 525 526 /* PPS 8 */ 527 pps_val = DSC_PPS8_FINAL_OFFSET(vdsc_cfg->final_offset) | 528 DSC_PPS8_INITIAL_OFFSET(vdsc_cfg->initial_offset); 529 intel_dsc_pps_write(crtc_state, 8, pps_val); 530 531 /* PPS 9 */ 532 pps_val = DSC_PPS9_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) | 533 DSC_PPS9_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); 534 intel_dsc_pps_write(crtc_state, 9, pps_val); 535 536 /* PPS 10 */ 537 pps_val = DSC_PPS10_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) | 538 DSC_PPS10_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | 539 DSC_PPS10_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | 540 DSC_PPS10_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); 541 intel_dsc_pps_write(crtc_state, 10, pps_val); 542 543 /* PPS 16 */ 544 pps_val = DSC_PPS16_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | 545 DSC_PPS16_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) / 546 vdsc_cfg->slice_width) | 547 DSC_PPS16_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / 548 vdsc_cfg->slice_height); 549 intel_dsc_pps_write(crtc_state, 16, pps_val); 550 551 if (DISPLAY_VER(display) >= 14) { 552 /* PPS 17 */ 553 pps_val = DSC_PPS17_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset); 554 intel_dsc_pps_write(crtc_state, 17, pps_val); 555 556 /* PPS 18 */ 557 pps_val = DSC_PPS18_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) | 558 DSC_PPS18_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj); 559 intel_dsc_pps_write(crtc_state, 18, pps_val); 560 } 561 562 /* Populate the RC_BUF_THRESH registers */ 563 memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword)); 564 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) 565 rc_buf_thresh_dword[i / 4] |= 566 (u32)(vdsc_cfg->rc_buf_thresh[i] << 567 BITS_PER_BYTE * (i % 4)); 568 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 569 intel_de_write(display, DSCA_RC_BUF_THRESH_0, 570 rc_buf_thresh_dword[0]); 571 intel_de_write(display, DSCA_RC_BUF_THRESH_0_UDW, 572 rc_buf_thresh_dword[1]); 573 intel_de_write(display, DSCA_RC_BUF_THRESH_1, 574 rc_buf_thresh_dword[2]); 575 intel_de_write(display, DSCA_RC_BUF_THRESH_1_UDW, 576 rc_buf_thresh_dword[3]); 577 if (vdsc_instances_per_pipe > 1) { 578 intel_de_write(display, DSCC_RC_BUF_THRESH_0, 579 rc_buf_thresh_dword[0]); 580 intel_de_write(display, DSCC_RC_BUF_THRESH_0_UDW, 581 rc_buf_thresh_dword[1]); 582 intel_de_write(display, DSCC_RC_BUF_THRESH_1, 583 rc_buf_thresh_dword[2]); 584 intel_de_write(display, DSCC_RC_BUF_THRESH_1_UDW, 585 rc_buf_thresh_dword[3]); 586 } 587 } else { 588 intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_0(pipe), 589 rc_buf_thresh_dword[0]); 590 intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe), 591 rc_buf_thresh_dword[1]); 592 intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_1(pipe), 593 rc_buf_thresh_dword[2]); 594 intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe), 595 rc_buf_thresh_dword[3]); 596 if (vdsc_instances_per_pipe > 1) { 597 intel_de_write(display, 598 ICL_DSC1_RC_BUF_THRESH_0(pipe), 599 rc_buf_thresh_dword[0]); 600 intel_de_write(display, 601 ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe), 602 rc_buf_thresh_dword[1]); 603 intel_de_write(display, 604 ICL_DSC1_RC_BUF_THRESH_1(pipe), 605 rc_buf_thresh_dword[2]); 606 intel_de_write(display, 607 ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe), 608 rc_buf_thresh_dword[3]); 609 } 610 } 611 612 /* Populate the RC_RANGE_PARAMETERS registers */ 613 memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword)); 614 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) 615 rc_range_params_dword[i / 2] |= 616 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset << 617 RC_BPG_OFFSET_SHIFT) | 618 (vdsc_cfg->rc_range_params[i].range_max_qp << 619 RC_MAX_QP_SHIFT) | 620 (vdsc_cfg->rc_range_params[i].range_min_qp << 621 RC_MIN_QP_SHIFT)) << 16 * (i % 2)); 622 if (!is_pipe_dsc(crtc, cpu_transcoder)) { 623 intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_0, 624 rc_range_params_dword[0]); 625 intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_0_UDW, 626 rc_range_params_dword[1]); 627 intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_1, 628 rc_range_params_dword[2]); 629 intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_1_UDW, 630 rc_range_params_dword[3]); 631 intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_2, 632 rc_range_params_dword[4]); 633 intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_2_UDW, 634 rc_range_params_dword[5]); 635 intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_3, 636 rc_range_params_dword[6]); 637 intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_3_UDW, 638 rc_range_params_dword[7]); 639 if (vdsc_instances_per_pipe > 1) { 640 intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_0, 641 rc_range_params_dword[0]); 642 intel_de_write(display, 643 DSCC_RC_RANGE_PARAMETERS_0_UDW, 644 rc_range_params_dword[1]); 645 intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_1, 646 rc_range_params_dword[2]); 647 intel_de_write(display, 648 DSCC_RC_RANGE_PARAMETERS_1_UDW, 649 rc_range_params_dword[3]); 650 intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_2, 651 rc_range_params_dword[4]); 652 intel_de_write(display, 653 DSCC_RC_RANGE_PARAMETERS_2_UDW, 654 rc_range_params_dword[5]); 655 intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_3, 656 rc_range_params_dword[6]); 657 intel_de_write(display, 658 DSCC_RC_RANGE_PARAMETERS_3_UDW, 659 rc_range_params_dword[7]); 660 } 661 } else { 662 intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe), 663 rc_range_params_dword[0]); 664 intel_de_write(display, 665 ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe), 666 rc_range_params_dword[1]); 667 intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe), 668 rc_range_params_dword[2]); 669 intel_de_write(display, 670 ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe), 671 rc_range_params_dword[3]); 672 intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe), 673 rc_range_params_dword[4]); 674 intel_de_write(display, 675 ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe), 676 rc_range_params_dword[5]); 677 intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe), 678 rc_range_params_dword[6]); 679 intel_de_write(display, 680 ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe), 681 rc_range_params_dword[7]); 682 if (vdsc_instances_per_pipe > 1) { 683 intel_de_write(display, 684 ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe), 685 rc_range_params_dword[0]); 686 intel_de_write(display, 687 ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe), 688 rc_range_params_dword[1]); 689 intel_de_write(display, 690 ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe), 691 rc_range_params_dword[2]); 692 intel_de_write(display, 693 ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe), 694 rc_range_params_dword[3]); 695 intel_de_write(display, 696 ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe), 697 rc_range_params_dword[4]); 698 intel_de_write(display, 699 ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe), 700 rc_range_params_dword[5]); 701 intel_de_write(display, 702 ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe), 703 rc_range_params_dword[6]); 704 intel_de_write(display, 705 ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe), 706 rc_range_params_dword[7]); 707 } 708 } 709 } 710 711 void intel_dsc_dsi_pps_write(struct intel_encoder *encoder, 712 const struct intel_crtc_state *crtc_state) 713 { 714 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 715 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 716 struct mipi_dsi_device *dsi; 717 struct drm_dsc_picture_parameter_set pps; 718 enum port port; 719 720 if (!crtc_state->dsc.compression_enable) 721 return; 722 723 drm_dsc_pps_payload_pack(&pps, vdsc_cfg); 724 725 for_each_dsi_port(port, intel_dsi->ports) { 726 dsi = intel_dsi->dsi_hosts[port]->device; 727 728 mipi_dsi_picture_parameter_set(dsi, &pps); 729 mipi_dsi_compression_mode(dsi, true); 730 } 731 } 732 733 void intel_dsc_dp_pps_write(struct intel_encoder *encoder, 734 const struct intel_crtc_state *crtc_state) 735 { 736 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 737 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 738 struct drm_dsc_pps_infoframe dp_dsc_pps_sdp; 739 740 if (!crtc_state->dsc.compression_enable) 741 return; 742 743 /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */ 744 drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp.pps_header); 745 746 /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */ 747 drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg); 748 749 dig_port->write_infoframe(encoder, crtc_state, 750 DP_SDP_PPS, &dp_dsc_pps_sdp, 751 sizeof(dp_dsc_pps_sdp)); 752 } 753 754 static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder) 755 { 756 return is_pipe_dsc(crtc, cpu_transcoder) ? 757 ICL_PIPE_DSS_CTL1(crtc->pipe) : DSS_CTL1; 758 } 759 760 static i915_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder) 761 { 762 return is_pipe_dsc(crtc, cpu_transcoder) ? 763 ICL_PIPE_DSS_CTL2(crtc->pipe) : DSS_CTL2; 764 } 765 766 void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state) 767 { 768 struct intel_display *display = to_intel_display(crtc_state); 769 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 770 u32 dss_ctl1_val = 0; 771 772 if (crtc_state->joiner_pipes && !crtc_state->dsc.compression_enable) { 773 if (intel_crtc_is_bigjoiner_secondary(crtc_state)) 774 dss_ctl1_val |= UNCOMPRESSED_JOINER_SECONDARY; 775 else 776 dss_ctl1_val |= UNCOMPRESSED_JOINER_PRIMARY; 777 778 intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), 779 dss_ctl1_val); 780 } 781 } 782 783 void intel_dsc_enable(const struct intel_crtc_state *crtc_state) 784 { 785 struct intel_display *display = to_intel_display(crtc_state); 786 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 787 u32 dss_ctl1_val = 0; 788 u32 dss_ctl2_val = 0; 789 int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); 790 791 if (!crtc_state->dsc.compression_enable) 792 return; 793 794 intel_dsc_pps_configure(crtc_state); 795 796 dss_ctl2_val |= VDSC0_ENABLE; 797 if (vdsc_instances_per_pipe > 1) { 798 dss_ctl2_val |= VDSC1_ENABLE; 799 dss_ctl1_val |= JOINER_ENABLE; 800 } 801 802 if (vdsc_instances_per_pipe > 2) { 803 dss_ctl2_val |= VDSC2_ENABLE; 804 dss_ctl2_val |= SMALL_JOINER_CONFIG_3_ENGINES; 805 } 806 807 if (crtc_state->joiner_pipes) { 808 if (intel_crtc_ultrajoiner_enable_needed(crtc_state)) 809 dss_ctl1_val |= ULTRA_JOINER_ENABLE; 810 811 if (intel_crtc_is_ultrajoiner_primary(crtc_state)) 812 dss_ctl1_val |= PRIMARY_ULTRA_JOINER_ENABLE; 813 814 dss_ctl1_val |= BIG_JOINER_ENABLE; 815 816 if (intel_crtc_is_bigjoiner_primary(crtc_state)) 817 dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE; 818 } 819 intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val); 820 intel_de_write(display, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val); 821 } 822 823 void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) 824 { 825 struct intel_display *display = to_intel_display(old_crtc_state); 826 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 827 828 /* Disable only if either of them is enabled */ 829 if (old_crtc_state->dsc.compression_enable || 830 old_crtc_state->joiner_pipes) { 831 intel_de_write(display, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0); 832 intel_de_write(display, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0); 833 } 834 } 835 836 static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps, 837 bool *all_equal) 838 { 839 struct intel_display *display = to_intel_display(crtc_state); 840 i915_reg_t dsc_reg[3]; 841 int i, vdsc_per_pipe, dsc_reg_num; 842 u32 val; 843 844 vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); 845 dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe); 846 847 drm_WARN_ON_ONCE(display->drm, dsc_reg_num < vdsc_per_pipe); 848 849 intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num); 850 851 *all_equal = true; 852 853 val = intel_de_read(display, dsc_reg[0]); 854 855 for (i = 1; i < dsc_reg_num; i++) { 856 if (intel_de_read(display, dsc_reg[i]) != val) { 857 *all_equal = false; 858 break; 859 } 860 } 861 862 return val; 863 } 864 865 static u32 intel_dsc_pps_read_and_verify(struct intel_crtc_state *crtc_state, int pps) 866 { 867 struct intel_display *display = to_intel_display(crtc_state); 868 u32 val; 869 bool all_equal; 870 871 val = intel_dsc_pps_read(crtc_state, pps, &all_equal); 872 drm_WARN_ON(display->drm, !all_equal); 873 874 return val; 875 } 876 877 static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state) 878 { 879 struct intel_display *display = to_intel_display(crtc_state); 880 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 881 int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state); 882 u32 pps_temp; 883 884 /* PPS 0 */ 885 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 0); 886 887 vdsc_cfg->bits_per_component = REG_FIELD_GET(DSC_PPS0_BPC_MASK, pps_temp); 888 vdsc_cfg->line_buf_depth = REG_FIELD_GET(DSC_PPS0_LINE_BUF_DEPTH_MASK, pps_temp); 889 vdsc_cfg->block_pred_enable = pps_temp & DSC_PPS0_BLOCK_PREDICTION; 890 vdsc_cfg->convert_rgb = pps_temp & DSC_PPS0_COLOR_SPACE_CONVERSION; 891 vdsc_cfg->simple_422 = pps_temp & DSC_PPS0_422_ENABLE; 892 vdsc_cfg->native_422 = pps_temp & DSC_PPS0_NATIVE_422_ENABLE; 893 vdsc_cfg->native_420 = pps_temp & DSC_PPS0_NATIVE_420_ENABLE; 894 vdsc_cfg->vbr_enable = pps_temp & DSC_PPS0_VBR_ENABLE; 895 896 /* PPS 1 */ 897 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 1); 898 899 vdsc_cfg->bits_per_pixel = REG_FIELD_GET(DSC_PPS1_BPP_MASK, pps_temp); 900 901 if (vdsc_cfg->native_420) 902 vdsc_cfg->bits_per_pixel >>= 1; 903 904 crtc_state->dsc.compressed_bpp_x16 = vdsc_cfg->bits_per_pixel; 905 906 /* PPS 2 */ 907 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2); 908 909 vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PPS2_PIC_WIDTH_MASK, pps_temp) * num_vdsc_instances; 910 vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PPS2_PIC_HEIGHT_MASK, pps_temp); 911 912 /* PPS 3 */ 913 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 3); 914 915 vdsc_cfg->slice_width = REG_FIELD_GET(DSC_PPS3_SLICE_WIDTH_MASK, pps_temp); 916 vdsc_cfg->slice_height = REG_FIELD_GET(DSC_PPS3_SLICE_HEIGHT_MASK, pps_temp); 917 918 /* PPS 4 */ 919 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 4); 920 921 vdsc_cfg->initial_dec_delay = REG_FIELD_GET(DSC_PPS4_INITIAL_DEC_DELAY_MASK, pps_temp); 922 vdsc_cfg->initial_xmit_delay = REG_FIELD_GET(DSC_PPS4_INITIAL_XMIT_DELAY_MASK, pps_temp); 923 924 /* PPS 5 */ 925 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 5); 926 927 vdsc_cfg->scale_decrement_interval = REG_FIELD_GET(DSC_PPS5_SCALE_DEC_INT_MASK, pps_temp); 928 vdsc_cfg->scale_increment_interval = REG_FIELD_GET(DSC_PPS5_SCALE_INC_INT_MASK, pps_temp); 929 930 /* PPS 6 */ 931 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 6); 932 933 vdsc_cfg->initial_scale_value = REG_FIELD_GET(DSC_PPS6_INITIAL_SCALE_VALUE_MASK, pps_temp); 934 vdsc_cfg->first_line_bpg_offset = REG_FIELD_GET(DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK, pps_temp); 935 vdsc_cfg->flatness_min_qp = REG_FIELD_GET(DSC_PPS6_FLATNESS_MIN_QP_MASK, pps_temp); 936 vdsc_cfg->flatness_max_qp = REG_FIELD_GET(DSC_PPS6_FLATNESS_MAX_QP_MASK, pps_temp); 937 938 /* PPS 7 */ 939 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 7); 940 941 vdsc_cfg->nfl_bpg_offset = REG_FIELD_GET(DSC_PPS7_NFL_BPG_OFFSET_MASK, pps_temp); 942 vdsc_cfg->slice_bpg_offset = REG_FIELD_GET(DSC_PPS7_SLICE_BPG_OFFSET_MASK, pps_temp); 943 944 /* PPS 8 */ 945 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 8); 946 947 vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_PPS8_INITIAL_OFFSET_MASK, pps_temp); 948 vdsc_cfg->final_offset = REG_FIELD_GET(DSC_PPS8_FINAL_OFFSET_MASK, pps_temp); 949 950 /* PPS 9 */ 951 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 9); 952 953 vdsc_cfg->rc_model_size = REG_FIELD_GET(DSC_PPS9_RC_MODEL_SIZE_MASK, pps_temp); 954 955 /* PPS 10 */ 956 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 10); 957 958 vdsc_cfg->rc_quant_incr_limit0 = REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK, pps_temp); 959 vdsc_cfg->rc_quant_incr_limit1 = REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK, pps_temp); 960 961 /* PPS 16 */ 962 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 16); 963 964 vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, pps_temp); 965 966 if (DISPLAY_VER(display) >= 14) { 967 /* PPS 17 */ 968 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 17); 969 970 vdsc_cfg->second_line_bpg_offset = REG_FIELD_GET(DSC_PPS17_SL_BPG_OFFSET_MASK, pps_temp); 971 972 /* PPS 18 */ 973 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 18); 974 975 vdsc_cfg->nsl_bpg_offset = REG_FIELD_GET(DSC_PPS18_NSL_BPG_OFFSET_MASK, pps_temp); 976 vdsc_cfg->second_line_offset_adj = REG_FIELD_GET(DSC_PPS18_SL_OFFSET_ADJ_MASK, pps_temp); 977 } 978 } 979 980 void intel_dsc_get_config(struct intel_crtc_state *crtc_state) 981 { 982 struct intel_display *display = to_intel_display(crtc_state); 983 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 984 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 985 enum intel_display_power_domain power_domain; 986 intel_wakeref_t wakeref; 987 u32 dss_ctl1, dss_ctl2; 988 989 if (!intel_dsc_source_support(crtc_state)) 990 return; 991 992 power_domain = intel_dsc_power_domain(crtc, cpu_transcoder); 993 994 wakeref = intel_display_power_get_if_enabled(display, power_domain); 995 if (!wakeref) 996 return; 997 998 dss_ctl1 = intel_de_read(display, dss_ctl1_reg(crtc, cpu_transcoder)); 999 dss_ctl2 = intel_de_read(display, dss_ctl2_reg(crtc, cpu_transcoder)); 1000 1001 crtc_state->dsc.compression_enable = dss_ctl2 & VDSC0_ENABLE; 1002 if (!crtc_state->dsc.compression_enable) 1003 goto out; 1004 1005 if (dss_ctl1 & JOINER_ENABLE && dss_ctl2 & (VDSC2_ENABLE | SMALL_JOINER_CONFIG_3_ENGINES)) 1006 crtc_state->dsc.num_streams = 3; 1007 else if (dss_ctl1 & JOINER_ENABLE && dss_ctl2 & VDSC1_ENABLE) 1008 crtc_state->dsc.num_streams = 2; 1009 else 1010 crtc_state->dsc.num_streams = 1; 1011 1012 intel_dsc_get_pps_config(crtc_state); 1013 out: 1014 intel_display_power_put(display, power_domain, wakeref); 1015 } 1016 1017 static void intel_vdsc_dump_state(struct drm_printer *p, int indent, 1018 const struct intel_crtc_state *crtc_state) 1019 { 1020 drm_printf_indent(p, indent, 1021 "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, num_streams: %d\n", 1022 FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16), 1023 crtc_state->dsc.slice_count, 1024 crtc_state->dsc.num_streams); 1025 } 1026 1027 void intel_vdsc_state_dump(struct drm_printer *p, int indent, 1028 const struct intel_crtc_state *crtc_state) 1029 { 1030 if (!crtc_state->dsc.compression_enable) 1031 return; 1032 1033 intel_vdsc_dump_state(p, indent, crtc_state); 1034 drm_dsc_dump_config(p, indent, &crtc_state->dsc.config); 1035 } 1036 1037 int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state) 1038 { 1039 struct intel_display *display = to_intel_display(crtc_state); 1040 int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state); 1041 int min_cdclk; 1042 1043 if (!crtc_state->dsc.compression_enable) 1044 return 0; 1045 1046 /* 1047 * When we decide to use only one VDSC engine, since 1048 * each VDSC operates with 1 ppc throughput, pixel clock 1049 * cannot be higher than the VDSC clock (cdclk) 1050 * If there 2 VDSC engines, then pixel clock can't be higher than 1051 * VDSC clock(cdclk) * 2 and so on. 1052 */ 1053 min_cdclk = DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances); 1054 1055 if (crtc_state->joiner_pipes) { 1056 int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock); 1057 1058 /* 1059 * According to Bigjoiner bw check: 1060 * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock 1061 * 1062 * We have already computed compressed_bpp, so now compute the min CDCLK that 1063 * is required to support this compressed_bpp. 1064 * 1065 * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits) 1066 * 1067 * Since PPC = 2 with bigjoiner 1068 * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits 1069 */ 1070 int bigjoiner_interface_bits = DISPLAY_VER(display) >= 14 ? 36 : 24; 1071 int min_cdclk_bj = 1072 (fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) * 1073 pixel_clock) / (2 * bigjoiner_interface_bits); 1074 1075 min_cdclk = max(min_cdclk, min_cdclk_bj); 1076 } 1077 1078 return min_cdclk; 1079 } 1080