1 /* 2 * Copyright © 2009 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Daniel Vetter <daniel@ffwll.ch> 25 * 26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c 27 */ 28 29 #include <drm/drm_fourcc.h> 30 31 #include "gem/i915_gem_internal.h" 32 #include "gem/i915_gem_object_frontbuffer.h" 33 #include "gem/i915_gem_pm.h" 34 #include "gt/intel_gpu_commands.h" 35 #include "gt/intel_ring.h" 36 37 #include "i915_drv.h" 38 #include "i915_reg.h" 39 #include "intel_color_regs.h" 40 #include "intel_de.h" 41 #include "intel_display_types.h" 42 #include "intel_frontbuffer.h" 43 #include "intel_overlay.h" 44 #include "intel_pci_config.h" 45 #include "intel_pfit_regs.h" 46 47 /* Limits for overlay size. According to intel doc, the real limits are: 48 * Y width: 4095, UV width (planar): 2047, Y height: 2047, 49 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use 50 * the minimum of both. 51 */ 52 #define IMAGE_MAX_WIDTH 2048 53 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */ 54 /* on 830 and 845 these large limits result in the card hanging */ 55 #define IMAGE_MAX_WIDTH_LEGACY 1024 56 #define IMAGE_MAX_HEIGHT_LEGACY 1088 57 58 /* overlay register definitions */ 59 /* OCMD register */ 60 #define OCMD_TILED_SURFACE (0x1<<19) 61 #define OCMD_MIRROR_MASK (0x3<<17) 62 #define OCMD_MIRROR_MODE (0x3<<17) 63 #define OCMD_MIRROR_HORIZONTAL (0x1<<17) 64 #define OCMD_MIRROR_VERTICAL (0x2<<17) 65 #define OCMD_MIRROR_BOTH (0x3<<17) 66 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */ 67 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */ 68 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */ 69 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */ 70 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10) 71 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */ 72 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */ 73 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */ 74 #define OCMD_YUV_422_PACKED (0x8<<10) 75 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */ 76 #define OCMD_YUV_420_PLANAR (0xc<<10) 77 #define OCMD_YUV_422_PLANAR (0xd<<10) 78 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */ 79 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9) 80 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7) 81 #define OCMD_BUF_TYPE_MASK (0x1<<5) 82 #define OCMD_BUF_TYPE_FRAME (0x0<<5) 83 #define OCMD_BUF_TYPE_FIELD (0x1<<5) 84 #define OCMD_TEST_MODE (0x1<<4) 85 #define OCMD_BUFFER_SELECT (0x3<<2) 86 #define OCMD_BUFFER0 (0x0<<2) 87 #define OCMD_BUFFER1 (0x1<<2) 88 #define OCMD_FIELD_SELECT (0x1<<2) 89 #define OCMD_FIELD0 (0x0<<1) 90 #define OCMD_FIELD1 (0x1<<1) 91 #define OCMD_ENABLE (0x1<<0) 92 93 /* OCONFIG register */ 94 #define OCONF_PIPE_MASK (0x1<<18) 95 #define OCONF_PIPE_A (0x0<<18) 96 #define OCONF_PIPE_B (0x1<<18) 97 #define OCONF_GAMMA2_ENABLE (0x1<<16) 98 #define OCONF_CSC_MODE_BT601 (0x0<<5) 99 #define OCONF_CSC_MODE_BT709 (0x1<<5) 100 #define OCONF_CSC_BYPASS (0x1<<4) 101 #define OCONF_CC_OUT_8BIT (0x1<<3) 102 #define OCONF_TEST_MODE (0x1<<2) 103 #define OCONF_THREE_LINE_BUFFER (0x1<<0) 104 #define OCONF_TWO_LINE_BUFFER (0x0<<0) 105 106 /* DCLRKM (dst-key) register */ 107 #define DST_KEY_ENABLE (0x1<<31) 108 #define CLK_RGB24_MASK 0x0 109 #define CLK_RGB16_MASK 0x070307 110 #define CLK_RGB15_MASK 0x070707 111 112 #define RGB30_TO_COLORKEY(c) \ 113 ((((c) & 0x3fc00000) >> 6) | (((c) & 0x000ff000) >> 4) | (((c) & 0x000003fc) >> 2)) 114 #define RGB16_TO_COLORKEY(c) \ 115 ((((c) & 0xf800) << 8) | (((c) & 0x07e0) << 5) | (((c) & 0x001f) << 3)) 116 #define RGB15_TO_COLORKEY(c) \ 117 ((((c) & 0x7c00) << 9) | (((c) & 0x03e0) << 6) | (((c) & 0x001f) << 3)) 118 #define RGB8I_TO_COLORKEY(c) \ 119 ((((c) & 0xff) << 16) | (((c) & 0xff) << 8) | (((c) & 0xff) << 0)) 120 121 /* overlay flip addr flag */ 122 #define OFC_UPDATE 0x1 123 124 /* polyphase filter coefficients */ 125 #define N_HORIZ_Y_TAPS 5 126 #define N_VERT_Y_TAPS 3 127 #define N_HORIZ_UV_TAPS 3 128 #define N_VERT_UV_TAPS 3 129 #define N_PHASES 17 130 #define MAX_TAPS 5 131 132 /* memory bufferd overlay registers */ 133 struct overlay_registers { 134 u32 OBUF_0Y; 135 u32 OBUF_1Y; 136 u32 OBUF_0U; 137 u32 OBUF_0V; 138 u32 OBUF_1U; 139 u32 OBUF_1V; 140 u32 OSTRIDE; 141 u32 YRGB_VPH; 142 u32 UV_VPH; 143 u32 HORZ_PH; 144 u32 INIT_PHS; 145 u32 DWINPOS; 146 u32 DWINSZ; 147 u32 SWIDTH; 148 u32 SWIDTHSW; 149 u32 SHEIGHT; 150 u32 YRGBSCALE; 151 u32 UVSCALE; 152 u32 OCLRC0; 153 u32 OCLRC1; 154 u32 DCLRKV; 155 u32 DCLRKM; 156 u32 SCLRKVH; 157 u32 SCLRKVL; 158 u32 SCLRKEN; 159 u32 OCONFIG; 160 u32 OCMD; 161 u32 RESERVED1; /* 0x6C */ 162 u32 OSTART_0Y; 163 u32 OSTART_1Y; 164 u32 OSTART_0U; 165 u32 OSTART_0V; 166 u32 OSTART_1U; 167 u32 OSTART_1V; 168 u32 OTILEOFF_0Y; 169 u32 OTILEOFF_1Y; 170 u32 OTILEOFF_0U; 171 u32 OTILEOFF_0V; 172 u32 OTILEOFF_1U; 173 u32 OTILEOFF_1V; 174 u32 FASTHSCALE; /* 0xA0 */ 175 u32 UVSCALEV; /* 0xA4 */ 176 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */ 177 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */ 178 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES]; 179 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */ 180 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES]; 181 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */ 182 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES]; 183 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */ 184 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; 185 }; 186 187 struct intel_overlay { 188 struct intel_display *display; 189 struct intel_context *context; 190 struct intel_crtc *crtc; 191 struct i915_vma *vma; 192 struct i915_vma *old_vma; 193 struct intel_frontbuffer *frontbuffer; 194 bool active; 195 bool pfit_active; 196 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */ 197 u32 color_key:24; 198 u32 color_key_enabled:1; 199 u32 brightness, contrast, saturation; 200 u32 old_xscale, old_yscale; 201 /* register access */ 202 struct drm_i915_gem_object *reg_bo; 203 struct overlay_registers __iomem *regs; 204 u32 flip_addr; 205 /* flip handling */ 206 struct i915_active last_flip; 207 void (*flip_complete)(struct intel_overlay *ovl); 208 }; 209 210 static void i830_overlay_clock_gating(struct intel_display *display, 211 bool enable) 212 { 213 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 214 u8 val; 215 216 /* WA_OVERLAY_CLKGATE:alm */ 217 if (enable) 218 intel_de_write(display, DSPCLK_GATE_D(display), 0); 219 else 220 intel_de_write(display, DSPCLK_GATE_D(display), 221 OVRUNIT_CLOCK_GATE_DISABLE); 222 223 /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */ 224 pci_bus_read_config_byte(pdev->bus, 225 PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val); 226 if (enable) 227 val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE; 228 else 229 val |= I830_L2_CACHE_CLOCK_GATE_DISABLE; 230 pci_bus_write_config_byte(pdev->bus, 231 PCI_DEVFN(0, 0), I830_CLOCK_GATE, val); 232 } 233 234 static struct i915_request * 235 alloc_request(struct intel_overlay *overlay, void (*fn)(struct intel_overlay *)) 236 { 237 struct i915_request *rq; 238 int err; 239 240 overlay->flip_complete = fn; 241 242 rq = i915_request_create(overlay->context); 243 if (IS_ERR(rq)) 244 return rq; 245 246 err = i915_active_add_request(&overlay->last_flip, rq); 247 if (err) { 248 i915_request_add(rq); 249 return ERR_PTR(err); 250 } 251 252 return rq; 253 } 254 255 /* overlay needs to be disable in OCMD reg */ 256 static int intel_overlay_on(struct intel_overlay *overlay) 257 { 258 struct intel_display *display = overlay->display; 259 struct i915_request *rq; 260 u32 *cs; 261 262 drm_WARN_ON(display->drm, overlay->active); 263 264 rq = alloc_request(overlay, NULL); 265 if (IS_ERR(rq)) 266 return PTR_ERR(rq); 267 268 cs = intel_ring_begin(rq, 4); 269 if (IS_ERR(cs)) { 270 i915_request_add(rq); 271 return PTR_ERR(cs); 272 } 273 274 overlay->active = true; 275 276 if (display->platform.i830) 277 i830_overlay_clock_gating(display, false); 278 279 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON; 280 *cs++ = overlay->flip_addr | OFC_UPDATE; 281 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 282 *cs++ = MI_NOOP; 283 intel_ring_advance(rq, cs); 284 285 i915_request_add(rq); 286 287 return i915_active_wait(&overlay->last_flip); 288 } 289 290 static void intel_overlay_flip_prepare(struct intel_overlay *overlay, 291 struct i915_vma *vma) 292 { 293 struct intel_display *display = overlay->display; 294 enum pipe pipe = overlay->crtc->pipe; 295 struct intel_frontbuffer *frontbuffer = NULL; 296 297 drm_WARN_ON(display->drm, overlay->old_vma); 298 299 if (vma) 300 frontbuffer = intel_frontbuffer_get(intel_bo_to_drm_bo(vma->obj)); 301 302 intel_frontbuffer_track(overlay->frontbuffer, frontbuffer, 303 INTEL_FRONTBUFFER_OVERLAY(pipe)); 304 305 if (overlay->frontbuffer) 306 intel_frontbuffer_put(overlay->frontbuffer); 307 overlay->frontbuffer = frontbuffer; 308 309 intel_frontbuffer_flip_prepare(display, INTEL_FRONTBUFFER_OVERLAY(pipe)); 310 311 overlay->old_vma = overlay->vma; 312 if (vma) 313 overlay->vma = i915_vma_get(vma); 314 else 315 overlay->vma = NULL; 316 } 317 318 /* overlay needs to be enabled in OCMD reg */ 319 static int intel_overlay_continue(struct intel_overlay *overlay, 320 struct i915_vma *vma, 321 bool load_polyphase_filter) 322 { 323 struct intel_display *display = overlay->display; 324 struct i915_request *rq; 325 u32 flip_addr = overlay->flip_addr; 326 u32 tmp, *cs; 327 328 drm_WARN_ON(display->drm, !overlay->active); 329 330 if (load_polyphase_filter) 331 flip_addr |= OFC_UPDATE; 332 333 /* check for underruns */ 334 tmp = intel_de_read(display, DOVSTA); 335 if (tmp & (1 << 17)) 336 drm_dbg(display->drm, "overlay underrun, DOVSTA: %x\n", tmp); 337 338 rq = alloc_request(overlay, NULL); 339 if (IS_ERR(rq)) 340 return PTR_ERR(rq); 341 342 cs = intel_ring_begin(rq, 2); 343 if (IS_ERR(cs)) { 344 i915_request_add(rq); 345 return PTR_ERR(cs); 346 } 347 348 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 349 *cs++ = flip_addr; 350 intel_ring_advance(rq, cs); 351 352 intel_overlay_flip_prepare(overlay, vma); 353 i915_request_add(rq); 354 355 return 0; 356 } 357 358 static void intel_overlay_release_old_vma(struct intel_overlay *overlay) 359 { 360 struct intel_display *display = overlay->display; 361 struct i915_vma *vma; 362 363 vma = fetch_and_zero(&overlay->old_vma); 364 if (drm_WARN_ON(display->drm, !vma)) 365 return; 366 367 intel_frontbuffer_flip_complete(display, INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe)); 368 369 i915_vma_unpin(vma); 370 i915_vma_put(vma); 371 } 372 373 static void 374 intel_overlay_release_old_vid_tail(struct intel_overlay *overlay) 375 { 376 intel_overlay_release_old_vma(overlay); 377 } 378 379 static void intel_overlay_off_tail(struct intel_overlay *overlay) 380 { 381 struct intel_display *display = overlay->display; 382 383 intel_overlay_release_old_vma(overlay); 384 385 overlay->crtc->overlay = NULL; 386 overlay->crtc = NULL; 387 overlay->active = false; 388 389 if (display->platform.i830) 390 i830_overlay_clock_gating(display, true); 391 } 392 393 static void intel_overlay_last_flip_retire(struct i915_active *active) 394 { 395 struct intel_overlay *overlay = 396 container_of(active, typeof(*overlay), last_flip); 397 398 if (overlay->flip_complete) 399 overlay->flip_complete(overlay); 400 } 401 402 /* overlay needs to be disabled in OCMD reg */ 403 static int intel_overlay_off(struct intel_overlay *overlay) 404 { 405 struct intel_display *display = overlay->display; 406 struct i915_request *rq; 407 u32 *cs, flip_addr = overlay->flip_addr; 408 409 drm_WARN_ON(display->drm, !overlay->active); 410 411 /* 412 * According to intel docs the overlay hw may hang (when switching 413 * off) without loading the filter coeffs. It is however unclear whether 414 * this applies to the disabling of the overlay or to the switching off 415 * of the hw. Do it in both cases. 416 */ 417 flip_addr |= OFC_UPDATE; 418 419 rq = alloc_request(overlay, intel_overlay_off_tail); 420 if (IS_ERR(rq)) 421 return PTR_ERR(rq); 422 423 cs = intel_ring_begin(rq, 6); 424 if (IS_ERR(cs)) { 425 i915_request_add(rq); 426 return PTR_ERR(cs); 427 } 428 429 /* wait for overlay to go idle */ 430 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 431 *cs++ = flip_addr; 432 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 433 434 /* turn overlay off */ 435 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF; 436 *cs++ = flip_addr; 437 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 438 439 intel_ring_advance(rq, cs); 440 441 intel_overlay_flip_prepare(overlay, NULL); 442 i915_request_add(rq); 443 444 return i915_active_wait(&overlay->last_flip); 445 } 446 447 /* 448 * Recover from an interruption due to a signal. 449 * We have to be careful not to repeat work forever an make forward progress. 450 */ 451 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay) 452 { 453 return i915_active_wait(&overlay->last_flip); 454 } 455 456 /* 457 * Wait for pending overlay flip and release old frame. 458 * Needs to be called before the overlay register are changed 459 * via intel_overlay_(un)map_regs. 460 */ 461 static int intel_overlay_release_old_vid(struct intel_overlay *overlay) 462 { 463 struct intel_display *display = overlay->display; 464 struct i915_request *rq; 465 u32 *cs; 466 467 /* 468 * Only wait if there is actually an old frame to release to 469 * guarantee forward progress. 470 */ 471 if (!overlay->old_vma) 472 return 0; 473 474 if (!(intel_de_read(display, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) { 475 intel_overlay_release_old_vid_tail(overlay); 476 return 0; 477 } 478 479 rq = alloc_request(overlay, intel_overlay_release_old_vid_tail); 480 if (IS_ERR(rq)) 481 return PTR_ERR(rq); 482 483 cs = intel_ring_begin(rq, 2); 484 if (IS_ERR(cs)) { 485 i915_request_add(rq); 486 return PTR_ERR(cs); 487 } 488 489 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 490 *cs++ = MI_NOOP; 491 intel_ring_advance(rq, cs); 492 493 i915_request_add(rq); 494 495 return i915_active_wait(&overlay->last_flip); 496 } 497 498 void intel_overlay_reset(struct intel_display *display) 499 { 500 struct intel_overlay *overlay = display->overlay; 501 502 if (!overlay) 503 return; 504 505 overlay->old_xscale = 0; 506 overlay->old_yscale = 0; 507 overlay->crtc = NULL; 508 overlay->active = false; 509 } 510 511 static int packed_depth_bytes(u32 format) 512 { 513 switch (format & I915_OVERLAY_DEPTH_MASK) { 514 case I915_OVERLAY_YUV422: 515 return 4; 516 case I915_OVERLAY_YUV411: 517 /* return 6; not implemented */ 518 default: 519 return -EINVAL; 520 } 521 } 522 523 static int packed_width_bytes(u32 format, short width) 524 { 525 switch (format & I915_OVERLAY_DEPTH_MASK) { 526 case I915_OVERLAY_YUV422: 527 return width << 1; 528 default: 529 return -EINVAL; 530 } 531 } 532 533 static int uv_hsubsampling(u32 format) 534 { 535 switch (format & I915_OVERLAY_DEPTH_MASK) { 536 case I915_OVERLAY_YUV422: 537 case I915_OVERLAY_YUV420: 538 return 2; 539 case I915_OVERLAY_YUV411: 540 case I915_OVERLAY_YUV410: 541 return 4; 542 default: 543 return -EINVAL; 544 } 545 } 546 547 static int uv_vsubsampling(u32 format) 548 { 549 switch (format & I915_OVERLAY_DEPTH_MASK) { 550 case I915_OVERLAY_YUV420: 551 case I915_OVERLAY_YUV410: 552 return 2; 553 case I915_OVERLAY_YUV422: 554 case I915_OVERLAY_YUV411: 555 return 1; 556 default: 557 return -EINVAL; 558 } 559 } 560 561 static u32 calc_swidthsw(struct intel_display *display, u32 offset, u32 width) 562 { 563 u32 sw; 564 565 if (DISPLAY_VER(display) == 2) 566 sw = ALIGN((offset & 31) + width, 32); 567 else 568 sw = ALIGN((offset & 63) + width, 64); 569 570 if (sw == 0) 571 return 0; 572 573 return (sw - 32) >> 3; 574 } 575 576 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = { 577 [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, }, 578 [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, }, 579 [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, }, 580 [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, }, 581 [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, }, 582 [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, }, 583 [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, }, 584 [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, }, 585 [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, }, 586 [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, }, 587 [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, }, 588 [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, }, 589 [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, }, 590 [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, }, 591 [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, }, 592 [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, }, 593 [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, }, 594 }; 595 596 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = { 597 [ 0] = { 0x3000, 0x1800, 0x1800, }, 598 [ 1] = { 0xb000, 0x18d0, 0x2e60, }, 599 [ 2] = { 0xb000, 0x1990, 0x2ce0, }, 600 [ 3] = { 0xb020, 0x1a68, 0x2b40, }, 601 [ 4] = { 0xb040, 0x1b20, 0x29e0, }, 602 [ 5] = { 0xb060, 0x1bd8, 0x2880, }, 603 [ 6] = { 0xb080, 0x1c88, 0x3e60, }, 604 [ 7] = { 0xb0a0, 0x1d28, 0x3c00, }, 605 [ 8] = { 0xb0c0, 0x1db8, 0x39e0, }, 606 [ 9] = { 0xb0e0, 0x1e40, 0x37e0, }, 607 [10] = { 0xb100, 0x1eb8, 0x3620, }, 608 [11] = { 0xb100, 0x1f18, 0x34a0, }, 609 [12] = { 0xb100, 0x1f68, 0x3360, }, 610 [13] = { 0xb0e0, 0x1fa8, 0x3240, }, 611 [14] = { 0xb0c0, 0x1fe0, 0x3140, }, 612 [15] = { 0xb060, 0x1ff0, 0x30a0, }, 613 [16] = { 0x3000, 0x0800, 0x3000, }, 614 }; 615 616 static void update_polyphase_filter(struct overlay_registers __iomem *regs) 617 { 618 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs)); 619 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs, 620 sizeof(uv_static_hcoeffs)); 621 } 622 623 static bool update_scaling_factors(struct intel_overlay *overlay, 624 struct overlay_registers __iomem *regs, 625 struct drm_intel_overlay_put_image *params) 626 { 627 /* fixed point with a 12 bit shift */ 628 u32 xscale, yscale, xscale_UV, yscale_UV; 629 #define FP_SHIFT 12 630 #define FRACT_MASK 0xfff 631 bool scale_changed = false; 632 int uv_hscale = uv_hsubsampling(params->flags); 633 int uv_vscale = uv_vsubsampling(params->flags); 634 635 if (params->dst_width > 1) 636 xscale = ((params->src_scan_width - 1) << FP_SHIFT) / 637 params->dst_width; 638 else 639 xscale = 1 << FP_SHIFT; 640 641 if (params->dst_height > 1) 642 yscale = ((params->src_scan_height - 1) << FP_SHIFT) / 643 params->dst_height; 644 else 645 yscale = 1 << FP_SHIFT; 646 647 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/ 648 xscale_UV = xscale/uv_hscale; 649 yscale_UV = yscale/uv_vscale; 650 /* make the Y scale to UV scale ratio an exact multiply */ 651 xscale = xscale_UV * uv_hscale; 652 yscale = yscale_UV * uv_vscale; 653 /*} else { 654 xscale_UV = 0; 655 yscale_UV = 0; 656 }*/ 657 658 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale) 659 scale_changed = true; 660 overlay->old_xscale = xscale; 661 overlay->old_yscale = yscale; 662 663 iowrite32(((yscale & FRACT_MASK) << 20) | 664 ((xscale >> FP_SHIFT) << 16) | 665 ((xscale & FRACT_MASK) << 3), 666 ®s->YRGBSCALE); 667 668 iowrite32(((yscale_UV & FRACT_MASK) << 20) | 669 ((xscale_UV >> FP_SHIFT) << 16) | 670 ((xscale_UV & FRACT_MASK) << 3), 671 ®s->UVSCALE); 672 673 iowrite32((((yscale >> FP_SHIFT) << 16) | 674 ((yscale_UV >> FP_SHIFT) << 0)), 675 ®s->UVSCALEV); 676 677 if (scale_changed) 678 update_polyphase_filter(regs); 679 680 return scale_changed; 681 } 682 683 static void update_colorkey(struct intel_overlay *overlay, 684 struct overlay_registers __iomem *regs) 685 { 686 const struct intel_plane_state *state = 687 to_intel_plane_state(overlay->crtc->base.primary->state); 688 u32 key = overlay->color_key; 689 u32 format = 0; 690 u32 flags = 0; 691 692 if (overlay->color_key_enabled) 693 flags |= DST_KEY_ENABLE; 694 695 if (state->uapi.visible) 696 format = state->hw.fb->format->format; 697 698 switch (format) { 699 case DRM_FORMAT_C8: 700 key = RGB8I_TO_COLORKEY(key); 701 flags |= CLK_RGB24_MASK; 702 break; 703 case DRM_FORMAT_XRGB1555: 704 key = RGB15_TO_COLORKEY(key); 705 flags |= CLK_RGB15_MASK; 706 break; 707 case DRM_FORMAT_RGB565: 708 key = RGB16_TO_COLORKEY(key); 709 flags |= CLK_RGB16_MASK; 710 break; 711 case DRM_FORMAT_XRGB2101010: 712 case DRM_FORMAT_XBGR2101010: 713 key = RGB30_TO_COLORKEY(key); 714 flags |= CLK_RGB24_MASK; 715 break; 716 default: 717 flags |= CLK_RGB24_MASK; 718 break; 719 } 720 721 iowrite32(key, ®s->DCLRKV); 722 iowrite32(flags, ®s->DCLRKM); 723 } 724 725 static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params) 726 { 727 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0; 728 729 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 730 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 731 case I915_OVERLAY_YUV422: 732 cmd |= OCMD_YUV_422_PLANAR; 733 break; 734 case I915_OVERLAY_YUV420: 735 cmd |= OCMD_YUV_420_PLANAR; 736 break; 737 case I915_OVERLAY_YUV411: 738 case I915_OVERLAY_YUV410: 739 cmd |= OCMD_YUV_410_PLANAR; 740 break; 741 } 742 } else { /* YUV packed */ 743 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 744 case I915_OVERLAY_YUV422: 745 cmd |= OCMD_YUV_422_PACKED; 746 break; 747 case I915_OVERLAY_YUV411: 748 cmd |= OCMD_YUV_411_PACKED; 749 break; 750 } 751 752 switch (params->flags & I915_OVERLAY_SWAP_MASK) { 753 case I915_OVERLAY_NO_SWAP: 754 break; 755 case I915_OVERLAY_UV_SWAP: 756 cmd |= OCMD_UV_SWAP; 757 break; 758 case I915_OVERLAY_Y_SWAP: 759 cmd |= OCMD_Y_SWAP; 760 break; 761 case I915_OVERLAY_Y_AND_UV_SWAP: 762 cmd |= OCMD_Y_AND_UV_SWAP; 763 break; 764 } 765 } 766 767 return cmd; 768 } 769 770 static struct i915_vma *intel_overlay_pin_fb(struct drm_i915_gem_object *new_bo) 771 { 772 struct i915_gem_ww_ctx ww; 773 struct i915_vma *vma; 774 int ret; 775 776 i915_gem_ww_ctx_init(&ww, true); 777 retry: 778 ret = i915_gem_object_lock(new_bo, &ww); 779 if (!ret) { 780 vma = i915_gem_object_pin_to_display_plane(new_bo, &ww, 0, 0, 781 NULL, PIN_MAPPABLE); 782 ret = PTR_ERR_OR_ZERO(vma); 783 } 784 if (ret == -EDEADLK) { 785 ret = i915_gem_ww_ctx_backoff(&ww); 786 if (!ret) 787 goto retry; 788 } 789 i915_gem_ww_ctx_fini(&ww); 790 if (ret) 791 return ERR_PTR(ret); 792 793 return vma; 794 } 795 796 static int intel_overlay_do_put_image(struct intel_overlay *overlay, 797 struct drm_i915_gem_object *new_bo, 798 struct drm_intel_overlay_put_image *params) 799 { 800 struct intel_display *display = overlay->display; 801 struct overlay_registers __iomem *regs = overlay->regs; 802 u32 swidth, swidthsw, sheight, ostride; 803 enum pipe pipe = overlay->crtc->pipe; 804 bool scale_changed = false; 805 struct i915_vma *vma; 806 int ret, tmp_width; 807 808 drm_WARN_ON(display->drm, 809 !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex)); 810 811 ret = intel_overlay_release_old_vid(overlay); 812 if (ret != 0) 813 return ret; 814 815 atomic_inc(&display->restore.pending_fb_pin); 816 817 vma = intel_overlay_pin_fb(new_bo); 818 if (IS_ERR(vma)) { 819 ret = PTR_ERR(vma); 820 goto out_pin_section; 821 } 822 823 i915_gem_object_flush_frontbuffer(new_bo, ORIGIN_DIRTYFB); 824 825 if (!overlay->active) { 826 const struct intel_crtc_state *crtc_state = 827 overlay->crtc->config; 828 u32 oconfig = 0; 829 830 if (crtc_state->gamma_enable && 831 crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) 832 oconfig |= OCONF_CC_OUT_8BIT; 833 if (crtc_state->gamma_enable) 834 oconfig |= OCONF_GAMMA2_ENABLE; 835 if (DISPLAY_VER(display) == 4) 836 oconfig |= OCONF_CSC_MODE_BT709; 837 oconfig |= pipe == 0 ? 838 OCONF_PIPE_A : OCONF_PIPE_B; 839 iowrite32(oconfig, ®s->OCONFIG); 840 841 ret = intel_overlay_on(overlay); 842 if (ret != 0) 843 goto out_unpin; 844 } 845 846 iowrite32(params->dst_y << 16 | params->dst_x, ®s->DWINPOS); 847 iowrite32(params->dst_height << 16 | params->dst_width, ®s->DWINSZ); 848 849 if (params->flags & I915_OVERLAY_YUV_PACKED) 850 tmp_width = packed_width_bytes(params->flags, 851 params->src_width); 852 else 853 tmp_width = params->src_width; 854 855 swidth = params->src_width; 856 swidthsw = calc_swidthsw(display, params->offset_Y, tmp_width); 857 sheight = params->src_height; 858 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, ®s->OBUF_0Y); 859 ostride = params->stride_Y; 860 861 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 862 int uv_hscale = uv_hsubsampling(params->flags); 863 int uv_vscale = uv_vsubsampling(params->flags); 864 u32 tmp_U, tmp_V; 865 866 swidth |= (params->src_width / uv_hscale) << 16; 867 sheight |= (params->src_height / uv_vscale) << 16; 868 869 tmp_U = calc_swidthsw(display, params->offset_U, 870 params->src_width / uv_hscale); 871 tmp_V = calc_swidthsw(display, params->offset_V, 872 params->src_width / uv_hscale); 873 swidthsw |= max(tmp_U, tmp_V) << 16; 874 875 iowrite32(i915_ggtt_offset(vma) + params->offset_U, 876 ®s->OBUF_0U); 877 iowrite32(i915_ggtt_offset(vma) + params->offset_V, 878 ®s->OBUF_0V); 879 880 ostride |= params->stride_UV << 16; 881 } 882 883 iowrite32(swidth, ®s->SWIDTH); 884 iowrite32(swidthsw, ®s->SWIDTHSW); 885 iowrite32(sheight, ®s->SHEIGHT); 886 iowrite32(ostride, ®s->OSTRIDE); 887 888 scale_changed = update_scaling_factors(overlay, regs, params); 889 890 update_colorkey(overlay, regs); 891 892 iowrite32(overlay_cmd_reg(params), ®s->OCMD); 893 894 ret = intel_overlay_continue(overlay, vma, scale_changed); 895 if (ret) 896 goto out_unpin; 897 898 return 0; 899 900 out_unpin: 901 i915_vma_unpin(vma); 902 out_pin_section: 903 atomic_dec(&display->restore.pending_fb_pin); 904 905 return ret; 906 } 907 908 int intel_overlay_switch_off(struct intel_overlay *overlay) 909 { 910 struct intel_display *display = overlay->display; 911 int ret; 912 913 drm_WARN_ON(display->drm, 914 !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex)); 915 916 ret = intel_overlay_recover_from_interrupt(overlay); 917 if (ret != 0) 918 return ret; 919 920 if (!overlay->active) 921 return 0; 922 923 ret = intel_overlay_release_old_vid(overlay); 924 if (ret != 0) 925 return ret; 926 927 iowrite32(0, &overlay->regs->OCMD); 928 929 return intel_overlay_off(overlay); 930 } 931 932 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, 933 struct intel_crtc *crtc) 934 { 935 if (!crtc->active) 936 return -EINVAL; 937 938 /* can't use the overlay with double wide pipe */ 939 if (crtc->config->double_wide) 940 return -EINVAL; 941 942 return 0; 943 } 944 945 static void update_pfit_vscale_ratio(struct intel_overlay *overlay) 946 { 947 struct intel_display *display = overlay->display; 948 u32 ratio; 949 950 /* XXX: This is not the same logic as in the xorg driver, but more in 951 * line with the intel documentation for the i965 952 */ 953 if (DISPLAY_VER(display) >= 4) { 954 u32 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display)); 955 956 /* on i965 use the PGM reg to read out the autoscaler values */ 957 ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK_965, tmp); 958 } else { 959 u32 tmp; 960 961 if (intel_de_read(display, PFIT_CONTROL(display)) & PFIT_VERT_AUTO_SCALE) 962 tmp = intel_de_read(display, PFIT_AUTO_RATIOS(display)); 963 else 964 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display)); 965 966 ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK, tmp); 967 } 968 969 overlay->pfit_vscale_ratio = ratio; 970 } 971 972 static int check_overlay_dst(struct intel_overlay *overlay, 973 struct drm_intel_overlay_put_image *rec) 974 { 975 const struct intel_crtc_state *crtc_state = 976 overlay->crtc->config; 977 struct drm_rect req, clipped; 978 979 drm_rect_init(&req, rec->dst_x, rec->dst_y, 980 rec->dst_width, rec->dst_height); 981 982 clipped = req; 983 984 if (!drm_rect_intersect(&clipped, &crtc_state->pipe_src)) 985 return -EINVAL; 986 987 if (!drm_rect_equals(&clipped, &req)) 988 return -EINVAL; 989 990 return 0; 991 } 992 993 static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec) 994 { 995 u32 tmp; 996 997 /* downscaling limit is 8.0 */ 998 tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16; 999 if (tmp > 7) 1000 return -EINVAL; 1001 1002 tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16; 1003 if (tmp > 7) 1004 return -EINVAL; 1005 1006 return 0; 1007 } 1008 1009 static int check_overlay_src(struct intel_display *display, 1010 struct drm_intel_overlay_put_image *rec, 1011 struct drm_i915_gem_object *new_bo) 1012 { 1013 int uv_hscale = uv_hsubsampling(rec->flags); 1014 int uv_vscale = uv_vsubsampling(rec->flags); 1015 u32 stride_mask; 1016 int depth; 1017 u32 tmp; 1018 1019 /* check src dimensions */ 1020 if (display->platform.i845g || display->platform.i830) { 1021 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY || 1022 rec->src_width > IMAGE_MAX_WIDTH_LEGACY) 1023 return -EINVAL; 1024 } else { 1025 if (rec->src_height > IMAGE_MAX_HEIGHT || 1026 rec->src_width > IMAGE_MAX_WIDTH) 1027 return -EINVAL; 1028 } 1029 1030 /* better safe than sorry, use 4 as the maximal subsampling ratio */ 1031 if (rec->src_height < N_VERT_Y_TAPS*4 || 1032 rec->src_width < N_HORIZ_Y_TAPS*4) 1033 return -EINVAL; 1034 1035 /* check alignment constraints */ 1036 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 1037 case I915_OVERLAY_RGB: 1038 /* not implemented */ 1039 return -EINVAL; 1040 1041 case I915_OVERLAY_YUV_PACKED: 1042 if (uv_vscale != 1) 1043 return -EINVAL; 1044 1045 depth = packed_depth_bytes(rec->flags); 1046 if (depth < 0) 1047 return depth; 1048 1049 /* ignore UV planes */ 1050 rec->stride_UV = 0; 1051 rec->offset_U = 0; 1052 rec->offset_V = 0; 1053 /* check pixel alignment */ 1054 if (rec->offset_Y % depth) 1055 return -EINVAL; 1056 break; 1057 1058 case I915_OVERLAY_YUV_PLANAR: 1059 if (uv_vscale < 0 || uv_hscale < 0) 1060 return -EINVAL; 1061 /* no offset restrictions for planar formats */ 1062 break; 1063 1064 default: 1065 return -EINVAL; 1066 } 1067 1068 if (rec->src_width % uv_hscale) 1069 return -EINVAL; 1070 1071 /* stride checking */ 1072 if (display->platform.i830 || display->platform.i845g) 1073 stride_mask = 255; 1074 else 1075 stride_mask = 63; 1076 1077 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) 1078 return -EINVAL; 1079 if (DISPLAY_VER(display) == 4 && rec->stride_Y < 512) 1080 return -EINVAL; 1081 1082 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? 1083 4096 : 8192; 1084 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024) 1085 return -EINVAL; 1086 1087 /* check buffer dimensions */ 1088 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 1089 case I915_OVERLAY_RGB: 1090 case I915_OVERLAY_YUV_PACKED: 1091 /* always 4 Y values per depth pixels */ 1092 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y) 1093 return -EINVAL; 1094 1095 tmp = rec->stride_Y*rec->src_height; 1096 if (rec->offset_Y + tmp > new_bo->base.size) 1097 return -EINVAL; 1098 break; 1099 1100 case I915_OVERLAY_YUV_PLANAR: 1101 if (rec->src_width > rec->stride_Y) 1102 return -EINVAL; 1103 if (rec->src_width/uv_hscale > rec->stride_UV) 1104 return -EINVAL; 1105 1106 tmp = rec->stride_Y * rec->src_height; 1107 if (rec->offset_Y + tmp > new_bo->base.size) 1108 return -EINVAL; 1109 1110 tmp = rec->stride_UV * (rec->src_height / uv_vscale); 1111 if (rec->offset_U + tmp > new_bo->base.size || 1112 rec->offset_V + tmp > new_bo->base.size) 1113 return -EINVAL; 1114 break; 1115 } 1116 1117 return 0; 1118 } 1119 1120 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, 1121 struct drm_file *file_priv) 1122 { 1123 struct intel_display *display = to_intel_display(dev); 1124 struct drm_intel_overlay_put_image *params = data; 1125 struct intel_overlay *overlay; 1126 struct drm_crtc *drmmode_crtc; 1127 struct intel_crtc *crtc; 1128 struct drm_i915_gem_object *new_bo; 1129 int ret; 1130 1131 overlay = display->overlay; 1132 if (!overlay) { 1133 drm_dbg(display->drm, "userspace bug: no overlay\n"); 1134 return -ENODEV; 1135 } 1136 1137 if (!(params->flags & I915_OVERLAY_ENABLE)) { 1138 drm_modeset_lock_all(dev); 1139 ret = intel_overlay_switch_off(overlay); 1140 drm_modeset_unlock_all(dev); 1141 1142 return ret; 1143 } 1144 1145 drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id); 1146 if (!drmmode_crtc) 1147 return -ENOENT; 1148 crtc = to_intel_crtc(drmmode_crtc); 1149 1150 new_bo = i915_gem_object_lookup(file_priv, params->bo_handle); 1151 if (!new_bo) 1152 return -ENOENT; 1153 1154 drm_modeset_lock_all(dev); 1155 1156 if (i915_gem_object_is_tiled(new_bo)) { 1157 drm_dbg_kms(display->drm, 1158 "buffer used for overlay image can not be tiled\n"); 1159 ret = -EINVAL; 1160 goto out_unlock; 1161 } 1162 1163 ret = intel_overlay_recover_from_interrupt(overlay); 1164 if (ret != 0) 1165 goto out_unlock; 1166 1167 if (overlay->crtc != crtc) { 1168 ret = intel_overlay_switch_off(overlay); 1169 if (ret != 0) 1170 goto out_unlock; 1171 1172 ret = check_overlay_possible_on_crtc(overlay, crtc); 1173 if (ret != 0) 1174 goto out_unlock; 1175 1176 overlay->crtc = crtc; 1177 crtc->overlay = overlay; 1178 1179 /* line too wide, i.e. one-line-mode */ 1180 if (drm_rect_width(&crtc->config->pipe_src) > 1024 && 1181 crtc->config->gmch_pfit.control & PFIT_ENABLE) { 1182 overlay->pfit_active = true; 1183 update_pfit_vscale_ratio(overlay); 1184 } else 1185 overlay->pfit_active = false; 1186 } 1187 1188 ret = check_overlay_dst(overlay, params); 1189 if (ret != 0) 1190 goto out_unlock; 1191 1192 if (overlay->pfit_active) { 1193 params->dst_y = (((u32)params->dst_y << 12) / 1194 overlay->pfit_vscale_ratio); 1195 /* shifting right rounds downwards, so add 1 */ 1196 params->dst_height = (((u32)params->dst_height << 12) / 1197 overlay->pfit_vscale_ratio) + 1; 1198 } 1199 1200 if (params->src_scan_height > params->src_height || 1201 params->src_scan_width > params->src_width) { 1202 ret = -EINVAL; 1203 goto out_unlock; 1204 } 1205 1206 ret = check_overlay_src(display, params, new_bo); 1207 if (ret != 0) 1208 goto out_unlock; 1209 1210 /* Check scaling after src size to prevent a divide-by-zero. */ 1211 ret = check_overlay_scaling(params); 1212 if (ret != 0) 1213 goto out_unlock; 1214 1215 ret = intel_overlay_do_put_image(overlay, new_bo, params); 1216 if (ret != 0) 1217 goto out_unlock; 1218 1219 drm_modeset_unlock_all(dev); 1220 i915_gem_object_put(new_bo); 1221 1222 return 0; 1223 1224 out_unlock: 1225 drm_modeset_unlock_all(dev); 1226 i915_gem_object_put(new_bo); 1227 1228 return ret; 1229 } 1230 1231 static void update_reg_attrs(struct intel_overlay *overlay, 1232 struct overlay_registers __iomem *regs) 1233 { 1234 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff), 1235 ®s->OCLRC0); 1236 iowrite32(overlay->saturation, ®s->OCLRC1); 1237 } 1238 1239 static bool check_gamma_bounds(u32 gamma1, u32 gamma2) 1240 { 1241 int i; 1242 1243 if (gamma1 & 0xff000000 || gamma2 & 0xff000000) 1244 return false; 1245 1246 for (i = 0; i < 3; i++) { 1247 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff)) 1248 return false; 1249 } 1250 1251 return true; 1252 } 1253 1254 static bool check_gamma5_errata(u32 gamma5) 1255 { 1256 int i; 1257 1258 for (i = 0; i < 3; i++) { 1259 if (((gamma5 >> i*8) & 0xff) == 0x80) 1260 return false; 1261 } 1262 1263 return true; 1264 } 1265 1266 static int check_gamma(struct drm_intel_overlay_attrs *attrs) 1267 { 1268 if (!check_gamma_bounds(0, attrs->gamma0) || 1269 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) || 1270 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) || 1271 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) || 1272 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) || 1273 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) || 1274 !check_gamma_bounds(attrs->gamma5, 0x00ffffff)) 1275 return -EINVAL; 1276 1277 if (!check_gamma5_errata(attrs->gamma5)) 1278 return -EINVAL; 1279 1280 return 0; 1281 } 1282 1283 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, 1284 struct drm_file *file_priv) 1285 { 1286 struct intel_display *display = to_intel_display(dev); 1287 struct drm_intel_overlay_attrs *attrs = data; 1288 struct intel_overlay *overlay; 1289 int ret; 1290 1291 overlay = display->overlay; 1292 if (!overlay) { 1293 drm_dbg(display->drm, "userspace bug: no overlay\n"); 1294 return -ENODEV; 1295 } 1296 1297 drm_modeset_lock_all(dev); 1298 1299 ret = -EINVAL; 1300 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) { 1301 attrs->color_key = overlay->color_key; 1302 attrs->brightness = overlay->brightness; 1303 attrs->contrast = overlay->contrast; 1304 attrs->saturation = overlay->saturation; 1305 1306 if (DISPLAY_VER(display) != 2) { 1307 attrs->gamma0 = intel_de_read(display, OGAMC0); 1308 attrs->gamma1 = intel_de_read(display, OGAMC1); 1309 attrs->gamma2 = intel_de_read(display, OGAMC2); 1310 attrs->gamma3 = intel_de_read(display, OGAMC3); 1311 attrs->gamma4 = intel_de_read(display, OGAMC4); 1312 attrs->gamma5 = intel_de_read(display, OGAMC5); 1313 } 1314 } else { 1315 if (attrs->brightness < -128 || attrs->brightness > 127) 1316 goto out_unlock; 1317 if (attrs->contrast > 255) 1318 goto out_unlock; 1319 if (attrs->saturation > 1023) 1320 goto out_unlock; 1321 1322 overlay->color_key = attrs->color_key; 1323 overlay->brightness = attrs->brightness; 1324 overlay->contrast = attrs->contrast; 1325 overlay->saturation = attrs->saturation; 1326 1327 update_reg_attrs(overlay, overlay->regs); 1328 1329 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { 1330 if (DISPLAY_VER(display) == 2) 1331 goto out_unlock; 1332 1333 if (overlay->active) { 1334 ret = -EBUSY; 1335 goto out_unlock; 1336 } 1337 1338 ret = check_gamma(attrs); 1339 if (ret) 1340 goto out_unlock; 1341 1342 intel_de_write(display, OGAMC0, attrs->gamma0); 1343 intel_de_write(display, OGAMC1, attrs->gamma1); 1344 intel_de_write(display, OGAMC2, attrs->gamma2); 1345 intel_de_write(display, OGAMC3, attrs->gamma3); 1346 intel_de_write(display, OGAMC4, attrs->gamma4); 1347 intel_de_write(display, OGAMC5, attrs->gamma5); 1348 } 1349 } 1350 overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0; 1351 1352 ret = 0; 1353 out_unlock: 1354 drm_modeset_unlock_all(dev); 1355 1356 return ret; 1357 } 1358 1359 static int get_registers(struct intel_overlay *overlay, bool use_phys) 1360 { 1361 struct intel_display *display = overlay->display; 1362 struct drm_i915_private *i915 = to_i915(display->drm); 1363 struct drm_i915_gem_object *obj = ERR_PTR(-ENODEV); 1364 struct i915_vma *vma; 1365 int err; 1366 1367 if (!display->platform.meteorlake) /* Wa_22018444074 */ 1368 obj = i915_gem_object_create_stolen(i915, PAGE_SIZE); 1369 if (IS_ERR(obj)) 1370 obj = i915_gem_object_create_internal(i915, PAGE_SIZE); 1371 if (IS_ERR(obj)) 1372 return PTR_ERR(obj); 1373 1374 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); 1375 if (IS_ERR(vma)) { 1376 err = PTR_ERR(vma); 1377 goto err_put_bo; 1378 } 1379 1380 if (use_phys) 1381 overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl); 1382 else 1383 overlay->flip_addr = i915_ggtt_offset(vma); 1384 overlay->regs = i915_vma_pin_iomap(vma); 1385 i915_vma_unpin(vma); 1386 1387 if (IS_ERR(overlay->regs)) { 1388 err = PTR_ERR(overlay->regs); 1389 goto err_put_bo; 1390 } 1391 1392 overlay->reg_bo = obj; 1393 return 0; 1394 1395 err_put_bo: 1396 i915_gem_object_put(obj); 1397 return err; 1398 } 1399 1400 void intel_overlay_setup(struct intel_display *display) 1401 { 1402 struct drm_i915_private *dev_priv = to_i915(display->drm); 1403 struct intel_overlay *overlay; 1404 struct intel_engine_cs *engine; 1405 int ret; 1406 1407 if (!HAS_OVERLAY(display)) 1408 return; 1409 1410 engine = to_gt(dev_priv)->engine[RCS0]; 1411 if (!engine || !engine->kernel_context) 1412 return; 1413 1414 overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); 1415 if (!overlay) 1416 return; 1417 1418 overlay->display = display; 1419 overlay->context = engine->kernel_context; 1420 overlay->color_key = 0x0101fe; 1421 overlay->color_key_enabled = true; 1422 overlay->brightness = -19; 1423 overlay->contrast = 75; 1424 overlay->saturation = 146; 1425 1426 i915_active_init(&overlay->last_flip, 1427 NULL, intel_overlay_last_flip_retire, 0); 1428 1429 ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(display)); 1430 if (ret) 1431 goto out_free; 1432 1433 memset_io(overlay->regs, 0, sizeof(struct overlay_registers)); 1434 update_polyphase_filter(overlay->regs); 1435 update_reg_attrs(overlay, overlay->regs); 1436 1437 display->overlay = overlay; 1438 drm_info(display->drm, "Initialized overlay support.\n"); 1439 return; 1440 1441 out_free: 1442 kfree(overlay); 1443 } 1444 1445 bool intel_overlay_available(struct intel_display *display) 1446 { 1447 return display->overlay; 1448 } 1449 1450 void intel_overlay_cleanup(struct intel_display *display) 1451 { 1452 struct intel_overlay *overlay; 1453 1454 overlay = fetch_and_zero(&display->overlay); 1455 if (!overlay) 1456 return; 1457 1458 /* 1459 * The bo's should be free'd by the generic code already. 1460 * Furthermore modesetting teardown happens beforehand so the 1461 * hardware should be off already. 1462 */ 1463 drm_WARN_ON(display->drm, overlay->active); 1464 1465 i915_gem_object_put(overlay->reg_bo); 1466 i915_active_fini(&overlay->last_flip); 1467 1468 kfree(overlay); 1469 } 1470 1471 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 1472 1473 struct intel_overlay_snapshot { 1474 struct overlay_registers regs; 1475 unsigned long base; 1476 u32 dovsta; 1477 u32 isr; 1478 }; 1479 1480 struct intel_overlay_snapshot * 1481 intel_overlay_snapshot_capture(struct intel_display *display) 1482 { 1483 struct intel_overlay *overlay = display->overlay; 1484 struct intel_overlay_snapshot *error; 1485 1486 if (!overlay || !overlay->active) 1487 return NULL; 1488 1489 error = kmalloc(sizeof(*error), GFP_ATOMIC); 1490 if (error == NULL) 1491 return NULL; 1492 1493 error->dovsta = intel_de_read(display, DOVSTA); 1494 error->isr = intel_de_read(display, GEN2_ISR); 1495 error->base = overlay->flip_addr; 1496 1497 memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs)); 1498 1499 return error; 1500 } 1501 1502 void 1503 intel_overlay_snapshot_print(const struct intel_overlay_snapshot *error, 1504 struct drm_printer *p) 1505 { 1506 if (!error) 1507 return; 1508 1509 drm_printf(p, "Overlay, status: 0x%08x, interrupt: 0x%08x\n", 1510 error->dovsta, error->isr); 1511 drm_printf(p, " Register file at 0x%08lx:\n", error->base); 1512 1513 #define P(x) drm_printf(p, " " #x ": 0x%08x\n", error->regs.x) 1514 P(OBUF_0Y); 1515 P(OBUF_1Y); 1516 P(OBUF_0U); 1517 P(OBUF_0V); 1518 P(OBUF_1U); 1519 P(OBUF_1V); 1520 P(OSTRIDE); 1521 P(YRGB_VPH); 1522 P(UV_VPH); 1523 P(HORZ_PH); 1524 P(INIT_PHS); 1525 P(DWINPOS); 1526 P(DWINSZ); 1527 P(SWIDTH); 1528 P(SWIDTHSW); 1529 P(SHEIGHT); 1530 P(YRGBSCALE); 1531 P(UVSCALE); 1532 P(OCLRC0); 1533 P(OCLRC1); 1534 P(DCLRKV); 1535 P(DCLRKM); 1536 P(SCLRKVH); 1537 P(SCLRKVL); 1538 P(SCLRKEN); 1539 P(OCONFIG); 1540 P(OCMD); 1541 P(OSTART_0Y); 1542 P(OSTART_1Y); 1543 P(OSTART_0U); 1544 P(OSTART_0V); 1545 P(OSTART_1U); 1546 P(OSTART_1V); 1547 P(OTILEOFF_0Y); 1548 P(OTILEOFF_1Y); 1549 P(OTILEOFF_0U); 1550 P(OTILEOFF_0V); 1551 P(OTILEOFF_1U); 1552 P(OTILEOFF_1V); 1553 P(FASTHSCALE); 1554 P(UVSCALEV); 1555 #undef P 1556 } 1557 1558 #endif 1559