1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/iopoll.h> 29 #include <linux/string_helpers.h> 30 31 #include <drm/display/drm_dp_helper.h> 32 #include <drm/display/drm_scdc_helper.h> 33 #include <drm/drm_print.h> 34 #include <drm/drm_privacy_screen_consumer.h> 35 36 #include "i915_reg.h" 37 #include "i915_utils.h" 38 #include "icl_dsi.h" 39 #include "intel_alpm.h" 40 #include "intel_audio.h" 41 #include "intel_audio_regs.h" 42 #include "intel_backlight.h" 43 #include "intel_combo_phy.h" 44 #include "intel_combo_phy_regs.h" 45 #include "intel_connector.h" 46 #include "intel_crtc.h" 47 #include "intel_cx0_phy.h" 48 #include "intel_cx0_phy_regs.h" 49 #include "intel_ddi.h" 50 #include "intel_ddi_buf_trans.h" 51 #include "intel_de.h" 52 #include "intel_display_power.h" 53 #include "intel_display_types.h" 54 #include "intel_dkl_phy.h" 55 #include "intel_dkl_phy_regs.h" 56 #include "intel_dp.h" 57 #include "intel_dp_aux.h" 58 #include "intel_dp_link_training.h" 59 #include "intel_dp_mst.h" 60 #include "intel_dp_test.h" 61 #include "intel_dp_tunnel.h" 62 #include "intel_dpio_phy.h" 63 #include "intel_dsi.h" 64 #include "intel_encoder.h" 65 #include "intel_fdi.h" 66 #include "intel_fifo_underrun.h" 67 #include "intel_gmbus.h" 68 #include "intel_hdcp.h" 69 #include "intel_hdmi.h" 70 #include "intel_hotplug.h" 71 #include "intel_hti.h" 72 #include "intel_lspcon.h" 73 #include "intel_mg_phy_regs.h" 74 #include "intel_modeset_lock.h" 75 #include "intel_pfit.h" 76 #include "intel_pps.h" 77 #include "intel_psr.h" 78 #include "intel_quirks.h" 79 #include "intel_snps_phy.h" 80 #include "intel_tc.h" 81 #include "intel_vdsc.h" 82 #include "intel_vdsc_regs.h" 83 #include "intel_vrr.h" 84 #include "skl_scaler.h" 85 #include "skl_universal_plane.h" 86 87 static const u8 index_to_dp_signal_levels[] = { 88 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 89 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 90 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 91 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 92 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 93 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 94 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 95 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 96 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 97 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 98 }; 99 100 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 101 const struct intel_ddi_buf_trans *trans) 102 { 103 int level; 104 105 level = intel_bios_hdmi_level_shift(encoder->devdata); 106 if (level < 0) 107 level = trans->hdmi_default_entry; 108 109 return level; 110 } 111 112 static bool has_buf_trans_select(struct intel_display *display) 113 { 114 return DISPLAY_VER(display) < 10 && !display->platform.broxton; 115 } 116 117 static bool has_iboost(struct intel_display *display) 118 { 119 return DISPLAY_VER(display) == 9 && !display->platform.broxton; 120 } 121 122 /* 123 * Starting with Haswell, DDI port buffers must be programmed with correct 124 * values in advance. This function programs the correct values for 125 * DP/eDP/FDI use cases. 126 */ 127 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 128 const struct intel_crtc_state *crtc_state) 129 { 130 struct intel_display *display = to_intel_display(encoder); 131 u32 iboost_bit = 0; 132 int i, n_entries; 133 enum port port = encoder->port; 134 const struct intel_ddi_buf_trans *trans; 135 136 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 137 if (drm_WARN_ON_ONCE(display->drm, !trans)) 138 return; 139 140 /* If we're boosting the current, set bit 31 of trans1 */ 141 if (has_iboost(display) && 142 intel_bios_dp_boost_level(encoder->devdata)) 143 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 144 145 for (i = 0; i < n_entries; i++) { 146 intel_de_write(display, DDI_BUF_TRANS_LO(port, i), 147 trans->entries[i].hsw.trans1 | iboost_bit); 148 intel_de_write(display, DDI_BUF_TRANS_HI(port, i), 149 trans->entries[i].hsw.trans2); 150 } 151 } 152 153 /* 154 * Starting with Haswell, DDI port buffers must be programmed with correct 155 * values in advance. This function programs the correct values for 156 * HDMI/DVI use cases. 157 */ 158 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 159 const struct intel_crtc_state *crtc_state) 160 { 161 struct intel_display *display = to_intel_display(encoder); 162 int level = intel_ddi_level(encoder, crtc_state, 0); 163 u32 iboost_bit = 0; 164 int n_entries; 165 enum port port = encoder->port; 166 const struct intel_ddi_buf_trans *trans; 167 168 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 169 if (drm_WARN_ON_ONCE(display->drm, !trans)) 170 return; 171 172 /* If we're boosting the current, set bit 31 of trans1 */ 173 if (has_iboost(display) && 174 intel_bios_hdmi_boost_level(encoder->devdata)) 175 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 176 177 /* Entry 9 is for HDMI: */ 178 intel_de_write(display, DDI_BUF_TRANS_LO(port, 9), 179 trans->entries[level].hsw.trans1 | iboost_bit); 180 intel_de_write(display, DDI_BUF_TRANS_HI(port, 9), 181 trans->entries[level].hsw.trans2); 182 } 183 184 static i915_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port) 185 { 186 if (DISPLAY_VER(display) >= 14) 187 return XELPDP_PORT_BUF_CTL1(display, port); 188 else 189 return DDI_BUF_CTL(port); 190 } 191 192 void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port) 193 { 194 /* 195 * Bspec's platform specific timeouts: 196 * MTL+ : 100 us 197 * BXT : fixed 16 us 198 * HSW-ADL: 8 us 199 * 200 * FIXME: MTL requires 10 ms based on tests, find out why 100 us is too short 201 */ 202 if (display->platform.broxton) { 203 udelay(16); 204 return; 205 } 206 207 static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); 208 if (intel_de_wait_for_set(display, intel_ddi_buf_status_reg(display, port), 209 DDI_BUF_IS_IDLE, 10)) 210 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get idle\n", 211 port_name(port)); 212 } 213 214 static void intel_wait_ddi_buf_active(struct intel_encoder *encoder) 215 { 216 struct intel_display *display = to_intel_display(encoder); 217 enum port port = encoder->port; 218 219 /* 220 * Bspec's platform specific timeouts: 221 * MTL+ : 10000 us 222 * DG2 : 1200 us 223 * TGL-ADL combo PHY: 1000 us 224 * TGL-ADL TypeC PHY: 3000 us 225 * HSW-ICL : fixed 518 us 226 */ 227 if (DISPLAY_VER(display) < 10) { 228 usleep_range(518, 1000); 229 return; 230 } 231 232 static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); 233 if (intel_de_wait_for_clear(display, intel_ddi_buf_status_reg(display, port), 234 DDI_BUF_IS_IDLE, 10)) 235 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get active\n", 236 port_name(port)); 237 } 238 239 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 240 { 241 switch (pll->info->id) { 242 case DPLL_ID_WRPLL1: 243 return PORT_CLK_SEL_WRPLL1; 244 case DPLL_ID_WRPLL2: 245 return PORT_CLK_SEL_WRPLL2; 246 case DPLL_ID_SPLL: 247 return PORT_CLK_SEL_SPLL; 248 case DPLL_ID_LCPLL_810: 249 return PORT_CLK_SEL_LCPLL_810; 250 case DPLL_ID_LCPLL_1350: 251 return PORT_CLK_SEL_LCPLL_1350; 252 case DPLL_ID_LCPLL_2700: 253 return PORT_CLK_SEL_LCPLL_2700; 254 default: 255 MISSING_CASE(pll->info->id); 256 return PORT_CLK_SEL_NONE; 257 } 258 } 259 260 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 261 const struct intel_crtc_state *crtc_state) 262 { 263 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 264 int clock = crtc_state->port_clock; 265 const enum intel_dpll_id id = pll->info->id; 266 267 switch (id) { 268 default: 269 /* 270 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 271 * here, so do warn if this get passed in 272 */ 273 MISSING_CASE(id); 274 return DDI_CLK_SEL_NONE; 275 case DPLL_ID_ICL_TBTPLL: 276 switch (clock) { 277 case 162000: 278 return DDI_CLK_SEL_TBT_162; 279 case 270000: 280 return DDI_CLK_SEL_TBT_270; 281 case 540000: 282 return DDI_CLK_SEL_TBT_540; 283 case 810000: 284 return DDI_CLK_SEL_TBT_810; 285 default: 286 MISSING_CASE(clock); 287 return DDI_CLK_SEL_NONE; 288 } 289 case DPLL_ID_ICL_MGPLL1: 290 case DPLL_ID_ICL_MGPLL2: 291 case DPLL_ID_ICL_MGPLL3: 292 case DPLL_ID_ICL_MGPLL4: 293 case DPLL_ID_TGL_MGPLL5: 294 case DPLL_ID_TGL_MGPLL6: 295 return DDI_CLK_SEL_MG; 296 } 297 } 298 299 static u32 ddi_buf_phy_link_rate(int port_clock) 300 { 301 switch (port_clock) { 302 case 162000: 303 return DDI_BUF_PHY_LINK_RATE(0); 304 case 216000: 305 return DDI_BUF_PHY_LINK_RATE(4); 306 case 243000: 307 return DDI_BUF_PHY_LINK_RATE(5); 308 case 270000: 309 return DDI_BUF_PHY_LINK_RATE(1); 310 case 324000: 311 return DDI_BUF_PHY_LINK_RATE(6); 312 case 432000: 313 return DDI_BUF_PHY_LINK_RATE(7); 314 case 540000: 315 return DDI_BUF_PHY_LINK_RATE(2); 316 case 810000: 317 return DDI_BUF_PHY_LINK_RATE(3); 318 default: 319 MISSING_CASE(port_clock); 320 return DDI_BUF_PHY_LINK_RATE(0); 321 } 322 } 323 324 static int dp_phy_lane_stagger_delay(int port_clock) 325 { 326 /* 327 * Return the number of symbol clocks delay used to stagger the 328 * assertion/desassertion of the port lane enables. The target delay 329 * time is 100 ns or greater, return the number of symbols specific to 330 * the provided port_clock (aka link clock) corresponding to this delay 331 * time, i.e. so that 332 * 333 * number_of_symbols * duration_of_one_symbol >= 100 ns 334 * 335 * The delay must be applied only on TypeC DP outputs, for everything else 336 * the delay must be set to 0. 337 * 338 * Return the number of link symbols per 100 ns: 339 * port_clock (10 kHz) -> bits / 100 us 340 * / symbol_size -> symbols / 100 us 341 * / 1000 -> symbols / 100 ns 342 */ 343 return DIV_ROUND_UP(port_clock, intel_dp_link_symbol_size(port_clock) * 1000); 344 } 345 346 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 347 const struct intel_crtc_state *crtc_state) 348 { 349 struct intel_display *display = to_intel_display(encoder); 350 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 351 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 352 353 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 354 intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) | 355 DDI_BUF_TRANS_SELECT(0); 356 357 if (dig_port->lane_reversal) 358 intel_dp->DP |= DDI_BUF_PORT_REVERSAL; 359 if (dig_port->ddi_a_4_lanes) 360 intel_dp->DP |= DDI_A_4_LANES; 361 362 if (DISPLAY_VER(display) >= 14) { 363 if (intel_dp_is_uhbr(crtc_state)) 364 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; 365 else 366 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; 367 } 368 369 if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { 370 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 371 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 372 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 373 } 374 375 if (IS_DISPLAY_VER(display, 11, 13) && intel_encoder_is_tc(encoder)) { 376 int delay = dp_phy_lane_stagger_delay(crtc_state->port_clock); 377 378 intel_dp->DP |= DDI_BUF_LANE_STAGGER_DELAY(delay); 379 } 380 } 381 382 static int icl_calc_tbt_pll_link(struct intel_display *display, enum port port) 383 { 384 u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 385 386 switch (val) { 387 case DDI_CLK_SEL_NONE: 388 return 0; 389 case DDI_CLK_SEL_TBT_162: 390 return 162000; 391 case DDI_CLK_SEL_TBT_270: 392 return 270000; 393 case DDI_CLK_SEL_TBT_540: 394 return 540000; 395 case DDI_CLK_SEL_TBT_810: 396 return 810000; 397 default: 398 MISSING_CASE(val); 399 return 0; 400 } 401 } 402 403 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 404 { 405 /* CRT dotclock is determined via other means */ 406 if (pipe_config->has_pch_encoder) 407 return; 408 409 pipe_config->hw.adjusted_mode.crtc_clock = 410 intel_crtc_dotclock(pipe_config); 411 } 412 413 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 414 const struct drm_connector_state *conn_state) 415 { 416 struct intel_display *display = to_intel_display(crtc_state); 417 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 418 u32 temp; 419 420 if (!intel_crtc_has_dp_encoder(crtc_state)) 421 return; 422 423 drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)); 424 425 temp = DP_MSA_MISC_SYNC_CLOCK; 426 427 switch (crtc_state->pipe_bpp) { 428 case 18: 429 temp |= DP_MSA_MISC_6_BPC; 430 break; 431 case 24: 432 temp |= DP_MSA_MISC_8_BPC; 433 break; 434 case 30: 435 temp |= DP_MSA_MISC_10_BPC; 436 break; 437 case 36: 438 temp |= DP_MSA_MISC_12_BPC; 439 break; 440 default: 441 MISSING_CASE(crtc_state->pipe_bpp); 442 break; 443 } 444 445 /* nonsense combination */ 446 drm_WARN_ON(display->drm, crtc_state->limited_color_range && 447 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 448 449 if (crtc_state->limited_color_range) 450 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 451 452 /* 453 * As per DP 1.2 spec section 2.3.4.3 while sending 454 * YCBCR 444 signals we should program MSA MISC1/0 fields with 455 * colorspace information. 456 */ 457 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 458 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 459 460 /* 461 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 462 * of Color Encoding Format and Content Color Gamut] while sending 463 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 464 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 465 */ 466 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 467 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 468 469 intel_de_write(display, TRANS_MSA_MISC(display, cpu_transcoder), 470 temp); 471 } 472 473 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 474 { 475 if (master_transcoder == TRANSCODER_EDP) 476 return 0; 477 else 478 return master_transcoder + 1; 479 } 480 481 static void 482 intel_ddi_config_transcoder_dp2(const struct intel_crtc_state *crtc_state, 483 bool enable) 484 { 485 struct intel_display *display = to_intel_display(crtc_state); 486 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 487 u32 val = 0; 488 489 if (!HAS_DP20(display)) 490 return; 491 492 if (enable && intel_dp_is_uhbr(crtc_state)) 493 val = TRANS_DP2_128B132B_CHANNEL_CODING; 494 495 intel_de_write(display, TRANS_DP2_CTL(cpu_transcoder), val); 496 } 497 498 /* 499 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 500 * 501 * Only intended to be used by intel_ddi_enable_transcoder_func() and 502 * intel_ddi_config_transcoder_func(). 503 */ 504 static u32 505 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 506 const struct intel_crtc_state *crtc_state) 507 { 508 struct intel_display *display = to_intel_display(crtc_state); 509 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 510 enum pipe pipe = crtc->pipe; 511 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 512 enum port port = encoder->port; 513 u32 temp; 514 515 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 516 temp = TRANS_DDI_FUNC_ENABLE; 517 if (DISPLAY_VER(display) >= 12) 518 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 519 else 520 temp |= TRANS_DDI_SELECT_PORT(port); 521 522 switch (crtc_state->pipe_bpp) { 523 default: 524 MISSING_CASE(crtc_state->pipe_bpp); 525 fallthrough; 526 case 18: 527 temp |= TRANS_DDI_BPC_6; 528 break; 529 case 24: 530 temp |= TRANS_DDI_BPC_8; 531 break; 532 case 30: 533 temp |= TRANS_DDI_BPC_10; 534 break; 535 case 36: 536 temp |= TRANS_DDI_BPC_12; 537 break; 538 } 539 540 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 541 temp |= TRANS_DDI_PVSYNC; 542 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 543 temp |= TRANS_DDI_PHSYNC; 544 545 if (cpu_transcoder == TRANSCODER_EDP) { 546 switch (pipe) { 547 default: 548 MISSING_CASE(pipe); 549 fallthrough; 550 case PIPE_A: 551 /* On Haswell, can only use the always-on power well for 552 * eDP when not using the panel fitter, and when not 553 * using motion blur mitigation (which we don't 554 * support). */ 555 if (crtc_state->pch_pfit.force_thru) 556 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 557 else 558 temp |= TRANS_DDI_EDP_INPUT_A_ON; 559 break; 560 case PIPE_B: 561 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 562 break; 563 case PIPE_C: 564 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 565 break; 566 } 567 } 568 569 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 570 if (crtc_state->has_hdmi_sink) 571 temp |= TRANS_DDI_MODE_SELECT_HDMI; 572 else 573 temp |= TRANS_DDI_MODE_SELECT_DVI; 574 575 if (crtc_state->hdmi_scrambling) 576 temp |= TRANS_DDI_HDMI_SCRAMBLING; 577 if (crtc_state->hdmi_high_tmds_clock_ratio) 578 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 579 if (DISPLAY_VER(display) >= 14) 580 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); 581 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 582 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 583 temp |= (crtc_state->fdi_lanes - 1) << 1; 584 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 585 intel_dp_is_uhbr(crtc_state)) { 586 if (intel_dp_is_uhbr(crtc_state)) 587 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 588 else 589 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 590 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 591 592 if (DISPLAY_VER(display) >= 12) { 593 enum transcoder master; 594 595 master = crtc_state->mst_master_transcoder; 596 drm_WARN_ON(display->drm, 597 master == INVALID_TRANSCODER); 598 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 599 } 600 } else { 601 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 602 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 603 } 604 605 if (IS_DISPLAY_VER(display, 8, 10) && 606 crtc_state->master_transcoder != INVALID_TRANSCODER) { 607 u8 master_select = 608 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 609 610 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 611 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 612 } 613 614 return temp; 615 } 616 617 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 618 const struct intel_crtc_state *crtc_state) 619 { 620 struct intel_display *display = to_intel_display(crtc_state); 621 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 622 623 if (DISPLAY_VER(display) >= 11) { 624 enum transcoder master_transcoder = crtc_state->master_transcoder; 625 u32 ctl2 = 0; 626 627 if (master_transcoder != INVALID_TRANSCODER) { 628 u8 master_select = 629 bdw_trans_port_sync_master_select(master_transcoder); 630 631 ctl2 |= PORT_SYNC_MODE_ENABLE | 632 PORT_SYNC_MODE_MASTER_SELECT(master_select); 633 } 634 635 intel_de_write(display, 636 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 637 ctl2); 638 } 639 640 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 641 intel_ddi_transcoder_func_reg_val_get(encoder, 642 crtc_state)); 643 } 644 645 /* 646 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 647 * bit for the DDI function and enables the DP2 configuration. Called for all 648 * transcoder types. 649 */ 650 void 651 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 652 const struct intel_crtc_state *crtc_state) 653 { 654 struct intel_display *display = to_intel_display(crtc_state); 655 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 656 u32 ctl; 657 658 intel_ddi_config_transcoder_dp2(crtc_state, true); 659 660 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 661 ctl &= ~TRANS_DDI_FUNC_ENABLE; 662 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 663 ctl); 664 } 665 666 /* 667 * Disable the DDI function and port syncing. 668 * For SST, pre-TGL MST, TGL+ MST-slave transcoders: deselect the DDI port, 669 * SST/MST mode and disable the DP2 configuration. For TGL+ MST-master 670 * transcoders these are done later in intel_ddi_post_disable_dp(). 671 */ 672 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 673 { 674 struct intel_display *display = to_intel_display(crtc_state); 675 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 676 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 677 u32 ctl; 678 679 if (DISPLAY_VER(display) >= 11) 680 intel_de_write(display, 681 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 682 0); 683 684 ctl = intel_de_read(display, 685 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 686 687 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 688 689 ctl &= ~TRANS_DDI_FUNC_ENABLE; 690 691 if (IS_DISPLAY_VER(display, 8, 10)) 692 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 693 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 694 695 if (DISPLAY_VER(display) >= 12) { 696 if (!intel_dp_mst_is_master_trans(crtc_state)) { 697 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 698 TRANS_DDI_MODE_SELECT_MASK); 699 } 700 } else { 701 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 702 } 703 704 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 705 ctl); 706 707 if (intel_dp_mst_is_slave_trans(crtc_state)) 708 intel_ddi_config_transcoder_dp2(crtc_state, false); 709 710 if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) && 711 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 712 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n"); 713 /* Quirk time at 100ms for reliable operation */ 714 msleep(100); 715 } 716 } 717 718 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 719 enum transcoder cpu_transcoder, 720 bool enable, u32 hdcp_mask) 721 { 722 struct intel_display *display = to_intel_display(intel_encoder); 723 intel_wakeref_t wakeref; 724 int ret = 0; 725 726 wakeref = intel_display_power_get_if_enabled(display, 727 intel_encoder->power_domain); 728 if (drm_WARN_ON(display->drm, !wakeref)) 729 return -ENXIO; 730 731 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 732 hdcp_mask, enable ? hdcp_mask : 0); 733 intel_display_power_put(display, intel_encoder->power_domain, wakeref); 734 return ret; 735 } 736 737 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 738 { 739 struct intel_display *display = to_intel_display(intel_connector); 740 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 741 int type = intel_connector->base.connector_type; 742 enum port port = encoder->port; 743 enum transcoder cpu_transcoder; 744 intel_wakeref_t wakeref; 745 enum pipe pipe = 0; 746 u32 ddi_mode; 747 bool ret; 748 749 wakeref = intel_display_power_get_if_enabled(display, 750 encoder->power_domain); 751 if (!wakeref) 752 return false; 753 754 /* Note: This returns false for DP MST primary encoders. */ 755 if (!encoder->get_hw_state(encoder, &pipe)) { 756 ret = false; 757 goto out; 758 } 759 760 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) 761 cpu_transcoder = TRANSCODER_EDP; 762 else 763 cpu_transcoder = (enum transcoder) pipe; 764 765 ddi_mode = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & 766 TRANS_DDI_MODE_SELECT_MASK; 767 768 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI || 769 ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 770 ret = type == DRM_MODE_CONNECTOR_HDMIA; 771 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 772 ret = type == DRM_MODE_CONNECTOR_VGA; 773 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 774 ret = type == DRM_MODE_CONNECTOR_eDP || 775 type == DRM_MODE_CONNECTOR_DisplayPort; 776 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 777 /* 778 * encoder->get_hw_state() should have bailed out on MST. This 779 * must be SST and non-eDP. 780 */ 781 ret = type == DRM_MODE_CONNECTOR_DisplayPort; 782 } else if (drm_WARN_ON(display->drm, ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)) { 783 /* encoder->get_hw_state() should have bailed out on MST. */ 784 ret = false; 785 } else { 786 ret = false; 787 } 788 789 out: 790 intel_display_power_put(display, encoder->power_domain, wakeref); 791 792 return ret; 793 } 794 795 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 796 u8 *pipe_mask, bool *is_dp_mst) 797 { 798 struct intel_display *display = to_intel_display(encoder); 799 enum port port = encoder->port; 800 intel_wakeref_t wakeref; 801 enum pipe p; 802 u32 tmp; 803 u8 mst_pipe_mask = 0, dp128b132b_pipe_mask = 0; 804 805 *pipe_mask = 0; 806 *is_dp_mst = false; 807 808 wakeref = intel_display_power_get_if_enabled(display, 809 encoder->power_domain); 810 if (!wakeref) 811 return; 812 813 tmp = intel_de_read(display, DDI_BUF_CTL(port)); 814 if (!(tmp & DDI_BUF_CTL_ENABLE)) 815 goto out; 816 817 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) { 818 tmp = intel_de_read(display, 819 TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP)); 820 821 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 822 default: 823 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 824 fallthrough; 825 case TRANS_DDI_EDP_INPUT_A_ON: 826 case TRANS_DDI_EDP_INPUT_A_ONOFF: 827 *pipe_mask = BIT(PIPE_A); 828 break; 829 case TRANS_DDI_EDP_INPUT_B_ONOFF: 830 *pipe_mask = BIT(PIPE_B); 831 break; 832 case TRANS_DDI_EDP_INPUT_C_ONOFF: 833 *pipe_mask = BIT(PIPE_C); 834 break; 835 } 836 837 goto out; 838 } 839 840 for_each_pipe(display, p) { 841 enum transcoder cpu_transcoder = (enum transcoder)p; 842 u32 port_mask, ddi_select, ddi_mode; 843 intel_wakeref_t trans_wakeref; 844 845 trans_wakeref = intel_display_power_get_if_enabled(display, 846 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 847 if (!trans_wakeref) 848 continue; 849 850 if (DISPLAY_VER(display) >= 12) { 851 port_mask = TGL_TRANS_DDI_PORT_MASK; 852 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 853 } else { 854 port_mask = TRANS_DDI_PORT_MASK; 855 ddi_select = TRANS_DDI_SELECT_PORT(port); 856 } 857 858 tmp = intel_de_read(display, 859 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 860 intel_display_power_put(display, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 861 trans_wakeref); 862 863 if ((tmp & port_mask) != ddi_select) 864 continue; 865 866 ddi_mode = tmp & TRANS_DDI_MODE_SELECT_MASK; 867 868 if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) 869 mst_pipe_mask |= BIT(p); 870 else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) 871 dp128b132b_pipe_mask |= BIT(p); 872 873 *pipe_mask |= BIT(p); 874 } 875 876 if (!*pipe_mask) 877 drm_dbg_kms(display->drm, 878 "No pipe for [ENCODER:%d:%s] found\n", 879 encoder->base.base.id, encoder->base.name); 880 881 if (!mst_pipe_mask && dp128b132b_pipe_mask) { 882 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 883 884 /* 885 * If we don't have 8b/10b MST, but have more than one 886 * transcoder in 128b/132b mode, we know it must be 128b/132b 887 * MST. 888 * 889 * Otherwise, we fall back to checking the current MST 890 * state. It's not accurate for hardware takeover at probe, but 891 * we don't expect MST to have been enabled at that point, and 892 * can assume it's SST. 893 */ 894 if (hweight8(dp128b132b_pipe_mask) > 1 || 895 intel_dp_mst_active_streams(intel_dp)) 896 mst_pipe_mask = dp128b132b_pipe_mask; 897 } 898 899 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 900 drm_dbg_kms(display->drm, 901 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 902 encoder->base.base.id, encoder->base.name, 903 *pipe_mask); 904 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 905 } 906 907 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 908 drm_dbg_kms(display->drm, 909 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b %02x)\n", 910 encoder->base.base.id, encoder->base.name, 911 *pipe_mask, mst_pipe_mask, dp128b132b_pipe_mask); 912 else 913 *is_dp_mst = mst_pipe_mask; 914 915 out: 916 if (*pipe_mask && (display->platform.geminilake || display->platform.broxton)) { 917 tmp = intel_de_read(display, BXT_PHY_CTL(port)); 918 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 919 BXT_PHY_LANE_POWERDOWN_ACK | 920 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 921 drm_err(display->drm, 922 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 923 encoder->base.base.id, encoder->base.name, tmp); 924 } 925 926 intel_display_power_put(display, encoder->power_domain, wakeref); 927 } 928 929 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 930 enum pipe *pipe) 931 { 932 u8 pipe_mask; 933 bool is_mst; 934 935 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 936 937 if (is_mst || !pipe_mask) 938 return false; 939 940 *pipe = ffs(pipe_mask) - 1; 941 942 return true; 943 } 944 945 static enum intel_display_power_domain 946 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 947 const struct intel_crtc_state *crtc_state) 948 { 949 struct intel_display *display = to_intel_display(dig_port); 950 951 /* 952 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 953 * DC states enabled at the same time, while for driver initiated AUX 954 * transfers we need the same AUX IOs to be powered but with DC states 955 * disabled. Accordingly use the AUX_IO_<port> power domain here which 956 * leaves DC states enabled. 957 * 958 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 959 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 960 * well, so we can acquire a wider AUX_<port> power domain reference 961 * instead of a specific AUX_IO_<port> reference without powering up any 962 * extra wells. 963 */ 964 if (intel_psr_needs_aux_io_power(&dig_port->base, crtc_state)) 965 return intel_display_power_aux_io_domain(display, dig_port->aux_ch); 966 else if (DISPLAY_VER(display) < 14 && 967 (intel_crtc_has_dp_encoder(crtc_state) || 968 intel_encoder_is_tc(&dig_port->base))) 969 return intel_aux_power_domain(dig_port); 970 else 971 return POWER_DOMAIN_INVALID; 972 } 973 974 static void 975 main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 976 const struct intel_crtc_state *crtc_state) 977 { 978 struct intel_display *display = to_intel_display(dig_port); 979 enum intel_display_power_domain domain = 980 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 981 982 drm_WARN_ON(display->drm, dig_port->aux_wakeref); 983 984 if (domain == POWER_DOMAIN_INVALID) 985 return; 986 987 dig_port->aux_wakeref = intel_display_power_get(display, domain); 988 } 989 990 static void 991 main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 992 const struct intel_crtc_state *crtc_state) 993 { 994 struct intel_display *display = to_intel_display(dig_port); 995 enum intel_display_power_domain domain = 996 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 997 intel_wakeref_t wf; 998 999 wf = fetch_and_zero(&dig_port->aux_wakeref); 1000 if (!wf) 1001 return; 1002 1003 intel_display_power_put(display, domain, wf); 1004 } 1005 1006 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 1007 struct intel_crtc_state *crtc_state) 1008 { 1009 struct intel_display *display = to_intel_display(encoder); 1010 struct intel_digital_port *dig_port; 1011 1012 /* 1013 * TODO: Add support for MST encoders. Atm, the following should never 1014 * happen since fake-MST encoders don't set their get_power_domains() 1015 * hook. 1016 */ 1017 if (drm_WARN_ON(display->drm, 1018 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 1019 return; 1020 1021 dig_port = enc_to_dig_port(encoder); 1022 1023 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 1024 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 1025 dig_port->ddi_io_wakeref = intel_display_power_get(display, 1026 dig_port->ddi_io_power_domain); 1027 } 1028 1029 main_link_aux_power_domain_get(dig_port, crtc_state); 1030 } 1031 1032 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, 1033 const struct intel_crtc_state *crtc_state) 1034 { 1035 struct intel_display *display = to_intel_display(crtc_state); 1036 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1037 enum phy phy = intel_encoder_to_phy(encoder); 1038 u32 val; 1039 1040 if (cpu_transcoder == TRANSCODER_EDP) 1041 return; 1042 1043 if (DISPLAY_VER(display) >= 13) 1044 val = TGL_TRANS_CLK_SEL_PORT(phy); 1045 else if (DISPLAY_VER(display) >= 12) 1046 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 1047 else 1048 val = TRANS_CLK_SEL_PORT(encoder->port); 1049 1050 intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val); 1051 } 1052 1053 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) 1054 { 1055 struct intel_display *display = to_intel_display(crtc_state); 1056 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1057 u32 val; 1058 1059 if (cpu_transcoder == TRANSCODER_EDP) 1060 return; 1061 1062 if (DISPLAY_VER(display) >= 12) 1063 val = TGL_TRANS_CLK_SEL_DISABLED; 1064 else 1065 val = TRANS_CLK_SEL_DISABLED; 1066 1067 intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val); 1068 } 1069 1070 static void _skl_ddi_set_iboost(struct intel_display *display, 1071 enum port port, u8 iboost) 1072 { 1073 u32 tmp; 1074 1075 tmp = intel_de_read(display, DISPIO_CR_TX_BMU_CR0); 1076 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1077 if (iboost) 1078 tmp |= iboost << BALANCE_LEG_SHIFT(port); 1079 else 1080 tmp |= BALANCE_LEG_DISABLE(port); 1081 intel_de_write(display, DISPIO_CR_TX_BMU_CR0, tmp); 1082 } 1083 1084 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1085 const struct intel_crtc_state *crtc_state, 1086 int level) 1087 { 1088 struct intel_display *display = to_intel_display(encoder); 1089 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1090 u8 iboost; 1091 1092 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1093 iboost = intel_bios_hdmi_boost_level(encoder->devdata); 1094 else 1095 iboost = intel_bios_dp_boost_level(encoder->devdata); 1096 1097 if (iboost == 0) { 1098 const struct intel_ddi_buf_trans *trans; 1099 int n_entries; 1100 1101 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1102 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1103 return; 1104 1105 iboost = trans->entries[level].hsw.i_boost; 1106 } 1107 1108 /* Make sure that the requested I_boost is valid */ 1109 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1110 drm_err(display->drm, "Invalid I_boost value %u\n", iboost); 1111 return; 1112 } 1113 1114 _skl_ddi_set_iboost(display, encoder->port, iboost); 1115 1116 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1117 _skl_ddi_set_iboost(display, PORT_E, iboost); 1118 } 1119 1120 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1121 const struct intel_crtc_state *crtc_state) 1122 { 1123 struct intel_display *display = to_intel_display(intel_dp); 1124 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1125 int n_entries; 1126 1127 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1128 1129 if (drm_WARN_ON(display->drm, n_entries < 1)) 1130 n_entries = 1; 1131 if (drm_WARN_ON(display->drm, 1132 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1133 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1134 1135 return index_to_dp_signal_levels[n_entries - 1] & 1136 DP_TRAIN_VOLTAGE_SWING_MASK; 1137 } 1138 1139 /* 1140 * We assume that the full set of pre-emphasis values can be 1141 * used on all DDI platforms. Should that change we need to 1142 * rethink this code. 1143 */ 1144 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1145 { 1146 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1147 } 1148 1149 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1150 int lane) 1151 { 1152 if (crtc_state->port_clock > 600000) 1153 return 0; 1154 1155 if (crtc_state->lane_count == 4) 1156 return lane >= 1 ? LOADGEN_SELECT : 0; 1157 else 1158 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1159 } 1160 1161 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1162 const struct intel_crtc_state *crtc_state) 1163 { 1164 struct intel_display *display = to_intel_display(encoder); 1165 const struct intel_ddi_buf_trans *trans; 1166 enum phy phy = intel_encoder_to_phy(encoder); 1167 int n_entries, ln; 1168 u32 val; 1169 1170 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1171 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1172 return; 1173 1174 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1175 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1176 1177 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1178 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1179 intel_de_rmw(display, ICL_PORT_CL_DW10(phy), val, 1180 intel_dp->hobl_active ? val : 0); 1181 } 1182 1183 /* Set PORT_TX_DW5 */ 1184 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1185 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1186 COEFF_POLARITY | CURSOR_PROGRAM | 1187 TAP2_DISABLE | TAP3_DISABLE); 1188 val |= SCALING_MODE_SEL(0x2); 1189 val |= RTERM_SELECT(0x6); 1190 val |= TAP3_DISABLE; 1191 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1192 1193 /* Program PORT_TX_DW2 */ 1194 for (ln = 0; ln < 4; ln++) { 1195 int level = intel_ddi_level(encoder, crtc_state, ln); 1196 1197 intel_de_rmw(display, ICL_PORT_TX_DW2_LN(ln, phy), 1198 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1199 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1200 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1201 RCOMP_SCALAR(0x98)); 1202 } 1203 1204 /* Program PORT_TX_DW4 */ 1205 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1206 for (ln = 0; ln < 4; ln++) { 1207 int level = intel_ddi_level(encoder, crtc_state, ln); 1208 1209 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy), 1210 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1211 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1212 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1213 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1214 } 1215 1216 /* Program PORT_TX_DW7 */ 1217 for (ln = 0; ln < 4; ln++) { 1218 int level = intel_ddi_level(encoder, crtc_state, ln); 1219 1220 intel_de_rmw(display, ICL_PORT_TX_DW7_LN(ln, phy), 1221 N_SCALAR_MASK, 1222 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1223 } 1224 } 1225 1226 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1227 const struct intel_crtc_state *crtc_state) 1228 { 1229 struct intel_display *display = to_intel_display(encoder); 1230 enum phy phy = intel_encoder_to_phy(encoder); 1231 u32 val; 1232 int ln; 1233 1234 /* 1235 * 1. If port type is eDP or DP, 1236 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1237 * else clear to 0b. 1238 */ 1239 val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy)); 1240 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1241 val &= ~COMMON_KEEPER_EN; 1242 else 1243 val |= COMMON_KEEPER_EN; 1244 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val); 1245 1246 /* 2. Program loadgen select */ 1247 /* 1248 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1249 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1250 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1251 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1252 */ 1253 for (ln = 0; ln < 4; ln++) { 1254 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy), 1255 LOADGEN_SELECT, 1256 icl_combo_phy_loadgen_select(crtc_state, ln)); 1257 } 1258 1259 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1260 intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 1261 0, SUS_CLOCK_CONFIG); 1262 1263 /* 4. Clear training enable to change swing values */ 1264 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1265 val &= ~TX_TRAINING_EN; 1266 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1267 1268 /* 5. Program swing and de-emphasis */ 1269 icl_ddi_combo_vswing_program(encoder, crtc_state); 1270 1271 /* 6. Set training enable to trigger update */ 1272 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1273 val |= TX_TRAINING_EN; 1274 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1275 } 1276 1277 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1278 const struct intel_crtc_state *crtc_state) 1279 { 1280 struct intel_display *display = to_intel_display(encoder); 1281 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1282 const struct intel_ddi_buf_trans *trans; 1283 int n_entries, ln; 1284 1285 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1286 return; 1287 1288 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1289 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1290 return; 1291 1292 for (ln = 0; ln < 2; ln++) { 1293 intel_de_rmw(display, MG_TX1_LINK_PARAMS(ln, tc_port), 1294 CRI_USE_FS32, 0); 1295 intel_de_rmw(display, MG_TX2_LINK_PARAMS(ln, tc_port), 1296 CRI_USE_FS32, 0); 1297 } 1298 1299 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1300 for (ln = 0; ln < 2; ln++) { 1301 int level; 1302 1303 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1304 1305 intel_de_rmw(display, MG_TX1_SWINGCTRL(ln, tc_port), 1306 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1307 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1308 1309 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1310 1311 intel_de_rmw(display, MG_TX2_SWINGCTRL(ln, tc_port), 1312 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1313 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1314 } 1315 1316 /* Program MG_TX_DRVCTRL with values from vswing table */ 1317 for (ln = 0; ln < 2; ln++) { 1318 int level; 1319 1320 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1321 1322 intel_de_rmw(display, MG_TX1_DRVCTRL(ln, tc_port), 1323 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1324 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1325 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1326 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1327 CRI_TXDEEMPH_OVERRIDE_EN); 1328 1329 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1330 1331 intel_de_rmw(display, MG_TX2_DRVCTRL(ln, tc_port), 1332 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1333 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1334 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1335 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1336 CRI_TXDEEMPH_OVERRIDE_EN); 1337 1338 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1339 } 1340 1341 /* 1342 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1343 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1344 * values from table for which TX1 and TX2 enabled. 1345 */ 1346 for (ln = 0; ln < 2; ln++) { 1347 intel_de_rmw(display, MG_CLKHUB(ln, tc_port), 1348 CFG_LOW_RATE_LKREN_EN, 1349 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1350 } 1351 1352 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1353 for (ln = 0; ln < 2; ln++) { 1354 intel_de_rmw(display, MG_TX1_DCC(ln, tc_port), 1355 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1356 CFG_AMI_CK_DIV_OVERRIDE_EN, 1357 crtc_state->port_clock > 500000 ? 1358 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1359 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1360 1361 intel_de_rmw(display, MG_TX2_DCC(ln, tc_port), 1362 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1363 CFG_AMI_CK_DIV_OVERRIDE_EN, 1364 crtc_state->port_clock > 500000 ? 1365 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1366 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1367 } 1368 1369 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1370 for (ln = 0; ln < 2; ln++) { 1371 intel_de_rmw(display, MG_TX1_PISO_READLOAD(ln, tc_port), 1372 0, CRI_CALCINIT); 1373 intel_de_rmw(display, MG_TX2_PISO_READLOAD(ln, tc_port), 1374 0, CRI_CALCINIT); 1375 } 1376 } 1377 1378 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1379 const struct intel_crtc_state *crtc_state) 1380 { 1381 struct intel_display *display = to_intel_display(encoder); 1382 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1383 const struct intel_ddi_buf_trans *trans; 1384 int n_entries, ln; 1385 1386 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1387 return; 1388 1389 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1390 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1391 return; 1392 1393 for (ln = 0; ln < 2; ln++) { 1394 int level; 1395 1396 intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1397 1398 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1399 1400 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL0(tc_port, ln), 1401 DKL_TX_PRESHOOT_COEFF_MASK | 1402 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1403 DKL_TX_VSWING_CONTROL_MASK, 1404 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1405 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1406 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1407 1408 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1409 1410 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL1(tc_port, ln), 1411 DKL_TX_PRESHOOT_COEFF_MASK | 1412 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1413 DKL_TX_VSWING_CONTROL_MASK, 1414 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1415 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1416 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1417 1418 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1419 DKL_TX_DP20BITMODE, 0); 1420 1421 if (display->platform.alderlake_p) { 1422 u32 val; 1423 1424 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1425 if (ln == 0) { 1426 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1427 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1428 } else { 1429 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1430 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1431 } 1432 } else { 1433 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1434 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1435 } 1436 1437 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1438 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1439 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1440 val); 1441 } 1442 } 1443 } 1444 1445 static int translate_signal_level(struct intel_dp *intel_dp, 1446 u8 signal_levels) 1447 { 1448 struct intel_display *display = to_intel_display(intel_dp); 1449 int i; 1450 1451 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1452 if (index_to_dp_signal_levels[i] == signal_levels) 1453 return i; 1454 } 1455 1456 drm_WARN(display->drm, 1, 1457 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1458 signal_levels); 1459 1460 return 0; 1461 } 1462 1463 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1464 const struct intel_crtc_state *crtc_state, 1465 int lane) 1466 { 1467 u8 train_set = intel_dp->train_set[lane]; 1468 1469 if (intel_dp_is_uhbr(crtc_state)) { 1470 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1471 } else { 1472 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1473 DP_TRAIN_PRE_EMPHASIS_MASK); 1474 1475 return translate_signal_level(intel_dp, signal_levels); 1476 } 1477 } 1478 1479 int intel_ddi_level(struct intel_encoder *encoder, 1480 const struct intel_crtc_state *crtc_state, 1481 int lane) 1482 { 1483 struct intel_display *display = to_intel_display(encoder); 1484 const struct intel_ddi_buf_trans *trans; 1485 int level, n_entries; 1486 1487 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1488 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1489 return 0; 1490 1491 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1492 level = intel_ddi_hdmi_level(encoder, trans); 1493 else 1494 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1495 lane); 1496 1497 if (drm_WARN_ON_ONCE(display->drm, level >= n_entries)) 1498 level = n_entries - 1; 1499 1500 return level; 1501 } 1502 1503 static void 1504 hsw_set_signal_levels(struct intel_encoder *encoder, 1505 const struct intel_crtc_state *crtc_state) 1506 { 1507 struct intel_display *display = to_intel_display(encoder); 1508 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1509 int level = intel_ddi_level(encoder, crtc_state, 0); 1510 enum port port = encoder->port; 1511 u32 signal_levels; 1512 1513 if (has_iboost(display)) 1514 skl_ddi_set_iboost(encoder, crtc_state, level); 1515 1516 /* HDMI ignores the rest */ 1517 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1518 return; 1519 1520 signal_levels = DDI_BUF_TRANS_SELECT(level); 1521 1522 drm_dbg_kms(display->drm, "Using signal levels %08x\n", 1523 signal_levels); 1524 1525 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1526 intel_dp->DP |= signal_levels; 1527 1528 intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP); 1529 intel_de_posting_read(display, DDI_BUF_CTL(port)); 1530 } 1531 1532 static void _icl_ddi_enable_clock(struct intel_display *display, i915_reg_t reg, 1533 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1534 { 1535 mutex_lock(&display->dpll.lock); 1536 1537 intel_de_rmw(display, reg, clk_sel_mask, clk_sel); 1538 1539 /* 1540 * "This step and the step before must be 1541 * done with separate register writes." 1542 */ 1543 intel_de_rmw(display, reg, clk_off, 0); 1544 1545 mutex_unlock(&display->dpll.lock); 1546 } 1547 1548 static void _icl_ddi_disable_clock(struct intel_display *display, i915_reg_t reg, 1549 u32 clk_off) 1550 { 1551 mutex_lock(&display->dpll.lock); 1552 1553 intel_de_rmw(display, reg, 0, clk_off); 1554 1555 mutex_unlock(&display->dpll.lock); 1556 } 1557 1558 static bool _icl_ddi_is_clock_enabled(struct intel_display *display, i915_reg_t reg, 1559 u32 clk_off) 1560 { 1561 return !(intel_de_read(display, reg) & clk_off); 1562 } 1563 1564 static struct intel_shared_dpll * 1565 _icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg, 1566 u32 clk_sel_mask, u32 clk_sel_shift) 1567 { 1568 enum intel_dpll_id id; 1569 1570 id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift; 1571 1572 return intel_get_shared_dpll_by_id(display, id); 1573 } 1574 1575 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1576 const struct intel_crtc_state *crtc_state) 1577 { 1578 struct intel_display *display = to_intel_display(encoder); 1579 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1580 enum phy phy = intel_encoder_to_phy(encoder); 1581 1582 if (drm_WARN_ON(display->drm, !pll)) 1583 return; 1584 1585 _icl_ddi_enable_clock(display, ADLS_DPCLKA_CFGCR(phy), 1586 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1587 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1588 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1589 } 1590 1591 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1592 { 1593 struct intel_display *display = to_intel_display(encoder); 1594 enum phy phy = intel_encoder_to_phy(encoder); 1595 1596 _icl_ddi_disable_clock(display, ADLS_DPCLKA_CFGCR(phy), 1597 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1598 } 1599 1600 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1601 { 1602 struct intel_display *display = to_intel_display(encoder); 1603 enum phy phy = intel_encoder_to_phy(encoder); 1604 1605 return _icl_ddi_is_clock_enabled(display, ADLS_DPCLKA_CFGCR(phy), 1606 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1607 } 1608 1609 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1610 { 1611 struct intel_display *display = to_intel_display(encoder); 1612 enum phy phy = intel_encoder_to_phy(encoder); 1613 1614 return _icl_ddi_get_pll(display, ADLS_DPCLKA_CFGCR(phy), 1615 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1616 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1617 } 1618 1619 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1620 const struct intel_crtc_state *crtc_state) 1621 { 1622 struct intel_display *display = to_intel_display(encoder); 1623 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1624 enum phy phy = intel_encoder_to_phy(encoder); 1625 1626 if (drm_WARN_ON(display->drm, !pll)) 1627 return; 1628 1629 _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0, 1630 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1631 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1632 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1633 } 1634 1635 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1636 { 1637 struct intel_display *display = to_intel_display(encoder); 1638 enum phy phy = intel_encoder_to_phy(encoder); 1639 1640 _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0, 1641 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1642 } 1643 1644 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1645 { 1646 struct intel_display *display = to_intel_display(encoder); 1647 enum phy phy = intel_encoder_to_phy(encoder); 1648 1649 return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0, 1650 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1651 } 1652 1653 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1654 { 1655 struct intel_display *display = to_intel_display(encoder); 1656 enum phy phy = intel_encoder_to_phy(encoder); 1657 1658 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0, 1659 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1660 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1661 } 1662 1663 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1664 const struct intel_crtc_state *crtc_state) 1665 { 1666 struct intel_display *display = to_intel_display(encoder); 1667 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1668 enum phy phy = intel_encoder_to_phy(encoder); 1669 1670 if (drm_WARN_ON(display->drm, !pll)) 1671 return; 1672 1673 /* 1674 * If we fail this, something went very wrong: first 2 PLLs should be 1675 * used by first 2 phys and last 2 PLLs by last phys 1676 */ 1677 if (drm_WARN_ON(display->drm, 1678 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1679 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1680 return; 1681 1682 _icl_ddi_enable_clock(display, DG1_DPCLKA_CFGCR0(phy), 1683 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1684 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1685 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1686 } 1687 1688 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1689 { 1690 struct intel_display *display = to_intel_display(encoder); 1691 enum phy phy = intel_encoder_to_phy(encoder); 1692 1693 _icl_ddi_disable_clock(display, DG1_DPCLKA_CFGCR0(phy), 1694 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1695 } 1696 1697 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1698 { 1699 struct intel_display *display = to_intel_display(encoder); 1700 enum phy phy = intel_encoder_to_phy(encoder); 1701 1702 return _icl_ddi_is_clock_enabled(display, DG1_DPCLKA_CFGCR0(phy), 1703 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1704 } 1705 1706 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1707 { 1708 struct intel_display *display = to_intel_display(encoder); 1709 enum phy phy = intel_encoder_to_phy(encoder); 1710 enum intel_dpll_id id; 1711 u32 val; 1712 1713 val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy)); 1714 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1715 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1716 id = val; 1717 1718 /* 1719 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1720 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1721 * bit for phy C and D. 1722 */ 1723 if (phy >= PHY_C) 1724 id += DPLL_ID_DG1_DPLL2; 1725 1726 return intel_get_shared_dpll_by_id(display, id); 1727 } 1728 1729 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1730 const struct intel_crtc_state *crtc_state) 1731 { 1732 struct intel_display *display = to_intel_display(encoder); 1733 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1734 enum phy phy = intel_encoder_to_phy(encoder); 1735 1736 if (drm_WARN_ON(display->drm, !pll)) 1737 return; 1738 1739 _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0, 1740 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1741 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1742 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1743 } 1744 1745 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1746 { 1747 struct intel_display *display = to_intel_display(encoder); 1748 enum phy phy = intel_encoder_to_phy(encoder); 1749 1750 _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0, 1751 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1752 } 1753 1754 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1755 { 1756 struct intel_display *display = to_intel_display(encoder); 1757 enum phy phy = intel_encoder_to_phy(encoder); 1758 1759 return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0, 1760 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1761 } 1762 1763 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1764 { 1765 struct intel_display *display = to_intel_display(encoder); 1766 enum phy phy = intel_encoder_to_phy(encoder); 1767 1768 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0, 1769 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1770 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1771 } 1772 1773 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1774 const struct intel_crtc_state *crtc_state) 1775 { 1776 struct intel_display *display = to_intel_display(encoder); 1777 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1778 enum port port = encoder->port; 1779 1780 if (drm_WARN_ON(display->drm, !pll)) 1781 return; 1782 1783 /* 1784 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1785 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1786 */ 1787 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1788 1789 icl_ddi_combo_enable_clock(encoder, crtc_state); 1790 } 1791 1792 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1793 { 1794 struct intel_display *display = to_intel_display(encoder); 1795 enum port port = encoder->port; 1796 1797 icl_ddi_combo_disable_clock(encoder); 1798 1799 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1800 } 1801 1802 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1803 { 1804 struct intel_display *display = to_intel_display(encoder); 1805 enum port port = encoder->port; 1806 u32 tmp; 1807 1808 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1809 1810 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1811 return false; 1812 1813 return icl_ddi_combo_is_clock_enabled(encoder); 1814 } 1815 1816 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1817 const struct intel_crtc_state *crtc_state) 1818 { 1819 struct intel_display *display = to_intel_display(encoder); 1820 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1821 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1822 enum port port = encoder->port; 1823 1824 if (drm_WARN_ON(display->drm, !pll)) 1825 return; 1826 1827 intel_de_write(display, DDI_CLK_SEL(port), 1828 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1829 1830 mutex_lock(&display->dpll.lock); 1831 1832 intel_de_rmw(display, ICL_DPCLKA_CFGCR0, 1833 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1834 1835 mutex_unlock(&display->dpll.lock); 1836 } 1837 1838 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1839 { 1840 struct intel_display *display = to_intel_display(encoder); 1841 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1842 enum port port = encoder->port; 1843 1844 mutex_lock(&display->dpll.lock); 1845 1846 intel_de_rmw(display, ICL_DPCLKA_CFGCR0, 1847 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1848 1849 mutex_unlock(&display->dpll.lock); 1850 1851 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1852 } 1853 1854 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1855 { 1856 struct intel_display *display = to_intel_display(encoder); 1857 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1858 enum port port = encoder->port; 1859 u32 tmp; 1860 1861 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1862 1863 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1864 return false; 1865 1866 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); 1867 1868 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1869 } 1870 1871 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1872 { 1873 struct intel_display *display = to_intel_display(encoder); 1874 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1875 enum port port = encoder->port; 1876 enum intel_dpll_id id; 1877 u32 tmp; 1878 1879 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1880 1881 switch (tmp & DDI_CLK_SEL_MASK) { 1882 case DDI_CLK_SEL_TBT_162: 1883 case DDI_CLK_SEL_TBT_270: 1884 case DDI_CLK_SEL_TBT_540: 1885 case DDI_CLK_SEL_TBT_810: 1886 id = DPLL_ID_ICL_TBTPLL; 1887 break; 1888 case DDI_CLK_SEL_MG: 1889 id = icl_tc_port_to_pll_id(tc_port); 1890 break; 1891 default: 1892 MISSING_CASE(tmp); 1893 fallthrough; 1894 case DDI_CLK_SEL_NONE: 1895 return NULL; 1896 } 1897 1898 return intel_get_shared_dpll_by_id(display, id); 1899 } 1900 1901 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1902 { 1903 struct intel_display *display = to_intel_display(encoder->base.dev); 1904 enum intel_dpll_id id; 1905 1906 switch (encoder->port) { 1907 case PORT_A: 1908 id = DPLL_ID_SKL_DPLL0; 1909 break; 1910 case PORT_B: 1911 id = DPLL_ID_SKL_DPLL1; 1912 break; 1913 case PORT_C: 1914 id = DPLL_ID_SKL_DPLL2; 1915 break; 1916 default: 1917 MISSING_CASE(encoder->port); 1918 return NULL; 1919 } 1920 1921 return intel_get_shared_dpll_by_id(display, id); 1922 } 1923 1924 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1925 const struct intel_crtc_state *crtc_state) 1926 { 1927 struct intel_display *display = to_intel_display(encoder); 1928 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1929 enum port port = encoder->port; 1930 1931 if (drm_WARN_ON(display->drm, !pll)) 1932 return; 1933 1934 mutex_lock(&display->dpll.lock); 1935 1936 intel_de_rmw(display, DPLL_CTRL2, 1937 DPLL_CTRL2_DDI_CLK_OFF(port) | 1938 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1939 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1940 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1941 1942 mutex_unlock(&display->dpll.lock); 1943 } 1944 1945 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1946 { 1947 struct intel_display *display = to_intel_display(encoder); 1948 enum port port = encoder->port; 1949 1950 mutex_lock(&display->dpll.lock); 1951 1952 intel_de_rmw(display, DPLL_CTRL2, 1953 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1954 1955 mutex_unlock(&display->dpll.lock); 1956 } 1957 1958 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1959 { 1960 struct intel_display *display = to_intel_display(encoder); 1961 enum port port = encoder->port; 1962 1963 /* 1964 * FIXME Not sure if the override affects both 1965 * the PLL selection and the CLK_OFF bit. 1966 */ 1967 return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1968 } 1969 1970 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1971 { 1972 struct intel_display *display = to_intel_display(encoder); 1973 enum port port = encoder->port; 1974 enum intel_dpll_id id; 1975 u32 tmp; 1976 1977 tmp = intel_de_read(display, DPLL_CTRL2); 1978 1979 /* 1980 * FIXME Not sure if the override affects both 1981 * the PLL selection and the CLK_OFF bit. 1982 */ 1983 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 1984 return NULL; 1985 1986 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 1987 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 1988 1989 return intel_get_shared_dpll_by_id(display, id); 1990 } 1991 1992 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 1993 const struct intel_crtc_state *crtc_state) 1994 { 1995 struct intel_display *display = to_intel_display(encoder); 1996 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1997 enum port port = encoder->port; 1998 1999 if (drm_WARN_ON(display->drm, !pll)) 2000 return; 2001 2002 intel_de_write(display, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 2003 } 2004 2005 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 2006 { 2007 struct intel_display *display = to_intel_display(encoder); 2008 enum port port = encoder->port; 2009 2010 intel_de_write(display, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 2011 } 2012 2013 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 2014 { 2015 struct intel_display *display = to_intel_display(encoder); 2016 enum port port = encoder->port; 2017 2018 return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 2019 } 2020 2021 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 2022 { 2023 struct intel_display *display = to_intel_display(encoder); 2024 enum port port = encoder->port; 2025 enum intel_dpll_id id; 2026 u32 tmp; 2027 2028 tmp = intel_de_read(display, PORT_CLK_SEL(port)); 2029 2030 switch (tmp & PORT_CLK_SEL_MASK) { 2031 case PORT_CLK_SEL_WRPLL1: 2032 id = DPLL_ID_WRPLL1; 2033 break; 2034 case PORT_CLK_SEL_WRPLL2: 2035 id = DPLL_ID_WRPLL2; 2036 break; 2037 case PORT_CLK_SEL_SPLL: 2038 id = DPLL_ID_SPLL; 2039 break; 2040 case PORT_CLK_SEL_LCPLL_810: 2041 id = DPLL_ID_LCPLL_810; 2042 break; 2043 case PORT_CLK_SEL_LCPLL_1350: 2044 id = DPLL_ID_LCPLL_1350; 2045 break; 2046 case PORT_CLK_SEL_LCPLL_2700: 2047 id = DPLL_ID_LCPLL_2700; 2048 break; 2049 default: 2050 MISSING_CASE(tmp); 2051 fallthrough; 2052 case PORT_CLK_SEL_NONE: 2053 return NULL; 2054 } 2055 2056 return intel_get_shared_dpll_by_id(display, id); 2057 } 2058 2059 void intel_ddi_enable_clock(struct intel_encoder *encoder, 2060 const struct intel_crtc_state *crtc_state) 2061 { 2062 if (encoder->enable_clock) 2063 encoder->enable_clock(encoder, crtc_state); 2064 } 2065 2066 void intel_ddi_disable_clock(struct intel_encoder *encoder) 2067 { 2068 if (encoder->disable_clock) 2069 encoder->disable_clock(encoder); 2070 } 2071 2072 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2073 { 2074 struct intel_display *display = to_intel_display(encoder); 2075 u32 port_mask; 2076 bool ddi_clk_needed; 2077 2078 /* 2079 * In case of DP MST, we sanitize the primary encoder only, not the 2080 * virtual ones. 2081 */ 2082 if (encoder->type == INTEL_OUTPUT_DP_MST) 2083 return; 2084 2085 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2086 u8 pipe_mask; 2087 bool is_mst; 2088 2089 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2090 /* 2091 * In the unlikely case that BIOS enables DP in MST mode, just 2092 * warn since our MST HW readout is incomplete. 2093 */ 2094 if (drm_WARN_ON(display->drm, is_mst)) 2095 return; 2096 } 2097 2098 port_mask = BIT(encoder->port); 2099 ddi_clk_needed = encoder->base.crtc; 2100 2101 if (encoder->type == INTEL_OUTPUT_DSI) { 2102 struct intel_encoder *other_encoder; 2103 2104 port_mask = intel_dsi_encoder_ports(encoder); 2105 /* 2106 * Sanity check that we haven't incorrectly registered another 2107 * encoder using any of the ports of this DSI encoder. 2108 */ 2109 for_each_intel_encoder(display->drm, other_encoder) { 2110 if (other_encoder == encoder) 2111 continue; 2112 2113 if (drm_WARN_ON(display->drm, 2114 port_mask & BIT(other_encoder->port))) 2115 return; 2116 } 2117 /* 2118 * For DSI we keep the ddi clocks gated 2119 * except during enable/disable sequence. 2120 */ 2121 ddi_clk_needed = false; 2122 } 2123 2124 if (ddi_clk_needed || !encoder->is_clock_enabled || 2125 !encoder->is_clock_enabled(encoder)) 2126 return; 2127 2128 drm_dbg_kms(display->drm, 2129 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2130 encoder->base.base.id, encoder->base.name); 2131 2132 encoder->disable_clock(encoder); 2133 } 2134 2135 static void 2136 tgl_dkl_phy_check_and_rewrite(struct intel_display *display, 2137 enum tc_port tc_port, u32 ln0, u32 ln1) 2138 { 2139 if (ln0 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0))) 2140 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); 2141 if (ln1 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1))) 2142 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); 2143 } 2144 2145 static void 2146 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2147 const struct intel_crtc_state *crtc_state) 2148 { 2149 struct intel_display *display = to_intel_display(crtc_state); 2150 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); 2151 u32 ln0, ln1, pin_assignment; 2152 u8 width; 2153 2154 if (DISPLAY_VER(display) >= 14) 2155 return; 2156 2157 if (!intel_encoder_is_tc(&dig_port->base) || 2158 intel_tc_port_in_tbt_alt_mode(dig_port)) 2159 return; 2160 2161 if (DISPLAY_VER(display) >= 12) { 2162 ln0 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0)); 2163 ln1 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1)); 2164 } else { 2165 ln0 = intel_de_read(display, MG_DP_MODE(0, tc_port)); 2166 ln1 = intel_de_read(display, MG_DP_MODE(1, tc_port)); 2167 } 2168 2169 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2170 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2171 2172 /* DPPATC */ 2173 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2174 width = crtc_state->lane_count; 2175 2176 switch (pin_assignment) { 2177 case 0x0: 2178 drm_WARN_ON(display->drm, 2179 !intel_tc_port_in_legacy_mode(dig_port)); 2180 if (width == 1) { 2181 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2182 } else { 2183 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2184 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2185 } 2186 break; 2187 case 0x1: 2188 if (width == 4) { 2189 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2190 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2191 } 2192 break; 2193 case 0x2: 2194 if (width == 2) { 2195 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2196 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2197 } 2198 break; 2199 case 0x3: 2200 case 0x5: 2201 if (width == 1) { 2202 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2203 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2204 } else { 2205 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2206 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2207 } 2208 break; 2209 case 0x4: 2210 case 0x6: 2211 if (width == 1) { 2212 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2213 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2214 } else { 2215 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2216 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2217 } 2218 break; 2219 default: 2220 MISSING_CASE(pin_assignment); 2221 } 2222 2223 if (DISPLAY_VER(display) >= 12) { 2224 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); 2225 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); 2226 /* WA_14018221282 */ 2227 if (IS_DISPLAY_VER(display, 12, 13)) 2228 tgl_dkl_phy_check_and_rewrite(display, tc_port, ln0, ln1); 2229 2230 } else { 2231 intel_de_write(display, MG_DP_MODE(0, tc_port), ln0); 2232 intel_de_write(display, MG_DP_MODE(1, tc_port), ln1); 2233 } 2234 } 2235 2236 static enum transcoder 2237 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2238 { 2239 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2240 return crtc_state->mst_master_transcoder; 2241 else 2242 return crtc_state->cpu_transcoder; 2243 } 2244 2245 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2246 const struct intel_crtc_state *crtc_state) 2247 { 2248 struct intel_display *display = to_intel_display(encoder); 2249 2250 if (DISPLAY_VER(display) >= 12) 2251 return TGL_DP_TP_CTL(display, 2252 tgl_dp_tp_transcoder(crtc_state)); 2253 else 2254 return DP_TP_CTL(encoder->port); 2255 } 2256 2257 static i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2258 const struct intel_crtc_state *crtc_state) 2259 { 2260 struct intel_display *display = to_intel_display(encoder); 2261 2262 if (DISPLAY_VER(display) >= 12) 2263 return TGL_DP_TP_STATUS(display, 2264 tgl_dp_tp_transcoder(crtc_state)); 2265 else 2266 return DP_TP_STATUS(encoder->port); 2267 } 2268 2269 void intel_ddi_clear_act_sent(struct intel_encoder *encoder, 2270 const struct intel_crtc_state *crtc_state) 2271 { 2272 struct intel_display *display = to_intel_display(encoder); 2273 2274 intel_de_write(display, dp_tp_status_reg(encoder, crtc_state), 2275 DP_TP_STATUS_ACT_SENT); 2276 } 2277 2278 void intel_ddi_wait_for_act_sent(struct intel_encoder *encoder, 2279 const struct intel_crtc_state *crtc_state) 2280 { 2281 struct intel_display *display = to_intel_display(encoder); 2282 2283 if (intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), 2284 DP_TP_STATUS_ACT_SENT, 1)) 2285 drm_err(display->drm, "Timed out waiting for ACT sent\n"); 2286 } 2287 2288 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2289 const struct intel_crtc_state *crtc_state, 2290 bool enable) 2291 { 2292 struct intel_display *display = to_intel_display(intel_dp); 2293 2294 if (!crtc_state->vrr.enable) 2295 return; 2296 2297 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2298 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2299 drm_dbg_kms(display->drm, 2300 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2301 str_enable_disable(enable)); 2302 } 2303 2304 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2305 const struct intel_crtc_state *crtc_state, 2306 bool enable) 2307 { 2308 struct intel_display *display = to_intel_display(intel_dp); 2309 2310 if (!crtc_state->fec_enable) 2311 return; 2312 2313 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, 2314 enable ? DP_FEC_READY : 0) <= 0) 2315 drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n", 2316 str_enabled_disabled(enable)); 2317 2318 if (enable && 2319 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS, 2320 DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0) 2321 drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n"); 2322 } 2323 2324 static int read_fec_detected_status(struct drm_dp_aux *aux) 2325 { 2326 int ret; 2327 u8 status; 2328 2329 ret = drm_dp_dpcd_readb(aux, DP_FEC_STATUS, &status); 2330 if (ret < 0) 2331 return ret; 2332 2333 return status; 2334 } 2335 2336 static int wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled) 2337 { 2338 struct intel_display *display = to_intel_display(aux->drm_dev); 2339 int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED; 2340 int status; 2341 int err; 2342 2343 err = readx_poll_timeout(read_fec_detected_status, aux, status, 2344 status & mask || status < 0, 2345 10000, 200000); 2346 2347 if (err || status < 0) { 2348 drm_dbg_kms(display->drm, 2349 "Failed waiting for FEC %s to get detected: %d (status %d)\n", 2350 str_enabled_disabled(enabled), err, status); 2351 return err ? err : status; 2352 } 2353 2354 return 0; 2355 } 2356 2357 int intel_ddi_wait_for_fec_status(struct intel_encoder *encoder, 2358 const struct intel_crtc_state *crtc_state, 2359 bool enabled) 2360 { 2361 struct intel_display *display = to_intel_display(encoder); 2362 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2363 int ret; 2364 2365 if (!crtc_state->fec_enable) 2366 return 0; 2367 2368 if (enabled) 2369 ret = intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), 2370 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2371 else 2372 ret = intel_de_wait_for_clear(display, dp_tp_status_reg(encoder, crtc_state), 2373 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2374 2375 if (ret) { 2376 drm_err(display->drm, 2377 "Timeout waiting for FEC live state to get %s\n", 2378 str_enabled_disabled(enabled)); 2379 return ret; 2380 } 2381 /* 2382 * At least the Synoptics MST hub doesn't set the detected flag for 2383 * FEC decoding disabling so skip waiting for that. 2384 */ 2385 if (enabled) { 2386 ret = wait_for_fec_detected(&intel_dp->aux, enabled); 2387 if (ret) 2388 return ret; 2389 } 2390 2391 return 0; 2392 } 2393 2394 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2395 const struct intel_crtc_state *crtc_state) 2396 { 2397 struct intel_display *display = to_intel_display(encoder); 2398 int i; 2399 int ret; 2400 2401 if (!crtc_state->fec_enable) 2402 return; 2403 2404 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2405 0, DP_TP_CTL_FEC_ENABLE); 2406 2407 if (DISPLAY_VER(display) < 30) 2408 return; 2409 2410 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2411 if (!ret) 2412 return; 2413 2414 for (i = 0; i < 3; i++) { 2415 drm_dbg_kms(display->drm, "Retry FEC enabling\n"); 2416 2417 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2418 DP_TP_CTL_FEC_ENABLE, 0); 2419 2420 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 2421 if (ret) 2422 continue; 2423 2424 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2425 0, DP_TP_CTL_FEC_ENABLE); 2426 2427 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2428 if (!ret) 2429 return; 2430 } 2431 2432 drm_err(display->drm, "Failed to enable FEC after retries\n"); 2433 } 2434 2435 static void intel_ddi_disable_fec(struct intel_encoder *encoder, 2436 const struct intel_crtc_state *crtc_state) 2437 { 2438 struct intel_display *display = to_intel_display(encoder); 2439 2440 if (!crtc_state->fec_enable) 2441 return; 2442 2443 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2444 DP_TP_CTL_FEC_ENABLE, 0); 2445 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 2446 } 2447 2448 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2449 const struct intel_crtc_state *crtc_state) 2450 { 2451 struct intel_display *display = to_intel_display(encoder); 2452 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2453 2454 if (intel_encoder_is_combo(encoder)) { 2455 enum phy phy = intel_encoder_to_phy(encoder); 2456 2457 intel_combo_phy_power_up_lanes(display, phy, false, 2458 crtc_state->lane_count, 2459 dig_port->lane_reversal); 2460 } 2461 } 2462 2463 /* 2464 * Splitter enable for eDP MSO is limited to certain pipes, on certain 2465 * platforms. 2466 */ 2467 static u8 intel_ddi_splitter_pipe_mask(struct intel_display *display) 2468 { 2469 if (DISPLAY_VER(display) > 20) 2470 return ~0; 2471 else if (display->platform.alderlake_p) 2472 return BIT(PIPE_A) | BIT(PIPE_B); 2473 else 2474 return BIT(PIPE_A); 2475 } 2476 2477 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2478 struct intel_crtc_state *pipe_config) 2479 { 2480 struct intel_display *display = to_intel_display(pipe_config); 2481 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2482 enum pipe pipe = crtc->pipe; 2483 u32 dss1; 2484 2485 if (!HAS_MSO(display)) 2486 return; 2487 2488 dss1 = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); 2489 2490 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2491 if (!pipe_config->splitter.enable) 2492 return; 2493 2494 if (drm_WARN_ON(display->drm, !(intel_ddi_splitter_pipe_mask(display) & BIT(pipe)))) { 2495 pipe_config->splitter.enable = false; 2496 return; 2497 } 2498 2499 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2500 default: 2501 drm_WARN(display->drm, true, 2502 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2503 fallthrough; 2504 case SPLITTER_CONFIGURATION_2_SEGMENT: 2505 pipe_config->splitter.link_count = 2; 2506 break; 2507 case SPLITTER_CONFIGURATION_4_SEGMENT: 2508 pipe_config->splitter.link_count = 4; 2509 break; 2510 } 2511 2512 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2513 } 2514 2515 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2516 { 2517 struct intel_display *display = to_intel_display(crtc_state); 2518 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2519 enum pipe pipe = crtc->pipe; 2520 u32 dss1 = 0; 2521 2522 if (!HAS_MSO(display)) 2523 return; 2524 2525 if (crtc_state->splitter.enable) { 2526 dss1 |= SPLITTER_ENABLE; 2527 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2528 if (crtc_state->splitter.link_count == 2) 2529 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2530 else 2531 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2532 } 2533 2534 intel_de_rmw(display, ICL_PIPE_DSS_CTL1(pipe), 2535 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2536 OVERLAP_PIXELS_MASK, dss1); 2537 } 2538 2539 static void 2540 mtl_ddi_enable_d2d(struct intel_encoder *encoder) 2541 { 2542 struct intel_display *display = to_intel_display(encoder); 2543 enum port port = encoder->port; 2544 i915_reg_t reg; 2545 u32 set_bits, wait_bits; 2546 2547 if (DISPLAY_VER(display) < 14) 2548 return; 2549 2550 if (DISPLAY_VER(display) >= 20) { 2551 reg = DDI_BUF_CTL(port); 2552 set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2553 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2554 } else { 2555 reg = XELPDP_PORT_BUF_CTL1(display, port); 2556 set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2557 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2558 } 2559 2560 intel_de_rmw(display, reg, 0, set_bits); 2561 if (wait_for_us(intel_de_read(display, reg) & wait_bits, 100)) { 2562 drm_err(display->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", 2563 port_name(port)); 2564 } 2565 } 2566 2567 static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, 2568 const struct intel_crtc_state *crtc_state) 2569 { 2570 struct intel_display *display = to_intel_display(encoder); 2571 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2572 enum port port = encoder->port; 2573 u32 val = 0; 2574 2575 val |= XELPDP_PORT_WIDTH(crtc_state->lane_count); 2576 2577 if (intel_dp_is_uhbr(crtc_state)) 2578 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; 2579 else 2580 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; 2581 2582 if (dig_port->lane_reversal) 2583 val |= XELPDP_PORT_REVERSAL; 2584 2585 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), 2586 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2587 val); 2588 } 2589 2590 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder) 2591 { 2592 struct intel_display *display = to_intel_display(encoder); 2593 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2594 u32 val; 2595 2596 val = intel_tc_port_in_tbt_alt_mode(dig_port) ? 2597 XELPDP_PORT_BUF_IO_SELECT_TBT : 0; 2598 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), 2599 XELPDP_PORT_BUF_IO_SELECT_TBT, val); 2600 } 2601 2602 static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2603 struct intel_encoder *encoder, 2604 const struct intel_crtc_state *crtc_state, 2605 const struct drm_connector_state *conn_state) 2606 { 2607 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2608 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2609 bool transparent_mode; 2610 int ret; 2611 2612 intel_dp_set_link_params(intel_dp, 2613 crtc_state->port_clock, 2614 crtc_state->lane_count); 2615 2616 /* 2617 * We only configure what the register value will be here. Actual 2618 * enabling happens during link training farther down. 2619 */ 2620 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2621 2622 /* 2623 * 1. Enable Power Wells 2624 * 2625 * This was handled at the beginning of intel_atomic_commit_tail(), 2626 * before we called down into this function. 2627 */ 2628 2629 /* 2. PMdemand was already set */ 2630 2631 /* 3. Select Thunderbolt */ 2632 mtl_port_buf_ctl_io_selection(encoder); 2633 2634 /* 4. Enable Panel Power if PPS is required */ 2635 intel_pps_on(intel_dp); 2636 2637 /* 5. Enable the port PLL */ 2638 intel_ddi_enable_clock(encoder, crtc_state); 2639 2640 /* 2641 * 6.a Configure Transcoder Clock Select to direct the Port clock to the 2642 * Transcoder. 2643 */ 2644 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2645 2646 /* 2647 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. 2648 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2649 * Transport Select 2650 */ 2651 intel_ddi_config_transcoder_func(encoder, crtc_state); 2652 2653 /* 2654 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2655 */ 2656 intel_ddi_mso_configure(crtc_state); 2657 2658 if (!is_mst) 2659 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2660 2661 transparent_mode = intel_dp_lttpr_transparent_mode_enabled(intel_dp); 2662 drm_dp_lttpr_wake_timeout_setup(&intel_dp->aux, transparent_mode); 2663 2664 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2665 if (!is_mst) 2666 intel_dp_sink_enable_decompression(state, 2667 to_intel_connector(conn_state->connector), 2668 crtc_state); 2669 2670 /* 2671 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2672 * in the FEC_CONFIGURATION register to 1 before initiating link 2673 * training 2674 */ 2675 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2676 2677 intel_dp_check_frl_training(intel_dp); 2678 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2679 2680 /* 2681 * 6. The rest of the below are substeps under the bspec's "Enable and 2682 * Train Display Port" step. Note that steps that are specific to 2683 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2684 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2685 * us when active_mst_links==0, so any steps designated for "single 2686 * stream or multi-stream master transcoder" can just be performed 2687 * unconditionally here. 2688 * 2689 * mtl_ddi_prepare_link_retrain() that is called by 2690 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h, 2691 * 6.i and 6.j 2692 * 2693 * 6.k Follow DisplayPort specification training sequence (see notes for 2694 * failure handling) 2695 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2696 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2697 * (timeout after 800 us) 2698 */ 2699 intel_dp_start_link_train(state, intel_dp, crtc_state); 2700 2701 /* 6.n Set DP_TP_CTL link training to Normal */ 2702 if (!is_trans_port_sync_mode(crtc_state)) 2703 intel_dp_stop_link_train(intel_dp, crtc_state); 2704 2705 /* 6.o Configure and enable FEC if needed */ 2706 intel_ddi_enable_fec(encoder, crtc_state); 2707 2708 /* 7.a 128b/132b SST. */ 2709 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2710 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2711 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2712 if (ret < 0) 2713 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2714 } 2715 2716 if (!is_mst) 2717 intel_dsc_dp_pps_write(encoder, crtc_state); 2718 } 2719 2720 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2721 struct intel_encoder *encoder, 2722 const struct intel_crtc_state *crtc_state, 2723 const struct drm_connector_state *conn_state) 2724 { 2725 struct intel_display *display = to_intel_display(encoder); 2726 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2727 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2728 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2729 int ret; 2730 2731 intel_dp_set_link_params(intel_dp, 2732 crtc_state->port_clock, 2733 crtc_state->lane_count); 2734 2735 /* 2736 * We only configure what the register value will be here. Actual 2737 * enabling happens during link training farther down. 2738 */ 2739 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2740 2741 /* 2742 * 1. Enable Power Wells 2743 * 2744 * This was handled at the beginning of intel_atomic_commit_tail(), 2745 * before we called down into this function. 2746 */ 2747 2748 /* 2. Enable Panel Power if PPS is required */ 2749 intel_pps_on(intel_dp); 2750 2751 /* 2752 * 3. For non-TBT Type-C ports, set FIA lane count 2753 * (DFLEXDPSP.DPX4TXLATC) 2754 * 2755 * This was done before tgl_ddi_pre_enable_dp by 2756 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2757 */ 2758 2759 /* 2760 * 4. Enable the port PLL. 2761 * 2762 * The PLL enabling itself was already done before this function by 2763 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2764 * configure the PLL to port mapping here. 2765 */ 2766 intel_ddi_enable_clock(encoder, crtc_state); 2767 2768 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2769 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2770 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2771 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2772 dig_port->ddi_io_power_domain); 2773 } 2774 2775 /* 6. Program DP_MODE */ 2776 icl_program_mg_dp_mode(dig_port, crtc_state); 2777 2778 /* 2779 * 7. The rest of the below are substeps under the bspec's "Enable and 2780 * Train Display Port" step. Note that steps that are specific to 2781 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2782 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2783 * us when active_mst_links==0, so any steps designated for "single 2784 * stream or multi-stream master transcoder" can just be performed 2785 * unconditionally here. 2786 */ 2787 2788 /* 2789 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2790 * Transcoder. 2791 */ 2792 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2793 2794 /* 2795 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2796 * Transport Select 2797 */ 2798 intel_ddi_config_transcoder_func(encoder, crtc_state); 2799 2800 /* 2801 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2802 * selected 2803 * 2804 * This will be handled by the intel_dp_start_link_train() farther 2805 * down this function. 2806 */ 2807 2808 /* 7.e Configure voltage swing and related IO settings */ 2809 encoder->set_signal_levels(encoder, crtc_state); 2810 2811 /* 2812 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2813 * the used lanes of the DDI. 2814 */ 2815 intel_ddi_power_up_lanes(encoder, crtc_state); 2816 2817 /* 2818 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2819 */ 2820 intel_ddi_mso_configure(crtc_state); 2821 2822 if (!is_mst) 2823 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2824 2825 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2826 if (!is_mst) 2827 intel_dp_sink_enable_decompression(state, 2828 to_intel_connector(conn_state->connector), 2829 crtc_state); 2830 /* 2831 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2832 * in the FEC_CONFIGURATION register to 1 before initiating link 2833 * training 2834 */ 2835 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2836 2837 intel_dp_check_frl_training(intel_dp); 2838 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2839 2840 /* 2841 * 7.i Follow DisplayPort specification training sequence (see notes for 2842 * failure handling) 2843 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2844 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2845 * (timeout after 800 us) 2846 */ 2847 intel_dp_start_link_train(state, intel_dp, crtc_state); 2848 2849 /* 7.k Set DP_TP_CTL link training to Normal */ 2850 if (!is_trans_port_sync_mode(crtc_state)) 2851 intel_dp_stop_link_train(intel_dp, crtc_state); 2852 2853 /* 7.l Configure and enable FEC if needed */ 2854 intel_ddi_enable_fec(encoder, crtc_state); 2855 2856 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2857 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2858 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2859 if (ret < 0) 2860 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2861 } 2862 2863 if (!is_mst) 2864 intel_dsc_dp_pps_write(encoder, crtc_state); 2865 } 2866 2867 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2868 struct intel_encoder *encoder, 2869 const struct intel_crtc_state *crtc_state, 2870 const struct drm_connector_state *conn_state) 2871 { 2872 struct intel_display *display = to_intel_display(encoder); 2873 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2874 enum port port = encoder->port; 2875 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2876 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2877 2878 if (DISPLAY_VER(display) < 11) 2879 drm_WARN_ON(display->drm, 2880 is_mst && (port == PORT_A || port == PORT_E)); 2881 else 2882 drm_WARN_ON(display->drm, is_mst && port == PORT_A); 2883 2884 intel_dp_set_link_params(intel_dp, 2885 crtc_state->port_clock, 2886 crtc_state->lane_count); 2887 2888 /* 2889 * We only configure what the register value will be here. Actual 2890 * enabling happens during link training farther down. 2891 */ 2892 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2893 2894 intel_pps_on(intel_dp); 2895 2896 intel_ddi_enable_clock(encoder, crtc_state); 2897 2898 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2899 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2900 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2901 dig_port->ddi_io_power_domain); 2902 } 2903 2904 icl_program_mg_dp_mode(dig_port, crtc_state); 2905 2906 if (has_buf_trans_select(display)) 2907 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2908 2909 encoder->set_signal_levels(encoder, crtc_state); 2910 2911 intel_ddi_power_up_lanes(encoder, crtc_state); 2912 2913 if (!is_mst) 2914 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2915 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2916 if (!is_mst) 2917 intel_dp_sink_enable_decompression(state, 2918 to_intel_connector(conn_state->connector), 2919 crtc_state); 2920 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2921 intel_dp_start_link_train(state, intel_dp, crtc_state); 2922 if ((port != PORT_A || DISPLAY_VER(display) >= 9) && 2923 !is_trans_port_sync_mode(crtc_state)) 2924 intel_dp_stop_link_train(intel_dp, crtc_state); 2925 2926 intel_ddi_enable_fec(encoder, crtc_state); 2927 2928 if (!is_mst) { 2929 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2930 intel_dsc_dp_pps_write(encoder, crtc_state); 2931 } 2932 } 2933 2934 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2935 struct intel_encoder *encoder, 2936 const struct intel_crtc_state *crtc_state, 2937 const struct drm_connector_state *conn_state) 2938 { 2939 struct intel_display *display = to_intel_display(encoder); 2940 2941 if (HAS_DP20(display)) 2942 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), 2943 crtc_state); 2944 2945 /* Panel replay has to be enabled in sink dpcd before link training. */ 2946 intel_psr_panel_replay_enable_sink(enc_to_intel_dp(encoder)); 2947 2948 if (DISPLAY_VER(display) >= 14) 2949 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2950 else if (DISPLAY_VER(display) >= 12) 2951 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2952 else 2953 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2954 2955 /* MST will call a setting of MSA after an allocating of Virtual Channel 2956 * from MST encoder pre_enable callback. 2957 */ 2958 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2959 intel_ddi_set_dp_msa(crtc_state, conn_state); 2960 } 2961 2962 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2963 struct intel_encoder *encoder, 2964 const struct intel_crtc_state *crtc_state, 2965 const struct drm_connector_state *conn_state) 2966 { 2967 struct intel_display *display = to_intel_display(encoder); 2968 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2969 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2970 2971 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2972 intel_ddi_enable_clock(encoder, crtc_state); 2973 2974 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2975 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2976 dig_port->ddi_io_power_domain); 2977 2978 icl_program_mg_dp_mode(dig_port, crtc_state); 2979 2980 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2981 2982 dig_port->set_infoframes(encoder, 2983 crtc_state->has_infoframe, 2984 crtc_state, conn_state); 2985 } 2986 2987 /* 2988 * Note: Also called from the ->pre_enable of the first active MST stream 2989 * encoder on its primary encoder. 2990 * 2991 * When called from DP MST code: 2992 * 2993 * - conn_state will be NULL 2994 * 2995 * - encoder will be the primary encoder (i.e. mst->primary) 2996 * 2997 * - the main connector associated with this port won't be active or linked to a 2998 * crtc 2999 * 3000 * - crtc_state will be the state of the first stream to be activated on this 3001 * port, and it may not be the same stream that will be deactivated last, but 3002 * each stream should have a state that is identical when it comes to the DP 3003 * link parameters. 3004 */ 3005 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 3006 struct intel_encoder *encoder, 3007 const struct intel_crtc_state *crtc_state, 3008 const struct drm_connector_state *conn_state) 3009 { 3010 struct intel_display *display = to_intel_display(state); 3011 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3012 enum pipe pipe = crtc->pipe; 3013 3014 drm_WARN_ON(display->drm, crtc_state->has_pch_encoder); 3015 3016 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 3017 3018 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 3019 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 3020 conn_state); 3021 } else { 3022 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3023 3024 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 3025 conn_state); 3026 3027 /* FIXME precompute everything properly */ 3028 /* FIXME how do we turn infoframes off again? */ 3029 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp)) 3030 dig_port->set_infoframes(encoder, 3031 crtc_state->has_infoframe, 3032 crtc_state, conn_state); 3033 } 3034 } 3035 3036 static void 3037 mtl_ddi_disable_d2d(struct intel_encoder *encoder) 3038 { 3039 struct intel_display *display = to_intel_display(encoder); 3040 enum port port = encoder->port; 3041 i915_reg_t reg; 3042 u32 clr_bits, wait_bits; 3043 3044 if (DISPLAY_VER(display) < 14) 3045 return; 3046 3047 if (DISPLAY_VER(display) >= 20) { 3048 reg = DDI_BUF_CTL(port); 3049 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3050 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 3051 } else { 3052 reg = XELPDP_PORT_BUF_CTL1(display, port); 3053 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 3054 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 3055 } 3056 3057 intel_de_rmw(display, reg, clr_bits, 0); 3058 if (wait_for_us(!(intel_de_read(display, reg) & wait_bits), 100)) 3059 drm_err(display->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", 3060 port_name(port)); 3061 } 3062 3063 static void intel_ddi_buf_enable(struct intel_encoder *encoder, u32 buf_ctl) 3064 { 3065 struct intel_display *display = to_intel_display(encoder); 3066 enum port port = encoder->port; 3067 3068 intel_de_write(display, DDI_BUF_CTL(port), buf_ctl | DDI_BUF_CTL_ENABLE); 3069 intel_de_posting_read(display, DDI_BUF_CTL(port)); 3070 3071 intel_wait_ddi_buf_active(encoder); 3072 } 3073 3074 static void intel_ddi_buf_disable(struct intel_encoder *encoder, 3075 const struct intel_crtc_state *crtc_state) 3076 { 3077 struct intel_display *display = to_intel_display(encoder); 3078 enum port port = encoder->port; 3079 3080 intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); 3081 3082 if (DISPLAY_VER(display) >= 14) 3083 intel_wait_ddi_buf_idle(display, port); 3084 3085 mtl_ddi_disable_d2d(encoder); 3086 3087 if (intel_crtc_has_dp_encoder(crtc_state)) { 3088 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 3089 DP_TP_CTL_ENABLE, 0); 3090 } 3091 3092 intel_ddi_disable_fec(encoder, crtc_state); 3093 3094 if (DISPLAY_VER(display) < 14) 3095 intel_wait_ddi_buf_idle(display, port); 3096 3097 intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 3098 } 3099 3100 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3101 struct intel_encoder *encoder, 3102 const struct intel_crtc_state *old_crtc_state, 3103 const struct drm_connector_state *old_conn_state) 3104 { 3105 struct intel_display *display = to_intel_display(encoder); 3106 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3107 struct intel_dp *intel_dp = &dig_port->dp; 3108 intel_wakeref_t wakeref; 3109 bool is_mst = intel_crtc_has_type(old_crtc_state, 3110 INTEL_OUTPUT_DP_MST); 3111 3112 if (!is_mst) 3113 intel_dp_set_infoframes(encoder, false, 3114 old_crtc_state, old_conn_state); 3115 3116 /* 3117 * Power down sink before disabling the port, otherwise we end 3118 * up getting interrupts from the sink on detecting link loss. 3119 */ 3120 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 3121 3122 if (DISPLAY_VER(display) >= 12) { 3123 if (is_mst || intel_dp_is_uhbr(old_crtc_state)) { 3124 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3125 3126 intel_de_rmw(display, 3127 TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 3128 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 3129 0); 3130 } 3131 } else { 3132 if (!is_mst) 3133 intel_ddi_disable_transcoder_clock(old_crtc_state); 3134 } 3135 3136 intel_ddi_buf_disable(encoder, old_crtc_state); 3137 3138 intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); 3139 3140 intel_ddi_config_transcoder_dp2(old_crtc_state, false); 3141 3142 /* 3143 * From TGL spec: "If single stream or multi-stream master transcoder: 3144 * Configure Transcoder Clock select to direct no clock to the 3145 * transcoder" 3146 */ 3147 if (DISPLAY_VER(display) >= 12) 3148 intel_ddi_disable_transcoder_clock(old_crtc_state); 3149 3150 intel_pps_vdd_on(intel_dp); 3151 intel_pps_off(intel_dp); 3152 3153 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3154 3155 if (wakeref) 3156 intel_display_power_put(display, 3157 dig_port->ddi_io_power_domain, 3158 wakeref); 3159 3160 intel_ddi_disable_clock(encoder); 3161 3162 /* De-select Thunderbolt */ 3163 if (DISPLAY_VER(display) >= 14) 3164 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), 3165 XELPDP_PORT_BUF_IO_SELECT_TBT, 0); 3166 } 3167 3168 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3169 struct intel_encoder *encoder, 3170 const struct intel_crtc_state *old_crtc_state, 3171 const struct drm_connector_state *old_conn_state) 3172 { 3173 struct intel_display *display = to_intel_display(encoder); 3174 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3175 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3176 intel_wakeref_t wakeref; 3177 3178 dig_port->set_infoframes(encoder, false, 3179 old_crtc_state, old_conn_state); 3180 3181 if (DISPLAY_VER(display) < 12) 3182 intel_ddi_disable_transcoder_clock(old_crtc_state); 3183 3184 intel_ddi_buf_disable(encoder, old_crtc_state); 3185 3186 if (DISPLAY_VER(display) >= 12) 3187 intel_ddi_disable_transcoder_clock(old_crtc_state); 3188 3189 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3190 if (wakeref) 3191 intel_display_power_put(display, 3192 dig_port->ddi_io_power_domain, 3193 wakeref); 3194 3195 intel_ddi_disable_clock(encoder); 3196 3197 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3198 } 3199 3200 static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, 3201 struct intel_encoder *encoder, 3202 const struct intel_crtc_state *old_crtc_state, 3203 const struct drm_connector_state *old_conn_state) 3204 { 3205 struct intel_display *display = to_intel_display(encoder); 3206 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3207 struct intel_crtc *pipe_crtc; 3208 bool is_hdmi = intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI); 3209 int i; 3210 3211 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 3212 const struct intel_crtc_state *old_pipe_crtc_state = 3213 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3214 3215 intel_crtc_vblank_off(old_pipe_crtc_state); 3216 } 3217 3218 intel_disable_transcoder(old_crtc_state); 3219 3220 /* 128b/132b SST */ 3221 if (!is_hdmi && intel_dp_is_uhbr(old_crtc_state)) { 3222 /* VCPID 1, start slot 0 for 128b/132b, clear */ 3223 drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, 0); 3224 3225 intel_ddi_clear_act_sent(encoder, old_crtc_state); 3226 3227 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder), 3228 TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0); 3229 3230 intel_ddi_wait_for_act_sent(encoder, old_crtc_state); 3231 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3232 } 3233 3234 intel_vrr_transcoder_disable(old_crtc_state); 3235 3236 intel_ddi_disable_transcoder_func(old_crtc_state); 3237 3238 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 3239 const struct intel_crtc_state *old_pipe_crtc_state = 3240 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3241 3242 intel_dsc_disable(old_pipe_crtc_state); 3243 3244 if (DISPLAY_VER(display) >= 9) 3245 skl_scaler_disable(old_pipe_crtc_state); 3246 else 3247 ilk_pfit_disable(old_pipe_crtc_state); 3248 } 3249 } 3250 3251 /* 3252 * Note: Also called from the ->post_disable of the last active MST stream 3253 * encoder on its primary encoder. See also the comment for 3254 * intel_ddi_pre_enable(). 3255 */ 3256 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3257 struct intel_encoder *encoder, 3258 const struct intel_crtc_state *old_crtc_state, 3259 const struct drm_connector_state *old_conn_state) 3260 { 3261 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 3262 intel_ddi_post_disable_hdmi_or_sst(state, encoder, old_crtc_state, 3263 old_conn_state); 3264 3265 /* 3266 * When called from DP MST code: 3267 * - old_conn_state will be NULL 3268 * - encoder will be the main encoder (ie. mst->primary) 3269 * - the main connector associated with this port 3270 * won't be active or linked to a crtc 3271 * - old_crtc_state will be the state of the last stream to 3272 * be deactivated on this port, and it may not be the same 3273 * stream that was activated last, but each stream 3274 * should have a state that is identical when it comes to 3275 * the DP link parameters 3276 */ 3277 3278 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3279 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3280 old_conn_state); 3281 else 3282 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3283 old_conn_state); 3284 } 3285 3286 /* 3287 * Note: Also called from the ->post_pll_disable of the last active MST stream 3288 * encoder on its primary encoder. See also the comment for 3289 * intel_ddi_pre_enable(). 3290 */ 3291 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state, 3292 struct intel_encoder *encoder, 3293 const struct intel_crtc_state *old_crtc_state, 3294 const struct drm_connector_state *old_conn_state) 3295 { 3296 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3297 3298 main_link_aux_power_domain_put(dig_port, old_crtc_state); 3299 3300 if (intel_encoder_is_tc(encoder)) 3301 intel_tc_port_put_link(dig_port); 3302 } 3303 3304 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3305 struct intel_encoder *encoder, 3306 const struct intel_crtc_state *crtc_state) 3307 { 3308 const struct drm_connector_state *conn_state; 3309 struct drm_connector *conn; 3310 int i; 3311 3312 if (!crtc_state->sync_mode_slaves_mask) 3313 return; 3314 3315 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3316 struct intel_encoder *slave_encoder = 3317 to_intel_encoder(conn_state->best_encoder); 3318 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3319 const struct intel_crtc_state *slave_crtc_state; 3320 3321 if (!slave_crtc) 3322 continue; 3323 3324 slave_crtc_state = 3325 intel_atomic_get_new_crtc_state(state, slave_crtc); 3326 3327 if (slave_crtc_state->master_transcoder != 3328 crtc_state->cpu_transcoder) 3329 continue; 3330 3331 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3332 slave_crtc_state); 3333 } 3334 3335 usleep_range(200, 400); 3336 3337 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3338 crtc_state); 3339 } 3340 3341 static void intel_ddi_enable_dp(struct intel_atomic_state *state, 3342 struct intel_encoder *encoder, 3343 const struct intel_crtc_state *crtc_state, 3344 const struct drm_connector_state *conn_state) 3345 { 3346 struct intel_display *display = to_intel_display(encoder); 3347 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3348 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3349 enum port port = encoder->port; 3350 3351 if (port == PORT_A && DISPLAY_VER(display) < 9) 3352 intel_dp_stop_link_train(intel_dp, crtc_state); 3353 3354 drm_connector_update_privacy_screen(conn_state); 3355 intel_edp_backlight_on(crtc_state, conn_state); 3356 3357 if (!intel_lspcon_active(dig_port) || intel_dp_has_hdmi_sink(&dig_port->dp)) 3358 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3359 3360 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3361 } 3362 3363 static i915_reg_t 3364 gen9_chicken_trans_reg_by_port(struct intel_display *display, enum port port) 3365 { 3366 static const enum transcoder trans[] = { 3367 [PORT_A] = TRANSCODER_EDP, 3368 [PORT_B] = TRANSCODER_A, 3369 [PORT_C] = TRANSCODER_B, 3370 [PORT_D] = TRANSCODER_C, 3371 [PORT_E] = TRANSCODER_A, 3372 }; 3373 3374 drm_WARN_ON(display->drm, DISPLAY_VER(display) < 9); 3375 3376 if (drm_WARN_ON(display->drm, port < PORT_A || port > PORT_E)) 3377 port = PORT_A; 3378 3379 return CHICKEN_TRANS(display, trans[port]); 3380 } 3381 3382 static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, 3383 struct intel_encoder *encoder, 3384 const struct intel_crtc_state *crtc_state, 3385 const struct drm_connector_state *conn_state) 3386 { 3387 struct intel_display *display = to_intel_display(encoder); 3388 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3389 struct drm_connector *connector = conn_state->connector; 3390 enum port port = encoder->port; 3391 u32 buf_ctl = 0; 3392 3393 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3394 crtc_state->hdmi_high_tmds_clock_ratio, 3395 crtc_state->hdmi_scrambling)) 3396 drm_dbg_kms(display->drm, 3397 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3398 connector->base.id, connector->name); 3399 3400 if (has_buf_trans_select(display)) 3401 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 3402 3403 /* e. Enable D2D Link for C10/C20 Phy */ 3404 mtl_ddi_enable_d2d(encoder); 3405 3406 encoder->set_signal_levels(encoder, crtc_state); 3407 3408 /* Display WA #1143: skl,kbl,cfl */ 3409 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) { 3410 /* 3411 * For some reason these chicken bits have been 3412 * stuffed into a transcoder register, event though 3413 * the bits affect a specific DDI port rather than 3414 * a specific transcoder. 3415 */ 3416 i915_reg_t reg = gen9_chicken_trans_reg_by_port(display, port); 3417 u32 val; 3418 3419 val = intel_de_read(display, reg); 3420 3421 if (port == PORT_E) 3422 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3423 DDIE_TRAINING_OVERRIDE_VALUE; 3424 else 3425 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3426 DDI_TRAINING_OVERRIDE_VALUE; 3427 3428 intel_de_write(display, reg, val); 3429 intel_de_posting_read(display, reg); 3430 3431 udelay(1); 3432 3433 if (port == PORT_E) 3434 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3435 DDIE_TRAINING_OVERRIDE_VALUE); 3436 else 3437 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3438 DDI_TRAINING_OVERRIDE_VALUE); 3439 3440 intel_de_write(display, reg, val); 3441 } 3442 3443 intel_ddi_power_up_lanes(encoder, crtc_state); 3444 3445 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3446 * are ignored so nothing special needs to be done besides 3447 * enabling the port. 3448 * 3449 * On ADL_P the PHY link rate and lane count must be programmed but 3450 * these are both 0 for HDMI. 3451 * 3452 * But MTL onwards HDMI2.1 is supported and in TMDS mode this 3453 * is filled with lane count, already set in the crtc_state. 3454 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. 3455 */ 3456 if (dig_port->lane_reversal) 3457 buf_ctl |= DDI_BUF_PORT_REVERSAL; 3458 if (dig_port->ddi_a_4_lanes) 3459 buf_ctl |= DDI_A_4_LANES; 3460 3461 if (DISPLAY_VER(display) >= 14) { 3462 u32 port_buf = 0; 3463 3464 port_buf |= XELPDP_PORT_WIDTH(crtc_state->lane_count); 3465 3466 if (dig_port->lane_reversal) 3467 port_buf |= XELPDP_PORT_REVERSAL; 3468 3469 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), 3470 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); 3471 3472 buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count); 3473 3474 if (DISPLAY_VER(display) >= 20) 3475 buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3476 } else if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { 3477 drm_WARN_ON(display->drm, !intel_tc_port_in_legacy_mode(dig_port)); 3478 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 3479 } 3480 3481 intel_ddi_buf_enable(encoder, buf_ctl); 3482 } 3483 3484 static void intel_ddi_enable(struct intel_atomic_state *state, 3485 struct intel_encoder *encoder, 3486 const struct intel_crtc_state *crtc_state, 3487 const struct drm_connector_state *conn_state) 3488 { 3489 struct intel_display *display = to_intel_display(encoder); 3490 struct intel_crtc *pipe_crtc; 3491 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3492 bool is_hdmi = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI); 3493 int i; 3494 3495 /* 128b/132b SST */ 3496 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3497 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 3498 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); 3499 3500 intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder), 3501 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); 3502 intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder), 3503 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); 3504 } 3505 3506 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3507 3508 intel_vrr_transcoder_enable(crtc_state); 3509 3510 /* 128b/132b SST */ 3511 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3512 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3513 3514 intel_ddi_clear_act_sent(encoder, crtc_state); 3515 3516 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 0, 3517 TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 3518 3519 intel_ddi_wait_for_act_sent(encoder, crtc_state); 3520 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3521 } 3522 3523 intel_enable_transcoder(crtc_state); 3524 3525 intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 3526 3527 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state, i) { 3528 const struct intel_crtc_state *pipe_crtc_state = 3529 intel_atomic_get_new_crtc_state(state, pipe_crtc); 3530 3531 intel_crtc_vblank_on(pipe_crtc_state); 3532 } 3533 3534 if (is_hdmi) 3535 intel_ddi_enable_hdmi(state, encoder, crtc_state, conn_state); 3536 else 3537 intel_ddi_enable_dp(state, encoder, crtc_state, conn_state); 3538 3539 intel_hdcp_enable(state, encoder, crtc_state, conn_state); 3540 3541 } 3542 3543 static void intel_ddi_disable_dp(struct intel_atomic_state *state, 3544 struct intel_encoder *encoder, 3545 const struct intel_crtc_state *old_crtc_state, 3546 const struct drm_connector_state *old_conn_state) 3547 { 3548 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3549 struct intel_connector *connector = 3550 to_intel_connector(old_conn_state->connector); 3551 3552 intel_dp->link.active = false; 3553 3554 intel_psr_disable(intel_dp, old_crtc_state); 3555 intel_alpm_disable(intel_dp); 3556 intel_edp_backlight_off(old_conn_state); 3557 /* Disable the decompression in DP Sink */ 3558 intel_dp_sink_disable_decompression(state, 3559 connector, old_crtc_state); 3560 /* Disable Ignore_MSA bit in DP Sink */ 3561 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3562 false); 3563 } 3564 3565 static void intel_ddi_disable_hdmi(struct intel_atomic_state *state, 3566 struct intel_encoder *encoder, 3567 const struct intel_crtc_state *old_crtc_state, 3568 const struct drm_connector_state *old_conn_state) 3569 { 3570 struct intel_display *display = to_intel_display(encoder); 3571 struct drm_connector *connector = old_conn_state->connector; 3572 3573 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3574 false, false)) 3575 drm_dbg_kms(display->drm, 3576 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3577 connector->base.id, connector->name); 3578 } 3579 3580 static void intel_ddi_disable(struct intel_atomic_state *state, 3581 struct intel_encoder *encoder, 3582 const struct intel_crtc_state *old_crtc_state, 3583 const struct drm_connector_state *old_conn_state) 3584 { 3585 intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder)); 3586 3587 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3588 3589 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3590 intel_ddi_disable_hdmi(state, encoder, old_crtc_state, 3591 old_conn_state); 3592 else 3593 intel_ddi_disable_dp(state, encoder, old_crtc_state, 3594 old_conn_state); 3595 } 3596 3597 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3598 struct intel_encoder *encoder, 3599 const struct intel_crtc_state *crtc_state, 3600 const struct drm_connector_state *conn_state) 3601 { 3602 intel_ddi_set_dp_msa(crtc_state, conn_state); 3603 3604 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3605 3606 intel_backlight_update(state, encoder, crtc_state, conn_state); 3607 drm_connector_update_privacy_screen(conn_state); 3608 } 3609 3610 static void intel_ddi_update_pipe_hdmi(struct intel_encoder *encoder, 3611 const struct intel_crtc_state *crtc_state, 3612 const struct drm_connector_state *conn_state) 3613 { 3614 intel_hdmi_fastset_infoframes(encoder, crtc_state, conn_state); 3615 } 3616 3617 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3618 struct intel_encoder *encoder, 3619 const struct intel_crtc_state *crtc_state, 3620 const struct drm_connector_state *conn_state) 3621 { 3622 3623 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3624 !intel_encoder_is_mst(encoder)) 3625 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3626 conn_state); 3627 3628 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3629 intel_ddi_update_pipe_hdmi(encoder, crtc_state, 3630 conn_state); 3631 3632 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3633 } 3634 3635 void intel_ddi_update_active_dpll(struct intel_atomic_state *state, 3636 struct intel_encoder *encoder, 3637 struct intel_crtc *crtc) 3638 { 3639 struct intel_display *display = to_intel_display(encoder); 3640 const struct intel_crtc_state *crtc_state = 3641 intel_atomic_get_new_crtc_state(state, crtc); 3642 struct intel_crtc *pipe_crtc; 3643 3644 /* FIXME: Add MTL pll_mgr */ 3645 if (DISPLAY_VER(display) >= 14 || !intel_encoder_is_tc(encoder)) 3646 return; 3647 3648 for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, 3649 intel_crtc_joined_pipe_mask(crtc_state)) 3650 intel_update_active_dpll(state, pipe_crtc, encoder); 3651 } 3652 3653 /* 3654 * Note: Also called from the ->pre_pll_enable of the first active MST stream 3655 * encoder on its primary encoder. See also the comment for 3656 * intel_ddi_pre_enable(). 3657 */ 3658 static void 3659 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3660 struct intel_encoder *encoder, 3661 const struct intel_crtc_state *crtc_state, 3662 const struct drm_connector_state *conn_state) 3663 { 3664 struct intel_display *display = to_intel_display(encoder); 3665 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3666 bool is_tc_port = intel_encoder_is_tc(encoder); 3667 3668 if (is_tc_port) { 3669 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3670 3671 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3672 intel_ddi_update_active_dpll(state, encoder, crtc); 3673 } 3674 3675 main_link_aux_power_domain_get(dig_port, crtc_state); 3676 3677 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3678 /* 3679 * Program the lane count for static/dynamic connections on 3680 * Type-C ports. Skip this step for TBT. 3681 */ 3682 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3683 else if (display->platform.geminilake || display->platform.broxton) 3684 bxt_dpio_phy_set_lane_optim_mask(encoder, 3685 crtc_state->lane_lat_optim_mask); 3686 } 3687 3688 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3689 { 3690 struct intel_display *display = to_intel_display(encoder); 3691 enum tc_port tc_port = intel_encoder_to_tc(encoder); 3692 int ln; 3693 3694 for (ln = 0; ln < 2; ln++) 3695 intel_dkl_phy_rmw(display, DKL_PCS_DW5(tc_port, ln), 3696 DKL_PCS_DW5_CORE_SOFTRESET, 0); 3697 } 3698 3699 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3700 const struct intel_crtc_state *crtc_state) 3701 { 3702 struct intel_display *display = to_intel_display(crtc_state); 3703 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3704 struct intel_encoder *encoder = &dig_port->base; 3705 u32 dp_tp_ctl; 3706 3707 /* 3708 * TODO: To train with only a different voltage swing entry is not 3709 * necessary disable and enable port 3710 */ 3711 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3712 3713 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); 3714 3715 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ 3716 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3717 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3718 intel_dp_is_uhbr(crtc_state)) { 3719 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3720 } else { 3721 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3722 if (crtc_state->enhanced_framing) 3723 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3724 } 3725 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3726 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3727 3728 /* 6.f Enable D2D Link */ 3729 mtl_ddi_enable_d2d(encoder); 3730 3731 /* 6.g Configure voltage swing and related IO settings */ 3732 encoder->set_signal_levels(encoder, crtc_state); 3733 3734 /* 6.h Configure PORT_BUF_CTL1 */ 3735 mtl_port_buf_ctl_program(encoder, crtc_state); 3736 3737 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ 3738 if (DISPLAY_VER(display) >= 20) 3739 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3740 3741 intel_ddi_buf_enable(encoder, intel_dp->DP); 3742 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3743 } 3744 3745 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3746 const struct intel_crtc_state *crtc_state) 3747 { 3748 struct intel_display *display = to_intel_display(intel_dp); 3749 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3750 struct intel_encoder *encoder = &dig_port->base; 3751 u32 dp_tp_ctl; 3752 3753 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3754 3755 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); 3756 3757 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3758 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3759 intel_dp_is_uhbr(crtc_state)) { 3760 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3761 } else { 3762 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3763 if (crtc_state->enhanced_framing) 3764 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3765 } 3766 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3767 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3768 3769 if (display->platform.alderlake_p && 3770 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3771 adlp_tbt_to_dp_alt_switch_wa(encoder); 3772 3773 intel_ddi_buf_enable(encoder, intel_dp->DP); 3774 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3775 } 3776 3777 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3778 const struct intel_crtc_state *crtc_state, 3779 u8 dp_train_pat) 3780 { 3781 struct intel_display *display = to_intel_display(intel_dp); 3782 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3783 u32 temp; 3784 3785 temp = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3786 3787 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3788 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3789 case DP_TRAINING_PATTERN_DISABLE: 3790 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3791 break; 3792 case DP_TRAINING_PATTERN_1: 3793 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3794 break; 3795 case DP_TRAINING_PATTERN_2: 3796 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3797 break; 3798 case DP_TRAINING_PATTERN_3: 3799 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3800 break; 3801 case DP_TRAINING_PATTERN_4: 3802 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3803 break; 3804 } 3805 3806 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), temp); 3807 } 3808 3809 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3810 const struct intel_crtc_state *crtc_state) 3811 { 3812 struct intel_display *display = to_intel_display(intel_dp); 3813 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3814 enum port port = encoder->port; 3815 3816 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 3817 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); 3818 3819 /* 3820 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3821 * reason we need to set idle transmission mode is to work around a HW 3822 * issue where we enable the pipe while not in idle link-training mode. 3823 * In this case there is requirement to wait for a minimum number of 3824 * idle patterns to be sent. 3825 */ 3826 if (port == PORT_A && DISPLAY_VER(display) < 12) 3827 return; 3828 3829 if (intel_de_wait_for_set(display, 3830 dp_tp_status_reg(encoder, crtc_state), 3831 DP_TP_STATUS_IDLE_DONE, 2)) 3832 drm_err(display->drm, 3833 "Timed out waiting for DP idle patterns\n"); 3834 } 3835 3836 static bool intel_ddi_is_audio_enabled(struct intel_display *display, 3837 enum transcoder cpu_transcoder) 3838 { 3839 if (cpu_transcoder == TRANSCODER_EDP) 3840 return false; 3841 3842 if (!intel_display_power_is_enabled(display, POWER_DOMAIN_AUDIO_MMIO)) 3843 return false; 3844 3845 return intel_de_read(display, HSW_AUD_PIN_ELD_CP_VLD) & 3846 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3847 } 3848 3849 static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3850 { 3851 if (crtc_state->port_clock > 594000) 3852 return 2; 3853 else 3854 return 0; 3855 } 3856 3857 static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3858 { 3859 if (crtc_state->port_clock > 594000) 3860 return 3; 3861 else 3862 return 0; 3863 } 3864 3865 static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3866 { 3867 if (crtc_state->port_clock > 594000) 3868 return 1; 3869 else 3870 return 0; 3871 } 3872 3873 void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state) 3874 { 3875 struct intel_display *display = to_intel_display(crtc_state); 3876 3877 if (DISPLAY_VER(display) >= 14) 3878 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3879 else if (DISPLAY_VER(display) >= 12) 3880 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); 3881 else if (display->platform.jasperlake || display->platform.elkhartlake) 3882 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); 3883 else if (DISPLAY_VER(display) >= 11) 3884 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3885 } 3886 3887 static enum transcoder bdw_transcoder_master_readout(struct intel_display *display, 3888 enum transcoder cpu_transcoder) 3889 { 3890 u32 master_select; 3891 3892 if (DISPLAY_VER(display) >= 11) { 3893 u32 ctl2 = intel_de_read(display, 3894 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder)); 3895 3896 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3897 return INVALID_TRANSCODER; 3898 3899 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3900 } else { 3901 u32 ctl = intel_de_read(display, 3902 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 3903 3904 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3905 return INVALID_TRANSCODER; 3906 3907 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3908 } 3909 3910 if (master_select == 0) 3911 return TRANSCODER_EDP; 3912 else 3913 return master_select - 1; 3914 } 3915 3916 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3917 { 3918 struct intel_display *display = to_intel_display(crtc_state); 3919 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3920 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3921 enum transcoder cpu_transcoder; 3922 3923 crtc_state->master_transcoder = 3924 bdw_transcoder_master_readout(display, crtc_state->cpu_transcoder); 3925 3926 for_each_cpu_transcoder_masked(display, cpu_transcoder, transcoders) { 3927 enum intel_display_power_domain power_domain; 3928 intel_wakeref_t trans_wakeref; 3929 3930 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3931 trans_wakeref = intel_display_power_get_if_enabled(display, 3932 power_domain); 3933 3934 if (!trans_wakeref) 3935 continue; 3936 3937 if (bdw_transcoder_master_readout(display, cpu_transcoder) == 3938 crtc_state->cpu_transcoder) 3939 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3940 3941 intel_display_power_put(display, power_domain, trans_wakeref); 3942 } 3943 3944 drm_WARN_ON(display->drm, 3945 crtc_state->master_transcoder != INVALID_TRANSCODER && 3946 crtc_state->sync_mode_slaves_mask); 3947 } 3948 3949 static void intel_ddi_read_func_ctl_dvi(struct intel_encoder *encoder, 3950 struct intel_crtc_state *crtc_state, 3951 u32 ddi_func_ctl) 3952 { 3953 struct intel_display *display = to_intel_display(encoder); 3954 3955 crtc_state->output_types |= BIT(INTEL_OUTPUT_HDMI); 3956 if (DISPLAY_VER(display) >= 14) 3957 crtc_state->lane_count = 3958 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3959 else 3960 crtc_state->lane_count = 4; 3961 } 3962 3963 static void intel_ddi_read_func_ctl_hdmi(struct intel_encoder *encoder, 3964 struct intel_crtc_state *crtc_state, 3965 u32 ddi_func_ctl) 3966 { 3967 crtc_state->has_hdmi_sink = true; 3968 3969 crtc_state->infoframes.enable |= 3970 intel_hdmi_infoframes_enabled(encoder, crtc_state); 3971 3972 if (crtc_state->infoframes.enable) 3973 crtc_state->has_infoframe = true; 3974 3975 if (ddi_func_ctl & TRANS_DDI_HDMI_SCRAMBLING) 3976 crtc_state->hdmi_scrambling = true; 3977 if (ddi_func_ctl & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3978 crtc_state->hdmi_high_tmds_clock_ratio = true; 3979 3980 intel_ddi_read_func_ctl_dvi(encoder, crtc_state, ddi_func_ctl); 3981 } 3982 3983 static void intel_ddi_read_func_ctl_fdi(struct intel_encoder *encoder, 3984 struct intel_crtc_state *crtc_state, 3985 u32 ddi_func_ctl) 3986 { 3987 struct intel_display *display = to_intel_display(encoder); 3988 3989 crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG); 3990 crtc_state->enhanced_framing = 3991 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 3992 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3993 } 3994 3995 static void intel_ddi_read_func_ctl_dp_sst(struct intel_encoder *encoder, 3996 struct intel_crtc_state *crtc_state, 3997 u32 ddi_func_ctl) 3998 { 3999 struct intel_display *display = to_intel_display(encoder); 4000 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4001 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4002 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4003 4004 if (encoder->type == INTEL_OUTPUT_EDP) 4005 crtc_state->output_types |= BIT(INTEL_OUTPUT_EDP); 4006 else 4007 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP); 4008 crtc_state->lane_count = 4009 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4010 4011 if (DISPLAY_VER(display) >= 12 && 4012 (ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B) 4013 crtc_state->mst_master_transcoder = 4014 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4015 4016 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4017 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2); 4018 4019 crtc_state->enhanced_framing = 4020 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4021 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4022 4023 if (DISPLAY_VER(display) >= 11) 4024 crtc_state->fec_enable = 4025 intel_de_read(display, 4026 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4027 4028 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp)) 4029 crtc_state->infoframes.enable |= 4030 intel_lspcon_infoframes_enabled(encoder, crtc_state); 4031 else 4032 crtc_state->infoframes.enable |= 4033 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4034 } 4035 4036 static void intel_ddi_read_func_ctl_dp_mst(struct intel_encoder *encoder, 4037 struct intel_crtc_state *crtc_state, 4038 u32 ddi_func_ctl) 4039 { 4040 struct intel_display *display = to_intel_display(encoder); 4041 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4042 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4043 4044 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP_MST); 4045 crtc_state->lane_count = 4046 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4047 4048 if (DISPLAY_VER(display) >= 12) 4049 crtc_state->mst_master_transcoder = 4050 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4051 4052 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4053 4054 if (DISPLAY_VER(display) >= 11) 4055 crtc_state->fec_enable = 4056 intel_de_read(display, 4057 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4058 4059 crtc_state->infoframes.enable |= 4060 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4061 } 4062 4063 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 4064 struct intel_crtc_state *pipe_config) 4065 { 4066 struct intel_display *display = to_intel_display(encoder); 4067 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4068 u32 ddi_func_ctl, ddi_mode, flags = 0; 4069 4070 ddi_func_ctl = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 4071 if (ddi_func_ctl & TRANS_DDI_PHSYNC) 4072 flags |= DRM_MODE_FLAG_PHSYNC; 4073 else 4074 flags |= DRM_MODE_FLAG_NHSYNC; 4075 if (ddi_func_ctl & TRANS_DDI_PVSYNC) 4076 flags |= DRM_MODE_FLAG_PVSYNC; 4077 else 4078 flags |= DRM_MODE_FLAG_NVSYNC; 4079 4080 pipe_config->hw.adjusted_mode.flags |= flags; 4081 4082 switch (ddi_func_ctl & TRANS_DDI_BPC_MASK) { 4083 case TRANS_DDI_BPC_6: 4084 pipe_config->pipe_bpp = 18; 4085 break; 4086 case TRANS_DDI_BPC_8: 4087 pipe_config->pipe_bpp = 24; 4088 break; 4089 case TRANS_DDI_BPC_10: 4090 pipe_config->pipe_bpp = 30; 4091 break; 4092 case TRANS_DDI_BPC_12: 4093 pipe_config->pipe_bpp = 36; 4094 break; 4095 default: 4096 break; 4097 } 4098 4099 ddi_mode = ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK; 4100 4101 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI) { 4102 intel_ddi_read_func_ctl_hdmi(encoder, pipe_config, ddi_func_ctl); 4103 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 4104 intel_ddi_read_func_ctl_dvi(encoder, pipe_config, ddi_func_ctl); 4105 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 4106 intel_ddi_read_func_ctl_fdi(encoder, pipe_config, ddi_func_ctl); 4107 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 4108 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4109 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) { 4110 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4111 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 4112 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4113 4114 /* 4115 * If this is true, we know we're being called from mst stream 4116 * encoder's ->get_config(). 4117 */ 4118 if (intel_dp_mst_active_streams(intel_dp)) 4119 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4120 else 4121 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4122 } 4123 } 4124 4125 /* 4126 * Note: Also called from the ->get_config of the MST stream encoders on their 4127 * primary encoder, via the platform specific hooks here. See also the comment 4128 * for intel_ddi_pre_enable(). 4129 */ 4130 static void intel_ddi_get_config(struct intel_encoder *encoder, 4131 struct intel_crtc_state *pipe_config) 4132 { 4133 struct intel_display *display = to_intel_display(encoder); 4134 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4135 4136 /* XXX: DSI transcoder paranoia */ 4137 if (drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder))) 4138 return; 4139 4140 intel_ddi_read_func_ctl(encoder, pipe_config); 4141 4142 intel_ddi_mso_get_config(encoder, pipe_config); 4143 4144 pipe_config->has_audio = 4145 intel_ddi_is_audio_enabled(display, cpu_transcoder); 4146 4147 if (encoder->type == INTEL_OUTPUT_EDP) 4148 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 4149 4150 ddi_dotclock_get(pipe_config); 4151 4152 if (display->platform.geminilake || display->platform.broxton) 4153 pipe_config->lane_lat_optim_mask = 4154 bxt_dpio_phy_get_lane_lat_optim_mask(encoder); 4155 4156 intel_ddi_compute_min_voltage_level(pipe_config); 4157 4158 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 4159 4160 intel_read_infoframe(encoder, pipe_config, 4161 HDMI_INFOFRAME_TYPE_AVI, 4162 &pipe_config->infoframes.avi); 4163 intel_read_infoframe(encoder, pipe_config, 4164 HDMI_INFOFRAME_TYPE_SPD, 4165 &pipe_config->infoframes.spd); 4166 intel_read_infoframe(encoder, pipe_config, 4167 HDMI_INFOFRAME_TYPE_VENDOR, 4168 &pipe_config->infoframes.hdmi); 4169 intel_read_infoframe(encoder, pipe_config, 4170 HDMI_INFOFRAME_TYPE_DRM, 4171 &pipe_config->infoframes.drm); 4172 4173 if (DISPLAY_VER(display) >= 8) 4174 bdw_get_trans_port_sync_config(pipe_config); 4175 4176 intel_psr_get_config(encoder, pipe_config); 4177 4178 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 4179 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 4180 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); 4181 4182 intel_audio_codec_get_config(encoder, pipe_config); 4183 } 4184 4185 void intel_ddi_get_clock(struct intel_encoder *encoder, 4186 struct intel_crtc_state *crtc_state, 4187 struct intel_shared_dpll *pll) 4188 { 4189 struct intel_display *display = to_intel_display(encoder); 4190 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4191 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4192 bool pll_active; 4193 4194 if (drm_WARN_ON(display->drm, !pll)) 4195 return; 4196 4197 port_dpll->pll = pll; 4198 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4199 drm_WARN_ON(display->drm, !pll_active); 4200 4201 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4202 4203 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll, 4204 &crtc_state->dpll_hw_state); 4205 } 4206 4207 static void mtl_ddi_get_config(struct intel_encoder *encoder, 4208 struct intel_crtc_state *crtc_state) 4209 { 4210 intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); 4211 4212 if (crtc_state->dpll_hw_state.cx0pll.tbt_mode) 4213 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 4214 else 4215 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); 4216 4217 intel_ddi_get_config(encoder, crtc_state); 4218 } 4219 4220 static void dg2_ddi_get_config(struct intel_encoder *encoder, 4221 struct intel_crtc_state *crtc_state) 4222 { 4223 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb); 4224 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb); 4225 4226 intel_ddi_get_config(encoder, crtc_state); 4227 } 4228 4229 static void adls_ddi_get_config(struct intel_encoder *encoder, 4230 struct intel_crtc_state *crtc_state) 4231 { 4232 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 4233 intel_ddi_get_config(encoder, crtc_state); 4234 } 4235 4236 static void rkl_ddi_get_config(struct intel_encoder *encoder, 4237 struct intel_crtc_state *crtc_state) 4238 { 4239 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 4240 intel_ddi_get_config(encoder, crtc_state); 4241 } 4242 4243 static void dg1_ddi_get_config(struct intel_encoder *encoder, 4244 struct intel_crtc_state *crtc_state) 4245 { 4246 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 4247 intel_ddi_get_config(encoder, crtc_state); 4248 } 4249 4250 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 4251 struct intel_crtc_state *crtc_state) 4252 { 4253 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 4254 intel_ddi_get_config(encoder, crtc_state); 4255 } 4256 4257 static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll) 4258 { 4259 return pll->info->id == DPLL_ID_ICL_TBTPLL; 4260 } 4261 4262 static enum icl_port_dpll_id 4263 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, 4264 const struct intel_crtc_state *crtc_state) 4265 { 4266 struct intel_display *display = to_intel_display(encoder); 4267 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 4268 4269 if (drm_WARN_ON(display->drm, !pll)) 4270 return ICL_PORT_DPLL_DEFAULT; 4271 4272 if (icl_ddi_tc_pll_is_tbt(pll)) 4273 return ICL_PORT_DPLL_DEFAULT; 4274 else 4275 return ICL_PORT_DPLL_MG_PHY; 4276 } 4277 4278 enum icl_port_dpll_id 4279 intel_ddi_port_pll_type(struct intel_encoder *encoder, 4280 const struct intel_crtc_state *crtc_state) 4281 { 4282 if (!encoder->port_pll_type) 4283 return ICL_PORT_DPLL_DEFAULT; 4284 4285 return encoder->port_pll_type(encoder, crtc_state); 4286 } 4287 4288 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 4289 struct intel_crtc_state *crtc_state, 4290 struct intel_shared_dpll *pll) 4291 { 4292 struct intel_display *display = to_intel_display(encoder); 4293 enum icl_port_dpll_id port_dpll_id; 4294 struct icl_port_dpll *port_dpll; 4295 bool pll_active; 4296 4297 if (drm_WARN_ON(display->drm, !pll)) 4298 return; 4299 4300 if (icl_ddi_tc_pll_is_tbt(pll)) 4301 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4302 else 4303 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 4304 4305 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4306 4307 port_dpll->pll = pll; 4308 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4309 drm_WARN_ON(display->drm, !pll_active); 4310 4311 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4312 4313 if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll)) 4314 crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port); 4315 else 4316 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll, 4317 &crtc_state->dpll_hw_state); 4318 } 4319 4320 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 4321 struct intel_crtc_state *crtc_state) 4322 { 4323 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 4324 intel_ddi_get_config(encoder, crtc_state); 4325 } 4326 4327 static void bxt_ddi_get_config(struct intel_encoder *encoder, 4328 struct intel_crtc_state *crtc_state) 4329 { 4330 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 4331 intel_ddi_get_config(encoder, crtc_state); 4332 } 4333 4334 static void skl_ddi_get_config(struct intel_encoder *encoder, 4335 struct intel_crtc_state *crtc_state) 4336 { 4337 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 4338 intel_ddi_get_config(encoder, crtc_state); 4339 } 4340 4341 void hsw_ddi_get_config(struct intel_encoder *encoder, 4342 struct intel_crtc_state *crtc_state) 4343 { 4344 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 4345 intel_ddi_get_config(encoder, crtc_state); 4346 } 4347 4348 static void intel_ddi_sync_state(struct intel_encoder *encoder, 4349 const struct intel_crtc_state *crtc_state) 4350 { 4351 if (intel_encoder_is_tc(encoder)) 4352 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder), 4353 crtc_state); 4354 4355 if ((crtc_state && intel_crtc_has_dp_encoder(crtc_state)) || 4356 (!crtc_state && intel_encoder_is_dp(encoder))) 4357 intel_dp_sync_state(encoder, crtc_state); 4358 } 4359 4360 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 4361 struct intel_crtc_state *crtc_state) 4362 { 4363 struct intel_display *display = to_intel_display(encoder); 4364 bool fastset = true; 4365 4366 if (intel_encoder_is_tc(encoder)) { 4367 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 4368 encoder->base.base.id, encoder->base.name); 4369 crtc_state->uapi.mode_changed = true; 4370 fastset = false; 4371 } 4372 4373 if (intel_crtc_has_dp_encoder(crtc_state) && 4374 !intel_dp_initial_fastset_check(encoder, crtc_state)) 4375 fastset = false; 4376 4377 return fastset; 4378 } 4379 4380 static enum intel_output_type 4381 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4382 struct intel_crtc_state *crtc_state, 4383 struct drm_connector_state *conn_state) 4384 { 4385 switch (conn_state->connector->connector_type) { 4386 case DRM_MODE_CONNECTOR_HDMIA: 4387 return INTEL_OUTPUT_HDMI; 4388 case DRM_MODE_CONNECTOR_eDP: 4389 return INTEL_OUTPUT_EDP; 4390 case DRM_MODE_CONNECTOR_DisplayPort: 4391 return INTEL_OUTPUT_DP; 4392 default: 4393 MISSING_CASE(conn_state->connector->connector_type); 4394 return INTEL_OUTPUT_UNUSED; 4395 } 4396 } 4397 4398 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4399 struct intel_crtc_state *pipe_config, 4400 struct drm_connector_state *conn_state) 4401 { 4402 struct intel_display *display = to_intel_display(encoder); 4403 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4404 enum port port = encoder->port; 4405 int ret; 4406 4407 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) 4408 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4409 4410 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4411 pipe_config->has_hdmi_sink = 4412 intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state); 4413 4414 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4415 } else { 4416 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4417 } 4418 4419 if (ret) 4420 return ret; 4421 4422 if (display->platform.haswell && crtc->pipe == PIPE_A && 4423 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4424 pipe_config->pch_pfit.force_thru = 4425 pipe_config->pch_pfit.enabled || 4426 pipe_config->crc_enabled; 4427 4428 if (display->platform.geminilake || display->platform.broxton) 4429 pipe_config->lane_lat_optim_mask = 4430 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4431 4432 intel_ddi_compute_min_voltage_level(pipe_config); 4433 4434 return 0; 4435 } 4436 4437 static bool mode_equal(const struct drm_display_mode *mode1, 4438 const struct drm_display_mode *mode2) 4439 { 4440 return drm_mode_match(mode1, mode2, 4441 DRM_MODE_MATCH_TIMINGS | 4442 DRM_MODE_MATCH_FLAGS | 4443 DRM_MODE_MATCH_3D_FLAGS) && 4444 mode1->clock == mode2->clock; /* we want an exact match */ 4445 } 4446 4447 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4448 const struct intel_link_m_n *m_n_2) 4449 { 4450 return m_n_1->tu == m_n_2->tu && 4451 m_n_1->data_m == m_n_2->data_m && 4452 m_n_1->data_n == m_n_2->data_n && 4453 m_n_1->link_m == m_n_2->link_m && 4454 m_n_1->link_n == m_n_2->link_n; 4455 } 4456 4457 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4458 const struct intel_crtc_state *crtc_state2) 4459 { 4460 /* 4461 * FIXME the modeset sequence is currently wrong and 4462 * can't deal with joiner + port sync at the same time. 4463 */ 4464 return crtc_state1->hw.active && crtc_state2->hw.active && 4465 !crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes && 4466 crtc_state1->output_types == crtc_state2->output_types && 4467 crtc_state1->output_format == crtc_state2->output_format && 4468 crtc_state1->lane_count == crtc_state2->lane_count && 4469 crtc_state1->port_clock == crtc_state2->port_clock && 4470 mode_equal(&crtc_state1->hw.adjusted_mode, 4471 &crtc_state2->hw.adjusted_mode) && 4472 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4473 } 4474 4475 static u8 4476 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4477 int tile_group_id) 4478 { 4479 struct intel_display *display = to_intel_display(ref_crtc_state); 4480 struct drm_connector *connector; 4481 const struct drm_connector_state *conn_state; 4482 struct intel_atomic_state *state = 4483 to_intel_atomic_state(ref_crtc_state->uapi.state); 4484 u8 transcoders = 0; 4485 int i; 4486 4487 /* 4488 * We don't enable port sync on BDW due to missing w/as and 4489 * due to not having adjusted the modeset sequence appropriately. 4490 */ 4491 if (DISPLAY_VER(display) < 9) 4492 return 0; 4493 4494 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4495 return 0; 4496 4497 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4498 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4499 const struct intel_crtc_state *crtc_state; 4500 4501 if (!crtc) 4502 continue; 4503 4504 if (!connector->has_tile || 4505 connector->tile_group->id != 4506 tile_group_id) 4507 continue; 4508 crtc_state = intel_atomic_get_new_crtc_state(state, 4509 crtc); 4510 if (!crtcs_port_sync_compatible(ref_crtc_state, 4511 crtc_state)) 4512 continue; 4513 transcoders |= BIT(crtc_state->cpu_transcoder); 4514 } 4515 4516 return transcoders; 4517 } 4518 4519 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4520 struct intel_crtc_state *crtc_state, 4521 struct drm_connector_state *conn_state) 4522 { 4523 struct intel_display *display = to_intel_display(encoder); 4524 struct drm_connector *connector = conn_state->connector; 4525 u8 port_sync_transcoders = 0; 4526 4527 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", 4528 encoder->base.base.id, encoder->base.name, 4529 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4530 4531 if (connector->has_tile) 4532 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4533 connector->tile_group->id); 4534 4535 /* 4536 * EDP Transcoders cannot be ensalved 4537 * make them a master always when present 4538 */ 4539 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4540 crtc_state->master_transcoder = TRANSCODER_EDP; 4541 else 4542 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4543 4544 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4545 crtc_state->master_transcoder = INVALID_TRANSCODER; 4546 crtc_state->sync_mode_slaves_mask = 4547 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4548 } 4549 4550 return 0; 4551 } 4552 4553 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4554 { 4555 struct intel_display *display = to_intel_display(encoder->dev); 4556 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4557 4558 intel_dp_encoder_flush_work(encoder); 4559 if (intel_encoder_is_tc(&dig_port->base)) 4560 intel_tc_port_cleanup(dig_port); 4561 intel_display_power_flush_work(display); 4562 4563 drm_encoder_cleanup(encoder); 4564 kfree(dig_port->hdcp.port_data.streams); 4565 kfree(dig_port); 4566 } 4567 4568 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4569 { 4570 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4571 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4572 4573 intel_dp->reset_link_params = true; 4574 intel_dp_invalidate_source_oui(intel_dp); 4575 4576 intel_pps_encoder_reset(intel_dp); 4577 4578 if (intel_encoder_is_tc(&dig_port->base)) 4579 intel_tc_port_init_mode(dig_port); 4580 } 4581 4582 static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder) 4583 { 4584 struct intel_encoder *encoder = to_intel_encoder(_encoder); 4585 4586 intel_tc_port_link_reset(enc_to_dig_port(encoder)); 4587 4588 return 0; 4589 } 4590 4591 static const struct drm_encoder_funcs intel_ddi_funcs = { 4592 .reset = intel_ddi_encoder_reset, 4593 .destroy = intel_ddi_encoder_destroy, 4594 .late_register = intel_ddi_encoder_late_register, 4595 }; 4596 4597 static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4598 { 4599 struct intel_display *display = to_intel_display(dig_port); 4600 struct intel_connector *connector; 4601 enum port port = dig_port->base.port; 4602 4603 connector = intel_connector_alloc(); 4604 if (!connector) 4605 return -ENOMEM; 4606 4607 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4608 if (DISPLAY_VER(display) >= 14) 4609 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; 4610 else 4611 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4612 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4613 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4614 4615 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4616 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4617 4618 if (!intel_dp_init_connector(dig_port, connector)) { 4619 kfree(connector); 4620 return -EINVAL; 4621 } 4622 4623 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 4624 struct drm_privacy_screen *privacy_screen; 4625 4626 privacy_screen = drm_privacy_screen_get(display->drm->dev, NULL); 4627 if (!IS_ERR(privacy_screen)) { 4628 drm_connector_attach_privacy_screen_provider(&connector->base, 4629 privacy_screen); 4630 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 4631 drm_warn(display->drm, "Error getting privacy-screen\n"); 4632 } 4633 } 4634 4635 return 0; 4636 } 4637 4638 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4639 struct drm_modeset_acquire_ctx *ctx) 4640 { 4641 struct intel_display *display = to_intel_display(encoder); 4642 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4643 struct intel_connector *connector = hdmi->attached_connector; 4644 struct i2c_adapter *ddc = connector->base.ddc; 4645 struct drm_connector_state *conn_state; 4646 struct intel_crtc_state *crtc_state; 4647 struct intel_crtc *crtc; 4648 u8 config; 4649 int ret; 4650 4651 if (connector->base.status != connector_status_connected) 4652 return 0; 4653 4654 ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex, 4655 ctx); 4656 if (ret) 4657 return ret; 4658 4659 conn_state = connector->base.state; 4660 4661 crtc = to_intel_crtc(conn_state->crtc); 4662 if (!crtc) 4663 return 0; 4664 4665 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4666 if (ret) 4667 return ret; 4668 4669 crtc_state = to_intel_crtc_state(crtc->base.state); 4670 4671 drm_WARN_ON(display->drm, 4672 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4673 4674 if (!crtc_state->hw.active) 4675 return 0; 4676 4677 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4678 !crtc_state->hdmi_scrambling) 4679 return 0; 4680 4681 if (conn_state->commit && 4682 !try_wait_for_completion(&conn_state->commit->hw_done)) 4683 return 0; 4684 4685 ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config); 4686 if (ret < 0) { 4687 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", 4688 connector->base.base.id, connector->base.name, ret); 4689 return 0; 4690 } 4691 4692 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4693 crtc_state->hdmi_high_tmds_clock_ratio && 4694 !!(config & SCDC_SCRAMBLING_ENABLE) == 4695 crtc_state->hdmi_scrambling) 4696 return 0; 4697 4698 /* 4699 * HDMI 2.0 says that one should not send scrambled data 4700 * prior to configuring the sink scrambling, and that 4701 * TMDS clock/data transmission should be suspended when 4702 * changing the TMDS clock rate in the sink. So let's 4703 * just do a full modeset here, even though some sinks 4704 * would be perfectly happy if were to just reconfigure 4705 * the SCDC settings on the fly. 4706 */ 4707 return intel_modeset_commit_pipes(display, BIT(crtc->pipe), ctx); 4708 } 4709 4710 static void intel_ddi_link_check(struct intel_encoder *encoder) 4711 { 4712 struct intel_display *display = to_intel_display(encoder); 4713 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4714 4715 /* TODO: Move checking the HDMI link state here as well. */ 4716 drm_WARN_ON(display->drm, !dig_port->dp.attached_connector); 4717 4718 intel_dp_link_check(encoder); 4719 } 4720 4721 static enum intel_hotplug_state 4722 intel_ddi_hotplug(struct intel_encoder *encoder, 4723 struct intel_connector *connector) 4724 { 4725 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4726 struct intel_dp *intel_dp = &dig_port->dp; 4727 bool is_tc = intel_encoder_is_tc(encoder); 4728 struct drm_modeset_acquire_ctx ctx; 4729 enum intel_hotplug_state state; 4730 int ret; 4731 4732 if (intel_dp_test_phy(intel_dp)) 4733 return INTEL_HOTPLUG_UNCHANGED; 4734 4735 state = intel_encoder_hotplug(encoder, connector); 4736 4737 if (!intel_tc_port_link_reset(dig_port)) { 4738 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 4739 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) 4740 ret = intel_hdmi_reset_link(encoder, &ctx); 4741 drm_WARN_ON(encoder->base.dev, ret); 4742 } else { 4743 intel_dp_check_link_state(intel_dp); 4744 } 4745 } 4746 4747 /* 4748 * Unpowered type-c dongles can take some time to boot and be 4749 * responsible, so here giving some time to those dongles to power up 4750 * and then retrying the probe. 4751 * 4752 * On many platforms the HDMI live state signal is known to be 4753 * unreliable, so we can't use it to detect if a sink is connected or 4754 * not. Instead we detect if it's connected based on whether we can 4755 * read the EDID or not. That in turn has a problem during disconnect, 4756 * since the HPD interrupt may be raised before the DDC lines get 4757 * disconnected (due to how the required length of DDC vs. HPD 4758 * connector pins are specified) and so we'll still be able to get a 4759 * valid EDID. To solve this schedule another detection cycle if this 4760 * time around we didn't detect any change in the sink's connection 4761 * status. 4762 * 4763 * Type-c connectors which get their HPD signal deasserted then 4764 * reasserted, without unplugging/replugging the sink from the 4765 * connector, introduce a delay until the AUX channel communication 4766 * becomes functional. Retry the detection for 5 seconds on type-c 4767 * connectors to account for this delay. 4768 */ 4769 if (state == INTEL_HOTPLUG_UNCHANGED && 4770 connector->hotplug_retries < (is_tc ? 5 : 1) && 4771 !dig_port->dp.is_mst) 4772 state = INTEL_HOTPLUG_RETRY; 4773 4774 return state; 4775 } 4776 4777 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4778 { 4779 struct intel_display *display = to_intel_display(encoder); 4780 u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin]; 4781 4782 return intel_de_read(display, SDEISR) & bit; 4783 } 4784 4785 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4786 { 4787 struct intel_display *display = to_intel_display(encoder); 4788 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; 4789 4790 return intel_de_read(display, DEISR) & bit; 4791 } 4792 4793 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4794 { 4795 struct intel_display *display = to_intel_display(encoder); 4796 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; 4797 4798 return intel_de_read(display, GEN8_DE_PORT_ISR) & bit; 4799 } 4800 4801 static int intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4802 { 4803 struct intel_connector *connector; 4804 enum port port = dig_port->base.port; 4805 4806 connector = intel_connector_alloc(); 4807 if (!connector) 4808 return -ENOMEM; 4809 4810 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4811 4812 if (!intel_hdmi_init_connector(dig_port, connector)) { 4813 /* 4814 * HDMI connector init failures may just mean conflicting DDC 4815 * pins or not having enough lanes. Handle them gracefully, but 4816 * don't fail the entire DDI init. 4817 */ 4818 dig_port->hdmi.hdmi_reg = INVALID_MMIO_REG; 4819 kfree(connector); 4820 } 4821 4822 return 0; 4823 } 4824 4825 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4826 { 4827 struct intel_display *display = to_intel_display(dig_port); 4828 4829 if (dig_port->base.port != PORT_A) 4830 return false; 4831 4832 if (dig_port->ddi_a_4_lanes) 4833 return false; 4834 4835 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4836 * supported configuration 4837 */ 4838 if (display->platform.geminilake || display->platform.broxton) 4839 return true; 4840 4841 return false; 4842 } 4843 4844 static int 4845 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4846 { 4847 struct intel_display *display = to_intel_display(dig_port); 4848 enum port port = dig_port->base.port; 4849 int max_lanes = 4; 4850 4851 if (DISPLAY_VER(display) >= 11) 4852 return max_lanes; 4853 4854 if (port == PORT_A || port == PORT_E) { 4855 if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4856 max_lanes = port == PORT_A ? 4 : 0; 4857 else 4858 /* Both A and E share 2 lanes */ 4859 max_lanes = 2; 4860 } 4861 4862 /* 4863 * Some BIOS might fail to set this bit on port A if eDP 4864 * wasn't lit up at boot. Force this bit set when needed 4865 * so we use the proper lane count for our calculations. 4866 */ 4867 if (intel_ddi_a_force_4_lanes(dig_port)) { 4868 drm_dbg_kms(display->drm, 4869 "Forcing DDI_A_4_LANES for port A\n"); 4870 dig_port->ddi_a_4_lanes = true; 4871 max_lanes = 4; 4872 } 4873 4874 return max_lanes; 4875 } 4876 4877 static enum hpd_pin xelpd_hpd_pin(struct intel_display *display, enum port port) 4878 { 4879 if (port >= PORT_D_XELPD) 4880 return HPD_PORT_D + port - PORT_D_XELPD; 4881 else if (port >= PORT_TC1) 4882 return HPD_PORT_TC1 + port - PORT_TC1; 4883 else 4884 return HPD_PORT_A + port - PORT_A; 4885 } 4886 4887 static enum hpd_pin dg1_hpd_pin(struct intel_display *display, enum port port) 4888 { 4889 if (port >= PORT_TC1) 4890 return HPD_PORT_C + port - PORT_TC1; 4891 else 4892 return HPD_PORT_A + port - PORT_A; 4893 } 4894 4895 static enum hpd_pin tgl_hpd_pin(struct intel_display *display, enum port port) 4896 { 4897 if (port >= PORT_TC1) 4898 return HPD_PORT_TC1 + port - PORT_TC1; 4899 else 4900 return HPD_PORT_A + port - PORT_A; 4901 } 4902 4903 static enum hpd_pin rkl_hpd_pin(struct intel_display *display, enum port port) 4904 { 4905 if (HAS_PCH_TGP(display)) 4906 return tgl_hpd_pin(display, port); 4907 4908 if (port >= PORT_TC1) 4909 return HPD_PORT_C + port - PORT_TC1; 4910 else 4911 return HPD_PORT_A + port - PORT_A; 4912 } 4913 4914 static enum hpd_pin icl_hpd_pin(struct intel_display *display, enum port port) 4915 { 4916 if (port >= PORT_C) 4917 return HPD_PORT_TC1 + port - PORT_C; 4918 else 4919 return HPD_PORT_A + port - PORT_A; 4920 } 4921 4922 static enum hpd_pin ehl_hpd_pin(struct intel_display *display, enum port port) 4923 { 4924 if (port == PORT_D) 4925 return HPD_PORT_A; 4926 4927 if (HAS_PCH_TGP(display)) 4928 return icl_hpd_pin(display, port); 4929 4930 return HPD_PORT_A + port - PORT_A; 4931 } 4932 4933 static enum hpd_pin skl_hpd_pin(struct intel_display *display, enum port port) 4934 { 4935 if (HAS_PCH_TGP(display)) 4936 return icl_hpd_pin(display, port); 4937 4938 return HPD_PORT_A + port - PORT_A; 4939 } 4940 4941 static bool intel_ddi_is_tc(struct intel_display *display, enum port port) 4942 { 4943 if (DISPLAY_VER(display) >= 12) 4944 return port >= PORT_TC1; 4945 else if (DISPLAY_VER(display) >= 11) 4946 return port >= PORT_C; 4947 else 4948 return false; 4949 } 4950 4951 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 4952 { 4953 intel_dp_encoder_suspend(encoder); 4954 } 4955 4956 static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder) 4957 { 4958 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4959 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4960 4961 /* 4962 * TODO: Move this to intel_dp_encoder_suspend(), 4963 * once modeset locking around that is removed. 4964 */ 4965 intel_encoder_link_check_flush_work(encoder); 4966 intel_tc_port_suspend(dig_port); 4967 } 4968 4969 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 4970 { 4971 if (intel_encoder_is_dp(encoder)) 4972 intel_dp_encoder_shutdown(encoder); 4973 if (intel_encoder_is_hdmi(encoder)) 4974 intel_hdmi_encoder_shutdown(encoder); 4975 } 4976 4977 static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder) 4978 { 4979 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4980 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4981 4982 intel_tc_port_cleanup(dig_port); 4983 } 4984 4985 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 4986 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 4987 4988 static bool port_strap_detected(struct intel_display *display, enum port port) 4989 { 4990 /* straps not used on skl+ */ 4991 if (DISPLAY_VER(display) >= 9) 4992 return true; 4993 4994 switch (port) { 4995 case PORT_A: 4996 return intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 4997 case PORT_B: 4998 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; 4999 case PORT_C: 5000 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; 5001 case PORT_D: 5002 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; 5003 case PORT_E: 5004 return true; /* no strap for DDI-E */ 5005 default: 5006 MISSING_CASE(port); 5007 return false; 5008 } 5009 } 5010 5011 static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp) 5012 { 5013 return init_dp || intel_encoder_is_tc(encoder); 5014 } 5015 5016 static bool assert_has_icl_dsi(struct intel_display *display) 5017 { 5018 return !drm_WARN(display->drm, !display->platform.alderlake_p && 5019 !display->platform.tigerlake && DISPLAY_VER(display) != 11, 5020 "Platform does not support DSI\n"); 5021 } 5022 5023 static bool port_in_use(struct intel_display *display, enum port port) 5024 { 5025 struct intel_encoder *encoder; 5026 5027 for_each_intel_encoder(display->drm, encoder) { 5028 /* FIXME what about second port for dual link DSI? */ 5029 if (encoder->port == port) 5030 return true; 5031 } 5032 5033 return false; 5034 } 5035 5036 void intel_ddi_init(struct intel_display *display, 5037 const struct intel_bios_encoder_data *devdata) 5038 { 5039 struct intel_digital_port *dig_port; 5040 struct intel_encoder *encoder; 5041 bool init_hdmi, init_dp; 5042 enum port port; 5043 enum phy phy; 5044 u32 ddi_buf_ctl; 5045 5046 port = intel_bios_encoder_port(devdata); 5047 if (port == PORT_NONE) 5048 return; 5049 5050 if (!port_strap_detected(display, port)) { 5051 drm_dbg_kms(display->drm, 5052 "Port %c strap not detected\n", port_name(port)); 5053 return; 5054 } 5055 5056 if (!assert_port_valid(display, port)) 5057 return; 5058 5059 if (port_in_use(display, port)) { 5060 drm_dbg_kms(display->drm, 5061 "Port %c already claimed\n", port_name(port)); 5062 return; 5063 } 5064 5065 if (intel_bios_encoder_supports_dsi(devdata)) { 5066 /* BXT/GLK handled elsewhere, for now at least */ 5067 if (!assert_has_icl_dsi(display)) 5068 return; 5069 5070 icl_dsi_init(display, devdata); 5071 return; 5072 } 5073 5074 phy = intel_port_to_phy(display, port); 5075 5076 /* 5077 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 5078 * have taken over some of the PHYs and made them unavailable to the 5079 * driver. In that case we should skip initializing the corresponding 5080 * outputs. 5081 */ 5082 if (intel_hti_uses_phy(display, phy)) { 5083 drm_dbg_kms(display->drm, "PORT %c / PHY %c reserved by HTI\n", 5084 port_name(port), phy_name(phy)); 5085 return; 5086 } 5087 5088 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 5089 intel_bios_encoder_supports_hdmi(devdata); 5090 init_dp = intel_bios_encoder_supports_dp(devdata); 5091 5092 if (intel_bios_encoder_is_lspcon(devdata)) { 5093 /* 5094 * Lspcon device needs to be driven with DP connector 5095 * with special detection sequence. So make sure DP 5096 * is initialized before lspcon. 5097 */ 5098 init_dp = true; 5099 init_hdmi = false; 5100 drm_dbg_kms(display->drm, "VBT says port %c has lspcon\n", 5101 port_name(port)); 5102 } 5103 5104 if (!init_dp && !init_hdmi) { 5105 drm_dbg_kms(display->drm, 5106 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 5107 port_name(port)); 5108 return; 5109 } 5110 5111 if (intel_phy_is_snps(display, phy) && 5112 display->snps.phy_failed_calibration & BIT(phy)) { 5113 drm_dbg_kms(display->drm, 5114 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 5115 phy_name(phy)); 5116 } 5117 5118 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 5119 if (!dig_port) 5120 return; 5121 5122 dig_port->aux_ch = AUX_CH_NONE; 5123 5124 encoder = &dig_port->base; 5125 encoder->devdata = devdata; 5126 5127 if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD) { 5128 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, 5129 DRM_MODE_ENCODER_TMDS, 5130 "DDI %c/PHY %c", 5131 port_name(port - PORT_D_XELPD + PORT_D), 5132 phy_name(phy)); 5133 } else if (DISPLAY_VER(display) >= 12) { 5134 enum tc_port tc_port = intel_port_to_tc(display, port); 5135 5136 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, 5137 DRM_MODE_ENCODER_TMDS, 5138 "DDI %s%c/PHY %s%c", 5139 port >= PORT_TC1 ? "TC" : "", 5140 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 5141 tc_port != TC_PORT_NONE ? "TC" : "", 5142 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5143 } else if (DISPLAY_VER(display) >= 11) { 5144 enum tc_port tc_port = intel_port_to_tc(display, port); 5145 5146 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, 5147 DRM_MODE_ENCODER_TMDS, 5148 "DDI %c%s/PHY %s%c", 5149 port_name(port), 5150 port >= PORT_C ? " (TC)" : "", 5151 tc_port != TC_PORT_NONE ? "TC" : "", 5152 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5153 } else { 5154 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, 5155 DRM_MODE_ENCODER_TMDS, 5156 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 5157 } 5158 5159 intel_encoder_link_check_init(encoder, intel_ddi_link_check); 5160 5161 mutex_init(&dig_port->hdcp.mutex); 5162 dig_port->hdcp.num_streams = 0; 5163 5164 encoder->hotplug = intel_ddi_hotplug; 5165 encoder->compute_output_type = intel_ddi_compute_output_type; 5166 encoder->compute_config = intel_ddi_compute_config; 5167 encoder->compute_config_late = intel_ddi_compute_config_late; 5168 encoder->enable = intel_ddi_enable; 5169 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 5170 encoder->pre_enable = intel_ddi_pre_enable; 5171 encoder->disable = intel_ddi_disable; 5172 encoder->post_pll_disable = intel_ddi_post_pll_disable; 5173 encoder->post_disable = intel_ddi_post_disable; 5174 encoder->update_pipe = intel_ddi_update_pipe; 5175 encoder->audio_enable = intel_audio_codec_enable; 5176 encoder->audio_disable = intel_audio_codec_disable; 5177 encoder->get_hw_state = intel_ddi_get_hw_state; 5178 encoder->sync_state = intel_ddi_sync_state; 5179 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 5180 encoder->suspend = intel_ddi_encoder_suspend; 5181 encoder->shutdown = intel_ddi_encoder_shutdown; 5182 encoder->get_power_domains = intel_ddi_get_power_domains; 5183 5184 encoder->type = INTEL_OUTPUT_DDI; 5185 encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port); 5186 encoder->port = port; 5187 encoder->cloneable = 0; 5188 encoder->pipe_mask = ~0; 5189 5190 if (DISPLAY_VER(display) >= 14) { 5191 encoder->enable_clock = intel_mtl_pll_enable; 5192 encoder->disable_clock = intel_mtl_pll_disable; 5193 encoder->port_pll_type = intel_mtl_port_pll_type; 5194 encoder->get_config = mtl_ddi_get_config; 5195 } else if (display->platform.dg2) { 5196 encoder->enable_clock = intel_mpllb_enable; 5197 encoder->disable_clock = intel_mpllb_disable; 5198 encoder->get_config = dg2_ddi_get_config; 5199 } else if (display->platform.alderlake_s) { 5200 encoder->enable_clock = adls_ddi_enable_clock; 5201 encoder->disable_clock = adls_ddi_disable_clock; 5202 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 5203 encoder->get_config = adls_ddi_get_config; 5204 } else if (display->platform.rocketlake) { 5205 encoder->enable_clock = rkl_ddi_enable_clock; 5206 encoder->disable_clock = rkl_ddi_disable_clock; 5207 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 5208 encoder->get_config = rkl_ddi_get_config; 5209 } else if (display->platform.dg1) { 5210 encoder->enable_clock = dg1_ddi_enable_clock; 5211 encoder->disable_clock = dg1_ddi_disable_clock; 5212 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 5213 encoder->get_config = dg1_ddi_get_config; 5214 } else if (display->platform.jasperlake || display->platform.elkhartlake) { 5215 if (intel_ddi_is_tc(display, port)) { 5216 encoder->enable_clock = jsl_ddi_tc_enable_clock; 5217 encoder->disable_clock = jsl_ddi_tc_disable_clock; 5218 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 5219 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5220 encoder->get_config = icl_ddi_combo_get_config; 5221 } else { 5222 encoder->enable_clock = icl_ddi_combo_enable_clock; 5223 encoder->disable_clock = icl_ddi_combo_disable_clock; 5224 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5225 encoder->get_config = icl_ddi_combo_get_config; 5226 } 5227 } else if (DISPLAY_VER(display) >= 11) { 5228 if (intel_ddi_is_tc(display, port)) { 5229 encoder->enable_clock = icl_ddi_tc_enable_clock; 5230 encoder->disable_clock = icl_ddi_tc_disable_clock; 5231 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 5232 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5233 encoder->get_config = icl_ddi_tc_get_config; 5234 } else { 5235 encoder->enable_clock = icl_ddi_combo_enable_clock; 5236 encoder->disable_clock = icl_ddi_combo_disable_clock; 5237 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5238 encoder->get_config = icl_ddi_combo_get_config; 5239 } 5240 } else if (display->platform.geminilake || display->platform.broxton) { 5241 /* BXT/GLK have fixed PLL->port mapping */ 5242 encoder->get_config = bxt_ddi_get_config; 5243 } else if (DISPLAY_VER(display) == 9) { 5244 encoder->enable_clock = skl_ddi_enable_clock; 5245 encoder->disable_clock = skl_ddi_disable_clock; 5246 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 5247 encoder->get_config = skl_ddi_get_config; 5248 } else if (display->platform.broadwell || display->platform.haswell) { 5249 encoder->enable_clock = hsw_ddi_enable_clock; 5250 encoder->disable_clock = hsw_ddi_disable_clock; 5251 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 5252 encoder->get_config = hsw_ddi_get_config; 5253 } 5254 5255 if (DISPLAY_VER(display) >= 14) { 5256 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; 5257 } else if (display->platform.dg2) { 5258 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 5259 } else if (DISPLAY_VER(display) >= 12) { 5260 if (intel_encoder_is_combo(encoder)) 5261 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5262 else 5263 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 5264 } else if (DISPLAY_VER(display) >= 11) { 5265 if (intel_encoder_is_combo(encoder)) 5266 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5267 else 5268 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 5269 } else if (display->platform.geminilake || display->platform.broxton) { 5270 encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels; 5271 } else { 5272 encoder->set_signal_levels = hsw_set_signal_levels; 5273 } 5274 5275 intel_ddi_buf_trans_init(encoder); 5276 5277 if (DISPLAY_VER(display) >= 13) 5278 encoder->hpd_pin = xelpd_hpd_pin(display, port); 5279 else if (display->platform.dg1) 5280 encoder->hpd_pin = dg1_hpd_pin(display, port); 5281 else if (display->platform.rocketlake) 5282 encoder->hpd_pin = rkl_hpd_pin(display, port); 5283 else if (DISPLAY_VER(display) >= 12) 5284 encoder->hpd_pin = tgl_hpd_pin(display, port); 5285 else if (display->platform.jasperlake || display->platform.elkhartlake) 5286 encoder->hpd_pin = ehl_hpd_pin(display, port); 5287 else if (DISPLAY_VER(display) == 11) 5288 encoder->hpd_pin = icl_hpd_pin(display, port); 5289 else if (DISPLAY_VER(display) == 9 && !display->platform.broxton) 5290 encoder->hpd_pin = skl_hpd_pin(display, port); 5291 else 5292 encoder->hpd_pin = intel_hpd_pin_default(port); 5293 5294 ddi_buf_ctl = intel_de_read(display, DDI_BUF_CTL(port)); 5295 5296 dig_port->lane_reversal = intel_bios_encoder_lane_reversal(devdata) || 5297 ddi_buf_ctl & DDI_BUF_PORT_REVERSAL; 5298 5299 dig_port->ddi_a_4_lanes = DISPLAY_VER(display) < 11 && ddi_buf_ctl & DDI_A_4_LANES; 5300 5301 dig_port->dp.output_reg = INVALID_MMIO_REG; 5302 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 5303 5304 if (need_aux_ch(encoder, init_dp)) { 5305 dig_port->aux_ch = intel_dp_aux_ch(encoder); 5306 if (dig_port->aux_ch == AUX_CH_NONE) 5307 goto err; 5308 } 5309 5310 if (intel_encoder_is_tc(encoder)) { 5311 bool is_legacy = 5312 !intel_bios_encoder_supports_typec_usb(devdata) && 5313 !intel_bios_encoder_supports_tbt(devdata); 5314 5315 if (!is_legacy && init_hdmi) { 5316 is_legacy = !init_dp; 5317 5318 drm_dbg_kms(display->drm, 5319 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", 5320 port_name(port), 5321 str_yes_no(init_dp), 5322 is_legacy ? "legacy" : "non-legacy"); 5323 } 5324 5325 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; 5326 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; 5327 5328 dig_port->lock = intel_tc_port_lock; 5329 dig_port->unlock = intel_tc_port_unlock; 5330 5331 if (intel_tc_port_init(dig_port, is_legacy) < 0) 5332 goto err; 5333 } 5334 5335 drm_WARN_ON(display->drm, port > PORT_I); 5336 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(display, port); 5337 5338 if (DISPLAY_VER(display) >= 11) { 5339 if (intel_encoder_is_tc(encoder)) 5340 dig_port->connected = intel_tc_port_connected; 5341 else 5342 dig_port->connected = lpt_digital_port_connected; 5343 } else if (display->platform.geminilake || display->platform.broxton) { 5344 dig_port->connected = bdw_digital_port_connected; 5345 } else if (DISPLAY_VER(display) == 9) { 5346 dig_port->connected = lpt_digital_port_connected; 5347 } else if (display->platform.broadwell) { 5348 if (port == PORT_A) 5349 dig_port->connected = bdw_digital_port_connected; 5350 else 5351 dig_port->connected = lpt_digital_port_connected; 5352 } else if (display->platform.haswell) { 5353 if (port == PORT_A) 5354 dig_port->connected = hsw_digital_port_connected; 5355 else 5356 dig_port->connected = lpt_digital_port_connected; 5357 } 5358 5359 intel_infoframe_init(dig_port); 5360 5361 if (init_dp) { 5362 if (intel_ddi_init_dp_connector(dig_port)) 5363 goto err; 5364 5365 dig_port->hpd_pulse = intel_dp_hpd_pulse; 5366 5367 if (dig_port->dp.mso_link_count) 5368 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(display); 5369 } 5370 5371 /* 5372 * In theory we don't need the encoder->type check, 5373 * but leave it just in case we have some really bad VBTs... 5374 */ 5375 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 5376 if (intel_ddi_init_hdmi_connector(dig_port)) 5377 goto err; 5378 } 5379 5380 return; 5381 5382 err: 5383 drm_encoder_cleanup(&encoder->base); 5384 kfree(dig_port); 5385 } 5386