1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2024, Intel Corporation. 4 */ 5 6 #include <linux/debugfs.h> 7 8 #include <drm/drm_print.h> 9 10 #include "intel_alpm.h" 11 #include "intel_crtc.h" 12 #include "intel_de.h" 13 #include "intel_display_types.h" 14 #include "intel_dp.h" 15 #include "intel_dp_aux.h" 16 #include "intel_psr.h" 17 #include "intel_psr_regs.h" 18 19 bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp) 20 { 21 return intel_dp->alpm_dpcd & DP_ALPM_CAP; 22 } 23 24 bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp) 25 { 26 return intel_dp->alpm_dpcd & DP_ALPM_AUX_LESS_CAP; 27 } 28 29 void intel_alpm_init(struct intel_dp *intel_dp) 30 { 31 u8 dpcd; 32 33 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &dpcd) < 0) 34 return; 35 36 intel_dp->alpm_dpcd = dpcd; 37 mutex_init(&intel_dp->alpm_parameters.lock); 38 } 39 40 /* 41 * See Bspec: 71632 for the table 42 * 43 * Silence_period = tSilence,Min + ((tSilence,Max - tSilence,Min) / 2) 44 * 45 * Half cycle duration: 46 * 47 * Link rates 1.62 - 4.32 and tLFPS_Cycle = 70 ns 48 * FLOOR( (Link Rate * tLFPS_Cycle) / (2 * 10) ) 49 * 50 * Link rates 5.4 - 8.1 51 * PORT_ALPM_LFPS_CTL[ LFPS Cycle Count ] = 10 52 * LFPS Period chosen is the mid-point of the min:max values from the table 53 * FLOOR( LFPS Period in Symbol clocks / 54 * (2 * PORT_ALPM_LFPS_CTL[ LFPS Cycle Count ]) ) 55 */ 56 static bool _lnl_get_silence_period_and_lfps_half_cycle(int link_rate, 57 int *silence_period, 58 int *lfps_half_cycle) 59 { 60 switch (link_rate) { 61 case 162000: 62 *silence_period = 20; 63 *lfps_half_cycle = 5; 64 break; 65 case 216000: 66 *silence_period = 27; 67 *lfps_half_cycle = 7; 68 break; 69 case 243000: 70 *silence_period = 31; 71 *lfps_half_cycle = 8; 72 break; 73 case 270000: 74 *silence_period = 34; 75 *lfps_half_cycle = 9; 76 break; 77 case 324000: 78 *silence_period = 41; 79 *lfps_half_cycle = 11; 80 break; 81 case 432000: 82 *silence_period = 56; 83 *lfps_half_cycle = 15; 84 break; 85 case 540000: 86 *silence_period = 69; 87 *lfps_half_cycle = 12; 88 break; 89 case 648000: 90 *silence_period = 84; 91 *lfps_half_cycle = 15; 92 break; 93 case 675000: 94 *silence_period = 87; 95 *lfps_half_cycle = 15; 96 break; 97 case 810000: 98 *silence_period = 104; 99 *lfps_half_cycle = 19; 100 break; 101 default: 102 *silence_period = *lfps_half_cycle = -1; 103 return false; 104 } 105 return true; 106 } 107 108 /* 109 * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+ 110 * tSilence, Max+ tPHY Establishment + tCDS) / tline) 111 * For the "PHY P2 to P0" latency see the PHY Power Control page 112 * (PHY P2 to P0) : https://gfxspecs.intel.com/Predator/Home/Index/68965 113 * : 12 us 114 * The tLFPS_Period, Max term is 800ns 115 * The tSilence, Max term is 180ns 116 * The tPHY Establishment (a.k.a. t1) term is 50us 117 * The tCDS term is 1 or 2 times t2 118 * t2 = Number ML_PHY_LOCK * tML_PHY_LOCK 119 * Number ML_PHY_LOCK = ( 7 + CEILING( 6.5us / tML_PHY_LOCK ) + 1) 120 * Rounding up the 6.5us padding to the next ML_PHY_LOCK boundary and 121 * adding the "+ 1" term ensures all ML_PHY_LOCK sequences that start 122 * within the CDS period complete within the CDS period regardless of 123 * entry into the period 124 * tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) ) 125 * TPS4 Length = 252 Symbols 126 */ 127 static int _lnl_compute_aux_less_wake_time(int port_clock) 128 { 129 int tphy2_p2_to_p0 = 12 * 1000; 130 int tlfps_period_max = 800; 131 int tsilence_max = 180; 132 int t1 = 50 * 1000; 133 int tps4 = 252; 134 /* port_clock is link rate in 10kbit/s units */ 135 int tml_phy_lock = 1000 * 1000 * tps4 / port_clock; 136 int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1; 137 int t2 = num_ml_phy_lock * tml_phy_lock; 138 int tcds = 1 * t2; 139 140 return DIV_ROUND_UP(tphy2_p2_to_p0 + tlfps_period_max + tsilence_max + 141 t1 + tcds, 1000); 142 } 143 144 static int 145 _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp, 146 const struct intel_crtc_state *crtc_state) 147 { 148 struct intel_display *display = to_intel_display(intel_dp); 149 int aux_less_wake_time, aux_less_wake_lines, silence_period, 150 lfps_half_cycle; 151 152 aux_less_wake_time = 153 _lnl_compute_aux_less_wake_time(crtc_state->port_clock); 154 aux_less_wake_lines = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, 155 aux_less_wake_time); 156 157 if (!_lnl_get_silence_period_and_lfps_half_cycle(crtc_state->port_clock, 158 &silence_period, 159 &lfps_half_cycle)) 160 return false; 161 162 if (aux_less_wake_lines > ALPM_CTL_AUX_LESS_WAKE_TIME_MASK || 163 silence_period > PORT_ALPM_CTL_SILENCE_PERIOD_MASK || 164 lfps_half_cycle > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK) 165 return false; 166 167 if (display->params.psr_safest_params) 168 aux_less_wake_lines = ALPM_CTL_AUX_LESS_WAKE_TIME_MASK; 169 170 intel_dp->alpm_parameters.aux_less_wake_lines = aux_less_wake_lines; 171 intel_dp->alpm_parameters.silence_period_sym_clocks = silence_period; 172 intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms = lfps_half_cycle; 173 174 return true; 175 } 176 177 static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp, 178 const struct intel_crtc_state *crtc_state) 179 { 180 struct intel_display *display = to_intel_display(intel_dp); 181 int check_entry_lines; 182 183 if (DISPLAY_VER(display) < 20) 184 return true; 185 186 /* ALPM Entry Check = 2 + CEILING( 5us /tline ) */ 187 check_entry_lines = 2 + 188 intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, 5); 189 190 if (check_entry_lines > 15) 191 return false; 192 193 if (!_lnl_compute_aux_less_alpm_params(intel_dp, crtc_state)) 194 return false; 195 196 if (display->params.psr_safest_params) 197 check_entry_lines = 15; 198 199 intel_dp->alpm_parameters.check_entry_lines = check_entry_lines; 200 201 return true; 202 } 203 204 /* 205 * IO wake time for DISPLAY_VER < 12 is not directly mentioned in Bspec. There 206 * are 50 us io wake time and 32 us fast wake time. Clearly preharge pulses are 207 * not (improperly) included in 32 us fast wake time. 50 us - 32 us = 18 us. 208 */ 209 static int skl_io_buffer_wake_time(void) 210 { 211 return 18; 212 } 213 214 static int tgl_io_buffer_wake_time(void) 215 { 216 return 10; 217 } 218 219 static int io_buffer_wake_time(const struct intel_crtc_state *crtc_state) 220 { 221 struct intel_display *display = to_intel_display(crtc_state); 222 223 if (DISPLAY_VER(display) >= 12) 224 return tgl_io_buffer_wake_time(); 225 else 226 return skl_io_buffer_wake_time(); 227 } 228 229 bool intel_alpm_compute_params(struct intel_dp *intel_dp, 230 const struct intel_crtc_state *crtc_state) 231 { 232 struct intel_display *display = to_intel_display(intel_dp); 233 int io_wake_lines, io_wake_time, fast_wake_lines, fast_wake_time; 234 int tfw_exit_latency = 20; /* eDP spec */ 235 int phy_wake = 4; /* eDP spec */ 236 int preamble = 8; /* eDP spec */ 237 int precharge = intel_dp_aux_fw_sync_len(intel_dp) - preamble; 238 u8 max_wake_lines; 239 240 io_wake_time = max(precharge, io_buffer_wake_time(crtc_state)) + 241 preamble + phy_wake + tfw_exit_latency; 242 fast_wake_time = precharge + preamble + phy_wake + 243 tfw_exit_latency; 244 245 if (DISPLAY_VER(display) >= 20) 246 max_wake_lines = 68; 247 else if (DISPLAY_VER(display) >= 12) 248 max_wake_lines = 12; 249 else 250 max_wake_lines = 8; 251 252 io_wake_lines = intel_usecs_to_scanlines( 253 &crtc_state->hw.adjusted_mode, io_wake_time); 254 fast_wake_lines = intel_usecs_to_scanlines( 255 &crtc_state->hw.adjusted_mode, fast_wake_time); 256 257 if (io_wake_lines > max_wake_lines || 258 fast_wake_lines > max_wake_lines) 259 return false; 260 261 if (!_lnl_compute_alpm_params(intel_dp, crtc_state)) 262 return false; 263 264 if (display->params.psr_safest_params) 265 io_wake_lines = fast_wake_lines = max_wake_lines; 266 267 /* According to Bspec lower limit should be set as 7 lines. */ 268 intel_dp->alpm_parameters.io_wake_lines = max(io_wake_lines, 7); 269 intel_dp->alpm_parameters.fast_wake_lines = max(fast_wake_lines, 7); 270 271 return true; 272 } 273 274 void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp, 275 struct intel_crtc_state *crtc_state, 276 struct drm_connector_state *conn_state) 277 { 278 struct intel_display *display = to_intel_display(intel_dp); 279 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 280 int waketime_in_lines, first_sdp_position; 281 int context_latency, guardband; 282 283 if (intel_dp->alpm_parameters.lobf_disable_debug) { 284 drm_dbg_kms(display->drm, "LOBF is disabled by debug flag\n"); 285 return; 286 } 287 288 if (intel_dp->alpm_parameters.sink_alpm_error) 289 return; 290 291 if (!intel_dp_is_edp(intel_dp)) 292 return; 293 294 if (DISPLAY_VER(display) < 20) 295 return; 296 297 if (!intel_dp->as_sdp_supported) 298 return; 299 300 if (crtc_state->has_psr) 301 return; 302 303 if (crtc_state->vrr.vmin != crtc_state->vrr.vmax || 304 crtc_state->vrr.vmin != crtc_state->vrr.flipline) 305 return; 306 307 if (!(intel_alpm_aux_wake_supported(intel_dp) || 308 intel_alpm_aux_less_wake_supported(intel_dp))) 309 return; 310 311 if (!intel_alpm_compute_params(intel_dp, crtc_state)) 312 return; 313 314 context_latency = adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay; 315 guardband = adjusted_mode->crtc_vtotal - 316 adjusted_mode->crtc_vdisplay - context_latency; 317 first_sdp_position = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start; 318 if (intel_alpm_aux_less_wake_supported(intel_dp)) 319 waketime_in_lines = intel_dp->alpm_parameters.io_wake_lines; 320 else 321 waketime_in_lines = intel_dp->alpm_parameters.aux_less_wake_lines; 322 323 crtc_state->has_lobf = (context_latency + guardband) > 324 (first_sdp_position + waketime_in_lines); 325 } 326 327 static void lnl_alpm_configure(struct intel_dp *intel_dp, 328 const struct intel_crtc_state *crtc_state) 329 { 330 struct intel_display *display = to_intel_display(intel_dp); 331 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 332 enum port port = dp_to_dig_port(intel_dp)->base.port; 333 u32 alpm_ctl; 334 335 if (DISPLAY_VER(display) < 20 || (!intel_psr_needs_alpm(intel_dp, crtc_state) && 336 !crtc_state->has_lobf)) 337 return; 338 339 mutex_lock(&intel_dp->alpm_parameters.lock); 340 /* 341 * Panel Replay on eDP is always using ALPM aux less. I.e. no need to 342 * check panel support at this point. 343 */ 344 if ((crtc_state->has_panel_replay && intel_dp_is_edp(intel_dp)) || 345 (crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp))) { 346 alpm_ctl = ALPM_CTL_ALPM_ENABLE | 347 ALPM_CTL_ALPM_AUX_LESS_ENABLE | 348 ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS | 349 ALPM_CTL_AUX_LESS_WAKE_TIME(intel_dp->alpm_parameters.aux_less_wake_lines); 350 351 intel_de_write(display, 352 PORT_ALPM_CTL(port), 353 PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE | 354 PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) | 355 PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) | 356 PORT_ALPM_CTL_SILENCE_PERIOD( 357 intel_dp->alpm_parameters.silence_period_sym_clocks)); 358 359 intel_de_write(display, 360 PORT_ALPM_LFPS_CTL(port), 361 PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) | 362 PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION( 363 intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) | 364 PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION( 365 intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) | 366 PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION( 367 intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms)); 368 } else { 369 alpm_ctl = ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE | 370 ALPM_CTL_EXTENDED_FAST_WAKE_TIME(intel_dp->alpm_parameters.fast_wake_lines); 371 } 372 373 if (crtc_state->has_lobf) { 374 alpm_ctl |= ALPM_CTL_LOBF_ENABLE; 375 drm_dbg_kms(display->drm, "Link off between frames (LOBF) enabled\n"); 376 } 377 378 alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(intel_dp->alpm_parameters.check_entry_lines); 379 380 intel_de_write(display, ALPM_CTL(display, cpu_transcoder), alpm_ctl); 381 mutex_unlock(&intel_dp->alpm_parameters.lock); 382 } 383 384 void intel_alpm_configure(struct intel_dp *intel_dp, 385 const struct intel_crtc_state *crtc_state) 386 { 387 lnl_alpm_configure(intel_dp, crtc_state); 388 intel_dp->alpm_parameters.transcoder = crtc_state->cpu_transcoder; 389 } 390 391 void intel_alpm_pre_plane_update(struct intel_atomic_state *state, 392 struct intel_crtc *crtc) 393 { 394 struct intel_display *display = to_intel_display(state); 395 const struct intel_crtc_state *crtc_state = 396 intel_atomic_get_new_crtc_state(state, crtc); 397 const struct intel_crtc_state *old_crtc_state = 398 intel_atomic_get_old_crtc_state(state, crtc); 399 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 400 struct intel_encoder *encoder; 401 402 if (DISPLAY_VER(display) < 20) 403 return; 404 405 if (crtc_state->has_lobf || crtc_state->has_lobf == old_crtc_state->has_lobf) 406 return; 407 408 for_each_intel_encoder_mask(display->drm, encoder, 409 crtc_state->uapi.encoder_mask) { 410 struct intel_dp *intel_dp; 411 412 if (!intel_encoder_is_dp(encoder)) 413 continue; 414 415 intel_dp = enc_to_intel_dp(encoder); 416 417 if (!intel_dp_is_edp(intel_dp)) 418 continue; 419 420 if (old_crtc_state->has_lobf) { 421 mutex_lock(&intel_dp->alpm_parameters.lock); 422 intel_de_write(display, ALPM_CTL(display, cpu_transcoder), 0); 423 drm_dbg_kms(display->drm, "Link off between frames (LOBF) disabled\n"); 424 mutex_unlock(&intel_dp->alpm_parameters.lock); 425 } 426 } 427 } 428 429 void intel_alpm_enable_sink(struct intel_dp *intel_dp, 430 const struct intel_crtc_state *crtc_state) 431 { 432 u8 val; 433 434 if (!intel_psr_needs_alpm(intel_dp, crtc_state) && !crtc_state->has_lobf) 435 return; 436 437 val = DP_ALPM_ENABLE | DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE; 438 439 if (crtc_state->has_panel_replay || (crtc_state->has_lobf && 440 intel_alpm_aux_less_wake_supported(intel_dp))) 441 val |= DP_ALPM_MODE_AUX_LESS; 442 443 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, val); 444 } 445 446 void intel_alpm_post_plane_update(struct intel_atomic_state *state, 447 struct intel_crtc *crtc) 448 { 449 struct intel_display *display = to_intel_display(state); 450 const struct intel_crtc_state *crtc_state = 451 intel_atomic_get_new_crtc_state(state, crtc); 452 const struct intel_crtc_state *old_crtc_state = 453 intel_atomic_get_old_crtc_state(state, crtc); 454 struct intel_encoder *encoder; 455 456 if (crtc_state->has_psr || !crtc_state->has_lobf || 457 crtc_state->has_lobf == old_crtc_state->has_lobf) 458 return; 459 460 for_each_intel_encoder_mask(display->drm, encoder, 461 crtc_state->uapi.encoder_mask) { 462 struct intel_dp *intel_dp; 463 464 if (!intel_encoder_is_dp(encoder)) 465 continue; 466 467 intel_dp = enc_to_intel_dp(encoder); 468 469 if (intel_dp_is_edp(intel_dp)) { 470 intel_alpm_enable_sink(intel_dp, crtc_state); 471 intel_alpm_configure(intel_dp, crtc_state); 472 } 473 } 474 } 475 476 static int i915_edp_lobf_info_show(struct seq_file *m, void *data) 477 { 478 struct intel_connector *connector = m->private; 479 struct intel_display *display = to_intel_display(connector); 480 struct drm_crtc *crtc; 481 struct intel_crtc_state *crtc_state; 482 enum transcoder cpu_transcoder; 483 u32 alpm_ctl; 484 int ret; 485 486 ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 487 if (ret) 488 return ret; 489 490 crtc = connector->base.state->crtc; 491 if (connector->base.status != connector_status_connected || !crtc) { 492 ret = -ENODEV; 493 goto out; 494 } 495 496 crtc_state = to_intel_crtc_state(crtc->state); 497 cpu_transcoder = crtc_state->cpu_transcoder; 498 alpm_ctl = intel_de_read(display, ALPM_CTL(display, cpu_transcoder)); 499 seq_printf(m, "LOBF status: %s\n", str_enabled_disabled(alpm_ctl & ALPM_CTL_LOBF_ENABLE)); 500 seq_printf(m, "Aux-wake alpm status: %s\n", 501 str_enabled_disabled(!(alpm_ctl & ALPM_CTL_ALPM_AUX_LESS_ENABLE))); 502 seq_printf(m, "Aux-less alpm status: %s\n", 503 str_enabled_disabled(alpm_ctl & ALPM_CTL_ALPM_AUX_LESS_ENABLE)); 504 out: 505 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 506 507 return ret; 508 } 509 510 DEFINE_SHOW_ATTRIBUTE(i915_edp_lobf_info); 511 512 static int 513 i915_edp_lobf_debug_get(void *data, u64 *val) 514 { 515 struct intel_connector *connector = data; 516 struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); 517 518 *val = intel_dp->alpm_parameters.lobf_disable_debug; 519 520 return 0; 521 } 522 523 static int 524 i915_edp_lobf_debug_set(void *data, u64 val) 525 { 526 struct intel_connector *connector = data; 527 struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); 528 529 intel_dp->alpm_parameters.lobf_disable_debug = val; 530 531 return 0; 532 } 533 534 DEFINE_SIMPLE_ATTRIBUTE(i915_edp_lobf_debug_fops, 535 i915_edp_lobf_debug_get, i915_edp_lobf_debug_set, 536 "%llu\n"); 537 538 void intel_alpm_lobf_debugfs_add(struct intel_connector *connector) 539 { 540 struct intel_display *display = to_intel_display(connector); 541 struct dentry *root = connector->base.debugfs_entry; 542 543 if (DISPLAY_VER(display) < 20 || 544 connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) 545 return; 546 547 debugfs_create_file("i915_edp_lobf_debug", 0644, root, 548 connector, &i915_edp_lobf_debug_fops); 549 550 debugfs_create_file("i915_edp_lobf_info", 0444, root, 551 connector, &i915_edp_lobf_info_fops); 552 } 553 554 void intel_alpm_disable(struct intel_dp *intel_dp) 555 { 556 struct intel_display *display = to_intel_display(intel_dp); 557 enum transcoder cpu_transcoder = intel_dp->alpm_parameters.transcoder; 558 559 if (DISPLAY_VER(display) < 20 || !intel_dp->alpm_dpcd) 560 return; 561 562 mutex_lock(&intel_dp->alpm_parameters.lock); 563 564 intel_de_rmw(display, ALPM_CTL(display, cpu_transcoder), 565 ALPM_CTL_ALPM_ENABLE | ALPM_CTL_LOBF_ENABLE | 566 ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0); 567 568 intel_de_rmw(display, 569 PORT_ALPM_CTL(cpu_transcoder), 570 PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0); 571 572 drm_dbg_kms(display->drm, "Disabling ALPM\n"); 573 mutex_unlock(&intel_dp->alpm_parameters.lock); 574 } 575 576 bool intel_alpm_get_error(struct intel_dp *intel_dp) 577 { 578 struct intel_display *display = to_intel_display(intel_dp); 579 struct drm_dp_aux *aux = &intel_dp->aux; 580 u8 val; 581 int r; 582 583 r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val); 584 if (r != 1) { 585 drm_err(display->drm, "Error reading ALPM status\n"); 586 return true; 587 } 588 589 if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) { 590 drm_dbg_kms(display->drm, "ALPM lock timeout error\n"); 591 592 /* Clearing error */ 593 drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val); 594 return true; 595 } 596 597 return false; 598 } 599