1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include <linux/pci.h> 28 #include <linux/i2c.h> 29 #include "amdgpu.h" 30 #include "amdgpu_dpm.h" 31 #include "amdgpu_smu.h" 32 #include "atomfirmware.h" 33 #include "amdgpu_atomfirmware.h" 34 #include "amdgpu_atombios.h" 35 #include "smu_v11_0.h" 36 #include "smu11_driver_if_sienna_cichlid.h" 37 #include "soc15_common.h" 38 #include "atom.h" 39 #include "sienna_cichlid_ppt.h" 40 #include "smu_v11_0_7_pptable.h" 41 #include "smu_v11_0_7_ppsmc.h" 42 #include "nbio/nbio_2_3_offset.h" 43 #include "nbio/nbio_2_3_sh_mask.h" 44 #include "thm/thm_11_0_2_offset.h" 45 #include "thm/thm_11_0_2_sh_mask.h" 46 #include "mp/mp_11_0_offset.h" 47 #include "mp/mp_11_0_sh_mask.h" 48 49 #include "asic_reg/mp/mp_11_0_sh_mask.h" 50 #include "amdgpu_ras.h" 51 #include "smu_cmn.h" 52 53 /* 54 * DO NOT use these for err/warn/info/debug messages. 55 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 56 * They are more MGPU friendly. 57 */ 58 #undef pr_err 59 #undef pr_warn 60 #undef pr_info 61 #undef pr_debug 62 63 #define FEATURE_MASK(feature) (1ULL << feature) 64 #define SMC_DPM_FEATURE ( \ 65 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \ 66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 68 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ 69 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 70 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \ 72 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)) 73 74 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15 75 76 #define GET_PPTABLE_MEMBER(field, member) \ 77 do { \ 78 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == \ 79 IP_VERSION(11, 0, 13)) \ 80 (*member) = (smu->smu_table.driver_pptable + \ 81 offsetof(PPTable_beige_goby_t, field)); \ 82 else \ 83 (*member) = (smu->smu_table.driver_pptable + \ 84 offsetof(PPTable_t, field)); \ 85 } while (0) 86 87 /* STB FIFO depth is in 64bit units */ 88 #define SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES 8 89 90 /* 91 * SMU support ECCTABLE since version 58.70.0, 92 * use this to check whether ECCTABLE feature is supported. 93 */ 94 #define SUPPORT_ECCTABLE_SMU_VERSION 0x003a4600 95 96 static int get_table_size(struct smu_context *smu) 97 { 98 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13)) 99 return sizeof(PPTable_beige_goby_t); 100 else 101 return sizeof(PPTable_t); 102 } 103 104 static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = { 105 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 106 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 107 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 108 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0), 109 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0), 110 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 111 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 112 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1), 113 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1), 114 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1), 115 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1), 116 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1), 117 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1), 118 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), 119 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 120 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 121 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 122 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 123 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 124 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 125 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 126 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 127 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), 128 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0), 129 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1), 130 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1), 131 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1), 132 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 133 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1), 134 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1), 135 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 136 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0), 137 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0), 138 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0), 139 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0), 140 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0), 141 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0), 142 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0), 143 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0), 144 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1), 145 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0), 146 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0), 147 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), 148 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1), 149 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0), 150 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), 151 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), 152 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0), 153 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0), 154 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0), 155 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0), 156 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0), 157 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0), 158 MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0), 159 MSG_MAP(DisallowGpo, PPSMC_MSG_DisallowGpo, 0), 160 MSG_MAP(Enable2ndUSB20Port, PPSMC_MSG_Enable2ndUSB20Port, 0), 161 MSG_MAP(DriverMode2Reset, PPSMC_MSG_DriverMode2Reset, 0), 162 }; 163 164 static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = { 165 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 166 CLK_MAP(SCLK, PPCLK_GFXCLK), 167 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 168 CLK_MAP(FCLK, PPCLK_FCLK), 169 CLK_MAP(UCLK, PPCLK_UCLK), 170 CLK_MAP(MCLK, PPCLK_UCLK), 171 CLK_MAP(DCLK, PPCLK_DCLK_0), 172 CLK_MAP(DCLK1, PPCLK_DCLK_1), 173 CLK_MAP(VCLK, PPCLK_VCLK_0), 174 CLK_MAP(VCLK1, PPCLK_VCLK_1), 175 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK), 176 CLK_MAP(DISPCLK, PPCLK_DISPCLK), 177 CLK_MAP(PIXCLK, PPCLK_PIXCLK), 178 CLK_MAP(PHYCLK, PPCLK_PHYCLK), 179 }; 180 181 static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = { 182 FEA_MAP(DPM_PREFETCHER), 183 FEA_MAP(DPM_GFXCLK), 184 FEA_MAP(DPM_GFX_GPO), 185 FEA_MAP(DPM_UCLK), 186 FEA_MAP(DPM_FCLK), 187 FEA_MAP(DPM_SOCCLK), 188 FEA_MAP(DPM_MP0CLK), 189 FEA_MAP(DPM_LINK), 190 FEA_MAP(DPM_DCEFCLK), 191 FEA_MAP(DPM_XGMI), 192 FEA_MAP(MEM_VDDCI_SCALING), 193 FEA_MAP(MEM_MVDD_SCALING), 194 FEA_MAP(DS_GFXCLK), 195 FEA_MAP(DS_SOCCLK), 196 FEA_MAP(DS_FCLK), 197 FEA_MAP(DS_LCLK), 198 FEA_MAP(DS_DCEFCLK), 199 FEA_MAP(DS_UCLK), 200 FEA_MAP(GFX_ULV), 201 FEA_MAP(FW_DSTATE), 202 FEA_MAP(GFXOFF), 203 FEA_MAP(BACO), 204 FEA_MAP(MM_DPM_PG), 205 FEA_MAP(RSMU_SMN_CG), 206 FEA_MAP(PPT), 207 FEA_MAP(TDC), 208 FEA_MAP(APCC_PLUS), 209 FEA_MAP(GTHR), 210 FEA_MAP(ACDC), 211 FEA_MAP(VR0HOT), 212 FEA_MAP(VR1HOT), 213 FEA_MAP(FW_CTF), 214 FEA_MAP(FAN_CONTROL), 215 FEA_MAP(THERMAL), 216 FEA_MAP(GFX_DCS), 217 FEA_MAP(RM), 218 FEA_MAP(LED_DISPLAY), 219 FEA_MAP(GFX_SS), 220 FEA_MAP(OUT_OF_BAND_MONITOR), 221 FEA_MAP(TEMP_DEPENDENT_VMIN), 222 FEA_MAP(MMHUB_PG), 223 FEA_MAP(ATHUB_PG), 224 FEA_MAP(APCC_DFLL), 225 }; 226 227 static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = { 228 TAB_MAP(PPTABLE), 229 TAB_MAP(WATERMARKS), 230 TAB_MAP(AVFS_PSM_DEBUG), 231 TAB_MAP(AVFS_FUSE_OVERRIDE), 232 TAB_MAP(PMSTATUSLOG), 233 TAB_MAP(SMU_METRICS), 234 TAB_MAP(DRIVER_SMU_CONFIG), 235 TAB_MAP(ACTIVITY_MONITOR_COEFF), 236 TAB_MAP(OVERDRIVE), 237 TAB_MAP(I2C_COMMANDS), 238 TAB_MAP(PACE), 239 TAB_MAP(ECCINFO), 240 }; 241 242 static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { 243 PWR_MAP(AC), 244 PWR_MAP(DC), 245 }; 246 247 static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 248 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT), 249 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT), 250 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), 251 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 252 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), 253 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 254 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 255 }; 256 257 static const uint8_t sienna_cichlid_throttler_map[] = { 258 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT), 259 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT), 260 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 261 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 262 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 263 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT), 264 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 265 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT), 266 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT), 267 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 268 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 269 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 270 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 271 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT), 272 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT), 273 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT), 274 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT), 275 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT), 276 }; 277 278 static int 279 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu, 280 uint32_t *feature_mask, uint32_t num) 281 { 282 struct amdgpu_device *adev = smu->adev; 283 284 if (num > 2) 285 return -EINVAL; 286 287 memset(feature_mask, 0, sizeof(uint32_t) * num); 288 289 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) 290 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT) 291 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) 292 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) 293 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) 294 | FEATURE_MASK(FEATURE_DS_FCLK_BIT) 295 | FEATURE_MASK(FEATURE_DS_UCLK_BIT) 296 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) 297 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT) 298 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT) 299 | FEATURE_MASK(FEATURE_GFX_SS_BIT) 300 | FEATURE_MASK(FEATURE_VR0HOT_BIT) 301 | FEATURE_MASK(FEATURE_PPT_BIT) 302 | FEATURE_MASK(FEATURE_TDC_BIT) 303 | FEATURE_MASK(FEATURE_BACO_BIT) 304 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT) 305 | FEATURE_MASK(FEATURE_FW_CTF_BIT) 306 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT) 307 | FEATURE_MASK(FEATURE_THERMAL_BIT) 308 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT); 309 310 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) { 311 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 312 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT); 313 } 314 315 if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) && 316 (amdgpu_ip_version(adev, MP1_HWIP, 0) > IP_VERSION(11, 0, 7)) && 317 !(adev->flags & AMD_IS_APU)) 318 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT); 319 320 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) 321 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) 322 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT) 323 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT); 324 325 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) 326 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); 327 328 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) 329 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); 330 331 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) 332 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); 333 334 if (adev->pm.pp_feature & PP_ULV_MASK) 335 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); 336 337 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) 338 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); 339 340 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 341 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); 342 343 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB) 344 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT); 345 346 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB) 347 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); 348 349 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN || 350 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG) 351 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT); 352 353 if (smu->dc_controlled_by_gpio) 354 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT); 355 356 if (amdgpu_device_should_use_aspm(adev)) 357 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT); 358 359 return 0; 360 } 361 362 static void sienna_cichlid_check_bxco_support(struct smu_context *smu) 363 { 364 struct smu_table_context *table_context = &smu->smu_table; 365 struct smu_11_0_7_powerplay_table *powerplay_table = 366 table_context->power_play_table; 367 struct smu_baco_context *smu_baco = &smu->smu_baco; 368 struct amdgpu_device *adev = smu->adev; 369 uint32_t val; 370 371 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO) { 372 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); 373 smu_baco->platform_support = 374 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : 375 false; 376 377 /* 378 * Disable BACO entry/exit completely on below SKUs to 379 * avoid hardware intermittent failures. 380 */ 381 if (((adev->pdev->device == 0x73A1) && 382 (adev->pdev->revision == 0x00)) || 383 ((adev->pdev->device == 0x73BF) && 384 (adev->pdev->revision == 0xCF)) || 385 ((adev->pdev->device == 0x7422) && 386 (adev->pdev->revision == 0x00)) || 387 ((adev->pdev->device == 0x73A3) && 388 (adev->pdev->revision == 0x00)) || 389 ((adev->pdev->device == 0x73E3) && 390 (adev->pdev->revision == 0x00))) 391 smu_baco->platform_support = false; 392 393 } 394 } 395 396 static void sienna_cichlid_check_fan_support(struct smu_context *smu) 397 { 398 struct smu_table_context *table_context = &smu->smu_table; 399 PPTable_t *pptable = table_context->driver_pptable; 400 uint64_t features = *(uint64_t *) pptable->FeaturesToRun; 401 402 /* Fan control is not possible if PPTable has it disabled */ 403 smu->adev->pm.no_fan = 404 !(features & (1ULL << FEATURE_FAN_CONTROL_BIT)); 405 if (smu->adev->pm.no_fan) 406 dev_info_once(smu->adev->dev, 407 "PMFW based fan control disabled"); 408 } 409 410 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu) 411 { 412 struct smu_table_context *table_context = &smu->smu_table; 413 struct smu_11_0_7_powerplay_table *powerplay_table = 414 table_context->power_play_table; 415 416 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC) 417 smu->dc_controlled_by_gpio = true; 418 419 sienna_cichlid_check_bxco_support(smu); 420 sienna_cichlid_check_fan_support(smu); 421 422 table_context->thermal_controller_type = 423 powerplay_table->thermal_controller_type; 424 425 /* 426 * Instead of having its own buffer space and get overdrive_table copied, 427 * smu->od_settings just points to the actual overdrive_table 428 */ 429 smu->od_settings = &powerplay_table->overdrive_table; 430 431 return 0; 432 } 433 434 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu) 435 { 436 struct atom_smc_dpm_info_v4_9 *smc_dpm_table; 437 int index, ret; 438 PPTable_beige_goby_t *ppt_beige_goby; 439 PPTable_t *ppt; 440 441 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13)) 442 ppt_beige_goby = smu->smu_table.driver_pptable; 443 else 444 ppt = smu->smu_table.driver_pptable; 445 446 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 447 smc_dpm_info); 448 449 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, 450 (uint8_t **)&smc_dpm_table); 451 if (ret) 452 return ret; 453 454 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13)) 455 smu_memcpy_trailing(ppt_beige_goby, I2cControllers, BoardReserved, 456 smc_dpm_table, I2cControllers); 457 else 458 smu_memcpy_trailing(ppt, I2cControllers, BoardReserved, 459 smc_dpm_table, I2cControllers); 460 461 return 0; 462 } 463 464 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu) 465 { 466 struct smu_table_context *table_context = &smu->smu_table; 467 struct smu_11_0_7_powerplay_table *powerplay_table = 468 table_context->power_play_table; 469 int table_size; 470 471 table_size = get_table_size(smu); 472 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 473 table_size); 474 475 return 0; 476 } 477 478 static int sienna_cichlid_patch_pptable_quirk(struct smu_context *smu) 479 { 480 struct amdgpu_device *adev = smu->adev; 481 uint32_t *board_reserved; 482 uint16_t *freq_table_gfx; 483 uint32_t i; 484 485 /* Fix some OEM SKU specific stability issues */ 486 GET_PPTABLE_MEMBER(BoardReserved, &board_reserved); 487 if ((adev->pdev->device == 0x73DF) && 488 (adev->pdev->revision == 0XC3) && 489 (adev->pdev->subsystem_device == 0x16C2) && 490 (adev->pdev->subsystem_vendor == 0x1043)) 491 board_reserved[0] = 1387; 492 493 GET_PPTABLE_MEMBER(FreqTableGfx, &freq_table_gfx); 494 if ((adev->pdev->device == 0x73DF) && 495 (adev->pdev->revision == 0XC3) && 496 ((adev->pdev->subsystem_device == 0x16C2) || 497 (adev->pdev->subsystem_device == 0x133C)) && 498 (adev->pdev->subsystem_vendor == 0x1043)) { 499 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) { 500 if (freq_table_gfx[i] > 2500) 501 freq_table_gfx[i] = 2500; 502 } 503 } 504 505 return 0; 506 } 507 508 static int sienna_cichlid_setup_pptable(struct smu_context *smu) 509 { 510 int ret = 0; 511 512 ret = smu_v11_0_setup_pptable(smu); 513 if (ret) 514 return ret; 515 516 ret = sienna_cichlid_store_powerplay_table(smu); 517 if (ret) 518 return ret; 519 520 ret = sienna_cichlid_append_powerplay_table(smu); 521 if (ret) 522 return ret; 523 524 ret = sienna_cichlid_check_powerplay_table(smu); 525 if (ret) 526 return ret; 527 528 return sienna_cichlid_patch_pptable_quirk(smu); 529 } 530 531 static int sienna_cichlid_tables_init(struct smu_context *smu) 532 { 533 struct smu_table_context *smu_table = &smu->smu_table; 534 struct smu_table *tables = smu_table->tables; 535 int table_size; 536 537 table_size = get_table_size(smu); 538 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size, 539 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 540 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 541 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 542 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t), 543 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 544 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 545 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 546 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t), 547 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 548 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, 549 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 550 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, 551 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE, 552 AMDGPU_GEM_DOMAIN_VRAM); 553 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t), 554 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 555 SMU_TABLE_INIT(tables, SMU_TABLE_DRIVER_SMU_CONFIG, sizeof(DriverSmuConfigExternal_t), 556 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 557 558 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL); 559 if (!smu_table->metrics_table) 560 goto err0_out; 561 smu_table->metrics_time = 0; 562 563 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); 564 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 565 if (!smu_table->gpu_metrics_table) 566 goto err1_out; 567 568 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 569 if (!smu_table->watermarks_table) 570 goto err2_out; 571 572 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL); 573 if (!smu_table->ecc_table) 574 goto err3_out; 575 576 smu_table->driver_smu_config_table = 577 kzalloc(tables[SMU_TABLE_DRIVER_SMU_CONFIG].size, GFP_KERNEL); 578 if (!smu_table->driver_smu_config_table) 579 goto err4_out; 580 581 return 0; 582 583 err4_out: 584 kfree(smu_table->ecc_table); 585 err3_out: 586 kfree(smu_table->watermarks_table); 587 err2_out: 588 kfree(smu_table->gpu_metrics_table); 589 err1_out: 590 kfree(smu_table->metrics_table); 591 err0_out: 592 return -ENOMEM; 593 } 594 595 static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu, 596 bool use_metrics_v3, 597 bool use_metrics_v2) 598 { 599 struct smu_table_context *smu_table= &smu->smu_table; 600 SmuMetricsExternal_t *metrics_ext = 601 (SmuMetricsExternal_t *)(smu_table->metrics_table); 602 uint32_t throttler_status = 0; 603 int i; 604 605 if (use_metrics_v3) { 606 for (i = 0; i < THROTTLER_COUNT; i++) 607 throttler_status |= 608 (metrics_ext->SmuMetrics_V3.ThrottlingPercentage[i] ? 1U << i : 0); 609 } else if (use_metrics_v2) { 610 for (i = 0; i < THROTTLER_COUNT; i++) 611 throttler_status |= 612 (metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0); 613 } else { 614 throttler_status = metrics_ext->SmuMetrics.ThrottlerStatus; 615 } 616 617 return throttler_status; 618 } 619 620 static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table, 621 enum SMU_11_0_7_ODFEATURE_CAP cap) 622 { 623 return od_table->cap[cap]; 624 } 625 626 static int sienna_cichlid_get_power_limit(struct smu_context *smu, 627 uint32_t *current_power_limit, 628 uint32_t *default_power_limit, 629 uint32_t *max_power_limit, 630 uint32_t *min_power_limit) 631 { 632 struct smu_11_0_7_powerplay_table *powerplay_table = 633 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table; 634 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings; 635 uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0; 636 uint16_t *table_member; 637 638 GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member); 639 640 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) { 641 power_limit = 642 table_member[PPT_THROTTLER_PPT0]; 643 } 644 645 if (current_power_limit) 646 *current_power_limit = power_limit; 647 if (default_power_limit) 648 *default_power_limit = power_limit; 649 650 if (powerplay_table) { 651 if (smu->od_enabled && 652 sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_POWER_LIMIT)) { 653 od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]); 654 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]); 655 } else if ((sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_POWER_LIMIT))) { 656 od_percent_upper = 0; 657 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]); 658 } 659 } 660 661 dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n", 662 od_percent_upper, od_percent_lower, power_limit); 663 664 if (max_power_limit) { 665 *max_power_limit = power_limit * (100 + od_percent_upper); 666 *max_power_limit /= 100; 667 } 668 669 if (min_power_limit) { 670 *min_power_limit = power_limit * (100 - od_percent_lower); 671 *min_power_limit /= 100; 672 } 673 return 0; 674 } 675 676 static void sienna_cichlid_get_smartshift_power_percentage(struct smu_context *smu, 677 uint32_t *apu_percent, 678 uint32_t *dgpu_percent) 679 { 680 struct smu_table_context *smu_table = &smu->smu_table; 681 SmuMetrics_V4_t *metrics_v4 = 682 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V4); 683 uint16_t powerRatio = 0; 684 uint16_t apu_power_limit = 0; 685 uint16_t dgpu_power_limit = 0; 686 uint32_t apu_boost = 0; 687 uint32_t dgpu_boost = 0; 688 uint32_t cur_power_limit; 689 690 if (metrics_v4->ApuSTAPMSmartShiftLimit != 0) { 691 sienna_cichlid_get_power_limit(smu, &cur_power_limit, NULL, NULL, NULL); 692 apu_power_limit = metrics_v4->ApuSTAPMLimit; 693 dgpu_power_limit = cur_power_limit; 694 powerRatio = (((apu_power_limit + 695 dgpu_power_limit) * 100) / 696 metrics_v4->ApuSTAPMSmartShiftLimit); 697 if (powerRatio > 100) { 698 apu_power_limit = (apu_power_limit * 100) / 699 powerRatio; 700 dgpu_power_limit = (dgpu_power_limit * 100) / 701 powerRatio; 702 } 703 if (metrics_v4->AverageApuSocketPower > apu_power_limit && 704 apu_power_limit != 0) { 705 apu_boost = ((metrics_v4->AverageApuSocketPower - 706 apu_power_limit) * 100) / 707 apu_power_limit; 708 if (apu_boost > 100) 709 apu_boost = 100; 710 } 711 712 if (metrics_v4->AverageSocketPower > dgpu_power_limit && 713 dgpu_power_limit != 0) { 714 dgpu_boost = ((metrics_v4->AverageSocketPower - 715 dgpu_power_limit) * 100) / 716 dgpu_power_limit; 717 if (dgpu_boost > 100) 718 dgpu_boost = 100; 719 } 720 721 if (dgpu_boost >= apu_boost) 722 apu_boost = 0; 723 else 724 dgpu_boost = 0; 725 } 726 *apu_percent = apu_boost; 727 *dgpu_percent = dgpu_boost; 728 } 729 730 static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu, 731 MetricsMember_t member, 732 uint32_t *value) 733 { 734 struct smu_table_context *smu_table= &smu->smu_table; 735 SmuMetrics_t *metrics = 736 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics); 737 SmuMetrics_V2_t *metrics_v2 = 738 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2); 739 SmuMetrics_V3_t *metrics_v3 = 740 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V3); 741 bool use_metrics_v2 = false; 742 bool use_metrics_v3 = false; 743 uint16_t average_gfx_activity; 744 int ret = 0; 745 uint32_t apu_percent = 0; 746 uint32_t dgpu_percent = 0; 747 748 switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) { 749 case IP_VERSION(11, 0, 7): 750 if (smu->smc_fw_version >= 0x3A4900) 751 use_metrics_v3 = true; 752 else if (smu->smc_fw_version >= 0x3A4300) 753 use_metrics_v2 = true; 754 break; 755 case IP_VERSION(11, 0, 11): 756 if (smu->smc_fw_version >= 0x412D00) 757 use_metrics_v2 = true; 758 break; 759 case IP_VERSION(11, 0, 12): 760 if (smu->smc_fw_version >= 0x3B2300) 761 use_metrics_v2 = true; 762 break; 763 case IP_VERSION(11, 0, 13): 764 if (smu->smc_fw_version >= 0x491100) 765 use_metrics_v2 = true; 766 break; 767 default: 768 break; 769 } 770 771 ret = smu_cmn_get_metrics_table(smu, 772 NULL, 773 false); 774 if (ret) 775 return ret; 776 777 switch (member) { 778 case METRICS_CURR_GFXCLK: 779 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] : 780 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : 781 metrics->CurrClock[PPCLK_GFXCLK]; 782 break; 783 case METRICS_CURR_SOCCLK: 784 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] : 785 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : 786 metrics->CurrClock[PPCLK_SOCCLK]; 787 break; 788 case METRICS_CURR_UCLK: 789 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] : 790 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : 791 metrics->CurrClock[PPCLK_UCLK]; 792 break; 793 case METRICS_CURR_VCLK: 794 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] : 795 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : 796 metrics->CurrClock[PPCLK_VCLK_0]; 797 break; 798 case METRICS_CURR_VCLK1: 799 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] : 800 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : 801 metrics->CurrClock[PPCLK_VCLK_1]; 802 break; 803 case METRICS_CURR_DCLK: 804 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] : 805 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : 806 metrics->CurrClock[PPCLK_DCLK_0]; 807 break; 808 case METRICS_CURR_DCLK1: 809 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] : 810 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : 811 metrics->CurrClock[PPCLK_DCLK_1]; 812 break; 813 case METRICS_CURR_DCEFCLK: 814 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCEFCLK] : 815 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCEFCLK] : 816 metrics->CurrClock[PPCLK_DCEFCLK]; 817 break; 818 case METRICS_CURR_FCLK: 819 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_FCLK] : 820 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_FCLK] : 821 metrics->CurrClock[PPCLK_FCLK]; 822 break; 823 case METRICS_AVERAGE_GFXCLK: 824 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity : 825 use_metrics_v2 ? metrics_v2->AverageGfxActivity : 826 metrics->AverageGfxActivity; 827 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD) 828 *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs : 829 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs : 830 metrics->AverageGfxclkFrequencyPostDs; 831 else 832 *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs : 833 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs : 834 metrics->AverageGfxclkFrequencyPreDs; 835 break; 836 case METRICS_AVERAGE_FCLK: 837 *value = use_metrics_v3 ? metrics_v3->AverageFclkFrequencyPostDs : 838 use_metrics_v2 ? metrics_v2->AverageFclkFrequencyPostDs : 839 metrics->AverageFclkFrequencyPostDs; 840 break; 841 case METRICS_AVERAGE_UCLK: 842 *value = use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs : 843 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs : 844 metrics->AverageUclkFrequencyPostDs; 845 break; 846 case METRICS_AVERAGE_GFXACTIVITY: 847 *value = use_metrics_v3 ? metrics_v3->AverageGfxActivity : 848 use_metrics_v2 ? metrics_v2->AverageGfxActivity : 849 metrics->AverageGfxActivity; 850 break; 851 case METRICS_AVERAGE_MEMACTIVITY: 852 *value = use_metrics_v3 ? metrics_v3->AverageUclkActivity : 853 use_metrics_v2 ? metrics_v2->AverageUclkActivity : 854 metrics->AverageUclkActivity; 855 break; 856 case METRICS_AVERAGE_SOCKETPOWER: 857 *value = use_metrics_v3 ? metrics_v3->AverageSocketPower << 8 : 858 use_metrics_v2 ? metrics_v2->AverageSocketPower << 8 : 859 metrics->AverageSocketPower << 8; 860 break; 861 case METRICS_TEMPERATURE_EDGE: 862 *value = (use_metrics_v3 ? metrics_v3->TemperatureEdge : 863 use_metrics_v2 ? metrics_v2->TemperatureEdge : 864 metrics->TemperatureEdge) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 865 break; 866 case METRICS_TEMPERATURE_HOTSPOT: 867 *value = (use_metrics_v3 ? metrics_v3->TemperatureHotspot : 868 use_metrics_v2 ? metrics_v2->TemperatureHotspot : 869 metrics->TemperatureHotspot) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 870 break; 871 case METRICS_TEMPERATURE_MEM: 872 *value = (use_metrics_v3 ? metrics_v3->TemperatureMem : 873 use_metrics_v2 ? metrics_v2->TemperatureMem : 874 metrics->TemperatureMem) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 875 break; 876 case METRICS_TEMPERATURE_VRGFX: 877 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrGfx : 878 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : 879 metrics->TemperatureVrGfx) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 880 break; 881 case METRICS_TEMPERATURE_VRSOC: 882 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrSoc : 883 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : 884 metrics->TemperatureVrSoc) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 885 break; 886 case METRICS_THROTTLER_STATUS: 887 *value = sienna_cichlid_get_throttler_status_locked(smu, use_metrics_v3, use_metrics_v2); 888 break; 889 case METRICS_CURR_FANSPEED: 890 *value = use_metrics_v3 ? metrics_v3->CurrFanSpeed : 891 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed; 892 break; 893 case METRICS_UNIQUE_ID_UPPER32: 894 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */ 895 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumUpper32 : 0; 896 break; 897 case METRICS_UNIQUE_ID_LOWER32: 898 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */ 899 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumLower32 : 0; 900 break; 901 case METRICS_SS_APU_SHARE: 902 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent); 903 *value = apu_percent; 904 break; 905 case METRICS_SS_DGPU_SHARE: 906 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent); 907 *value = dgpu_percent; 908 break; 909 910 default: 911 *value = UINT_MAX; 912 break; 913 } 914 915 return ret; 916 917 } 918 919 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu) 920 { 921 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 922 923 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), 924 GFP_KERNEL); 925 if (!smu_dpm->dpm_context) 926 return -ENOMEM; 927 928 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); 929 930 return 0; 931 } 932 933 static void sienna_cichlid_stb_init(struct smu_context *smu); 934 935 static int sienna_cichlid_init_smc_tables(struct smu_context *smu) 936 { 937 struct amdgpu_device *adev = smu->adev; 938 int ret = 0; 939 940 ret = sienna_cichlid_tables_init(smu); 941 if (ret) 942 return ret; 943 944 ret = sienna_cichlid_allocate_dpm_context(smu); 945 if (ret) 946 return ret; 947 948 if (!amdgpu_sriov_vf(adev)) 949 sienna_cichlid_stb_init(smu); 950 951 return smu_v11_0_init_smc_tables(smu); 952 } 953 954 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) 955 { 956 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 957 struct smu_11_0_dpm_table *dpm_table; 958 struct amdgpu_device *adev = smu->adev; 959 int i, ret = 0; 960 DpmDescriptor_t *table_member; 961 962 /* socclk dpm table setup */ 963 dpm_table = &dpm_context->dpm_tables.soc_table; 964 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member); 965 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 966 ret = smu_v11_0_set_single_dpm_table(smu, 967 SMU_SOCCLK, 968 dpm_table); 969 if (ret) 970 return ret; 971 dpm_table->is_fine_grained = 972 !table_member[PPCLK_SOCCLK].SnapToDiscrete; 973 } else { 974 dpm_table->count = 1; 975 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 976 dpm_table->dpm_levels[0].enabled = true; 977 dpm_table->min = dpm_table->dpm_levels[0].value; 978 dpm_table->max = dpm_table->dpm_levels[0].value; 979 } 980 981 /* gfxclk dpm table setup */ 982 dpm_table = &dpm_context->dpm_tables.gfx_table; 983 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 984 ret = smu_v11_0_set_single_dpm_table(smu, 985 SMU_GFXCLK, 986 dpm_table); 987 if (ret) 988 return ret; 989 dpm_table->is_fine_grained = 990 !table_member[PPCLK_GFXCLK].SnapToDiscrete; 991 } else { 992 dpm_table->count = 1; 993 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 994 dpm_table->dpm_levels[0].enabled = true; 995 dpm_table->min = dpm_table->dpm_levels[0].value; 996 dpm_table->max = dpm_table->dpm_levels[0].value; 997 } 998 999 /* uclk dpm table setup */ 1000 dpm_table = &dpm_context->dpm_tables.uclk_table; 1001 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1002 ret = smu_v11_0_set_single_dpm_table(smu, 1003 SMU_UCLK, 1004 dpm_table); 1005 if (ret) 1006 return ret; 1007 dpm_table->is_fine_grained = 1008 !table_member[PPCLK_UCLK].SnapToDiscrete; 1009 } else { 1010 dpm_table->count = 1; 1011 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 1012 dpm_table->dpm_levels[0].enabled = true; 1013 dpm_table->min = dpm_table->dpm_levels[0].value; 1014 dpm_table->max = dpm_table->dpm_levels[0].value; 1015 } 1016 1017 /* fclk dpm table setup */ 1018 dpm_table = &dpm_context->dpm_tables.fclk_table; 1019 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { 1020 ret = smu_v11_0_set_single_dpm_table(smu, 1021 SMU_FCLK, 1022 dpm_table); 1023 if (ret) 1024 return ret; 1025 dpm_table->is_fine_grained = 1026 !table_member[PPCLK_FCLK].SnapToDiscrete; 1027 } else { 1028 dpm_table->count = 1; 1029 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; 1030 dpm_table->dpm_levels[0].enabled = true; 1031 dpm_table->min = dpm_table->dpm_levels[0].value; 1032 dpm_table->max = dpm_table->dpm_levels[0].value; 1033 } 1034 1035 /* vclk0/1 dpm table setup */ 1036 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1037 if (adev->vcn.harvest_config & (1 << i)) 1038 continue; 1039 1040 dpm_table = &dpm_context->dpm_tables.vclk_table; 1041 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 1042 ret = smu_v11_0_set_single_dpm_table(smu, 1043 i ? SMU_VCLK1 : SMU_VCLK, 1044 dpm_table); 1045 if (ret) 1046 return ret; 1047 dpm_table->is_fine_grained = 1048 !table_member[i ? PPCLK_VCLK_1 : PPCLK_VCLK_0].SnapToDiscrete; 1049 } else { 1050 dpm_table->count = 1; 1051 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; 1052 dpm_table->dpm_levels[0].enabled = true; 1053 dpm_table->min = dpm_table->dpm_levels[0].value; 1054 dpm_table->max = dpm_table->dpm_levels[0].value; 1055 } 1056 } 1057 1058 /* dclk0/1 dpm table setup */ 1059 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1060 if (adev->vcn.harvest_config & (1 << i)) 1061 continue; 1062 dpm_table = &dpm_context->dpm_tables.dclk_table; 1063 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 1064 ret = smu_v11_0_set_single_dpm_table(smu, 1065 i ? SMU_DCLK1 : SMU_DCLK, 1066 dpm_table); 1067 if (ret) 1068 return ret; 1069 dpm_table->is_fine_grained = 1070 !table_member[i ? PPCLK_DCLK_1 : PPCLK_DCLK_0].SnapToDiscrete; 1071 } else { 1072 dpm_table->count = 1; 1073 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; 1074 dpm_table->dpm_levels[0].enabled = true; 1075 dpm_table->min = dpm_table->dpm_levels[0].value; 1076 dpm_table->max = dpm_table->dpm_levels[0].value; 1077 } 1078 } 1079 1080 /* dcefclk dpm table setup */ 1081 dpm_table = &dpm_context->dpm_tables.dcef_table; 1082 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1083 ret = smu_v11_0_set_single_dpm_table(smu, 1084 SMU_DCEFCLK, 1085 dpm_table); 1086 if (ret) 1087 return ret; 1088 dpm_table->is_fine_grained = 1089 !table_member[PPCLK_DCEFCLK].SnapToDiscrete; 1090 } else { 1091 dpm_table->count = 1; 1092 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1093 dpm_table->dpm_levels[0].enabled = true; 1094 dpm_table->min = dpm_table->dpm_levels[0].value; 1095 dpm_table->max = dpm_table->dpm_levels[0].value; 1096 } 1097 1098 /* pixelclk dpm table setup */ 1099 dpm_table = &dpm_context->dpm_tables.pixel_table; 1100 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1101 ret = smu_v11_0_set_single_dpm_table(smu, 1102 SMU_PIXCLK, 1103 dpm_table); 1104 if (ret) 1105 return ret; 1106 dpm_table->is_fine_grained = 1107 !table_member[PPCLK_PIXCLK].SnapToDiscrete; 1108 } else { 1109 dpm_table->count = 1; 1110 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1111 dpm_table->dpm_levels[0].enabled = true; 1112 dpm_table->min = dpm_table->dpm_levels[0].value; 1113 dpm_table->max = dpm_table->dpm_levels[0].value; 1114 } 1115 1116 /* displayclk dpm table setup */ 1117 dpm_table = &dpm_context->dpm_tables.display_table; 1118 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1119 ret = smu_v11_0_set_single_dpm_table(smu, 1120 SMU_DISPCLK, 1121 dpm_table); 1122 if (ret) 1123 return ret; 1124 dpm_table->is_fine_grained = 1125 !table_member[PPCLK_DISPCLK].SnapToDiscrete; 1126 } else { 1127 dpm_table->count = 1; 1128 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1129 dpm_table->dpm_levels[0].enabled = true; 1130 dpm_table->min = dpm_table->dpm_levels[0].value; 1131 dpm_table->max = dpm_table->dpm_levels[0].value; 1132 } 1133 1134 /* phyclk dpm table setup */ 1135 dpm_table = &dpm_context->dpm_tables.phy_table; 1136 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1137 ret = smu_v11_0_set_single_dpm_table(smu, 1138 SMU_PHYCLK, 1139 dpm_table); 1140 if (ret) 1141 return ret; 1142 dpm_table->is_fine_grained = 1143 !table_member[PPCLK_PHYCLK].SnapToDiscrete; 1144 } else { 1145 dpm_table->count = 1; 1146 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; 1147 dpm_table->dpm_levels[0].enabled = true; 1148 dpm_table->min = dpm_table->dpm_levels[0].value; 1149 dpm_table->max = dpm_table->dpm_levels[0].value; 1150 } 1151 1152 return 0; 1153 } 1154 1155 static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 1156 { 1157 struct amdgpu_device *adev = smu->adev; 1158 int i, ret = 0; 1159 1160 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1161 if (adev->vcn.harvest_config & (1 << i)) 1162 continue; 1163 /* vcn dpm on is a prerequisite for vcn power gate messages */ 1164 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 1165 ret = smu_cmn_send_smc_msg_with_param(smu, enable ? 1166 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn, 1167 0x10000 * i, NULL); 1168 if (ret) 1169 return ret; 1170 } 1171 } 1172 1173 return ret; 1174 } 1175 1176 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) 1177 { 1178 int ret = 0; 1179 1180 if (enable) { 1181 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 1182 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL); 1183 if (ret) 1184 return ret; 1185 } 1186 } else { 1187 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { 1188 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL); 1189 if (ret) 1190 return ret; 1191 } 1192 } 1193 1194 return ret; 1195 } 1196 1197 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu, 1198 enum smu_clk_type clk_type, 1199 uint32_t *value) 1200 { 1201 MetricsMember_t member_type; 1202 int clk_id = 0; 1203 1204 clk_id = smu_cmn_to_asic_specific_index(smu, 1205 CMN2ASIC_MAPPING_CLK, 1206 clk_type); 1207 if (clk_id < 0) 1208 return clk_id; 1209 1210 switch (clk_id) { 1211 case PPCLK_GFXCLK: 1212 member_type = METRICS_CURR_GFXCLK; 1213 break; 1214 case PPCLK_UCLK: 1215 member_type = METRICS_CURR_UCLK; 1216 break; 1217 case PPCLK_SOCCLK: 1218 member_type = METRICS_CURR_SOCCLK; 1219 break; 1220 case PPCLK_FCLK: 1221 member_type = METRICS_CURR_FCLK; 1222 break; 1223 case PPCLK_VCLK_0: 1224 member_type = METRICS_CURR_VCLK; 1225 break; 1226 case PPCLK_VCLK_1: 1227 member_type = METRICS_CURR_VCLK1; 1228 break; 1229 case PPCLK_DCLK_0: 1230 member_type = METRICS_CURR_DCLK; 1231 break; 1232 case PPCLK_DCLK_1: 1233 member_type = METRICS_CURR_DCLK1; 1234 break; 1235 case PPCLK_DCEFCLK: 1236 member_type = METRICS_CURR_DCEFCLK; 1237 break; 1238 default: 1239 return -EINVAL; 1240 } 1241 1242 return sienna_cichlid_get_smu_metrics_data(smu, 1243 member_type, 1244 value); 1245 1246 } 1247 1248 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) 1249 { 1250 DpmDescriptor_t *dpm_desc = NULL; 1251 DpmDescriptor_t *table_member; 1252 uint32_t clk_index = 0; 1253 1254 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member); 1255 clk_index = smu_cmn_to_asic_specific_index(smu, 1256 CMN2ASIC_MAPPING_CLK, 1257 clk_type); 1258 dpm_desc = &table_member[clk_index]; 1259 1260 /* 0 - Fine grained DPM, 1 - Discrete DPM */ 1261 return dpm_desc->SnapToDiscrete == 0; 1262 } 1263 1264 static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table, 1265 enum SMU_11_0_7_ODSETTING_ID setting, 1266 uint32_t *min, uint32_t *max) 1267 { 1268 if (min) 1269 *min = od_table->min[setting]; 1270 if (max) 1271 *max = od_table->max[setting]; 1272 } 1273 1274 static int sienna_cichlid_print_clk_levels(struct smu_context *smu, 1275 enum smu_clk_type clk_type, char *buf) 1276 { 1277 struct amdgpu_device *adev = smu->adev; 1278 struct smu_table_context *table_context = &smu->smu_table; 1279 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1280 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; 1281 uint16_t *table_member; 1282 1283 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings; 1284 OverDriveTable_t *od_table = 1285 (OverDriveTable_t *)table_context->overdrive_table; 1286 int i, size = 0, ret = 0; 1287 uint32_t cur_value = 0, value = 0, count = 0; 1288 uint32_t freq_values[3] = {0}; 1289 uint32_t mark_index = 0; 1290 uint32_t gen_speed, lane_width; 1291 uint32_t min_value, max_value; 1292 1293 smu_cmn_get_sysfs_buf(&buf, &size); 1294 1295 switch (clk_type) { 1296 case SMU_GFXCLK: 1297 case SMU_SCLK: 1298 case SMU_SOCCLK: 1299 case SMU_MCLK: 1300 case SMU_UCLK: 1301 case SMU_FCLK: 1302 case SMU_VCLK: 1303 case SMU_VCLK1: 1304 case SMU_DCLK: 1305 case SMU_DCLK1: 1306 case SMU_DCEFCLK: 1307 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value); 1308 if (ret) 1309 goto print_clk_out; 1310 1311 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); 1312 if (ret) 1313 goto print_clk_out; 1314 1315 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) { 1316 for (i = 0; i < count; i++) { 1317 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value); 1318 if (ret) 1319 goto print_clk_out; 1320 1321 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 1322 cur_value == value ? "*" : ""); 1323 } 1324 } else { 1325 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]); 1326 if (ret) 1327 goto print_clk_out; 1328 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]); 1329 if (ret) 1330 goto print_clk_out; 1331 1332 freq_values[1] = cur_value; 1333 mark_index = cur_value == freq_values[0] ? 0 : 1334 cur_value == freq_values[2] ? 2 : 1; 1335 1336 count = 3; 1337 if (mark_index != 1) { 1338 count = 2; 1339 freq_values[1] = freq_values[2]; 1340 } 1341 1342 for (i = 0; i < count; i++) { 1343 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i], 1344 cur_value == freq_values[i] ? "*" : ""); 1345 } 1346 1347 } 1348 break; 1349 case SMU_PCIE: 1350 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); 1351 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); 1352 GET_PPTABLE_MEMBER(LclkFreq, &table_member); 1353 for (i = 0; i < NUM_LINK_LEVELS; i++) 1354 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i, 1355 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," : 1356 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," : 1357 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," : 1358 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "", 1359 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" : 1360 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" : 1361 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" : 1362 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" : 1363 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" : 1364 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "", 1365 table_member[i], 1366 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) && 1367 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? 1368 "*" : ""); 1369 break; 1370 case SMU_OD_SCLK: 1371 if (!smu->od_enabled || !od_table || !od_settings) 1372 break; 1373 1374 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) 1375 break; 1376 1377 size += sysfs_emit_at(buf, size, "OD_SCLK:\n"); 1378 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax); 1379 break; 1380 1381 case SMU_OD_MCLK: 1382 if (!smu->od_enabled || !od_table || !od_settings) 1383 break; 1384 1385 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) 1386 break; 1387 1388 size += sysfs_emit_at(buf, size, "OD_MCLK:\n"); 1389 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax); 1390 break; 1391 1392 case SMU_OD_VDDGFX_OFFSET: 1393 if (!smu->od_enabled || !od_table || !od_settings) 1394 break; 1395 1396 /* 1397 * OD GFX Voltage Offset functionality is supported only by 58.41.0 1398 * and onwards SMU firmwares. 1399 */ 1400 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == 1401 IP_VERSION(11, 0, 7)) && 1402 (smu->smc_fw_version < 0x003a2900)) 1403 break; 1404 1405 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n"); 1406 size += sysfs_emit_at(buf, size, "%dmV\n", od_table->VddGfxOffset); 1407 break; 1408 1409 case SMU_OD_RANGE: 1410 if (!smu->od_enabled || !od_table || !od_settings) 1411 break; 1412 1413 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 1414 1415 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) { 1416 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN, 1417 &min_value, NULL); 1418 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX, 1419 NULL, &max_value); 1420 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 1421 min_value, max_value); 1422 } 1423 1424 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) { 1425 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN, 1426 &min_value, NULL); 1427 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX, 1428 NULL, &max_value); 1429 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n", 1430 min_value, max_value); 1431 } 1432 break; 1433 1434 default: 1435 break; 1436 } 1437 1438 print_clk_out: 1439 return size; 1440 } 1441 1442 static int sienna_cichlid_force_clk_levels(struct smu_context *smu, 1443 enum smu_clk_type clk_type, uint32_t mask) 1444 { 1445 int ret = 0; 1446 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0; 1447 1448 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1449 soft_max_level = mask ? (fls(mask) - 1) : 0; 1450 1451 switch (clk_type) { 1452 case SMU_GFXCLK: 1453 case SMU_SCLK: 1454 case SMU_SOCCLK: 1455 case SMU_MCLK: 1456 case SMU_UCLK: 1457 case SMU_FCLK: 1458 /* There is only 2 levels for fine grained DPM */ 1459 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) { 1460 soft_max_level = (soft_max_level >= 1 ? 1 : 0); 1461 soft_min_level = (soft_min_level >= 1 ? 1 : 0); 1462 } 1463 1464 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq); 1465 if (ret) 1466 goto forec_level_out; 1467 1468 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq); 1469 if (ret) 1470 goto forec_level_out; 1471 1472 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 1473 if (ret) 1474 goto forec_level_out; 1475 break; 1476 case SMU_DCEFCLK: 1477 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n"); 1478 break; 1479 default: 1480 break; 1481 } 1482 1483 forec_level_out: 1484 return 0; 1485 } 1486 1487 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu) 1488 { 1489 struct smu_11_0_dpm_context *dpm_context = 1490 smu->smu_dpm.dpm_context; 1491 struct smu_11_0_dpm_table *gfx_table = 1492 &dpm_context->dpm_tables.gfx_table; 1493 struct smu_11_0_dpm_table *mem_table = 1494 &dpm_context->dpm_tables.uclk_table; 1495 struct smu_11_0_dpm_table *soc_table = 1496 &dpm_context->dpm_tables.soc_table; 1497 struct smu_umd_pstate_table *pstate_table = 1498 &smu->pstate_table; 1499 struct amdgpu_device *adev = smu->adev; 1500 1501 pstate_table->gfxclk_pstate.min = gfx_table->min; 1502 pstate_table->gfxclk_pstate.peak = gfx_table->max; 1503 1504 pstate_table->uclk_pstate.min = mem_table->min; 1505 pstate_table->uclk_pstate.peak = mem_table->max; 1506 1507 pstate_table->socclk_pstate.min = soc_table->min; 1508 pstate_table->socclk_pstate.peak = soc_table->max; 1509 1510 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1511 case IP_VERSION(11, 0, 7): 1512 case IP_VERSION(11, 0, 11): 1513 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK; 1514 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK; 1515 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK; 1516 break; 1517 case IP_VERSION(11, 0, 12): 1518 pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK; 1519 pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK; 1520 pstate_table->socclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK; 1521 break; 1522 case IP_VERSION(11, 0, 13): 1523 pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK; 1524 pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK; 1525 pstate_table->socclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK; 1526 break; 1527 default: 1528 break; 1529 } 1530 1531 return 0; 1532 } 1533 1534 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu) 1535 { 1536 int ret = 0; 1537 uint32_t max_freq = 0; 1538 1539 /* Sienna_Cichlid do not support to change display num currently */ 1540 return 0; 1541 #if 0 1542 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL); 1543 if (ret) 1544 return ret; 1545 #endif 1546 1547 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1548 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq); 1549 if (ret) 1550 return ret; 1551 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq); 1552 if (ret) 1553 return ret; 1554 } 1555 1556 return ret; 1557 } 1558 1559 static int sienna_cichlid_display_config_changed(struct smu_context *smu) 1560 { 1561 int ret = 0; 1562 1563 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1564 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) && 1565 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 1566 #if 0 1567 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 1568 smu->display_config->num_display, 1569 NULL); 1570 #endif 1571 if (ret) 1572 return ret; 1573 } 1574 1575 return ret; 1576 } 1577 1578 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu) 1579 { 1580 int ret = 0; 1581 uint64_t feature_enabled; 1582 1583 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 1584 if (ret) 1585 return false; 1586 1587 return !!(feature_enabled & SMC_DPM_FEATURE); 1588 } 1589 1590 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu, 1591 uint32_t *speed) 1592 { 1593 if (!speed) 1594 return -EINVAL; 1595 1596 /* 1597 * For Sienna_Cichlid and later, the fan speed(rpm) reported 1598 * by pmfw is always trustable(even when the fan control feature 1599 * disabled or 0 RPM kicked in). 1600 */ 1601 return sienna_cichlid_get_smu_metrics_data(smu, 1602 METRICS_CURR_FANSPEED, 1603 speed); 1604 } 1605 1606 static int sienna_cichlid_get_fan_parameters(struct smu_context *smu) 1607 { 1608 uint16_t *table_member; 1609 1610 GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member); 1611 smu->fan_max_rpm = *table_member; 1612 1613 return 0; 1614 } 1615 1616 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf) 1617 { 1618 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; 1619 DpmActivityMonitorCoeffInt_t *activity_monitor = 1620 &(activity_monitor_external.DpmActivityMonitorCoeffInt); 1621 uint32_t i, size = 0; 1622 int16_t workload_type = 0; 1623 static const char *title[] = { 1624 "PROFILE_INDEX(NAME)", 1625 "CLOCK_TYPE(NAME)", 1626 "FPS", 1627 "MinFreqType", 1628 "MinActiveFreqType", 1629 "MinActiveFreq", 1630 "BoosterFreqType", 1631 "BoosterFreq", 1632 "PD_Data_limit_c", 1633 "PD_Data_error_coeff", 1634 "PD_Data_error_rate_coeff"}; 1635 int result = 0; 1636 1637 if (!buf) 1638 return -EINVAL; 1639 1640 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n", 1641 title[0], title[1], title[2], title[3], title[4], title[5], 1642 title[6], title[7], title[8], title[9], title[10]); 1643 1644 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 1645 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1646 workload_type = smu_cmn_to_asic_specific_index(smu, 1647 CMN2ASIC_MAPPING_WORKLOAD, 1648 i); 1649 if (workload_type < 0) 1650 return -EINVAL; 1651 1652 result = smu_cmn_update_table(smu, 1653 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type, 1654 (void *)(&activity_monitor_external), false); 1655 if (result) { 1656 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1657 return result; 1658 } 1659 1660 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n", 1661 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1662 1663 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1664 " ", 1665 0, 1666 "GFXCLK", 1667 activity_monitor->Gfx_FPS, 1668 activity_monitor->Gfx_MinFreqStep, 1669 activity_monitor->Gfx_MinActiveFreqType, 1670 activity_monitor->Gfx_MinActiveFreq, 1671 activity_monitor->Gfx_BoosterFreqType, 1672 activity_monitor->Gfx_BoosterFreq, 1673 activity_monitor->Gfx_PD_Data_limit_c, 1674 activity_monitor->Gfx_PD_Data_error_coeff, 1675 activity_monitor->Gfx_PD_Data_error_rate_coeff); 1676 1677 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1678 " ", 1679 1, 1680 "SOCCLK", 1681 activity_monitor->Fclk_FPS, 1682 activity_monitor->Fclk_MinFreqStep, 1683 activity_monitor->Fclk_MinActiveFreqType, 1684 activity_monitor->Fclk_MinActiveFreq, 1685 activity_monitor->Fclk_BoosterFreqType, 1686 activity_monitor->Fclk_BoosterFreq, 1687 activity_monitor->Fclk_PD_Data_limit_c, 1688 activity_monitor->Fclk_PD_Data_error_coeff, 1689 activity_monitor->Fclk_PD_Data_error_rate_coeff); 1690 1691 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1692 " ", 1693 2, 1694 "MEMCLK", 1695 activity_monitor->Mem_FPS, 1696 activity_monitor->Mem_MinFreqStep, 1697 activity_monitor->Mem_MinActiveFreqType, 1698 activity_monitor->Mem_MinActiveFreq, 1699 activity_monitor->Mem_BoosterFreqType, 1700 activity_monitor->Mem_BoosterFreq, 1701 activity_monitor->Mem_PD_Data_limit_c, 1702 activity_monitor->Mem_PD_Data_error_coeff, 1703 activity_monitor->Mem_PD_Data_error_rate_coeff); 1704 } 1705 1706 return size; 1707 } 1708 1709 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) 1710 { 1711 1712 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; 1713 DpmActivityMonitorCoeffInt_t *activity_monitor = 1714 &(activity_monitor_external.DpmActivityMonitorCoeffInt); 1715 int workload_type, ret = 0; 1716 1717 smu->power_profile_mode = input[size]; 1718 1719 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 1720 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode); 1721 return -EINVAL; 1722 } 1723 1724 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 1725 if (size != 10) 1726 return -EINVAL; 1727 1728 ret = smu_cmn_update_table(smu, 1729 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 1730 (void *)(&activity_monitor_external), false); 1731 if (ret) { 1732 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1733 return ret; 1734 } 1735 1736 switch (input[0]) { 1737 case 0: /* Gfxclk */ 1738 activity_monitor->Gfx_FPS = input[1]; 1739 activity_monitor->Gfx_MinFreqStep = input[2]; 1740 activity_monitor->Gfx_MinActiveFreqType = input[3]; 1741 activity_monitor->Gfx_MinActiveFreq = input[4]; 1742 activity_monitor->Gfx_BoosterFreqType = input[5]; 1743 activity_monitor->Gfx_BoosterFreq = input[6]; 1744 activity_monitor->Gfx_PD_Data_limit_c = input[7]; 1745 activity_monitor->Gfx_PD_Data_error_coeff = input[8]; 1746 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9]; 1747 break; 1748 case 1: /* Socclk */ 1749 activity_monitor->Fclk_FPS = input[1]; 1750 activity_monitor->Fclk_MinFreqStep = input[2]; 1751 activity_monitor->Fclk_MinActiveFreqType = input[3]; 1752 activity_monitor->Fclk_MinActiveFreq = input[4]; 1753 activity_monitor->Fclk_BoosterFreqType = input[5]; 1754 activity_monitor->Fclk_BoosterFreq = input[6]; 1755 activity_monitor->Fclk_PD_Data_limit_c = input[7]; 1756 activity_monitor->Fclk_PD_Data_error_coeff = input[8]; 1757 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9]; 1758 break; 1759 case 2: /* Memclk */ 1760 activity_monitor->Mem_FPS = input[1]; 1761 activity_monitor->Mem_MinFreqStep = input[2]; 1762 activity_monitor->Mem_MinActiveFreqType = input[3]; 1763 activity_monitor->Mem_MinActiveFreq = input[4]; 1764 activity_monitor->Mem_BoosterFreqType = input[5]; 1765 activity_monitor->Mem_BoosterFreq = input[6]; 1766 activity_monitor->Mem_PD_Data_limit_c = input[7]; 1767 activity_monitor->Mem_PD_Data_error_coeff = input[8]; 1768 activity_monitor->Mem_PD_Data_error_rate_coeff = input[9]; 1769 break; 1770 default: 1771 return -EINVAL; 1772 } 1773 1774 ret = smu_cmn_update_table(smu, 1775 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, 1776 (void *)(&activity_monitor_external), true); 1777 if (ret) { 1778 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); 1779 return ret; 1780 } 1781 } 1782 1783 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1784 workload_type = smu_cmn_to_asic_specific_index(smu, 1785 CMN2ASIC_MAPPING_WORKLOAD, 1786 smu->power_profile_mode); 1787 if (workload_type < 0) 1788 return -EINVAL; 1789 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, 1790 1 << workload_type, NULL); 1791 if (ret) 1792 dev_err(smu->adev->dev, "[%s] Failed to set work load mask!", __func__); 1793 1794 return ret; 1795 } 1796 1797 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu) 1798 { 1799 struct smu_clocks min_clocks = {0}; 1800 struct pp_display_clock_request clock_req; 1801 int ret = 0; 1802 1803 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; 1804 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; 1805 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; 1806 1807 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { 1808 clock_req.clock_type = amd_pp_dcef_clock; 1809 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; 1810 1811 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req); 1812 if (!ret) { 1813 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) { 1814 ret = smu_cmn_send_smc_msg_with_param(smu, 1815 SMU_MSG_SetMinDeepSleepDcefclk, 1816 min_clocks.dcef_clock_in_sr/100, 1817 NULL); 1818 if (ret) { 1819 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!"); 1820 return ret; 1821 } 1822 } 1823 } else { 1824 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!"); 1825 } 1826 } 1827 1828 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 1829 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); 1830 if (ret) { 1831 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__); 1832 return ret; 1833 } 1834 } 1835 1836 return 0; 1837 } 1838 1839 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu, 1840 struct pp_smu_wm_range_sets *clock_ranges) 1841 { 1842 Watermarks_t *table = smu->smu_table.watermarks_table; 1843 int ret = 0; 1844 int i; 1845 1846 if (clock_ranges) { 1847 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 1848 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 1849 return -EINVAL; 1850 1851 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 1852 table->WatermarkRow[WM_DCEFCLK][i].MinClock = 1853 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 1854 table->WatermarkRow[WM_DCEFCLK][i].MaxClock = 1855 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 1856 table->WatermarkRow[WM_DCEFCLK][i].MinUclk = 1857 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 1858 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk = 1859 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 1860 1861 table->WatermarkRow[WM_DCEFCLK][i].WmSetting = 1862 clock_ranges->reader_wm_sets[i].wm_inst; 1863 } 1864 1865 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 1866 table->WatermarkRow[WM_SOCCLK][i].MinClock = 1867 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 1868 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 1869 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 1870 table->WatermarkRow[WM_SOCCLK][i].MinUclk = 1871 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 1872 table->WatermarkRow[WM_SOCCLK][i].MaxUclk = 1873 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 1874 1875 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 1876 clock_ranges->writer_wm_sets[i].wm_inst; 1877 } 1878 1879 smu->watermarks_bitmap |= WATERMARKS_EXIST; 1880 } 1881 1882 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 1883 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 1884 ret = smu_cmn_write_watermarks_table(smu); 1885 if (ret) { 1886 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 1887 return ret; 1888 } 1889 smu->watermarks_bitmap |= WATERMARKS_LOADED; 1890 } 1891 1892 return 0; 1893 } 1894 1895 static int sienna_cichlid_read_sensor(struct smu_context *smu, 1896 enum amd_pp_sensors sensor, 1897 void *data, uint32_t *size) 1898 { 1899 int ret = 0; 1900 uint16_t *temp; 1901 struct amdgpu_device *adev = smu->adev; 1902 1903 if(!data || !size) 1904 return -EINVAL; 1905 1906 switch (sensor) { 1907 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 1908 GET_PPTABLE_MEMBER(FanMaximumRpm, &temp); 1909 *(uint16_t *)data = *temp; 1910 *size = 4; 1911 break; 1912 case AMDGPU_PP_SENSOR_MEM_LOAD: 1913 ret = sienna_cichlid_get_smu_metrics_data(smu, 1914 METRICS_AVERAGE_MEMACTIVITY, 1915 (uint32_t *)data); 1916 *size = 4; 1917 break; 1918 case AMDGPU_PP_SENSOR_GPU_LOAD: 1919 ret = sienna_cichlid_get_smu_metrics_data(smu, 1920 METRICS_AVERAGE_GFXACTIVITY, 1921 (uint32_t *)data); 1922 *size = 4; 1923 break; 1924 case AMDGPU_PP_SENSOR_GPU_AVG_POWER: 1925 ret = sienna_cichlid_get_smu_metrics_data(smu, 1926 METRICS_AVERAGE_SOCKETPOWER, 1927 (uint32_t *)data); 1928 *size = 4; 1929 break; 1930 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1931 ret = sienna_cichlid_get_smu_metrics_data(smu, 1932 METRICS_TEMPERATURE_HOTSPOT, 1933 (uint32_t *)data); 1934 *size = 4; 1935 break; 1936 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1937 ret = sienna_cichlid_get_smu_metrics_data(smu, 1938 METRICS_TEMPERATURE_EDGE, 1939 (uint32_t *)data); 1940 *size = 4; 1941 break; 1942 case AMDGPU_PP_SENSOR_MEM_TEMP: 1943 ret = sienna_cichlid_get_smu_metrics_data(smu, 1944 METRICS_TEMPERATURE_MEM, 1945 (uint32_t *)data); 1946 *size = 4; 1947 break; 1948 case AMDGPU_PP_SENSOR_GFX_MCLK: 1949 ret = sienna_cichlid_get_smu_metrics_data(smu, 1950 METRICS_CURR_UCLK, 1951 (uint32_t *)data); 1952 *(uint32_t *)data *= 100; 1953 *size = 4; 1954 break; 1955 case AMDGPU_PP_SENSOR_GFX_SCLK: 1956 ret = sienna_cichlid_get_smu_metrics_data(smu, 1957 METRICS_AVERAGE_GFXCLK, 1958 (uint32_t *)data); 1959 *(uint32_t *)data *= 100; 1960 *size = 4; 1961 break; 1962 case AMDGPU_PP_SENSOR_VDDGFX: 1963 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data); 1964 *size = 4; 1965 break; 1966 case AMDGPU_PP_SENSOR_SS_APU_SHARE: 1967 if (amdgpu_ip_version(adev, MP1_HWIP, 0) != 1968 IP_VERSION(11, 0, 7)) { 1969 ret = sienna_cichlid_get_smu_metrics_data(smu, 1970 METRICS_SS_APU_SHARE, (uint32_t *)data); 1971 *size = 4; 1972 } else { 1973 ret = -EOPNOTSUPP; 1974 } 1975 break; 1976 case AMDGPU_PP_SENSOR_SS_DGPU_SHARE: 1977 if (amdgpu_ip_version(adev, MP1_HWIP, 0) != 1978 IP_VERSION(11, 0, 7)) { 1979 ret = sienna_cichlid_get_smu_metrics_data(smu, 1980 METRICS_SS_DGPU_SHARE, (uint32_t *)data); 1981 *size = 4; 1982 } else { 1983 ret = -EOPNOTSUPP; 1984 } 1985 break; 1986 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER: 1987 default: 1988 ret = -EOPNOTSUPP; 1989 break; 1990 } 1991 1992 return ret; 1993 } 1994 1995 static void sienna_cichlid_get_unique_id(struct smu_context *smu) 1996 { 1997 struct amdgpu_device *adev = smu->adev; 1998 uint32_t upper32 = 0, lower32 = 0; 1999 2000 /* Only supported as of version 0.58.83.0 and only on Sienna Cichlid */ 2001 if (smu->smc_fw_version < 0x3A5300 || 2002 amdgpu_ip_version(smu->adev, MP1_HWIP, 0) != IP_VERSION(11, 0, 7)) 2003 return; 2004 2005 if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32)) 2006 goto out; 2007 if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32)) 2008 goto out; 2009 2010 out: 2011 2012 adev->unique_id = ((uint64_t)upper32 << 32) | lower32; 2013 } 2014 2015 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states) 2016 { 2017 uint32_t num_discrete_levels = 0; 2018 uint16_t *dpm_levels = NULL; 2019 uint16_t i = 0; 2020 struct smu_table_context *table_context = &smu->smu_table; 2021 DpmDescriptor_t *table_member1; 2022 uint16_t *table_member2; 2023 2024 if (!clocks_in_khz || !num_states || !table_context->driver_pptable) 2025 return -EINVAL; 2026 2027 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1); 2028 num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels; 2029 GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2); 2030 dpm_levels = table_member2; 2031 2032 if (num_discrete_levels == 0 || dpm_levels == NULL) 2033 return -EINVAL; 2034 2035 *num_states = num_discrete_levels; 2036 for (i = 0; i < num_discrete_levels; i++) { 2037 /* convert to khz */ 2038 *clocks_in_khz = (*dpm_levels) * 1000; 2039 clocks_in_khz++; 2040 dpm_levels++; 2041 } 2042 2043 return 0; 2044 } 2045 2046 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu, 2047 struct smu_temperature_range *range) 2048 { 2049 struct smu_table_context *table_context = &smu->smu_table; 2050 struct smu_11_0_7_powerplay_table *powerplay_table = 2051 table_context->power_play_table; 2052 uint16_t *table_member; 2053 uint16_t temp_edge, temp_hotspot, temp_mem; 2054 2055 if (!range) 2056 return -EINVAL; 2057 2058 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range)); 2059 2060 GET_PPTABLE_MEMBER(TemperatureLimit, &table_member); 2061 temp_edge = table_member[TEMP_EDGE]; 2062 temp_hotspot = table_member[TEMP_HOTSPOT]; 2063 temp_mem = table_member[TEMP_MEM]; 2064 2065 range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2066 range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) * 2067 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2068 range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2069 range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) * 2070 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2071 range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2072 range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)* 2073 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 2074 2075 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 2076 2077 return 0; 2078 } 2079 2080 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu, 2081 bool disable_memory_clock_switch) 2082 { 2083 int ret = 0; 2084 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks = 2085 (struct smu_11_0_max_sustainable_clocks *) 2086 smu->smu_table.max_sustainable_clocks; 2087 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal; 2088 uint32_t max_memory_clock = max_sustainable_clocks->uclock; 2089 2090 if(smu->disable_uclk_switch == disable_memory_clock_switch) 2091 return 0; 2092 2093 if(disable_memory_clock_switch) 2094 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0); 2095 else 2096 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0); 2097 2098 if(!ret) 2099 smu->disable_uclk_switch = disable_memory_clock_switch; 2100 2101 return ret; 2102 } 2103 2104 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu, 2105 uint8_t pcie_gen_cap, 2106 uint8_t pcie_width_cap) 2107 { 2108 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 2109 struct smu_11_0_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table; 2110 uint8_t *table_member1, *table_member2; 2111 uint8_t min_gen_speed, max_gen_speed; 2112 uint8_t min_lane_width, max_lane_width; 2113 uint32_t smu_pcie_arg; 2114 int ret, i; 2115 2116 GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1); 2117 GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2); 2118 2119 min_gen_speed = max_t(uint8_t, 0, table_member1[0]); 2120 max_gen_speed = min(pcie_gen_cap, table_member1[1]); 2121 min_gen_speed = min_gen_speed > max_gen_speed ? 2122 max_gen_speed : min_gen_speed; 2123 min_lane_width = max_t(uint8_t, 1, table_member2[0]); 2124 max_lane_width = min(pcie_width_cap, table_member2[1]); 2125 min_lane_width = min_lane_width > max_lane_width ? 2126 max_lane_width : min_lane_width; 2127 2128 if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) { 2129 pcie_table->pcie_gen[0] = max_gen_speed; 2130 pcie_table->pcie_lane[0] = max_lane_width; 2131 } else { 2132 pcie_table->pcie_gen[0] = min_gen_speed; 2133 pcie_table->pcie_lane[0] = min_lane_width; 2134 } 2135 pcie_table->pcie_gen[1] = max_gen_speed; 2136 pcie_table->pcie_lane[1] = max_lane_width; 2137 2138 for (i = 0; i < NUM_LINK_LEVELS; i++) { 2139 smu_pcie_arg = (i << 16 | 2140 pcie_table->pcie_gen[i] << 8 | 2141 pcie_table->pcie_lane[i]); 2142 2143 ret = smu_cmn_send_smc_msg_with_param(smu, 2144 SMU_MSG_OverridePcieParameters, 2145 smu_pcie_arg, 2146 NULL); 2147 if (ret) 2148 return ret; 2149 } 2150 2151 return 0; 2152 } 2153 2154 static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu, 2155 enum smu_clk_type clk_type, 2156 uint32_t *min, uint32_t *max) 2157 { 2158 return smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max); 2159 } 2160 2161 static void sienna_cichlid_dump_od_table(struct smu_context *smu, 2162 OverDriveTable_t *od_table) 2163 { 2164 struct amdgpu_device *adev = smu->adev; 2165 2166 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, 2167 od_table->GfxclkFmax); 2168 dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin, 2169 od_table->UclkFmax); 2170 2171 if (!((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 7)) && 2172 (smu->smc_fw_version < 0x003a2900))) 2173 dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset); 2174 } 2175 2176 static int sienna_cichlid_set_default_od_settings(struct smu_context *smu) 2177 { 2178 OverDriveTable_t *od_table = 2179 (OverDriveTable_t *)smu->smu_table.overdrive_table; 2180 OverDriveTable_t *boot_od_table = 2181 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table; 2182 OverDriveTable_t *user_od_table = 2183 (OverDriveTable_t *)smu->smu_table.user_overdrive_table; 2184 OverDriveTable_t user_od_table_bak; 2185 int ret = 0; 2186 2187 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 2188 0, (void *)boot_od_table, false); 2189 if (ret) { 2190 dev_err(smu->adev->dev, "Failed to get overdrive table!\n"); 2191 return ret; 2192 } 2193 2194 sienna_cichlid_dump_od_table(smu, boot_od_table); 2195 2196 memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t)); 2197 2198 /* 2199 * For S3/S4/Runpm resume, we need to setup those overdrive tables again, 2200 * but we have to preserve user defined values in "user_od_table". 2201 */ 2202 if (!smu->adev->in_suspend) { 2203 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t)); 2204 smu->user_dpm_profile.user_od = false; 2205 } else if (smu->user_dpm_profile.user_od) { 2206 memcpy(&user_od_table_bak, user_od_table, sizeof(OverDriveTable_t)); 2207 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t)); 2208 user_od_table->GfxclkFmin = user_od_table_bak.GfxclkFmin; 2209 user_od_table->GfxclkFmax = user_od_table_bak.GfxclkFmax; 2210 user_od_table->UclkFmin = user_od_table_bak.UclkFmin; 2211 user_od_table->UclkFmax = user_od_table_bak.UclkFmax; 2212 user_od_table->VddGfxOffset = user_od_table_bak.VddGfxOffset; 2213 } 2214 2215 return 0; 2216 } 2217 2218 static int sienna_cichlid_od_setting_check_range(struct smu_context *smu, 2219 struct smu_11_0_7_overdrive_table *od_table, 2220 enum SMU_11_0_7_ODSETTING_ID setting, 2221 uint32_t value) 2222 { 2223 if (value < od_table->min[setting]) { 2224 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n", 2225 setting, value, od_table->min[setting]); 2226 return -EINVAL; 2227 } 2228 if (value > od_table->max[setting]) { 2229 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n", 2230 setting, value, od_table->max[setting]); 2231 return -EINVAL; 2232 } 2233 2234 return 0; 2235 } 2236 2237 static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu, 2238 enum PP_OD_DPM_TABLE_COMMAND type, 2239 long input[], uint32_t size) 2240 { 2241 struct smu_table_context *table_context = &smu->smu_table; 2242 OverDriveTable_t *od_table = 2243 (OverDriveTable_t *)table_context->overdrive_table; 2244 struct smu_11_0_7_overdrive_table *od_settings = 2245 (struct smu_11_0_7_overdrive_table *)smu->od_settings; 2246 struct amdgpu_device *adev = smu->adev; 2247 enum SMU_11_0_7_ODSETTING_ID freq_setting; 2248 uint16_t *freq_ptr; 2249 int i, ret = 0; 2250 2251 if (!smu->od_enabled) { 2252 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n"); 2253 return -EINVAL; 2254 } 2255 2256 if (!smu->od_settings) { 2257 dev_err(smu->adev->dev, "OD board limits are not set!\n"); 2258 return -ENOENT; 2259 } 2260 2261 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) { 2262 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n"); 2263 return -EINVAL; 2264 } 2265 2266 switch (type) { 2267 case PP_OD_EDIT_SCLK_VDDC_TABLE: 2268 if (!sienna_cichlid_is_od_feature_supported(od_settings, 2269 SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) { 2270 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n"); 2271 return -ENOTSUPP; 2272 } 2273 2274 for (i = 0; i < size; i += 2) { 2275 if (i + 2 > size) { 2276 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size); 2277 return -EINVAL; 2278 } 2279 2280 switch (input[i]) { 2281 case 0: 2282 if (input[i + 1] > od_table->GfxclkFmax) { 2283 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n", 2284 input[i + 1], od_table->GfxclkFmax); 2285 return -EINVAL; 2286 } 2287 2288 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN; 2289 freq_ptr = &od_table->GfxclkFmin; 2290 break; 2291 2292 case 1: 2293 if (input[i + 1] < od_table->GfxclkFmin) { 2294 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n", 2295 input[i + 1], od_table->GfxclkFmin); 2296 return -EINVAL; 2297 } 2298 2299 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX; 2300 freq_ptr = &od_table->GfxclkFmax; 2301 break; 2302 2303 default: 2304 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]); 2305 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n"); 2306 return -EINVAL; 2307 } 2308 2309 ret = sienna_cichlid_od_setting_check_range(smu, od_settings, 2310 freq_setting, input[i + 1]); 2311 if (ret) 2312 return ret; 2313 2314 *freq_ptr = (uint16_t)input[i + 1]; 2315 } 2316 break; 2317 2318 case PP_OD_EDIT_MCLK_VDDC_TABLE: 2319 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) { 2320 dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n"); 2321 return -ENOTSUPP; 2322 } 2323 2324 for (i = 0; i < size; i += 2) { 2325 if (i + 2 > size) { 2326 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size); 2327 return -EINVAL; 2328 } 2329 2330 switch (input[i]) { 2331 case 0: 2332 if (input[i + 1] > od_table->UclkFmax) { 2333 dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n", 2334 input[i + 1], od_table->UclkFmax); 2335 return -EINVAL; 2336 } 2337 2338 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN; 2339 freq_ptr = &od_table->UclkFmin; 2340 break; 2341 2342 case 1: 2343 if (input[i + 1] < od_table->UclkFmin) { 2344 dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n", 2345 input[i + 1], od_table->UclkFmin); 2346 return -EINVAL; 2347 } 2348 2349 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX; 2350 freq_ptr = &od_table->UclkFmax; 2351 break; 2352 2353 default: 2354 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]); 2355 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n"); 2356 return -EINVAL; 2357 } 2358 2359 ret = sienna_cichlid_od_setting_check_range(smu, od_settings, 2360 freq_setting, input[i + 1]); 2361 if (ret) 2362 return ret; 2363 2364 *freq_ptr = (uint16_t)input[i + 1]; 2365 } 2366 break; 2367 2368 case PP_OD_RESTORE_DEFAULT_TABLE: 2369 memcpy(table_context->overdrive_table, 2370 table_context->boot_overdrive_table, 2371 sizeof(OverDriveTable_t)); 2372 fallthrough; 2373 2374 case PP_OD_COMMIT_DPM_TABLE: 2375 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) { 2376 sienna_cichlid_dump_od_table(smu, od_table); 2377 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true); 2378 if (ret) { 2379 dev_err(smu->adev->dev, "Failed to import overdrive table!\n"); 2380 return ret; 2381 } 2382 memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t)); 2383 smu->user_dpm_profile.user_od = true; 2384 2385 if (!memcmp(table_context->user_overdrive_table, 2386 table_context->boot_overdrive_table, 2387 sizeof(OverDriveTable_t))) 2388 smu->user_dpm_profile.user_od = false; 2389 } 2390 break; 2391 2392 case PP_OD_EDIT_VDDGFX_OFFSET: 2393 if (size != 1) { 2394 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size); 2395 return -EINVAL; 2396 } 2397 2398 /* 2399 * OD GFX Voltage Offset functionality is supported only by 58.41.0 2400 * and onwards SMU firmwares. 2401 */ 2402 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == 2403 IP_VERSION(11, 0, 7)) && 2404 (smu->smc_fw_version < 0x003a2900)) { 2405 dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported " 2406 "only by 58.41.0 and onwards SMU firmwares!\n"); 2407 return -EOPNOTSUPP; 2408 } 2409 2410 od_table->VddGfxOffset = (int16_t)input[0]; 2411 2412 sienna_cichlid_dump_od_table(smu, od_table); 2413 break; 2414 2415 default: 2416 return -ENOSYS; 2417 } 2418 2419 return ret; 2420 } 2421 2422 static int sienna_cichlid_restore_user_od_settings(struct smu_context *smu) 2423 { 2424 struct smu_table_context *table_context = &smu->smu_table; 2425 OverDriveTable_t *od_table = table_context->overdrive_table; 2426 OverDriveTable_t *user_od_table = table_context->user_overdrive_table; 2427 int res; 2428 2429 res = smu_v11_0_restore_user_od_settings(smu); 2430 if (res == 0) 2431 memcpy(od_table, user_od_table, sizeof(OverDriveTable_t)); 2432 2433 return res; 2434 } 2435 2436 static int sienna_cichlid_run_btc(struct smu_context *smu) 2437 { 2438 int res; 2439 2440 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); 2441 if (res) 2442 dev_err(smu->adev->dev, "RunDcBtc failed!\n"); 2443 2444 return res; 2445 } 2446 2447 static int sienna_cichlid_baco_enter(struct smu_context *smu) 2448 { 2449 struct amdgpu_device *adev = smu->adev; 2450 2451 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) 2452 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO); 2453 else 2454 return smu_v11_0_baco_enter(smu); 2455 } 2456 2457 static int sienna_cichlid_baco_exit(struct smu_context *smu) 2458 { 2459 struct amdgpu_device *adev = smu->adev; 2460 2461 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) { 2462 /* Wait for PMFW handling for the Dstate change */ 2463 msleep(10); 2464 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS); 2465 } else { 2466 return smu_v11_0_baco_exit(smu); 2467 } 2468 } 2469 2470 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu) 2471 { 2472 struct amdgpu_device *adev = smu->adev; 2473 uint32_t val; 2474 uint32_t smu_version; 2475 int ret; 2476 2477 /** 2478 * SRIOV env will not support SMU mode1 reset 2479 * PM FW support mode1 reset from 58.26 2480 */ 2481 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 2482 if (ret) 2483 return false; 2484 2485 if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00)) 2486 return false; 2487 2488 /** 2489 * mode1 reset relies on PSP, so we should check if 2490 * PSP is alive. 2491 */ 2492 val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 2493 return val != 0x0; 2494 } 2495 2496 static void beige_goby_dump_pptable(struct smu_context *smu) 2497 { 2498 struct smu_table_context *table_context = &smu->smu_table; 2499 PPTable_beige_goby_t *pptable = table_context->driver_pptable; 2500 int i; 2501 2502 dev_info(smu->adev->dev, "Dumped PPTable:\n"); 2503 2504 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version); 2505 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]); 2506 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]); 2507 2508 for (i = 0; i < PPT_THROTTLER_COUNT; i++) { 2509 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]); 2510 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]); 2511 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]); 2512 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]); 2513 } 2514 2515 for (i = 0; i < TDC_THROTTLER_COUNT; i++) { 2516 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]); 2517 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]); 2518 } 2519 2520 for (i = 0; i < TEMP_COUNT; i++) { 2521 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]); 2522 } 2523 2524 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit); 2525 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig); 2526 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]); 2527 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]); 2528 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]); 2529 2530 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit); 2531 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) { 2532 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]); 2533 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]); 2534 } 2535 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask); 2536 2537 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask); 2538 2539 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc); 2540 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx); 2541 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx); 2542 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc); 2543 2544 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin); 2545 2546 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold); 2547 2548 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx); 2549 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc); 2550 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx); 2551 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc); 2552 2553 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx); 2554 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc); 2555 2556 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin); 2557 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin); 2558 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp); 2559 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp); 2560 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp); 2561 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp); 2562 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis); 2563 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis); 2564 2565 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n" 2566 " .VoltageMode = 0x%02x\n" 2567 " .SnapToDiscrete = 0x%02x\n" 2568 " .NumDiscreteLevels = 0x%02x\n" 2569 " .padding = 0x%02x\n" 2570 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2571 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2572 " .SsFmin = 0x%04x\n" 2573 " .Padding_16 = 0x%04x\n", 2574 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode, 2575 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete, 2576 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels, 2577 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding, 2578 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m, 2579 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b, 2580 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a, 2581 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b, 2582 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c, 2583 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin, 2584 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16); 2585 2586 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n" 2587 " .VoltageMode = 0x%02x\n" 2588 " .SnapToDiscrete = 0x%02x\n" 2589 " .NumDiscreteLevels = 0x%02x\n" 2590 " .padding = 0x%02x\n" 2591 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2592 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2593 " .SsFmin = 0x%04x\n" 2594 " .Padding_16 = 0x%04x\n", 2595 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode, 2596 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete, 2597 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels, 2598 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding, 2599 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m, 2600 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b, 2601 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a, 2602 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b, 2603 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c, 2604 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin, 2605 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16); 2606 2607 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n" 2608 " .VoltageMode = 0x%02x\n" 2609 " .SnapToDiscrete = 0x%02x\n" 2610 " .NumDiscreteLevels = 0x%02x\n" 2611 " .padding = 0x%02x\n" 2612 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2613 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2614 " .SsFmin = 0x%04x\n" 2615 " .Padding_16 = 0x%04x\n", 2616 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode, 2617 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete, 2618 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels, 2619 pptable->DpmDescriptor[PPCLK_UCLK].Padding, 2620 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m, 2621 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b, 2622 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a, 2623 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b, 2624 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c, 2625 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin, 2626 pptable->DpmDescriptor[PPCLK_UCLK].Padding16); 2627 2628 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n" 2629 " .VoltageMode = 0x%02x\n" 2630 " .SnapToDiscrete = 0x%02x\n" 2631 " .NumDiscreteLevels = 0x%02x\n" 2632 " .padding = 0x%02x\n" 2633 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2634 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2635 " .SsFmin = 0x%04x\n" 2636 " .Padding_16 = 0x%04x\n", 2637 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode, 2638 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete, 2639 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels, 2640 pptable->DpmDescriptor[PPCLK_FCLK].Padding, 2641 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m, 2642 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b, 2643 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a, 2644 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b, 2645 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c, 2646 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin, 2647 pptable->DpmDescriptor[PPCLK_FCLK].Padding16); 2648 2649 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n" 2650 " .VoltageMode = 0x%02x\n" 2651 " .SnapToDiscrete = 0x%02x\n" 2652 " .NumDiscreteLevels = 0x%02x\n" 2653 " .padding = 0x%02x\n" 2654 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2655 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2656 " .SsFmin = 0x%04x\n" 2657 " .Padding_16 = 0x%04x\n", 2658 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode, 2659 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete, 2660 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels, 2661 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding, 2662 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m, 2663 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b, 2664 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a, 2665 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b, 2666 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c, 2667 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin, 2668 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16); 2669 2670 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n" 2671 " .VoltageMode = 0x%02x\n" 2672 " .SnapToDiscrete = 0x%02x\n" 2673 " .NumDiscreteLevels = 0x%02x\n" 2674 " .padding = 0x%02x\n" 2675 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2676 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2677 " .SsFmin = 0x%04x\n" 2678 " .Padding_16 = 0x%04x\n", 2679 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode, 2680 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete, 2681 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels, 2682 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding, 2683 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m, 2684 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b, 2685 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a, 2686 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b, 2687 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c, 2688 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin, 2689 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16); 2690 2691 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n" 2692 " .VoltageMode = 0x%02x\n" 2693 " .SnapToDiscrete = 0x%02x\n" 2694 " .NumDiscreteLevels = 0x%02x\n" 2695 " .padding = 0x%02x\n" 2696 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2697 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2698 " .SsFmin = 0x%04x\n" 2699 " .Padding_16 = 0x%04x\n", 2700 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode, 2701 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete, 2702 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels, 2703 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding, 2704 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m, 2705 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b, 2706 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a, 2707 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b, 2708 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c, 2709 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin, 2710 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16); 2711 2712 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n" 2713 " .VoltageMode = 0x%02x\n" 2714 " .SnapToDiscrete = 0x%02x\n" 2715 " .NumDiscreteLevels = 0x%02x\n" 2716 " .padding = 0x%02x\n" 2717 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 2718 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 2719 " .SsFmin = 0x%04x\n" 2720 " .Padding_16 = 0x%04x\n", 2721 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode, 2722 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete, 2723 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels, 2724 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding, 2725 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m, 2726 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b, 2727 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a, 2728 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b, 2729 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c, 2730 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin, 2731 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16); 2732 2733 dev_info(smu->adev->dev, "FreqTableGfx\n"); 2734 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) 2735 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]); 2736 2737 dev_info(smu->adev->dev, "FreqTableVclk\n"); 2738 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++) 2739 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]); 2740 2741 dev_info(smu->adev->dev, "FreqTableDclk\n"); 2742 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++) 2743 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]); 2744 2745 dev_info(smu->adev->dev, "FreqTableSocclk\n"); 2746 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) 2747 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]); 2748 2749 dev_info(smu->adev->dev, "FreqTableUclk\n"); 2750 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2751 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]); 2752 2753 dev_info(smu->adev->dev, "FreqTableFclk\n"); 2754 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) 2755 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]); 2756 2757 dev_info(smu->adev->dev, "DcModeMaxFreq\n"); 2758 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]); 2759 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]); 2760 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]); 2761 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]); 2762 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]); 2763 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]); 2764 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]); 2765 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]); 2766 2767 dev_info(smu->adev->dev, "FreqTableUclkDiv\n"); 2768 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2769 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]); 2770 2771 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq); 2772 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding); 2773 2774 dev_info(smu->adev->dev, "Mp0clkFreq\n"); 2775 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) 2776 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]); 2777 2778 dev_info(smu->adev->dev, "Mp0DpmVoltage\n"); 2779 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) 2780 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]); 2781 2782 dev_info(smu->adev->dev, "MemVddciVoltage\n"); 2783 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2784 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]); 2785 2786 dev_info(smu->adev->dev, "MemMvddVoltage\n"); 2787 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2788 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]); 2789 2790 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry); 2791 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit); 2792 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle); 2793 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource); 2794 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding); 2795 2796 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask); 2797 2798 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask); 2799 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask); 2800 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]); 2801 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow); 2802 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]); 2803 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]); 2804 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]); 2805 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]); 2806 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt); 2807 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt); 2808 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt); 2809 2810 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage); 2811 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime); 2812 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime); 2813 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum); 2814 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis); 2815 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout); 2816 2817 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]); 2818 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]); 2819 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]); 2820 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]); 2821 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]); 2822 2823 dev_info(smu->adev->dev, "FlopsPerByteTable\n"); 2824 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++) 2825 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]); 2826 2827 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv); 2828 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]); 2829 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]); 2830 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]); 2831 2832 dev_info(smu->adev->dev, "UclkDpmPstates\n"); 2833 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 2834 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]); 2835 2836 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n"); 2837 dev_info(smu->adev->dev, " .Fmin = 0x%x\n", 2838 pptable->UclkDpmSrcFreqRange.Fmin); 2839 dev_info(smu->adev->dev, " .Fmax = 0x%x\n", 2840 pptable->UclkDpmSrcFreqRange.Fmax); 2841 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n"); 2842 dev_info(smu->adev->dev, " .Fmin = 0x%x\n", 2843 pptable->UclkDpmTargFreqRange.Fmin); 2844 dev_info(smu->adev->dev, " .Fmax = 0x%x\n", 2845 pptable->UclkDpmTargFreqRange.Fmax); 2846 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq); 2847 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding); 2848 2849 dev_info(smu->adev->dev, "PcieGenSpeed\n"); 2850 for (i = 0; i < NUM_LINK_LEVELS; i++) 2851 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]); 2852 2853 dev_info(smu->adev->dev, "PcieLaneCount\n"); 2854 for (i = 0; i < NUM_LINK_LEVELS; i++) 2855 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]); 2856 2857 dev_info(smu->adev->dev, "LclkFreq\n"); 2858 for (i = 0; i < NUM_LINK_LEVELS; i++) 2859 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]); 2860 2861 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp); 2862 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp); 2863 2864 dev_info(smu->adev->dev, "FanGain\n"); 2865 for (i = 0; i < TEMP_COUNT; i++) 2866 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]); 2867 2868 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin); 2869 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm); 2870 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm); 2871 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm); 2872 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm); 2873 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature); 2874 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk); 2875 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16); 2876 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect); 2877 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding); 2878 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable); 2879 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev); 2880 2881 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta); 2882 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta); 2883 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta); 2884 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved); 2885 2886 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]); 2887 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]); 2888 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect); 2889 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs); 2890 2891 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", 2892 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a, 2893 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b, 2894 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c); 2895 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", 2896 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a, 2897 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b, 2898 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c); 2899 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n", 2900 pptable->dBtcGbGfxPll.a, 2901 pptable->dBtcGbGfxPll.b, 2902 pptable->dBtcGbGfxPll.c); 2903 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n", 2904 pptable->dBtcGbGfxDfll.a, 2905 pptable->dBtcGbGfxDfll.b, 2906 pptable->dBtcGbGfxDfll.c); 2907 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n", 2908 pptable->dBtcGbSoc.a, 2909 pptable->dBtcGbSoc.b, 2910 pptable->dBtcGbSoc.c); 2911 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n", 2912 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m, 2913 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b); 2914 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n", 2915 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m, 2916 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b); 2917 2918 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n"); 2919 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) { 2920 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n", 2921 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]); 2922 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n", 2923 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]); 2924 } 2925 2926 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", 2927 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a, 2928 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b, 2929 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c); 2930 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", 2931 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a, 2932 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b, 2933 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c); 2934 2935 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]); 2936 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]); 2937 2938 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]); 2939 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]); 2940 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]); 2941 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]); 2942 2943 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]); 2944 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]); 2945 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]); 2946 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]); 2947 2948 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]); 2949 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]); 2950 2951 dev_info(smu->adev->dev, "XgmiDpmPstates\n"); 2952 for (i = 0; i < NUM_XGMI_LEVELS; i++) 2953 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]); 2954 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]); 2955 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]); 2956 2957 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides); 2958 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n", 2959 pptable->ReservedEquation0.a, 2960 pptable->ReservedEquation0.b, 2961 pptable->ReservedEquation0.c); 2962 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n", 2963 pptable->ReservedEquation1.a, 2964 pptable->ReservedEquation1.b, 2965 pptable->ReservedEquation1.c); 2966 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n", 2967 pptable->ReservedEquation2.a, 2968 pptable->ReservedEquation2.b, 2969 pptable->ReservedEquation2.c); 2970 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n", 2971 pptable->ReservedEquation3.a, 2972 pptable->ReservedEquation3.b, 2973 pptable->ReservedEquation3.c); 2974 2975 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]); 2976 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]); 2977 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]); 2978 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]); 2979 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]); 2980 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]); 2981 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]); 2982 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]); 2983 2984 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]); 2985 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]); 2986 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]); 2987 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]); 2988 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]); 2989 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]); 2990 2991 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) { 2992 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i); 2993 dev_info(smu->adev->dev, " .Enabled = 0x%x\n", 2994 pptable->I2cControllers[i].Enabled); 2995 dev_info(smu->adev->dev, " .Speed = 0x%x\n", 2996 pptable->I2cControllers[i].Speed); 2997 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n", 2998 pptable->I2cControllers[i].SlaveAddress); 2999 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n", 3000 pptable->I2cControllers[i].ControllerPort); 3001 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n", 3002 pptable->I2cControllers[i].ControllerName); 3003 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n", 3004 pptable->I2cControllers[i].ThermalThrotter); 3005 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n", 3006 pptable->I2cControllers[i].I2cProtocol); 3007 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n", 3008 pptable->I2cControllers[i].PaddingConfig); 3009 } 3010 3011 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl); 3012 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda); 3013 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr); 3014 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]); 3015 3016 dev_info(smu->adev->dev, "Board Parameters:\n"); 3017 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping); 3018 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping); 3019 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping); 3020 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping); 3021 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask); 3022 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask); 3023 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask); 3024 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask); 3025 3026 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent); 3027 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset); 3028 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx); 3029 3030 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent); 3031 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset); 3032 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc); 3033 3034 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent); 3035 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset); 3036 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0); 3037 3038 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent); 3039 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset); 3040 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1); 3041 3042 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio); 3043 3044 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio); 3045 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity); 3046 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio); 3047 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity); 3048 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio); 3049 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity); 3050 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio); 3051 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity); 3052 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0); 3053 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1); 3054 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2); 3055 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask); 3056 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie); 3057 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError); 3058 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]); 3059 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]); 3060 3061 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled); 3062 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent); 3063 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq); 3064 3065 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled); 3066 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent); 3067 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq); 3068 3069 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding); 3070 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq); 3071 3072 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled); 3073 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent); 3074 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq); 3075 3076 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled); 3077 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth); 3078 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]); 3079 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]); 3080 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]); 3081 3082 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower); 3083 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding); 3084 3085 dev_info(smu->adev->dev, "XgmiLinkSpeed\n"); 3086 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3087 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]); 3088 dev_info(smu->adev->dev, "XgmiLinkWidth\n"); 3089 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3090 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]); 3091 dev_info(smu->adev->dev, "XgmiFclkFreq\n"); 3092 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3093 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]); 3094 dev_info(smu->adev->dev, "XgmiSocVoltage\n"); 3095 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3096 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]); 3097 3098 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled); 3099 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled); 3100 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]); 3101 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]); 3102 3103 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]); 3104 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]); 3105 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]); 3106 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]); 3107 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]); 3108 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]); 3109 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]); 3110 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]); 3111 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]); 3112 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]); 3113 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]); 3114 3115 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]); 3116 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]); 3117 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]); 3118 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]); 3119 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]); 3120 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]); 3121 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]); 3122 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]); 3123 } 3124 3125 static void sienna_cichlid_dump_pptable(struct smu_context *smu) 3126 { 3127 struct smu_table_context *table_context = &smu->smu_table; 3128 PPTable_t *pptable = table_context->driver_pptable; 3129 int i; 3130 3131 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == 3132 IP_VERSION(11, 0, 13)) { 3133 beige_goby_dump_pptable(smu); 3134 return; 3135 } 3136 3137 dev_info(smu->adev->dev, "Dumped PPTable:\n"); 3138 3139 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version); 3140 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]); 3141 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]); 3142 3143 for (i = 0; i < PPT_THROTTLER_COUNT; i++) { 3144 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]); 3145 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]); 3146 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]); 3147 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]); 3148 } 3149 3150 for (i = 0; i < TDC_THROTTLER_COUNT; i++) { 3151 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]); 3152 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]); 3153 } 3154 3155 for (i = 0; i < TEMP_COUNT; i++) { 3156 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]); 3157 } 3158 3159 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit); 3160 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig); 3161 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]); 3162 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]); 3163 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]); 3164 3165 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit); 3166 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) { 3167 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]); 3168 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]); 3169 } 3170 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask); 3171 3172 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask); 3173 3174 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc); 3175 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx); 3176 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx); 3177 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc); 3178 3179 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin); 3180 dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin); 3181 3182 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold); 3183 dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]); 3184 dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]); 3185 dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]); 3186 3187 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx); 3188 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc); 3189 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx); 3190 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc); 3191 3192 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx); 3193 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc); 3194 3195 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin); 3196 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin); 3197 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp); 3198 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp); 3199 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp); 3200 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp); 3201 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis); 3202 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis); 3203 3204 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n" 3205 " .VoltageMode = 0x%02x\n" 3206 " .SnapToDiscrete = 0x%02x\n" 3207 " .NumDiscreteLevels = 0x%02x\n" 3208 " .padding = 0x%02x\n" 3209 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3210 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3211 " .SsFmin = 0x%04x\n" 3212 " .Padding_16 = 0x%04x\n", 3213 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode, 3214 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete, 3215 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels, 3216 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding, 3217 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m, 3218 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b, 3219 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a, 3220 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b, 3221 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c, 3222 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin, 3223 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16); 3224 3225 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n" 3226 " .VoltageMode = 0x%02x\n" 3227 " .SnapToDiscrete = 0x%02x\n" 3228 " .NumDiscreteLevels = 0x%02x\n" 3229 " .padding = 0x%02x\n" 3230 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3231 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3232 " .SsFmin = 0x%04x\n" 3233 " .Padding_16 = 0x%04x\n", 3234 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode, 3235 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete, 3236 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels, 3237 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding, 3238 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m, 3239 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b, 3240 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a, 3241 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b, 3242 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c, 3243 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin, 3244 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16); 3245 3246 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n" 3247 " .VoltageMode = 0x%02x\n" 3248 " .SnapToDiscrete = 0x%02x\n" 3249 " .NumDiscreteLevels = 0x%02x\n" 3250 " .padding = 0x%02x\n" 3251 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3252 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3253 " .SsFmin = 0x%04x\n" 3254 " .Padding_16 = 0x%04x\n", 3255 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode, 3256 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete, 3257 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels, 3258 pptable->DpmDescriptor[PPCLK_UCLK].Padding, 3259 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m, 3260 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b, 3261 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a, 3262 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b, 3263 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c, 3264 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin, 3265 pptable->DpmDescriptor[PPCLK_UCLK].Padding16); 3266 3267 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n" 3268 " .VoltageMode = 0x%02x\n" 3269 " .SnapToDiscrete = 0x%02x\n" 3270 " .NumDiscreteLevels = 0x%02x\n" 3271 " .padding = 0x%02x\n" 3272 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3273 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3274 " .SsFmin = 0x%04x\n" 3275 " .Padding_16 = 0x%04x\n", 3276 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode, 3277 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete, 3278 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels, 3279 pptable->DpmDescriptor[PPCLK_FCLK].Padding, 3280 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m, 3281 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b, 3282 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a, 3283 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b, 3284 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c, 3285 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin, 3286 pptable->DpmDescriptor[PPCLK_FCLK].Padding16); 3287 3288 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n" 3289 " .VoltageMode = 0x%02x\n" 3290 " .SnapToDiscrete = 0x%02x\n" 3291 " .NumDiscreteLevels = 0x%02x\n" 3292 " .padding = 0x%02x\n" 3293 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3294 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3295 " .SsFmin = 0x%04x\n" 3296 " .Padding_16 = 0x%04x\n", 3297 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode, 3298 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete, 3299 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels, 3300 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding, 3301 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m, 3302 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b, 3303 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a, 3304 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b, 3305 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c, 3306 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin, 3307 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16); 3308 3309 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n" 3310 " .VoltageMode = 0x%02x\n" 3311 " .SnapToDiscrete = 0x%02x\n" 3312 " .NumDiscreteLevels = 0x%02x\n" 3313 " .padding = 0x%02x\n" 3314 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3315 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3316 " .SsFmin = 0x%04x\n" 3317 " .Padding_16 = 0x%04x\n", 3318 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode, 3319 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete, 3320 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels, 3321 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding, 3322 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m, 3323 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b, 3324 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a, 3325 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b, 3326 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c, 3327 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin, 3328 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16); 3329 3330 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n" 3331 " .VoltageMode = 0x%02x\n" 3332 " .SnapToDiscrete = 0x%02x\n" 3333 " .NumDiscreteLevels = 0x%02x\n" 3334 " .padding = 0x%02x\n" 3335 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3336 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3337 " .SsFmin = 0x%04x\n" 3338 " .Padding_16 = 0x%04x\n", 3339 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode, 3340 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete, 3341 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels, 3342 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding, 3343 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m, 3344 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b, 3345 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a, 3346 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b, 3347 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c, 3348 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin, 3349 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16); 3350 3351 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n" 3352 " .VoltageMode = 0x%02x\n" 3353 " .SnapToDiscrete = 0x%02x\n" 3354 " .NumDiscreteLevels = 0x%02x\n" 3355 " .padding = 0x%02x\n" 3356 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 3357 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 3358 " .SsFmin = 0x%04x\n" 3359 " .Padding_16 = 0x%04x\n", 3360 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode, 3361 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete, 3362 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels, 3363 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding, 3364 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m, 3365 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b, 3366 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a, 3367 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b, 3368 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c, 3369 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin, 3370 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16); 3371 3372 dev_info(smu->adev->dev, "FreqTableGfx\n"); 3373 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) 3374 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]); 3375 3376 dev_info(smu->adev->dev, "FreqTableVclk\n"); 3377 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++) 3378 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]); 3379 3380 dev_info(smu->adev->dev, "FreqTableDclk\n"); 3381 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++) 3382 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]); 3383 3384 dev_info(smu->adev->dev, "FreqTableSocclk\n"); 3385 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) 3386 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]); 3387 3388 dev_info(smu->adev->dev, "FreqTableUclk\n"); 3389 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 3390 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]); 3391 3392 dev_info(smu->adev->dev, "FreqTableFclk\n"); 3393 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) 3394 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]); 3395 3396 dev_info(smu->adev->dev, "DcModeMaxFreq\n"); 3397 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]); 3398 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]); 3399 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]); 3400 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]); 3401 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]); 3402 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]); 3403 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]); 3404 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]); 3405 3406 dev_info(smu->adev->dev, "FreqTableUclkDiv\n"); 3407 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 3408 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]); 3409 3410 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq); 3411 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding); 3412 3413 dev_info(smu->adev->dev, "Mp0clkFreq\n"); 3414 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) 3415 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]); 3416 3417 dev_info(smu->adev->dev, "Mp0DpmVoltage\n"); 3418 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) 3419 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]); 3420 3421 dev_info(smu->adev->dev, "MemVddciVoltage\n"); 3422 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 3423 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]); 3424 3425 dev_info(smu->adev->dev, "MemMvddVoltage\n"); 3426 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 3427 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]); 3428 3429 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry); 3430 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit); 3431 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle); 3432 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource); 3433 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding); 3434 3435 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask); 3436 3437 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask); 3438 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask); 3439 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]); 3440 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow); 3441 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]); 3442 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]); 3443 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]); 3444 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]); 3445 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt); 3446 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt); 3447 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt); 3448 3449 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage); 3450 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime); 3451 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime); 3452 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum); 3453 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis); 3454 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout); 3455 3456 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]); 3457 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]); 3458 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]); 3459 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]); 3460 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]); 3461 3462 dev_info(smu->adev->dev, "FlopsPerByteTable\n"); 3463 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++) 3464 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]); 3465 3466 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv); 3467 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]); 3468 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]); 3469 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]); 3470 3471 dev_info(smu->adev->dev, "UclkDpmPstates\n"); 3472 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 3473 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]); 3474 3475 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n"); 3476 dev_info(smu->adev->dev, " .Fmin = 0x%x\n", 3477 pptable->UclkDpmSrcFreqRange.Fmin); 3478 dev_info(smu->adev->dev, " .Fmax = 0x%x\n", 3479 pptable->UclkDpmSrcFreqRange.Fmax); 3480 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n"); 3481 dev_info(smu->adev->dev, " .Fmin = 0x%x\n", 3482 pptable->UclkDpmTargFreqRange.Fmin); 3483 dev_info(smu->adev->dev, " .Fmax = 0x%x\n", 3484 pptable->UclkDpmTargFreqRange.Fmax); 3485 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq); 3486 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding); 3487 3488 dev_info(smu->adev->dev, "PcieGenSpeed\n"); 3489 for (i = 0; i < NUM_LINK_LEVELS; i++) 3490 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]); 3491 3492 dev_info(smu->adev->dev, "PcieLaneCount\n"); 3493 for (i = 0; i < NUM_LINK_LEVELS; i++) 3494 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]); 3495 3496 dev_info(smu->adev->dev, "LclkFreq\n"); 3497 for (i = 0; i < NUM_LINK_LEVELS; i++) 3498 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]); 3499 3500 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp); 3501 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp); 3502 3503 dev_info(smu->adev->dev, "FanGain\n"); 3504 for (i = 0; i < TEMP_COUNT; i++) 3505 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]); 3506 3507 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin); 3508 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm); 3509 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm); 3510 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm); 3511 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm); 3512 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature); 3513 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk); 3514 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16); 3515 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect); 3516 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding); 3517 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable); 3518 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev); 3519 3520 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta); 3521 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta); 3522 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta); 3523 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved); 3524 3525 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]); 3526 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]); 3527 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect); 3528 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs); 3529 3530 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", 3531 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a, 3532 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b, 3533 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c); 3534 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", 3535 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a, 3536 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b, 3537 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c); 3538 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n", 3539 pptable->dBtcGbGfxPll.a, 3540 pptable->dBtcGbGfxPll.b, 3541 pptable->dBtcGbGfxPll.c); 3542 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n", 3543 pptable->dBtcGbGfxDfll.a, 3544 pptable->dBtcGbGfxDfll.b, 3545 pptable->dBtcGbGfxDfll.c); 3546 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n", 3547 pptable->dBtcGbSoc.a, 3548 pptable->dBtcGbSoc.b, 3549 pptable->dBtcGbSoc.c); 3550 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n", 3551 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m, 3552 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b); 3553 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n", 3554 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m, 3555 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b); 3556 3557 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n"); 3558 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) { 3559 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n", 3560 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]); 3561 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n", 3562 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]); 3563 } 3564 3565 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", 3566 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a, 3567 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b, 3568 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c); 3569 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", 3570 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a, 3571 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b, 3572 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c); 3573 3574 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]); 3575 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]); 3576 3577 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]); 3578 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]); 3579 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]); 3580 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]); 3581 3582 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]); 3583 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]); 3584 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]); 3585 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]); 3586 3587 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]); 3588 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]); 3589 3590 dev_info(smu->adev->dev, "XgmiDpmPstates\n"); 3591 for (i = 0; i < NUM_XGMI_LEVELS; i++) 3592 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]); 3593 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]); 3594 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]); 3595 3596 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides); 3597 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n", 3598 pptable->ReservedEquation0.a, 3599 pptable->ReservedEquation0.b, 3600 pptable->ReservedEquation0.c); 3601 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n", 3602 pptable->ReservedEquation1.a, 3603 pptable->ReservedEquation1.b, 3604 pptable->ReservedEquation1.c); 3605 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n", 3606 pptable->ReservedEquation2.a, 3607 pptable->ReservedEquation2.b, 3608 pptable->ReservedEquation2.c); 3609 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n", 3610 pptable->ReservedEquation3.a, 3611 pptable->ReservedEquation3.b, 3612 pptable->ReservedEquation3.c); 3613 3614 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]); 3615 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]); 3616 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]); 3617 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]); 3618 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]); 3619 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]); 3620 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]); 3621 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]); 3622 3623 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]); 3624 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]); 3625 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]); 3626 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]); 3627 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]); 3628 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]); 3629 3630 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) { 3631 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i); 3632 dev_info(smu->adev->dev, " .Enabled = 0x%x\n", 3633 pptable->I2cControllers[i].Enabled); 3634 dev_info(smu->adev->dev, " .Speed = 0x%x\n", 3635 pptable->I2cControllers[i].Speed); 3636 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n", 3637 pptable->I2cControllers[i].SlaveAddress); 3638 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n", 3639 pptable->I2cControllers[i].ControllerPort); 3640 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n", 3641 pptable->I2cControllers[i].ControllerName); 3642 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n", 3643 pptable->I2cControllers[i].ThermalThrotter); 3644 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n", 3645 pptable->I2cControllers[i].I2cProtocol); 3646 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n", 3647 pptable->I2cControllers[i].PaddingConfig); 3648 } 3649 3650 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl); 3651 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda); 3652 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr); 3653 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]); 3654 3655 dev_info(smu->adev->dev, "Board Parameters:\n"); 3656 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping); 3657 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping); 3658 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping); 3659 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping); 3660 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask); 3661 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask); 3662 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask); 3663 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask); 3664 3665 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent); 3666 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset); 3667 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx); 3668 3669 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent); 3670 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset); 3671 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc); 3672 3673 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent); 3674 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset); 3675 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0); 3676 3677 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent); 3678 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset); 3679 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1); 3680 3681 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio); 3682 3683 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio); 3684 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity); 3685 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio); 3686 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity); 3687 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio); 3688 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity); 3689 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio); 3690 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity); 3691 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0); 3692 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1); 3693 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2); 3694 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask); 3695 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie); 3696 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError); 3697 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]); 3698 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]); 3699 3700 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled); 3701 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent); 3702 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq); 3703 3704 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled); 3705 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent); 3706 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq); 3707 3708 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding); 3709 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq); 3710 3711 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled); 3712 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent); 3713 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq); 3714 3715 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled); 3716 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth); 3717 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]); 3718 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]); 3719 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]); 3720 3721 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower); 3722 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding); 3723 3724 dev_info(smu->adev->dev, "XgmiLinkSpeed\n"); 3725 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3726 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]); 3727 dev_info(smu->adev->dev, "XgmiLinkWidth\n"); 3728 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3729 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]); 3730 dev_info(smu->adev->dev, "XgmiFclkFreq\n"); 3731 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3732 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]); 3733 dev_info(smu->adev->dev, "XgmiSocVoltage\n"); 3734 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 3735 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]); 3736 3737 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled); 3738 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled); 3739 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]); 3740 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]); 3741 3742 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]); 3743 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]); 3744 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]); 3745 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]); 3746 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]); 3747 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]); 3748 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]); 3749 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]); 3750 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]); 3751 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]); 3752 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]); 3753 3754 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]); 3755 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]); 3756 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]); 3757 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]); 3758 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]); 3759 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]); 3760 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]); 3761 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]); 3762 } 3763 3764 static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap, 3765 struct i2c_msg *msg, int num_msgs) 3766 { 3767 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap); 3768 struct amdgpu_device *adev = smu_i2c->adev; 3769 struct smu_context *smu = adev->powerplay.pp_handle; 3770 struct smu_table_context *smu_table = &smu->smu_table; 3771 struct smu_table *table = &smu_table->driver_table; 3772 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; 3773 int i, j, r, c; 3774 u16 dir; 3775 3776 if (!adev->pm.dpm_enabled) 3777 return -EBUSY; 3778 3779 req = kzalloc(sizeof(*req), GFP_KERNEL); 3780 if (!req) 3781 return -ENOMEM; 3782 3783 req->I2CcontrollerPort = smu_i2c->port; 3784 req->I2CSpeed = I2C_SPEED_FAST_400K; 3785 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ 3786 dir = msg[0].flags & I2C_M_RD; 3787 3788 for (c = i = 0; i < num_msgs; i++) { 3789 for (j = 0; j < msg[i].len; j++, c++) { 3790 SwI2cCmd_t *cmd = &req->SwI2cCmds[c]; 3791 3792 if (!(msg[i].flags & I2C_M_RD)) { 3793 /* write */ 3794 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK; 3795 cmd->ReadWriteData = msg[i].buf[j]; 3796 } 3797 3798 if ((dir ^ msg[i].flags) & I2C_M_RD) { 3799 /* The direction changes. 3800 */ 3801 dir = msg[i].flags & I2C_M_RD; 3802 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK; 3803 } 3804 3805 req->NumCmds++; 3806 3807 /* 3808 * Insert STOP if we are at the last byte of either last 3809 * message for the transaction or the client explicitly 3810 * requires a STOP at this particular message. 3811 */ 3812 if ((j == msg[i].len - 1) && 3813 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) { 3814 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK; 3815 cmd->CmdConfig |= CMDCONFIG_STOP_MASK; 3816 } 3817 } 3818 } 3819 mutex_lock(&adev->pm.mutex); 3820 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 3821 if (r) 3822 goto fail; 3823 3824 for (c = i = 0; i < num_msgs; i++) { 3825 if (!(msg[i].flags & I2C_M_RD)) { 3826 c += msg[i].len; 3827 continue; 3828 } 3829 for (j = 0; j < msg[i].len; j++, c++) { 3830 SwI2cCmd_t *cmd = &res->SwI2cCmds[c]; 3831 3832 msg[i].buf[j] = cmd->ReadWriteData; 3833 } 3834 } 3835 r = num_msgs; 3836 fail: 3837 mutex_unlock(&adev->pm.mutex); 3838 kfree(req); 3839 return r; 3840 } 3841 3842 static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap) 3843 { 3844 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 3845 } 3846 3847 3848 static const struct i2c_algorithm sienna_cichlid_i2c_algo = { 3849 .master_xfer = sienna_cichlid_i2c_xfer, 3850 .functionality = sienna_cichlid_i2c_func, 3851 }; 3852 3853 static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = { 3854 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN, 3855 .max_read_len = MAX_SW_I2C_COMMANDS, 3856 .max_write_len = MAX_SW_I2C_COMMANDS, 3857 .max_comb_1st_msg_len = 2, 3858 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2, 3859 }; 3860 3861 static int sienna_cichlid_i2c_control_init(struct smu_context *smu) 3862 { 3863 struct amdgpu_device *adev = smu->adev; 3864 int res, i; 3865 3866 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 3867 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 3868 struct i2c_adapter *control = &smu_i2c->adapter; 3869 3870 smu_i2c->adev = adev; 3871 smu_i2c->port = i; 3872 mutex_init(&smu_i2c->mutex); 3873 control->owner = THIS_MODULE; 3874 control->class = I2C_CLASS_HWMON; 3875 control->dev.parent = &adev->pdev->dev; 3876 control->algo = &sienna_cichlid_i2c_algo; 3877 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i); 3878 control->quirks = &sienna_cichlid_i2c_control_quirks; 3879 i2c_set_adapdata(control, smu_i2c); 3880 3881 res = i2c_add_adapter(control); 3882 if (res) { 3883 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 3884 goto Out_err; 3885 } 3886 } 3887 /* assign the buses used for the FRU EEPROM and RAS EEPROM */ 3888 /* XXX ideally this would be something in a vbios data table */ 3889 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter; 3890 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 3891 3892 return 0; 3893 Out_err: 3894 for ( ; i >= 0; i--) { 3895 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 3896 struct i2c_adapter *control = &smu_i2c->adapter; 3897 3898 i2c_del_adapter(control); 3899 } 3900 return res; 3901 } 3902 3903 static void sienna_cichlid_i2c_control_fini(struct smu_context *smu) 3904 { 3905 struct amdgpu_device *adev = smu->adev; 3906 int i; 3907 3908 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 3909 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 3910 struct i2c_adapter *control = &smu_i2c->adapter; 3911 3912 i2c_del_adapter(control); 3913 } 3914 adev->pm.ras_eeprom_i2c_bus = NULL; 3915 adev->pm.fru_eeprom_i2c_bus = NULL; 3916 } 3917 3918 static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu, 3919 void **table) 3920 { 3921 struct smu_table_context *smu_table = &smu->smu_table; 3922 struct gpu_metrics_v1_3 *gpu_metrics = 3923 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 3924 SmuMetricsExternal_t metrics_external; 3925 SmuMetrics_t *metrics = 3926 &(metrics_external.SmuMetrics); 3927 SmuMetrics_V2_t *metrics_v2 = 3928 &(metrics_external.SmuMetrics_V2); 3929 SmuMetrics_V3_t *metrics_v3 = 3930 &(metrics_external.SmuMetrics_V3); 3931 struct amdgpu_device *adev = smu->adev; 3932 bool use_metrics_v2 = false; 3933 bool use_metrics_v3 = false; 3934 uint16_t average_gfx_activity; 3935 int ret = 0; 3936 3937 switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) { 3938 case IP_VERSION(11, 0, 7): 3939 if (smu->smc_fw_version >= 0x3A4900) 3940 use_metrics_v3 = true; 3941 else if (smu->smc_fw_version >= 0x3A4300) 3942 use_metrics_v2 = true; 3943 break; 3944 case IP_VERSION(11, 0, 11): 3945 if (smu->smc_fw_version >= 0x412D00) 3946 use_metrics_v2 = true; 3947 break; 3948 case IP_VERSION(11, 0, 12): 3949 if (smu->smc_fw_version >= 0x3B2300) 3950 use_metrics_v2 = true; 3951 break; 3952 case IP_VERSION(11, 0, 13): 3953 if (smu->smc_fw_version >= 0x491100) 3954 use_metrics_v2 = true; 3955 break; 3956 default: 3957 break; 3958 } 3959 3960 ret = smu_cmn_get_metrics_table(smu, 3961 &metrics_external, 3962 true); 3963 if (ret) 3964 return ret; 3965 3966 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 3967 3968 gpu_metrics->temperature_edge = use_metrics_v3 ? metrics_v3->TemperatureEdge : 3969 use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge; 3970 gpu_metrics->temperature_hotspot = use_metrics_v3 ? metrics_v3->TemperatureHotspot : 3971 use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot; 3972 gpu_metrics->temperature_mem = use_metrics_v3 ? metrics_v3->TemperatureMem : 3973 use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem; 3974 gpu_metrics->temperature_vrgfx = use_metrics_v3 ? metrics_v3->TemperatureVrGfx : 3975 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx; 3976 gpu_metrics->temperature_vrsoc = use_metrics_v3 ? metrics_v3->TemperatureVrSoc : 3977 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc; 3978 gpu_metrics->temperature_vrmem = use_metrics_v3 ? metrics_v3->TemperatureVrMem0 : 3979 use_metrics_v2 ? metrics_v2->TemperatureVrMem0 : metrics->TemperatureVrMem0; 3980 3981 gpu_metrics->average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity : 3982 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity; 3983 gpu_metrics->average_umc_activity = use_metrics_v3 ? metrics_v3->AverageUclkActivity : 3984 use_metrics_v2 ? metrics_v2->AverageUclkActivity : metrics->AverageUclkActivity; 3985 gpu_metrics->average_mm_activity = use_metrics_v3 ? 3986 (metrics_v3->VcnUsagePercentage0 + metrics_v3->VcnUsagePercentage1) / 2 : 3987 use_metrics_v2 ? metrics_v2->VcnActivityPercentage : metrics->VcnActivityPercentage; 3988 3989 gpu_metrics->average_socket_power = use_metrics_v3 ? metrics_v3->AverageSocketPower : 3990 use_metrics_v2 ? metrics_v2->AverageSocketPower : metrics->AverageSocketPower; 3991 gpu_metrics->energy_accumulator = use_metrics_v3 ? metrics_v3->EnergyAccumulator : 3992 use_metrics_v2 ? metrics_v2->EnergyAccumulator : metrics->EnergyAccumulator; 3993 3994 if (metrics->CurrGfxVoltageOffset) 3995 gpu_metrics->voltage_gfx = 3996 (155000 - 625 * metrics->CurrGfxVoltageOffset) / 100; 3997 if (metrics->CurrMemVidOffset) 3998 gpu_metrics->voltage_mem = 3999 (155000 - 625 * metrics->CurrMemVidOffset) / 100; 4000 if (metrics->CurrSocVoltageOffset) 4001 gpu_metrics->voltage_soc = 4002 (155000 - 625 * metrics->CurrSocVoltageOffset) / 100; 4003 4004 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity : 4005 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity; 4006 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD) 4007 gpu_metrics->average_gfxclk_frequency = 4008 use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs : 4009 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs : 4010 metrics->AverageGfxclkFrequencyPostDs; 4011 else 4012 gpu_metrics->average_gfxclk_frequency = 4013 use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs : 4014 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs : 4015 metrics->AverageGfxclkFrequencyPreDs; 4016 4017 gpu_metrics->average_uclk_frequency = 4018 use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs : 4019 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs : 4020 metrics->AverageUclkFrequencyPostDs; 4021 gpu_metrics->average_vclk0_frequency = use_metrics_v3 ? metrics_v3->AverageVclk0Frequency : 4022 use_metrics_v2 ? metrics_v2->AverageVclk0Frequency : metrics->AverageVclk0Frequency; 4023 gpu_metrics->average_dclk0_frequency = use_metrics_v3 ? metrics_v3->AverageDclk0Frequency : 4024 use_metrics_v2 ? metrics_v2->AverageDclk0Frequency : metrics->AverageDclk0Frequency; 4025 gpu_metrics->average_vclk1_frequency = use_metrics_v3 ? metrics_v3->AverageVclk1Frequency : 4026 use_metrics_v2 ? metrics_v2->AverageVclk1Frequency : metrics->AverageVclk1Frequency; 4027 gpu_metrics->average_dclk1_frequency = use_metrics_v3 ? metrics_v3->AverageDclk1Frequency : 4028 use_metrics_v2 ? metrics_v2->AverageDclk1Frequency : metrics->AverageDclk1Frequency; 4029 4030 gpu_metrics->current_gfxclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] : 4031 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : metrics->CurrClock[PPCLK_GFXCLK]; 4032 gpu_metrics->current_socclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] : 4033 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : metrics->CurrClock[PPCLK_SOCCLK]; 4034 gpu_metrics->current_uclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] : 4035 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK]; 4036 gpu_metrics->current_vclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] : 4037 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : metrics->CurrClock[PPCLK_VCLK_0]; 4038 gpu_metrics->current_dclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] : 4039 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : metrics->CurrClock[PPCLK_DCLK_0]; 4040 gpu_metrics->current_vclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] : 4041 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : metrics->CurrClock[PPCLK_VCLK_1]; 4042 gpu_metrics->current_dclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] : 4043 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : metrics->CurrClock[PPCLK_DCLK_1]; 4044 4045 gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu, use_metrics_v3, use_metrics_v2); 4046 gpu_metrics->indep_throttle_status = 4047 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status, 4048 sienna_cichlid_throttler_map); 4049 4050 gpu_metrics->current_fan_speed = use_metrics_v3 ? metrics_v3->CurrFanSpeed : 4051 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed; 4052 4053 if (((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 7)) && 4054 smu->smc_fw_version > 0x003A1E00) || 4055 ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 11)) && 4056 smu->smc_fw_version > 0x00410400)) { 4057 gpu_metrics->pcie_link_width = use_metrics_v3 ? metrics_v3->PcieWidth : 4058 use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth; 4059 gpu_metrics->pcie_link_speed = link_speed[use_metrics_v3 ? metrics_v3->PcieRate : 4060 use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate]; 4061 } else { 4062 gpu_metrics->pcie_link_width = 4063 smu_v11_0_get_current_pcie_link_width(smu); 4064 gpu_metrics->pcie_link_speed = 4065 smu_v11_0_get_current_pcie_link_speed(smu); 4066 } 4067 4068 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 4069 4070 *table = (void *)gpu_metrics; 4071 4072 return sizeof(struct gpu_metrics_v1_3); 4073 } 4074 4075 static int sienna_cichlid_check_ecc_table_support(struct smu_context *smu) 4076 { 4077 int ret = 0; 4078 4079 if (smu->smc_fw_version < SUPPORT_ECCTABLE_SMU_VERSION) 4080 ret = -EOPNOTSUPP; 4081 4082 return ret; 4083 } 4084 4085 static ssize_t sienna_cichlid_get_ecc_info(struct smu_context *smu, 4086 void *table) 4087 { 4088 struct smu_table_context *smu_table = &smu->smu_table; 4089 EccInfoTable_t *ecc_table = NULL; 4090 struct ecc_info_per_ch *ecc_info_per_channel = NULL; 4091 int i, ret = 0; 4092 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table; 4093 4094 ret = sienna_cichlid_check_ecc_table_support(smu); 4095 if (ret) 4096 return ret; 4097 4098 ret = smu_cmn_update_table(smu, 4099 SMU_TABLE_ECCINFO, 4100 0, 4101 smu_table->ecc_table, 4102 false); 4103 if (ret) { 4104 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n"); 4105 return ret; 4106 } 4107 4108 ecc_table = (EccInfoTable_t *)smu_table->ecc_table; 4109 4110 for (i = 0; i < SIENNA_CICHLID_UMC_CHANNEL_NUM; i++) { 4111 ecc_info_per_channel = &(eccinfo->ecc[i]); 4112 ecc_info_per_channel->ce_count_lo_chip = 4113 ecc_table->EccInfo[i].ce_count_lo_chip; 4114 ecc_info_per_channel->ce_count_hi_chip = 4115 ecc_table->EccInfo[i].ce_count_hi_chip; 4116 ecc_info_per_channel->mca_umc_status = 4117 ecc_table->EccInfo[i].mca_umc_status; 4118 ecc_info_per_channel->mca_umc_addr = 4119 ecc_table->EccInfo[i].mca_umc_addr; 4120 } 4121 4122 return ret; 4123 } 4124 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu) 4125 { 4126 uint16_t *mgpu_fan_boost_limit_rpm; 4127 4128 GET_PPTABLE_MEMBER(MGpuFanBoostLimitRpm, &mgpu_fan_boost_limit_rpm); 4129 /* 4130 * Skip the MGpuFanBoost setting for those ASICs 4131 * which do not support it 4132 */ 4133 if (*mgpu_fan_boost_limit_rpm == 0) 4134 return 0; 4135 4136 return smu_cmn_send_smc_msg_with_param(smu, 4137 SMU_MSG_SetMGpuFanBoostLimitRpm, 4138 0, 4139 NULL); 4140 } 4141 4142 static int sienna_cichlid_gpo_control(struct smu_context *smu, 4143 bool enablement) 4144 { 4145 int ret = 0; 4146 4147 4148 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) { 4149 4150 if (enablement) { 4151 if (smu->smc_fw_version < 0x003a2500) { 4152 ret = smu_cmn_send_smc_msg_with_param(smu, 4153 SMU_MSG_SetGpoFeaturePMask, 4154 GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK, 4155 NULL); 4156 } else { 4157 ret = smu_cmn_send_smc_msg_with_param(smu, 4158 SMU_MSG_DisallowGpo, 4159 0, 4160 NULL); 4161 } 4162 } else { 4163 if (smu->smc_fw_version < 0x003a2500) { 4164 ret = smu_cmn_send_smc_msg_with_param(smu, 4165 SMU_MSG_SetGpoFeaturePMask, 4166 0, 4167 NULL); 4168 } else { 4169 ret = smu_cmn_send_smc_msg_with_param(smu, 4170 SMU_MSG_DisallowGpo, 4171 1, 4172 NULL); 4173 } 4174 } 4175 } 4176 4177 return ret; 4178 } 4179 4180 static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu) 4181 { 4182 /* 4183 * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45 4184 * onwards PMFWs. 4185 */ 4186 if (smu->smc_fw_version < 0x003A2D00) 4187 return 0; 4188 4189 return smu_cmn_send_smc_msg_with_param(smu, 4190 SMU_MSG_Enable2ndUSB20Port, 4191 smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ? 4192 1 : 0, 4193 NULL); 4194 } 4195 4196 static int sienna_cichlid_system_features_control(struct smu_context *smu, 4197 bool en) 4198 { 4199 int ret = 0; 4200 4201 if (en) { 4202 ret = sienna_cichlid_notify_2nd_usb20_port(smu); 4203 if (ret) 4204 return ret; 4205 } 4206 4207 return smu_v11_0_system_features_control(smu, en); 4208 } 4209 4210 static int sienna_cichlid_set_mp1_state(struct smu_context *smu, 4211 enum pp_mp1_state mp1_state) 4212 { 4213 int ret; 4214 4215 switch (mp1_state) { 4216 case PP_MP1_STATE_UNLOAD: 4217 ret = smu_cmn_set_mp1_state(smu, mp1_state); 4218 break; 4219 default: 4220 /* Ignore others */ 4221 ret = 0; 4222 } 4223 4224 return ret; 4225 } 4226 4227 static void sienna_cichlid_stb_init(struct smu_context *smu) 4228 { 4229 struct amdgpu_device *adev = smu->adev; 4230 uint32_t reg; 4231 4232 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_START); 4233 smu->stb_context.enabled = REG_GET_FIELD(reg, MP1_PMI_3_START, ENABLE); 4234 4235 /* STB is disabled */ 4236 if (!smu->stb_context.enabled) 4237 return; 4238 4239 spin_lock_init(&smu->stb_context.lock); 4240 4241 /* STB buffer size in bytes as function of FIFO depth */ 4242 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_FIFO); 4243 smu->stb_context.stb_buf_size = 1 << REG_GET_FIELD(reg, MP1_PMI_3_FIFO, DEPTH); 4244 smu->stb_context.stb_buf_size *= SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES; 4245 4246 dev_info(smu->adev->dev, "STB initialized to %d entries", 4247 smu->stb_context.stb_buf_size / SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES); 4248 4249 } 4250 4251 static int sienna_cichlid_get_default_config_table_settings(struct smu_context *smu, 4252 struct config_table_setting *table) 4253 { 4254 struct amdgpu_device *adev = smu->adev; 4255 4256 if (!table) 4257 return -EINVAL; 4258 4259 table->gfxclk_average_tau = 10; 4260 table->socclk_average_tau = 10; 4261 table->fclk_average_tau = 10; 4262 table->uclk_average_tau = 10; 4263 table->gfx_activity_average_tau = 10; 4264 table->mem_activity_average_tau = 10; 4265 table->socket_power_average_tau = 100; 4266 if (amdgpu_ip_version(adev, MP1_HWIP, 0) != IP_VERSION(11, 0, 7)) 4267 table->apu_socket_power_average_tau = 100; 4268 4269 return 0; 4270 } 4271 4272 static int sienna_cichlid_set_config_table(struct smu_context *smu, 4273 struct config_table_setting *table) 4274 { 4275 DriverSmuConfigExternal_t driver_smu_config_table; 4276 4277 if (!table) 4278 return -EINVAL; 4279 4280 memset(&driver_smu_config_table, 4281 0, 4282 sizeof(driver_smu_config_table)); 4283 driver_smu_config_table.DriverSmuConfig.GfxclkAverageLpfTau = 4284 table->gfxclk_average_tau; 4285 driver_smu_config_table.DriverSmuConfig.FclkAverageLpfTau = 4286 table->fclk_average_tau; 4287 driver_smu_config_table.DriverSmuConfig.UclkAverageLpfTau = 4288 table->uclk_average_tau; 4289 driver_smu_config_table.DriverSmuConfig.GfxActivityLpfTau = 4290 table->gfx_activity_average_tau; 4291 driver_smu_config_table.DriverSmuConfig.UclkActivityLpfTau = 4292 table->mem_activity_average_tau; 4293 driver_smu_config_table.DriverSmuConfig.SocketPowerLpfTau = 4294 table->socket_power_average_tau; 4295 4296 return smu_cmn_update_table(smu, 4297 SMU_TABLE_DRIVER_SMU_CONFIG, 4298 0, 4299 (void *)&driver_smu_config_table, 4300 true); 4301 } 4302 4303 static int sienna_cichlid_stb_get_data_direct(struct smu_context *smu, 4304 void *buf, 4305 uint32_t size) 4306 { 4307 uint32_t *p = buf; 4308 struct amdgpu_device *adev = smu->adev; 4309 4310 /* No need to disable interrupts for now as we don't lock it yet from ISR */ 4311 spin_lock(&smu->stb_context.lock); 4312 4313 /* 4314 * Read the STB FIFO in units of 32bit since this is the accessor window 4315 * (register width) we have. 4316 */ 4317 buf = ((char *) buf) + size; 4318 while ((void *)p < buf) 4319 *p++ = cpu_to_le32(RREG32_PCIE(MP1_Public | smnMP1_PMI_3)); 4320 4321 spin_unlock(&smu->stb_context.lock); 4322 4323 return 0; 4324 } 4325 4326 static bool sienna_cichlid_is_mode2_reset_supported(struct smu_context *smu) 4327 { 4328 return true; 4329 } 4330 4331 static int sienna_cichlid_mode2_reset(struct smu_context *smu) 4332 { 4333 int ret = 0, index; 4334 struct amdgpu_device *adev = smu->adev; 4335 int timeout = 100; 4336 4337 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 4338 SMU_MSG_DriverMode2Reset); 4339 4340 mutex_lock(&smu->message_lock); 4341 4342 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, 4343 SMU_RESET_MODE_2); 4344 4345 ret = smu_cmn_wait_for_response(smu); 4346 while (ret != 0 && timeout) { 4347 ret = smu_cmn_wait_for_response(smu); 4348 /* Wait a bit more time for getting ACK */ 4349 if (ret != 0) { 4350 --timeout; 4351 usleep_range(500, 1000); 4352 continue; 4353 } else { 4354 break; 4355 } 4356 } 4357 4358 if (!timeout) { 4359 dev_err(adev->dev, 4360 "failed to send mode2 message \tparam: 0x%08x response %#x\n", 4361 SMU_RESET_MODE_2, ret); 4362 goto out; 4363 } 4364 4365 dev_info(smu->adev->dev, "restore config space...\n"); 4366 /* Restore the config space saved during init */ 4367 amdgpu_device_load_pci_state(adev->pdev); 4368 out: 4369 mutex_unlock(&smu->message_lock); 4370 4371 return ret; 4372 } 4373 4374 static const struct pptable_funcs sienna_cichlid_ppt_funcs = { 4375 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask, 4376 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table, 4377 .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable, 4378 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable, 4379 .i2c_init = sienna_cichlid_i2c_control_init, 4380 .i2c_fini = sienna_cichlid_i2c_control_fini, 4381 .print_clk_levels = sienna_cichlid_print_clk_levels, 4382 .force_clk_levels = sienna_cichlid_force_clk_levels, 4383 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk, 4384 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed, 4385 .display_config_changed = sienna_cichlid_display_config_changed, 4386 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config, 4387 .is_dpm_running = sienna_cichlid_is_dpm_running, 4388 .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm, 4389 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm, 4390 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode, 4391 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode, 4392 .set_watermarks_table = sienna_cichlid_set_watermarks_table, 4393 .read_sensor = sienna_cichlid_read_sensor, 4394 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states, 4395 .set_performance_level = smu_v11_0_set_performance_level, 4396 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range, 4397 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch, 4398 .get_power_limit = sienna_cichlid_get_power_limit, 4399 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters, 4400 .dump_pptable = sienna_cichlid_dump_pptable, 4401 .init_microcode = smu_v11_0_init_microcode, 4402 .load_microcode = smu_v11_0_load_microcode, 4403 .fini_microcode = smu_v11_0_fini_microcode, 4404 .init_smc_tables = sienna_cichlid_init_smc_tables, 4405 .fini_smc_tables = smu_v11_0_fini_smc_tables, 4406 .init_power = smu_v11_0_init_power, 4407 .fini_power = smu_v11_0_fini_power, 4408 .check_fw_status = smu_v11_0_check_fw_status, 4409 .setup_pptable = sienna_cichlid_setup_pptable, 4410 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, 4411 .check_fw_version = smu_v11_0_check_fw_version, 4412 .write_pptable = smu_cmn_write_pptable, 4413 .set_driver_table_location = smu_v11_0_set_driver_table_location, 4414 .set_tool_table_location = smu_v11_0_set_tool_table_location, 4415 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 4416 .system_features_control = sienna_cichlid_system_features_control, 4417 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 4418 .send_smc_msg = smu_cmn_send_smc_msg, 4419 .init_display_count = NULL, 4420 .set_allowed_mask = smu_v11_0_set_allowed_mask, 4421 .get_enabled_mask = smu_cmn_get_enabled_mask, 4422 .feature_is_enabled = smu_cmn_feature_is_enabled, 4423 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 4424 .notify_display_change = NULL, 4425 .set_power_limit = smu_v11_0_set_power_limit, 4426 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks, 4427 .enable_thermal_alert = smu_v11_0_enable_thermal_alert, 4428 .disable_thermal_alert = smu_v11_0_disable_thermal_alert, 4429 .set_min_dcef_deep_sleep = NULL, 4430 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request, 4431 .get_fan_control_mode = smu_v11_0_get_fan_control_mode, 4432 .set_fan_control_mode = smu_v11_0_set_fan_control_mode, 4433 .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm, 4434 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm, 4435 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate, 4436 .gfx_off_control = smu_v11_0_gfx_off_control, 4437 .register_irq_handler = smu_v11_0_register_irq_handler, 4438 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme, 4439 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc, 4440 .get_bamaco_support = smu_v11_0_get_bamaco_support, 4441 .baco_enter = sienna_cichlid_baco_enter, 4442 .baco_exit = sienna_cichlid_baco_exit, 4443 .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported, 4444 .mode1_reset = smu_v11_0_mode1_reset, 4445 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq, 4446 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range, 4447 .set_default_od_settings = sienna_cichlid_set_default_od_settings, 4448 .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table, 4449 .restore_user_od_settings = sienna_cichlid_restore_user_od_settings, 4450 .run_btc = sienna_cichlid_run_btc, 4451 .set_power_source = smu_v11_0_set_power_source, 4452 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 4453 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 4454 .get_gpu_metrics = sienna_cichlid_get_gpu_metrics, 4455 .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost, 4456 .gfx_ulv_control = smu_v11_0_gfx_ulv_control, 4457 .deep_sleep_control = smu_v11_0_deep_sleep_control, 4458 .get_fan_parameters = sienna_cichlid_get_fan_parameters, 4459 .interrupt_work = smu_v11_0_interrupt_work, 4460 .gpo_control = sienna_cichlid_gpo_control, 4461 .set_mp1_state = sienna_cichlid_set_mp1_state, 4462 .stb_collect_info = sienna_cichlid_stb_get_data_direct, 4463 .get_ecc_info = sienna_cichlid_get_ecc_info, 4464 .get_default_config_table_settings = sienna_cichlid_get_default_config_table_settings, 4465 .set_config_table = sienna_cichlid_set_config_table, 4466 .get_unique_id = sienna_cichlid_get_unique_id, 4467 .mode2_reset_is_support = sienna_cichlid_is_mode2_reset_supported, 4468 .mode2_reset = sienna_cichlid_mode2_reset, 4469 }; 4470 4471 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu) 4472 { 4473 smu->ppt_funcs = &sienna_cichlid_ppt_funcs; 4474 smu->message_map = sienna_cichlid_message_map; 4475 smu->clock_map = sienna_cichlid_clk_map; 4476 smu->feature_map = sienna_cichlid_feature_mask_map; 4477 smu->table_map = sienna_cichlid_table_map; 4478 smu->pwr_src_map = sienna_cichlid_pwr_src_map; 4479 smu->workload_map = sienna_cichlid_workload_map; 4480 smu_v11_0_set_smu_mailbox_registers(smu); 4481 } 4482