1*9f4b3541SRex Zhu /* 2*9f4b3541SRex Zhu * Copyright 2017 Advanced Micro Devices, Inc. 3*9f4b3541SRex Zhu * 4*9f4b3541SRex Zhu * Permission is hereby granted, free of charge, to any person obtaining a 5*9f4b3541SRex Zhu * copy of this software and associated documentation files (the "Software"), 6*9f4b3541SRex Zhu * to deal in the Software without restriction, including without limitation 7*9f4b3541SRex Zhu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*9f4b3541SRex Zhu * and/or sell copies of the Software, and to permit persons to whom the 9*9f4b3541SRex Zhu * Software is furnished to do so, subject to the following conditions: 10*9f4b3541SRex Zhu * 11*9f4b3541SRex Zhu * The above copyright notice and this permission notice shall be included in 12*9f4b3541SRex Zhu * all copies or substantial portions of the Software. 13*9f4b3541SRex Zhu * 14*9f4b3541SRex Zhu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*9f4b3541SRex Zhu * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*9f4b3541SRex Zhu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*9f4b3541SRex Zhu * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*9f4b3541SRex Zhu * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*9f4b3541SRex Zhu * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*9f4b3541SRex Zhu * OTHER DEALINGS IN THE SOFTWARE. 21*9f4b3541SRex Zhu * 22*9f4b3541SRex Zhu */ 23*9f4b3541SRex Zhu #ifndef _CI_SMUMANAGER_H_ 24*9f4b3541SRex Zhu #define _CI_SMUMANAGER_H_ 25*9f4b3541SRex Zhu 26*9f4b3541SRex Zhu #define SMU__NUM_SCLK_DPM_STATE 8 27*9f4b3541SRex Zhu #define SMU__NUM_MCLK_DPM_LEVELS 6 28*9f4b3541SRex Zhu #define SMU__NUM_LCLK_DPM_LEVELS 8 29*9f4b3541SRex Zhu #define SMU__NUM_PCIE_DPM_LEVELS 8 30*9f4b3541SRex Zhu 31*9f4b3541SRex Zhu #include "smu7_discrete.h" 32*9f4b3541SRex Zhu #include <pp_endian.h> 33*9f4b3541SRex Zhu #include "ppatomctrl.h" 34*9f4b3541SRex Zhu 35*9f4b3541SRex Zhu struct ci_pt_defaults { 36*9f4b3541SRex Zhu u8 svi_load_line_en; 37*9f4b3541SRex Zhu u8 svi_load_line_vddc; 38*9f4b3541SRex Zhu u8 tdc_vddc_throttle_release_limit_perc; 39*9f4b3541SRex Zhu u8 tdc_mawt; 40*9f4b3541SRex Zhu u8 tdc_waterfall_ctl; 41*9f4b3541SRex Zhu u8 dte_ambient_temp_base; 42*9f4b3541SRex Zhu u32 display_cac; 43*9f4b3541SRex Zhu u32 bapm_temp_gradient; 44*9f4b3541SRex Zhu u16 bapmti_r[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS]; 45*9f4b3541SRex Zhu u16 bapmti_rc[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS]; 46*9f4b3541SRex Zhu }; 47*9f4b3541SRex Zhu 48*9f4b3541SRex Zhu struct ci_mc_reg_entry { 49*9f4b3541SRex Zhu uint32_t mclk_max; 50*9f4b3541SRex Zhu uint32_t mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; 51*9f4b3541SRex Zhu }; 52*9f4b3541SRex Zhu 53*9f4b3541SRex Zhu struct ci_mc_reg_table { 54*9f4b3541SRex Zhu uint8_t last; 55*9f4b3541SRex Zhu uint8_t num_entries; 56*9f4b3541SRex Zhu uint16_t validflag; 57*9f4b3541SRex Zhu struct ci_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; 58*9f4b3541SRex Zhu SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; 59*9f4b3541SRex Zhu }; 60*9f4b3541SRex Zhu 61*9f4b3541SRex Zhu struct ci_smumgr { 62*9f4b3541SRex Zhu uint32_t soft_regs_start; 63*9f4b3541SRex Zhu uint32_t dpm_table_start; 64*9f4b3541SRex Zhu uint32_t mc_reg_table_start; 65*9f4b3541SRex Zhu uint32_t fan_table_start; 66*9f4b3541SRex Zhu uint32_t arb_table_start; 67*9f4b3541SRex Zhu uint32_t ulv_setting_starts; 68*9f4b3541SRex Zhu struct SMU7_Discrete_DpmTable smc_state_table; 69*9f4b3541SRex Zhu struct SMU7_Discrete_PmFuses power_tune_table; 70*9f4b3541SRex Zhu const struct ci_pt_defaults *power_tune_defaults; 71*9f4b3541SRex Zhu SMU7_Discrete_MCRegisters mc_regs; 72*9f4b3541SRex Zhu struct ci_mc_reg_table mc_reg_table; 73*9f4b3541SRex Zhu }; 74*9f4b3541SRex Zhu 75*9f4b3541SRex Zhu #endif 76*9f4b3541SRex Zhu 77