1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _DMUB_SRV_H_ 27 #define _DMUB_SRV_H_ 28 29 /** 30 * DOC: DMUB interface and operation 31 * 32 * DMUB is the interface to the display DMCUB microcontroller on DCN hardware. 33 * It delegates hardware initialization and command submission to the 34 * microcontroller. DMUB is the shortname for DMCUB. 35 * 36 * This interface is not thread-safe. Ensure that all access to the interface 37 * is properly synchronized by the caller. 38 * 39 * Initialization and usage of the DMUB service should be done in the 40 * steps given below: 41 * 42 * 1. dmub_srv_create() 43 * 2. dmub_srv_has_hw_support() 44 * 3. dmub_srv_calc_region_info() 45 * 4. dmub_srv_hw_init() 46 * 47 * The call to dmub_srv_create() is required to use the server. 48 * 49 * The calls to dmub_srv_has_hw_support() and dmub_srv_calc_region_info() 50 * are helpers to query cache window size and allocate framebuffer(s) 51 * for the cache windows. 52 * 53 * The call to dmub_srv_hw_init() programs the DMCUB registers to prepare 54 * for command submission. Commands can be queued via dmub_srv_fb_cmd_queue() 55 * and executed via dmub_srv_fb_cmd_execute(). 56 * 57 * If the queue is full the dmub_srv_wait_for_idle() call can be used to 58 * wait until the queue has been cleared. 59 * 60 * Destroying the DMUB service can be done by calling dmub_srv_destroy(). 61 * This does not clear DMUB hardware state, only software state. 62 * 63 * The interface is intended to be standalone and should not depend on any 64 * other component within DAL. 65 */ 66 67 #include "inc/dmub_cmd.h" 68 #include "dc/dc_types.h" 69 70 #define DMUB_PC_SNAPSHOT_COUNT 10 71 72 /* Default tracebuffer size if meta is absent. */ 73 #define DMUB_TRACE_BUFFER_SIZE (64 * 1024) 74 75 /* Forward declarations */ 76 struct dmub_srv; 77 struct dmub_srv_common_regs; 78 struct dmub_srv_dcn31_regs; 79 80 struct dmcub_trace_buf_entry; 81 82 /* enum dmub_window_memory_type - memory location type specification for windows */ 83 enum dmub_window_memory_type { 84 DMUB_WINDOW_MEMORY_TYPE_FB = 0, 85 DMUB_WINDOW_MEMORY_TYPE_GART 86 }; 87 88 /* enum dmub_status - return code for dmcub functions */ 89 enum dmub_status { 90 DMUB_STATUS_OK = 0, 91 DMUB_STATUS_NO_CTX, 92 DMUB_STATUS_QUEUE_FULL, 93 DMUB_STATUS_TIMEOUT, 94 DMUB_STATUS_INVALID, 95 DMUB_STATUS_HW_FAILURE, 96 DMUB_STATUS_POWER_STATE_D3 97 }; 98 99 /* enum dmub_asic - dmub asic identifier */ 100 enum dmub_asic { 101 DMUB_ASIC_NONE = 0, 102 DMUB_ASIC_DCN20, 103 DMUB_ASIC_DCN21, 104 DMUB_ASIC_DCN30, 105 DMUB_ASIC_DCN301, 106 DMUB_ASIC_DCN302, 107 DMUB_ASIC_DCN303, 108 DMUB_ASIC_DCN31, 109 DMUB_ASIC_DCN31B, 110 DMUB_ASIC_DCN314, 111 DMUB_ASIC_DCN315, 112 DMUB_ASIC_DCN316, 113 DMUB_ASIC_DCN32, 114 DMUB_ASIC_DCN321, 115 DMUB_ASIC_DCN35, 116 DMUB_ASIC_DCN351, 117 DMUB_ASIC_DCN36, 118 DMUB_ASIC_DCN401, 119 DMUB_ASIC_MAX, 120 }; 121 122 /* enum dmub_window_id - dmub window identifier */ 123 enum dmub_window_id { 124 DMUB_WINDOW_0_INST_CONST = 0, 125 DMUB_WINDOW_1_STACK, 126 DMUB_WINDOW_2_BSS_DATA, 127 DMUB_WINDOW_3_VBIOS, 128 DMUB_WINDOW_4_MAILBOX, 129 DMUB_WINDOW_5_TRACEBUFF, 130 DMUB_WINDOW_6_FW_STATE, 131 DMUB_WINDOW_7_SCRATCH_MEM, 132 DMUB_WINDOW_SHARED_STATE, 133 DMUB_WINDOW_TOTAL, 134 }; 135 136 /* enum dmub_notification_type - dmub outbox notification identifier */ 137 enum dmub_notification_type { 138 DMUB_NOTIFICATION_NO_DATA = 0, 139 DMUB_NOTIFICATION_AUX_REPLY, 140 DMUB_NOTIFICATION_HPD, 141 DMUB_NOTIFICATION_HPD_IRQ, 142 DMUB_NOTIFICATION_SET_CONFIG_REPLY, 143 DMUB_NOTIFICATION_DPIA_NOTIFICATION, 144 DMUB_NOTIFICATION_HPD_SENSE_NOTIFY, 145 DMUB_NOTIFICATION_FUSED_IO, 146 DMUB_NOTIFICATION_MAX 147 }; 148 149 /** 150 * DPIA NOTIFICATION Response Type 151 */ 152 enum dpia_notify_bw_alloc_status { 153 154 DPIA_BW_REQ_FAILED = 0, 155 DPIA_BW_REQ_SUCCESS, 156 DPIA_EST_BW_CHANGED, 157 DPIA_BW_ALLOC_CAPS_CHANGED 158 }; 159 160 /* enum dmub_memory_access_type - memory access method */ 161 enum dmub_memory_access_type { 162 DMUB_MEMORY_ACCESS_DEFAULT, 163 DMUB_MEMORY_ACCESS_CPU = DMUB_MEMORY_ACCESS_DEFAULT, 164 DMUB_MEMORY_ACCESS_DMA 165 }; 166 167 /* enum dmub_power_state type - to track DC power state in dmub_srv */ 168 enum dmub_srv_power_state_type { 169 DMUB_POWER_STATE_UNDEFINED = 0, 170 DMUB_POWER_STATE_D0 = 1, 171 DMUB_POWER_STATE_D3 = 8 172 }; 173 174 /* enum dmub_inbox_cmd_interface type - defines default interface for host->dmub commands */ 175 enum dmub_inbox_cmd_interface_type { 176 DMUB_CMD_INTERFACE_DEFAULT = 0, 177 DMUB_CMD_INTERFACE_FB = 1, 178 DMUB_CMD_INTERFACE_REG = 2, 179 }; 180 181 /** 182 * struct dmub_region - dmub hw memory region 183 * @base: base address for region, must be 256 byte aligned 184 * @top: top address for region 185 */ 186 struct dmub_region { 187 uint32_t base; 188 uint32_t top; 189 }; 190 191 /** 192 * struct dmub_window - dmub hw cache window 193 * @off: offset to the fb memory in gpu address space 194 * @r: region in uc address space for cache window 195 */ 196 struct dmub_window { 197 union dmub_addr offset; 198 struct dmub_region region; 199 }; 200 201 /** 202 * struct dmub_fb - defines a dmub framebuffer memory region 203 * @cpu_addr: cpu virtual address for the region, NULL if invalid 204 * @gpu_addr: gpu virtual address for the region, NULL if invalid 205 * @size: size of the region in bytes, zero if invalid 206 */ 207 struct dmub_fb { 208 void *cpu_addr; 209 uint64_t gpu_addr; 210 uint32_t size; 211 }; 212 213 /** 214 * struct dmub_srv_region_params - params used for calculating dmub regions 215 * @inst_const_size: size of the fw inst const section 216 * @bss_data_size: size of the fw bss data section 217 * @vbios_size: size of the vbios data 218 * @fw_bss_data: raw firmware bss data section 219 */ 220 struct dmub_srv_region_params { 221 uint32_t inst_const_size; 222 uint32_t bss_data_size; 223 uint32_t vbios_size; 224 const uint8_t *fw_inst_const; 225 const uint8_t *fw_bss_data; 226 const enum dmub_window_memory_type *window_memory_type; 227 }; 228 229 /** 230 * struct dmub_srv_region_info - output region info from the dmub service 231 * @fb_size: required minimum fb size for all regions, aligned to 4096 bytes 232 * @num_regions: number of regions used by the dmub service 233 * @regions: region info 234 * 235 * The regions are aligned such that they can be all placed within the 236 * same framebuffer but they can also be placed into different framebuffers. 237 * 238 * The size of each region can be calculated by the caller: 239 * size = reg.top - reg.base 240 * 241 * Care must be taken when performing custom allocations to ensure that each 242 * region base address is 256 byte aligned. 243 */ 244 struct dmub_srv_region_info { 245 uint32_t fb_size; 246 uint32_t gart_size; 247 uint8_t num_regions; 248 struct dmub_region regions[DMUB_WINDOW_TOTAL]; 249 }; 250 251 /** 252 * struct dmub_srv_memory_params - parameters used for driver fb setup 253 * @region_info: region info calculated by dmub service 254 * @cpu_fb_addr: base cpu address for the framebuffer 255 * @cpu_inbox_addr: base cpu address for the gart 256 * @gpu_fb_addr: base gpu virtual address for the framebuffer 257 * @gpu_inbox_addr: base gpu virtual address for the gart 258 */ 259 struct dmub_srv_memory_params { 260 const struct dmub_srv_region_info *region_info; 261 void *cpu_fb_addr; 262 void *cpu_gart_addr; 263 uint64_t gpu_fb_addr; 264 uint64_t gpu_gart_addr; 265 const enum dmub_window_memory_type *window_memory_type; 266 }; 267 268 /** 269 * struct dmub_srv_fb_info - output fb info from the dmub service 270 * @num_fbs: number of required dmub framebuffers 271 * @fbs: fb data for each region 272 * 273 * Output from the dmub service helper that can be used by the 274 * driver to prepare dmub_fb that can be passed into the dmub 275 * hw init service. 276 * 277 * Assumes that all regions are within the same framebuffer 278 * and have been setup according to the region_info generated 279 * by the dmub service. 280 */ 281 struct dmub_srv_fb_info { 282 uint8_t num_fb; 283 struct dmub_fb fb[DMUB_WINDOW_TOTAL]; 284 }; 285 286 /* 287 * struct dmub_srv_hw_params - params for dmub hardware initialization 288 * @fb: framebuffer info for each region 289 * @fb_base: base of the framebuffer aperture 290 * @fb_offset: offset of the framebuffer aperture 291 * @psp_version: psp version to pass for DMCU init 292 * @load_inst_const: true if DMUB should load inst const fw 293 */ 294 struct dmub_srv_hw_params { 295 struct dmub_fb *fb[DMUB_WINDOW_TOTAL]; 296 uint64_t fb_base; 297 uint64_t fb_offset; 298 uint32_t psp_version; 299 bool load_inst_const; 300 bool skip_panel_power_sequence; 301 bool disable_z10; 302 bool power_optimization; 303 bool dpia_supported; 304 bool disable_dpia; 305 bool usb4_cm_version; 306 bool fw_in_system_memory; 307 bool dpia_hpd_int_enable_supported; 308 bool disable_clock_gate; 309 bool disallow_dispclk_dppclk_ds; 310 bool ips_sequential_ono; 311 enum dmub_memory_access_type mem_access_type; 312 enum dmub_ips_disable_type disable_ips; 313 bool disallow_phy_access; 314 bool disable_sldo_opt; 315 bool enable_non_transparent_setconfig; 316 bool lower_hbr3_phy_ssc; 317 }; 318 319 /** 320 * struct dmub_srv_debug - Debug info for dmub_srv 321 * @timeout_occured: Indicates a timeout occured on any message from driver to dmub 322 * @timeout_cmd: first cmd sent from driver that timed out - subsequent timeouts are not stored 323 */ 324 struct dmub_timeout_info { 325 bool timeout_occured; 326 union dmub_rb_cmd timeout_cmd; 327 unsigned long long timestamp; 328 }; 329 330 /** 331 * struct dmub_diagnostic_data - Diagnostic data retrieved from DMCUB for 332 * debugging purposes, including logging, crash analysis, etc. 333 */ 334 struct dmub_diagnostic_data { 335 uint32_t dmcub_version; 336 uint32_t scratch[17]; 337 uint32_t pc[DMUB_PC_SNAPSHOT_COUNT]; 338 uint32_t undefined_address_fault_addr; 339 uint32_t inst_fetch_fault_addr; 340 uint32_t data_write_fault_addr; 341 uint32_t inbox1_rptr; 342 uint32_t inbox1_wptr; 343 uint32_t inbox1_size; 344 uint32_t inbox0_rptr; 345 uint32_t inbox0_wptr; 346 uint32_t inbox0_size; 347 uint32_t outbox1_rptr; 348 uint32_t outbox1_wptr; 349 uint32_t outbox1_size; 350 uint32_t gpint_datain0; 351 struct dmub_timeout_info timeout_info; 352 uint8_t is_dmcub_enabled : 1; 353 uint8_t is_dmcub_soft_reset : 1; 354 uint8_t is_dmcub_secure_reset : 1; 355 uint8_t is_traceport_en : 1; 356 uint8_t is_cw0_enabled : 1; 357 uint8_t is_cw6_enabled : 1; 358 }; 359 360 struct dmub_srv_inbox { 361 /* generic status */ 362 uint64_t num_submitted; 363 uint64_t num_reported; 364 union { 365 /* frame buffer mailbox status */ 366 struct dmub_rb rb; 367 /* register mailbox status */ 368 struct { 369 bool is_pending; 370 bool is_multi_pending; 371 }; 372 }; 373 }; 374 375 /** 376 * struct dmub_srv_base_funcs - Driver specific base callbacks 377 */ 378 struct dmub_srv_base_funcs { 379 /** 380 * @reg_read: 381 * 382 * Hook for reading a register. 383 * 384 * Return: The 32-bit register value from the given address. 385 */ 386 uint32_t (*reg_read)(void *ctx, uint32_t address); 387 388 /** 389 * @reg_write: 390 * 391 * Hook for writing a value to the register specified by address. 392 */ 393 void (*reg_write)(void *ctx, uint32_t address, uint32_t value); 394 }; 395 396 /** 397 * struct dmub_srv_hw_funcs - hardware sequencer funcs for dmub 398 */ 399 struct dmub_srv_hw_funcs { 400 /* private: internal use only */ 401 402 void (*init)(struct dmub_srv *dmub); 403 404 void (*reset)(struct dmub_srv *dmub); 405 406 void (*reset_release)(struct dmub_srv *dmub); 407 408 void (*backdoor_load)(struct dmub_srv *dmub, 409 const struct dmub_window *cw0, 410 const struct dmub_window *cw1); 411 412 void (*backdoor_load_zfb_mode)(struct dmub_srv *dmub, 413 const struct dmub_window *cw0, 414 const struct dmub_window *cw1); 415 void (*setup_windows)(struct dmub_srv *dmub, 416 const struct dmub_window *cw2, 417 const struct dmub_window *cw3, 418 const struct dmub_window *cw4, 419 const struct dmub_window *cw5, 420 const struct dmub_window *cw6, 421 const struct dmub_window *region6); 422 423 void (*setup_mailbox)(struct dmub_srv *dmub, 424 const struct dmub_region *inbox1); 425 426 uint32_t (*get_inbox1_wptr)(struct dmub_srv *dmub); 427 428 uint32_t (*get_inbox1_rptr)(struct dmub_srv *dmub); 429 430 void (*set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset); 431 432 void (*setup_out_mailbox)(struct dmub_srv *dmub, 433 const struct dmub_region *outbox1); 434 435 uint32_t (*get_outbox1_wptr)(struct dmub_srv *dmub); 436 437 void (*set_outbox1_rptr)(struct dmub_srv *dmub, uint32_t rptr_offset); 438 439 void (*setup_outbox0)(struct dmub_srv *dmub, 440 const struct dmub_region *outbox0); 441 442 uint32_t (*get_outbox0_wptr)(struct dmub_srv *dmub); 443 444 void (*set_outbox0_rptr)(struct dmub_srv *dmub, uint32_t rptr_offset); 445 446 uint32_t (*emul_get_inbox1_rptr)(struct dmub_srv *dmub); 447 448 uint32_t (*emul_get_inbox1_wptr)(struct dmub_srv *dmub); 449 450 void (*emul_set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset); 451 452 bool (*is_supported)(struct dmub_srv *dmub); 453 454 bool (*is_psrsu_supported)(struct dmub_srv *dmub); 455 456 bool (*is_hw_init)(struct dmub_srv *dmub); 457 bool (*is_hw_powered_up)(struct dmub_srv *dmub); 458 459 void (*enable_dmub_boot_options)(struct dmub_srv *dmub, 460 const struct dmub_srv_hw_params *params); 461 462 void (*skip_dmub_panel_power_sequence)(struct dmub_srv *dmub, bool skip); 463 464 union dmub_fw_boot_status (*get_fw_status)(struct dmub_srv *dmub); 465 466 union dmub_fw_boot_options (*get_fw_boot_option)(struct dmub_srv *dmub); 467 468 void (*set_gpint)(struct dmub_srv *dmub, 469 union dmub_gpint_data_register reg); 470 471 bool (*is_gpint_acked)(struct dmub_srv *dmub, 472 union dmub_gpint_data_register reg); 473 474 uint32_t (*get_gpint_response)(struct dmub_srv *dmub); 475 476 uint32_t (*get_gpint_dataout)(struct dmub_srv *dmub); 477 478 void (*configure_dmub_in_system_memory)(struct dmub_srv *dmub); 479 void (*clear_inbox0_ack_register)(struct dmub_srv *dmub); 480 uint32_t (*read_inbox0_ack_register)(struct dmub_srv *dmub); 481 void (*send_inbox0_cmd)(struct dmub_srv *dmub, union dmub_inbox0_data_register data); 482 uint32_t (*get_current_time)(struct dmub_srv *dmub); 483 484 void (*get_diagnostic_data)(struct dmub_srv *dmub); 485 486 bool (*should_detect)(struct dmub_srv *dmub); 487 void (*init_reg_offsets)(struct dmub_srv *dmub, struct dc_context *ctx); 488 489 void (*subvp_save_surf_addr)(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index); 490 491 void (*send_reg_inbox0_cmd_msg)(struct dmub_srv *dmub, 492 union dmub_rb_cmd *cmd); 493 uint32_t (*read_reg_inbox0_rsp_int_status)(struct dmub_srv *dmub); 494 void (*read_reg_inbox0_cmd_rsp)(struct dmub_srv *dmub, 495 union dmub_rb_cmd *cmd); 496 void (*write_reg_inbox0_rsp_int_ack)(struct dmub_srv *dmub); 497 void (*clear_reg_inbox0_rsp_int_ack)(struct dmub_srv *dmub); 498 void (*enable_reg_inbox0_rsp_int)(struct dmub_srv *dmub, bool enable); 499 500 uint32_t (*read_reg_outbox0_rdy_int_status)(struct dmub_srv *dmub); 501 void (*write_reg_outbox0_rdy_int_ack)(struct dmub_srv *dmub); 502 void (*read_reg_outbox0_msg)(struct dmub_srv *dmub, uint32_t *msg); 503 void (*write_reg_outbox0_rsp)(struct dmub_srv *dmub, uint32_t *rsp); 504 uint32_t (*read_reg_outbox0_rsp_int_status)(struct dmub_srv *dmub); 505 void (*enable_reg_outbox0_rdy_int)(struct dmub_srv *dmub, bool enable); 506 }; 507 508 /** 509 * struct dmub_srv_create_params - params for dmub service creation 510 * @base_funcs: driver supplied base routines 511 * @hw_funcs: optional overrides for hw funcs 512 * @user_ctx: context data for callback funcs 513 * @asic: driver supplied asic 514 * @fw_version: the current firmware version, if any 515 * @is_virtual: false for hw support only 516 */ 517 struct dmub_srv_create_params { 518 struct dmub_srv_base_funcs funcs; 519 struct dmub_srv_hw_funcs *hw_funcs; 520 void *user_ctx; 521 enum dmub_asic asic; 522 uint32_t fw_version; 523 bool is_virtual; 524 enum dmub_inbox_cmd_interface_type inbox_type; 525 }; 526 527 /** 528 * struct dmub_srv - software state for dmcub 529 * @asic: dmub asic identifier 530 * @user_ctx: user provided context for the dmub_srv 531 * @fw_version: the current firmware version, if any 532 * @is_virtual: false if hardware support only 533 * @shared_state: dmub shared state between firmware and driver 534 * @fw_state: dmub firmware state pointer 535 */ 536 struct dmub_srv { 537 enum dmub_asic asic; 538 void *user_ctx; 539 uint32_t fw_version; 540 bool is_virtual; 541 struct dmub_fb scratch_mem_fb; 542 volatile struct dmub_shared_state_feature_block *shared_state; 543 volatile const struct dmub_fw_state *fw_state; 544 545 /* private: internal use only */ 546 const struct dmub_srv_common_regs *regs; 547 const struct dmub_srv_dcn31_regs *regs_dcn31; 548 struct dmub_srv_dcn32_regs *regs_dcn32; 549 struct dmub_srv_dcn35_regs *regs_dcn35; 550 const struct dmub_srv_dcn401_regs *regs_dcn401; 551 struct dmub_srv_base_funcs funcs; 552 struct dmub_srv_hw_funcs hw_funcs; 553 struct dmub_srv_inbox inbox1; 554 uint32_t inbox1_last_wptr; 555 struct dmub_srv_inbox reg_inbox0; 556 /** 557 * outbox1_rb is accessed without locks (dal & dc) 558 * and to be used only in dmub_srv_stat_get_notification() 559 */ 560 struct dmub_rb outbox1_rb; 561 562 struct dmub_rb outbox0_rb; 563 564 bool sw_init; 565 bool hw_init; 566 567 uint64_t fb_base; 568 uint64_t fb_offset; 569 uint32_t psp_version; 570 571 /* Feature capabilities reported by fw */ 572 struct dmub_fw_meta_info meta_info; 573 struct dmub_feature_caps feature_caps; 574 struct dmub_visual_confirm_color visual_confirm_color; 575 enum dmub_inbox_cmd_interface_type inbox_type; 576 577 enum dmub_srv_power_state_type power_state; 578 struct dmub_diagnostic_data debug; 579 }; 580 581 /** 582 * struct dmub_notification - dmub notification data 583 * @type: dmub notification type 584 * @link_index: link index to identify aux connection 585 * @result: USB4 status returned from dmub 586 * @pending_notification: Indicates there are other pending notifications 587 * @aux_reply: aux reply 588 * @hpd_status: hpd status 589 * @bw_alloc_reply: BW Allocation reply from CM/DPIA 590 */ 591 struct dmub_notification { 592 enum dmub_notification_type type; 593 uint8_t link_index; 594 uint8_t result; 595 bool pending_notification; 596 union { 597 struct aux_reply_data aux_reply; 598 enum dp_hpd_status hpd_status; 599 enum set_config_status sc_status; 600 struct dmub_rb_cmd_hpd_sense_notify_data hpd_sense_notify; 601 struct dmub_cmd_fused_request fused_request; 602 }; 603 }; 604 605 /* enum dmub_ips_mode - IPS mode identifier */ 606 enum dmub_ips_mode { 607 DMUB_IPS_MODE_IPS1_MAX = 0, 608 DMUB_IPS_MODE_IPS2, 609 DMUB_IPS_MODE_IPS1_RCG, 610 DMUB_IPS_MODE_IPS1_ONO2_ON 611 }; 612 613 /** 614 * DMUB firmware version helper macro - useful for checking if the version 615 * of a firmware to know if feature or functionality is supported or present. 616 */ 617 #define DMUB_FW_VERSION(major, minor, revision) \ 618 ((((major) & 0xFF) << 24) | (((minor) & 0xFF) << 16) | (((revision) & 0xFF) << 8)) 619 620 /** 621 * dmub_srv_create() - creates the DMUB service. 622 * @dmub: the dmub service 623 * @params: creation parameters for the service 624 * 625 * Return: 626 * DMUB_STATUS_OK - success 627 * DMUB_STATUS_INVALID - unspecified error 628 */ 629 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 630 const struct dmub_srv_create_params *params); 631 632 /** 633 * dmub_srv_destroy() - destroys the DMUB service. 634 * @dmub: the dmub service 635 */ 636 void dmub_srv_destroy(struct dmub_srv *dmub); 637 638 /** 639 * dmub_srv_calc_region_info() - retreives region info from the dmub service 640 * @dmub: the dmub service 641 * @params: parameters used to calculate region locations 642 * @info_out: the output region info from dmub 643 * 644 * Calculates the base and top address for all relevant dmub regions 645 * using the parameters given (if any). 646 * 647 * Return: 648 * DMUB_STATUS_OK - success 649 * DMUB_STATUS_INVALID - unspecified error 650 */ 651 enum dmub_status 652 dmub_srv_calc_region_info(struct dmub_srv *dmub, 653 const struct dmub_srv_region_params *params, 654 struct dmub_srv_region_info *out); 655 656 /** 657 * dmub_srv_calc_region_info() - retreives fb info from the dmub service 658 * @dmub: the dmub service 659 * @params: parameters used to calculate fb locations 660 * @info_out: the output fb info from dmub 661 * 662 * Calculates the base and top address for all relevant dmub regions 663 * using the parameters given (if any). 664 * 665 * Return: 666 * DMUB_STATUS_OK - success 667 * DMUB_STATUS_INVALID - unspecified error 668 */ 669 enum dmub_status dmub_srv_calc_mem_info(struct dmub_srv *dmub, 670 const struct dmub_srv_memory_params *params, 671 struct dmub_srv_fb_info *out); 672 673 /** 674 * dmub_srv_has_hw_support() - returns hw support state for dmcub 675 * @dmub: the dmub service 676 * @is_supported: hw support state 677 * 678 * Queries the hardware for DMCUB support and returns the result. 679 * 680 * Can be called before dmub_srv_hw_init(). 681 * 682 * Return: 683 * DMUB_STATUS_OK - success 684 * DMUB_STATUS_INVALID - unspecified error 685 */ 686 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 687 bool *is_supported); 688 689 /** 690 * dmub_srv_is_hw_init() - returns hardware init state 691 * 692 * Return: 693 * DMUB_STATUS_OK - success 694 * DMUB_STATUS_INVALID - unspecified error 695 */ 696 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init); 697 698 /** 699 * dmub_srv_hw_init() - initializes the underlying DMUB hardware 700 * @dmub: the dmub service 701 * @params: params for hardware initialization 702 * 703 * Resets the DMUB hardware and performs backdoor loading of the 704 * required cache regions based on the input framebuffer regions. 705 * 706 * Return: 707 * DMUB_STATUS_OK - success 708 * DMUB_STATUS_NO_CTX - dmcub context not initialized 709 * DMUB_STATUS_INVALID - unspecified error 710 */ 711 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 712 const struct dmub_srv_hw_params *params); 713 714 /** 715 * dmub_srv_hw_reset() - puts the DMUB hardware in reset state if initialized 716 * @dmub: the dmub service 717 * 718 * Before destroying the DMUB service or releasing the backing framebuffer 719 * memory we'll need to put the DMCUB into reset first. 720 * 721 * A subsequent call to dmub_srv_hw_init() will re-enable the DMCUB. 722 * 723 * Return: 724 * DMUB_STATUS_OK - success 725 * DMUB_STATUS_INVALID - unspecified error 726 */ 727 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub); 728 729 /** 730 * dmub_srv_fb_cmd_queue() - queues a command to the DMUB 731 * @dmub: the dmub service 732 * @cmd: the command to queue 733 * 734 * Queues a command to the DMUB service but does not begin execution 735 * immediately. 736 * 737 * Return: 738 * DMUB_STATUS_OK - success 739 * DMUB_STATUS_QUEUE_FULL - no remaining room in queue 740 * DMUB_STATUS_INVALID - unspecified error 741 */ 742 enum dmub_status dmub_srv_fb_cmd_queue(struct dmub_srv *dmub, 743 const union dmub_rb_cmd *cmd); 744 745 /** 746 * dmub_srv_fb_cmd_execute() - Executes a queued sequence to the dmub 747 * @dmub: the dmub service 748 * 749 * Begins execution of queued commands on the dmub. 750 * 751 * Return: 752 * DMUB_STATUS_OK - success 753 * DMUB_STATUS_INVALID - unspecified error 754 */ 755 enum dmub_status dmub_srv_fb_cmd_execute(struct dmub_srv *dmub); 756 757 /** 758 * dmub_srv_wait_for_hw_pwr_up() - Waits for firmware hardware power up is completed 759 * @dmub: the dmub service 760 * @timeout_us: the maximum number of microseconds to wait 761 * 762 * Waits until firmware hardware is powered up. The maximum 763 * wait time is given in microseconds to prevent spinning forever. 764 * 765 * Return: 766 * DMUB_STATUS_OK - success 767 * DMUB_STATUS_TIMEOUT - timed out 768 * DMUB_STATUS_INVALID - unspecified error 769 */ 770 enum dmub_status dmub_srv_wait_for_hw_pwr_up(struct dmub_srv *dmub, 771 uint32_t timeout_us); 772 773 bool dmub_srv_is_hw_pwr_up(struct dmub_srv *dmub); 774 775 /** 776 * dmub_srv_wait_for_auto_load() - Waits for firmware auto load to complete 777 * @dmub: the dmub service 778 * @timeout_us: the maximum number of microseconds to wait 779 * 780 * Waits until firmware has been autoloaded by the DMCUB. The maximum 781 * wait time is given in microseconds to prevent spinning forever. 782 * 783 * On ASICs without firmware autoload support this function will return 784 * immediately. 785 * 786 * Return: 787 * DMUB_STATUS_OK - success 788 * DMUB_STATUS_TIMEOUT - wait for phy init timed out 789 * DMUB_STATUS_INVALID - unspecified error 790 */ 791 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 792 uint32_t timeout_us); 793 794 /** 795 * dmub_srv_wait_for_phy_init() - Waits for DMUB PHY init to complete 796 * @dmub: the dmub service 797 * @timeout_us: the maximum number of microseconds to wait 798 * 799 * Waits until the PHY has been initialized by the DMUB. The maximum 800 * wait time is given in microseconds to prevent spinning forever. 801 * 802 * On ASICs without PHY init support this function will return 803 * immediately. 804 * 805 * Return: 806 * DMUB_STATUS_OK - success 807 * DMUB_STATUS_TIMEOUT - wait for phy init timed out 808 * DMUB_STATUS_INVALID - unspecified error 809 */ 810 enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub, 811 uint32_t timeout_us); 812 813 /** 814 * dmub_srv_wait_for_pending() - Re-entrant wait for messages currently pending 815 * @dmub: the dmub service 816 * @timeout_us: the maximum number of microseconds to wait 817 * 818 * Waits until the commands queued prior to this call are complete. 819 * If interfaces remain busy due to additional work being submitted 820 * concurrently, this function will not continue to wait. 821 * 822 * Return: 823 * DMUB_STATUS_OK - success 824 * DMUB_STATUS_TIMEOUT - wait for buffer to flush timed out 825 * DMUB_STATUS_INVALID - unspecified error 826 */ 827 enum dmub_status dmub_srv_wait_for_pending(struct dmub_srv *dmub, 828 uint32_t timeout_us); 829 830 /** 831 * dmub_srv_wait_for_idle() - Waits for the DMUB to be idle 832 * @dmub: the dmub service 833 * @timeout_us: the maximum number of microseconds to wait 834 * 835 * Waits until the DMUB buffer is empty and all commands have 836 * finished processing. The maximum wait time is given in 837 * microseconds to prevent spinning forever. 838 * 839 * Return: 840 * DMUB_STATUS_OK - success 841 * DMUB_STATUS_TIMEOUT - wait for buffer to flush timed out 842 * DMUB_STATUS_INVALID - unspecified error 843 */ 844 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 845 uint32_t timeout_us); 846 847 /** 848 * dmub_srv_send_gpint_command() - Sends a GPINT based command. 849 * @dmub: the dmub service 850 * @command_code: the command code to send 851 * @param: the command parameter to send 852 * @timeout_us: the maximum number of microseconds to wait 853 * 854 * Sends a command via the general purpose interrupt (GPINT). 855 * Waits for the number of microseconds specified by timeout_us 856 * for the command ACK before returning. 857 * 858 * Can be called after software initialization. 859 * 860 * Return: 861 * DMUB_STATUS_OK - success 862 * DMUB_STATUS_TIMEOUT - wait for ACK timed out 863 * DMUB_STATUS_INVALID - unspecified error 864 */ 865 enum dmub_status 866 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 867 enum dmub_gpint_command command_code, 868 uint16_t param, uint32_t timeout_us); 869 870 /** 871 * dmub_srv_get_gpint_response() - Queries the GPINT response. 872 * @dmub: the dmub service 873 * @response: the response for the last GPINT 874 * 875 * Returns the response code for the last GPINT interrupt. 876 * 877 * Can be called after software initialization. 878 * 879 * Return: 880 * DMUB_STATUS_OK - success 881 * DMUB_STATUS_INVALID - unspecified error 882 */ 883 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 884 uint32_t *response); 885 886 /** 887 * dmub_srv_get_gpint_dataout() - Queries the GPINT DATAOUT. 888 * @dmub: the dmub service 889 * @dataout: the data for the GPINT DATAOUT 890 * 891 * Returns the response code for the last GPINT DATAOUT interrupt. 892 * 893 * Can be called after software initialization. 894 * 895 * Return: 896 * DMUB_STATUS_OK - success 897 * DMUB_STATUS_INVALID - unspecified error 898 */ 899 enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub, 900 uint32_t *dataout); 901 902 /** 903 * dmub_flush_buffer_mem() - Read back entire frame buffer region. 904 * This ensures that the write from x86 has been flushed and will not 905 * hang the DMCUB. 906 * @fb: frame buffer to flush 907 * 908 * Can be called after software initialization. 909 */ 910 void dmub_flush_buffer_mem(const struct dmub_fb *fb); 911 912 /** 913 * dmub_srv_get_fw_boot_status() - Returns the DMUB boot status bits. 914 * 915 * @dmub: the dmub service 916 * @status: out pointer for firmware status 917 * 918 * Return: 919 * DMUB_STATUS_OK - success 920 * DMUB_STATUS_INVALID - unspecified error, unsupported 921 */ 922 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub, 923 union dmub_fw_boot_status *status); 924 925 enum dmub_status dmub_srv_get_fw_boot_option(struct dmub_srv *dmub, 926 union dmub_fw_boot_options *option); 927 928 enum dmub_status dmub_srv_set_skip_panel_power_sequence(struct dmub_srv *dmub, 929 bool skip); 930 931 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry); 932 933 bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub); 934 935 bool dmub_srv_should_detect(struct dmub_srv *dmub); 936 937 /** 938 * dmub_srv_send_inbox0_cmd() - Send command to DMUB using INBOX0 939 * @dmub: the dmub service 940 * @data: the data to be sent in the INBOX0 command 941 * 942 * Send command by writing directly to INBOX0 WPTR 943 * 944 * Return: 945 * DMUB_STATUS_OK - success 946 * DMUB_STATUS_INVALID - hw_init false or hw function does not exist 947 */ 948 enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data); 949 950 /** 951 * dmub_srv_wait_for_inbox0_ack() - wait for DMUB to ACK INBOX0 command 952 * @dmub: the dmub service 953 * @timeout_us: the maximum number of microseconds to wait 954 * 955 * Wait for DMUB to ACK the INBOX0 message 956 * 957 * Return: 958 * DMUB_STATUS_OK - success 959 * DMUB_STATUS_INVALID - hw_init false or hw function does not exist 960 * DMUB_STATUS_TIMEOUT - wait for ack timed out 961 */ 962 enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us); 963 964 /** 965 * dmub_srv_wait_for_inbox0_ack() - clear ACK register for INBOX0 966 * @dmub: the dmub service 967 * 968 * Clear ACK register for INBOX0 969 * 970 * Return: 971 * DMUB_STATUS_OK - success 972 * DMUB_STATUS_INVALID - hw_init false or hw function does not exist 973 */ 974 enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub); 975 976 /** 977 * dmub_srv_subvp_save_surf_addr() - Save primary and meta address for subvp on each flip 978 * @dmub: The dmub service 979 * @addr: The surface address to be programmed on the current flip 980 * @subvp_index: Index of subvp pipe, indicates which subvp pipe the address should be saved for 981 * 982 * Function to save the surface flip addr into scratch registers. This is to fix a race condition 983 * between FW and driver reading / writing to the surface address at the same time. This is 984 * required because there is no EARLIEST_IN_USE_META. 985 * 986 * Return: 987 * void 988 */ 989 void dmub_srv_subvp_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index); 990 991 /** 992 * dmub_srv_set_power_state() - Track DC power state in dmub_srv 993 * @dmub: The dmub service 994 * @power_state: DC power state setting 995 * 996 * Store DC power state in dmub_srv. If dmub_srv is in D3, then don't send messages to DMUB 997 * 998 * Return: 999 * void 1000 */ 1001 void dmub_srv_set_power_state(struct dmub_srv *dmub, enum dmub_srv_power_state_type dmub_srv_power_state); 1002 1003 /** 1004 * dmub_srv_reg_cmd_execute() - Executes provided command to the dmub 1005 * @dmub: the dmub service 1006 * @cmd: the command packet to be executed 1007 * 1008 * Executes a single command for the dmub. 1009 * 1010 * Return: 1011 * DMUB_STATUS_OK - success 1012 * DMUB_STATUS_INVALID - unspecified error 1013 */ 1014 enum dmub_status dmub_srv_reg_cmd_execute(struct dmub_srv *dmub, union dmub_rb_cmd *cmd); 1015 1016 1017 /** 1018 * dmub_srv_cmd_get_response() - Copies return data for command into buffer 1019 * @dmub: the dmub service 1020 * @cmd_rsp: response buffer 1021 * 1022 * Copies return data for command into buffer 1023 */ 1024 void dmub_srv_cmd_get_response(struct dmub_srv *dmub, 1025 union dmub_rb_cmd *cmd_rsp); 1026 1027 /** 1028 * dmub_srv_sync_inboxes() - Sync inbox state 1029 * @dmub: the dmub service 1030 * 1031 * Sync inbox state 1032 * 1033 * Return: 1034 * DMUB_STATUS_OK - success 1035 * DMUB_STATUS_INVALID - unspecified error 1036 */ 1037 enum dmub_status dmub_srv_sync_inboxes(struct dmub_srv *dmub); 1038 1039 /** 1040 * dmub_srv_wait_for_inbox_free() - Waits for space in the DMUB inbox to free up 1041 * @dmub: the dmub service 1042 * @timeout_us: the maximum number of microseconds to wait 1043 * @num_free_required: number of free entries required 1044 * 1045 * Waits until the DMUB buffer is freed to the specified number. 1046 * The maximum wait time is given in microseconds to prevent spinning 1047 * forever. 1048 * 1049 * Return: 1050 * DMUB_STATUS_OK - success 1051 * DMUB_STATUS_TIMEOUT - wait for buffer to flush timed out 1052 * DMUB_STATUS_INVALID - unspecified error 1053 */ 1054 enum dmub_status dmub_srv_wait_for_inbox_free(struct dmub_srv *dmub, 1055 uint32_t timeout_us, 1056 uint32_t num_free_required); 1057 1058 /** 1059 * dmub_srv_update_inbox_status() - Updates pending status for inbox & reg inbox0 1060 * @dmub: the dmub service 1061 * 1062 * Return: 1063 * DMUB_STATUS_OK - success 1064 * DMUB_STATUS_TIMEOUT - wait for buffer to flush timed out 1065 * DMUB_STATUS_HW_FAILURE - issue with HW programming 1066 * DMUB_STATUS_INVALID - unspecified error 1067 */ 1068 enum dmub_status dmub_srv_update_inbox_status(struct dmub_srv *dmub); 1069 1070 #endif /* _DMUB_SRV_H_ */ 1071