1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dcn302/dcn302_init.h" 27 #include "dcn302_resource.h" 28 #include "dcn302/dcn302_dccg.h" 29 #include "irq/dcn302/irq_service_dcn302.h" 30 31 #include "dcn30/dcn30_dio_link_encoder.h" 32 #include "dcn30/dcn30_dio_stream_encoder.h" 33 #include "dcn30/dcn30_dwb.h" 34 #include "dcn30/dcn30_dpp.h" 35 #include "dcn30/dcn30_hubbub.h" 36 #include "dcn30/dcn30_hubp.h" 37 #include "dcn30/dcn30_mmhubbub.h" 38 #include "dcn30/dcn30_mpc.h" 39 #include "dcn30/dcn30_opp.h" 40 #include "dcn30/dcn30_optc.h" 41 #include "dcn30/dcn30_resource.h" 42 43 #include "dcn20/dcn20_dsc.h" 44 #include "dcn20/dcn20_resource.h" 45 46 #include "dml/dcn30/dcn30_fpu.h" 47 48 #include "dcn10/dcn10_resource.h" 49 50 #include "link.h" 51 #include "dce/dce_abm.h" 52 #include "dce/dce_audio.h" 53 #include "dce/dce_aux.h" 54 #include "dce/dce_clock_source.h" 55 #include "dce/dce_hwseq.h" 56 #include "dce/dce_i2c_hw.h" 57 #include "dce/dce_panel_cntl.h" 58 #include "dce/dmub_abm.h" 59 #include "dce/dmub_psr.h" 60 #include "clk_mgr.h" 61 62 #include "hw_sequencer_private.h" 63 #include "reg_helper.h" 64 #include "resource.h" 65 #include "vm_helper.h" 66 67 #include "dml/dcn302/dcn302_fpu.h" 68 69 #include "dimgrey_cavefish_ip_offset.h" 70 #include "dcn/dcn_3_0_2_offset.h" 71 #include "dcn/dcn_3_0_2_sh_mask.h" 72 #include "dpcs/dpcs_3_0_0_offset.h" 73 #include "dpcs/dpcs_3_0_0_sh_mask.h" 74 #include "nbio/nbio_7_4_offset.h" 75 #include "amdgpu_socbb.h" 76 77 #define DC_LOGGER \ 78 dc->ctx->logger 79 #define DC_LOGGER_INIT(logger) 80 81 static const struct dc_debug_options debug_defaults_drv = { 82 .disable_dmcu = true, 83 .force_abm_enable = false, 84 .clock_trace = true, 85 .disable_pplib_clock_request = true, 86 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 87 .force_single_disp_pipe_split = false, 88 .disable_dcc = DCC_ENABLE, 89 .vsr_support = true, 90 .performance_trace = false, 91 .max_downscale_src_width = 7680,/*upto 8K*/ 92 .disable_pplib_wm_range = false, 93 .scl_reset_length10 = true, 94 .sanity_checks = false, 95 .underflow_assert_delay_us = 0xFFFFFFFF, 96 .dwb_fi_phase = -1, // -1 = disable, 97 .dmub_command_table = true, 98 .use_max_lb = true, 99 .exit_idle_opt_for_cursor_updates = true, 100 .enable_legacy_fast_update = false, 101 .using_dml2 = false, 102 }; 103 104 static const struct dc_panel_config panel_config_defaults = { 105 .psr = { 106 .disable_psr = false, 107 .disallow_psrsu = false, 108 .disallow_replay = false, 109 }, 110 }; 111 112 enum dcn302_clk_src_array_id { 113 DCN302_CLK_SRC_PLL0, 114 DCN302_CLK_SRC_PLL1, 115 DCN302_CLK_SRC_PLL2, 116 DCN302_CLK_SRC_PLL3, 117 DCN302_CLK_SRC_PLL4, 118 DCN302_CLK_SRC_TOTAL 119 }; 120 121 static const struct resource_caps res_cap_dcn302 = { 122 .num_timing_generator = 5, 123 .num_opp = 5, 124 .num_video_plane = 5, 125 .num_audio = 5, 126 .num_stream_encoder = 5, 127 .num_dwb = 1, 128 .num_ddc = 5, 129 .num_vmid = 16, 130 .num_mpc_3dlut = 2, 131 .num_dsc = 5, 132 }; 133 134 static const struct dc_plane_cap plane_cap = { 135 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 136 .per_pixel_alpha = true, 137 .pixel_format_support = { 138 .argb8888 = true, 139 .nv12 = true, 140 .fp16 = true, 141 .p010 = true, 142 .ayuv = false, 143 }, 144 .max_upscale_factor = { 145 .argb8888 = 16000, 146 .nv12 = 16000, 147 .fp16 = 16000 148 }, 149 /* 6:1 downscaling ratio: 1000/6 = 166.666 */ 150 .max_downscale_factor = { 151 .argb8888 = 167, 152 .nv12 = 167, 153 .fp16 = 167 154 }, 155 16, 156 16 157 }; 158 159 /* NBIO */ 160 #define NBIO_BASE_INNER(seg) \ 161 NBIO_BASE__INST0_SEG ## seg 162 163 #define NBIO_BASE(seg) \ 164 NBIO_BASE_INNER(seg) 165 166 #define NBIO_SR(reg_name)\ 167 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 168 mm ## reg_name 169 170 /* DCN */ 171 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 172 173 #define BASE(seg) BASE_INNER(seg) 174 175 #define SR(reg_name)\ 176 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 177 178 #define SF(reg_name, field_name, post_fix)\ 179 .field_name = reg_name ## __ ## field_name ## post_fix 180 181 #define SRI(reg_name, block, id)\ 182 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name 183 184 #define SRI2(reg_name, block, id)\ 185 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 186 187 #define SRII(reg_name, block, id)\ 188 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 189 mm ## block ## id ## _ ## reg_name 190 191 #define DCCG_SRII(reg_name, block, id)\ 192 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 193 mm ## block ## id ## _ ## reg_name 194 195 #define VUPDATE_SRII(reg_name, block, id)\ 196 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 197 mm ## reg_name ## _ ## block ## id 198 199 #define SRII_DWB(reg_name, temp_name, block, id)\ 200 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 201 mm ## block ## id ## _ ## temp_name 202 203 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 204 .field_name = reg_name ## __ ## field_name ## post_fix 205 206 #define SRII_MPC_RMU(reg_name, block, id)\ 207 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 208 mm ## block ## id ## _ ## reg_name 209 210 static const struct dcn_hubbub_registers hubbub_reg = { 211 HUBBUB_REG_LIST_DCN30(0) 212 }; 213 214 static const struct dcn_hubbub_shift hubbub_shift = { 215 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT) 216 }; 217 218 static const struct dcn_hubbub_mask hubbub_mask = { 219 HUBBUB_MASK_SH_LIST_DCN30(_MASK) 220 }; 221 222 #define vmid_regs(id)\ 223 [id] = { DCN20_VMID_REG_LIST(id) } 224 225 static const struct dcn_vmid_registers vmid_regs[] = { 226 vmid_regs(0), 227 vmid_regs(1), 228 vmid_regs(2), 229 vmid_regs(3), 230 vmid_regs(4), 231 vmid_regs(5), 232 vmid_regs(6), 233 vmid_regs(7), 234 vmid_regs(8), 235 vmid_regs(9), 236 vmid_regs(10), 237 vmid_regs(11), 238 vmid_regs(12), 239 vmid_regs(13), 240 vmid_regs(14), 241 vmid_regs(15) 242 }; 243 244 static const struct dcn20_vmid_shift vmid_shifts = { 245 DCN20_VMID_MASK_SH_LIST(__SHIFT) 246 }; 247 248 static const struct dcn20_vmid_mask vmid_masks = { 249 DCN20_VMID_MASK_SH_LIST(_MASK) 250 }; 251 252 static struct hubbub *dcn302_hubbub_create(struct dc_context *ctx) 253 { 254 int i; 255 256 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL); 257 258 if (!hubbub3) 259 return NULL; 260 261 hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask); 262 263 for (i = 0; i < res_cap_dcn302.num_vmid; i++) { 264 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 265 266 vmid->ctx = ctx; 267 268 vmid->regs = &vmid_regs[i]; 269 vmid->shifts = &vmid_shifts; 270 vmid->masks = &vmid_masks; 271 } 272 273 return &hubbub3->base; 274 } 275 276 #define vpg_regs(id)\ 277 [id] = { VPG_DCN3_REG_LIST(id) } 278 279 static const struct dcn30_vpg_registers vpg_regs[] = { 280 vpg_regs(0), 281 vpg_regs(1), 282 vpg_regs(2), 283 vpg_regs(3), 284 vpg_regs(4), 285 vpg_regs(5) 286 }; 287 288 static const struct dcn30_vpg_shift vpg_shift = { 289 DCN3_VPG_MASK_SH_LIST(__SHIFT) 290 }; 291 292 static const struct dcn30_vpg_mask vpg_mask = { 293 DCN3_VPG_MASK_SH_LIST(_MASK) 294 }; 295 296 static struct vpg *dcn302_vpg_create(struct dc_context *ctx, uint32_t inst) 297 { 298 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 299 300 if (!vpg3) 301 return NULL; 302 303 vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask); 304 305 return &vpg3->base; 306 } 307 308 #define afmt_regs(id)\ 309 [id] = { AFMT_DCN3_REG_LIST(id) } 310 311 static const struct dcn30_afmt_registers afmt_regs[] = { 312 afmt_regs(0), 313 afmt_regs(1), 314 afmt_regs(2), 315 afmt_regs(3), 316 afmt_regs(4), 317 afmt_regs(5) 318 }; 319 320 static const struct dcn30_afmt_shift afmt_shift = { 321 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 322 }; 323 324 static const struct dcn30_afmt_mask afmt_mask = { 325 DCN3_AFMT_MASK_SH_LIST(_MASK) 326 }; 327 328 static struct afmt *dcn302_afmt_create(struct dc_context *ctx, uint32_t inst) 329 { 330 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 331 332 if (!afmt3) 333 return NULL; 334 335 afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask); 336 337 return &afmt3->base; 338 } 339 340 #define audio_regs(id)\ 341 [id] = { AUD_COMMON_REG_LIST(id) } 342 343 static const struct dce_audio_registers audio_regs[] = { 344 audio_regs(0), 345 audio_regs(1), 346 audio_regs(2), 347 audio_regs(3), 348 audio_regs(4), 349 audio_regs(5), 350 audio_regs(6) 351 }; 352 353 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 354 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 355 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 356 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 357 358 static const struct dce_audio_shift audio_shift = { 359 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 360 }; 361 362 static const struct dce_audio_mask audio_mask = { 363 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 364 }; 365 366 static struct audio *dcn302_create_audio(struct dc_context *ctx, unsigned int inst) 367 { 368 return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask); 369 } 370 371 #define stream_enc_regs(id)\ 372 [id] = { SE_DCN3_REG_LIST(id) } 373 374 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 375 stream_enc_regs(0), 376 stream_enc_regs(1), 377 stream_enc_regs(2), 378 stream_enc_regs(3), 379 stream_enc_regs(4) 380 }; 381 382 static const struct dcn10_stream_encoder_shift se_shift = { 383 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 384 }; 385 386 static const struct dcn10_stream_encoder_mask se_mask = { 387 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 388 }; 389 390 static struct stream_encoder *dcn302_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx) 391 { 392 struct dcn10_stream_encoder *enc1; 393 struct vpg *vpg; 394 struct afmt *afmt; 395 int vpg_inst; 396 int afmt_inst; 397 398 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 399 if (eng_id <= ENGINE_ID_DIGE) { 400 vpg_inst = eng_id; 401 afmt_inst = eng_id; 402 } else 403 return NULL; 404 405 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 406 vpg = dcn302_vpg_create(ctx, vpg_inst); 407 afmt = dcn302_afmt_create(ctx, afmt_inst); 408 409 if (!enc1 || !vpg || !afmt) { 410 kfree(enc1); 411 kfree(vpg); 412 kfree(afmt); 413 return NULL; 414 } 415 416 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id], 417 &se_shift, &se_mask); 418 419 return &enc1->base; 420 } 421 422 #define clk_src_regs(index, pllid)\ 423 [index] = { CS_COMMON_REG_LIST_DCN3_02(index, pllid) } 424 425 static const struct dce110_clk_src_regs clk_src_regs[] = { 426 clk_src_regs(0, A), 427 clk_src_regs(1, B), 428 clk_src_regs(2, C), 429 clk_src_regs(3, D), 430 clk_src_regs(4, E) 431 }; 432 433 static const struct dce110_clk_src_shift cs_shift = { 434 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 435 }; 436 437 static const struct dce110_clk_src_mask cs_mask = { 438 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 439 }; 440 441 static struct clock_source *dcn302_clock_source_create(struct dc_context *ctx, struct dc_bios *bios, 442 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src) 443 { 444 struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 445 446 if (!clk_src) 447 return NULL; 448 449 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) { 450 clk_src->base.dp_clk_src = dp_clk_src; 451 return &clk_src->base; 452 } 453 454 kfree(clk_src); 455 BREAK_TO_DEBUGGER(); 456 return NULL; 457 } 458 459 static const struct dce_hwseq_registers hwseq_reg = { 460 HWSEQ_DCN302_REG_LIST() 461 }; 462 463 static const struct dce_hwseq_shift hwseq_shift = { 464 HWSEQ_DCN302_MASK_SH_LIST(__SHIFT) 465 }; 466 467 static const struct dce_hwseq_mask hwseq_mask = { 468 HWSEQ_DCN302_MASK_SH_LIST(_MASK) 469 }; 470 471 static struct dce_hwseq *dcn302_hwseq_create(struct dc_context *ctx) 472 { 473 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 474 475 if (hws) { 476 hws->ctx = ctx; 477 hws->regs = &hwseq_reg; 478 hws->shifts = &hwseq_shift; 479 hws->masks = &hwseq_mask; 480 } 481 return hws; 482 } 483 484 #define hubp_regs(id)\ 485 [id] = { HUBP_REG_LIST_DCN30(id) } 486 487 static const struct dcn_hubp2_registers hubp_regs[] = { 488 hubp_regs(0), 489 hubp_regs(1), 490 hubp_regs(2), 491 hubp_regs(3), 492 hubp_regs(4) 493 }; 494 495 static const struct dcn_hubp2_shift hubp_shift = { 496 HUBP_MASK_SH_LIST_DCN30(__SHIFT) 497 }; 498 499 static const struct dcn_hubp2_mask hubp_mask = { 500 HUBP_MASK_SH_LIST_DCN30(_MASK) 501 }; 502 503 static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst) 504 { 505 struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 506 507 if (!hubp2) 508 return NULL; 509 510 if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask)) 511 return &hubp2->base; 512 513 BREAK_TO_DEBUGGER(); 514 kfree(hubp2); 515 return NULL; 516 } 517 518 #define dpp_regs(id)\ 519 [id] = { DPP_REG_LIST_DCN30(id) } 520 521 static const struct dcn3_dpp_registers dpp_regs[] = { 522 dpp_regs(0), 523 dpp_regs(1), 524 dpp_regs(2), 525 dpp_regs(3), 526 dpp_regs(4) 527 }; 528 529 static const struct dcn3_dpp_shift tf_shift = { 530 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 531 }; 532 533 static const struct dcn3_dpp_mask tf_mask = { 534 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 535 }; 536 537 static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst) 538 { 539 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 540 541 if (!dpp) 542 return NULL; 543 544 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) 545 return &dpp->base; 546 547 BREAK_TO_DEBUGGER(); 548 kfree(dpp); 549 return NULL; 550 } 551 552 #define opp_regs(id)\ 553 [id] = { OPP_REG_LIST_DCN30(id) } 554 555 static const struct dcn20_opp_registers opp_regs[] = { 556 opp_regs(0), 557 opp_regs(1), 558 opp_regs(2), 559 opp_regs(3), 560 opp_regs(4) 561 }; 562 563 static const struct dcn20_opp_shift opp_shift = { 564 OPP_MASK_SH_LIST_DCN20(__SHIFT) 565 }; 566 567 static const struct dcn20_opp_mask opp_mask = { 568 OPP_MASK_SH_LIST_DCN20(_MASK) 569 }; 570 571 static struct output_pixel_processor *dcn302_opp_create(struct dc_context *ctx, uint32_t inst) 572 { 573 struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 574 575 if (!opp) { 576 BREAK_TO_DEBUGGER(); 577 return NULL; 578 } 579 580 dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 581 return &opp->base; 582 } 583 584 #define optc_regs(id)\ 585 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) } 586 587 static const struct dcn_optc_registers optc_regs[] = { 588 optc_regs(0), 589 optc_regs(1), 590 optc_regs(2), 591 optc_regs(3), 592 optc_regs(4) 593 }; 594 595 static const struct dcn_optc_shift optc_shift = { 596 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 597 }; 598 599 static const struct dcn_optc_mask optc_mask = { 600 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) 601 }; 602 603 static struct timing_generator *dcn302_timing_generator_create(struct dc_context *ctx, uint32_t instance) 604 { 605 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL); 606 607 if (!tgn10) 608 return NULL; 609 610 tgn10->base.inst = instance; 611 tgn10->base.ctx = ctx; 612 613 tgn10->tg_regs = &optc_regs[instance]; 614 tgn10->tg_shift = &optc_shift; 615 tgn10->tg_mask = &optc_mask; 616 617 dcn30_timing_generator_init(tgn10); 618 619 return &tgn10->base; 620 } 621 622 static const struct dcn30_mpc_registers mpc_regs = { 623 MPC_REG_LIST_DCN3_0(0), 624 MPC_REG_LIST_DCN3_0(1), 625 MPC_REG_LIST_DCN3_0(2), 626 MPC_REG_LIST_DCN3_0(3), 627 MPC_REG_LIST_DCN3_0(4), 628 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 629 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 630 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 631 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 632 MPC_OUT_MUX_REG_LIST_DCN3_0(4), 633 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 634 MPC_RMU_REG_LIST_DCN3AG(0), 635 MPC_RMU_REG_LIST_DCN3AG(1), 636 MPC_RMU_REG_LIST_DCN3AG(2), 637 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 638 }; 639 640 static const struct dcn30_mpc_shift mpc_shift = { 641 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 642 }; 643 644 static const struct dcn30_mpc_mask mpc_mask = { 645 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 646 }; 647 648 static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu) 649 { 650 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL); 651 652 if (!mpc30) 653 return NULL; 654 655 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); 656 657 return &mpc30->base; 658 } 659 660 #define dsc_regsDCN20(id)\ 661 [id] = { DSC_REG_LIST_DCN20(id) } 662 663 static const struct dcn20_dsc_registers dsc_regs[] = { 664 dsc_regsDCN20(0), 665 dsc_regsDCN20(1), 666 dsc_regsDCN20(2), 667 dsc_regsDCN20(3), 668 dsc_regsDCN20(4) 669 }; 670 671 static const struct dcn20_dsc_shift dsc_shift = { 672 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 673 }; 674 675 static const struct dcn20_dsc_mask dsc_mask = { 676 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 677 }; 678 679 static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ctx, uint32_t inst) 680 { 681 struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 682 683 if (!dsc) { 684 BREAK_TO_DEBUGGER(); 685 return NULL; 686 } 687 688 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 689 return &dsc->base; 690 } 691 692 #define dwbc_regs_dcn3(id)\ 693 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } 694 695 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 696 dwbc_regs_dcn3(0) 697 }; 698 699 static const struct dcn30_dwbc_shift dwbc30_shift = { 700 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 701 }; 702 703 static const struct dcn30_dwbc_mask dwbc30_mask = { 704 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 705 }; 706 707 static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 708 { 709 int i; 710 uint32_t pipe_count = pool->res_cap->num_dwb; 711 712 for (i = 0; i < pipe_count; i++) { 713 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL); 714 715 if (!dwbc30) { 716 dm_error("DC: failed to create dwbc30!\n"); 717 return false; 718 } 719 720 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i); 721 722 pool->dwbc[i] = &dwbc30->base; 723 } 724 return true; 725 } 726 727 #define mcif_wb_regs_dcn3(id)\ 728 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) } 729 730 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 731 mcif_wb_regs_dcn3(0) 732 }; 733 734 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 735 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 736 }; 737 738 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 739 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 740 }; 741 742 static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 743 { 744 int i; 745 uint32_t pipe_count = pool->res_cap->num_dwb; 746 747 for (i = 0; i < pipe_count; i++) { 748 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL); 749 750 if (!mcif_wb30) { 751 dm_error("DC: failed to create mcif_wb30!\n"); 752 return false; 753 } 754 755 dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i); 756 757 pool->mcif_wb[i] = &mcif_wb30->base; 758 } 759 return true; 760 } 761 762 #define aux_engine_regs(id)\ 763 [id] = {\ 764 AUX_COMMON_REG_LIST0(id), \ 765 .AUXN_IMPCAL = 0, \ 766 .AUXP_IMPCAL = 0, \ 767 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 768 } 769 770 static const struct dce110_aux_registers aux_engine_regs[] = { 771 aux_engine_regs(0), 772 aux_engine_regs(1), 773 aux_engine_regs(2), 774 aux_engine_regs(3), 775 aux_engine_regs(4) 776 }; 777 778 static const struct dce110_aux_registers_shift aux_shift = { 779 DCN_AUX_MASK_SH_LIST(__SHIFT) 780 }; 781 782 static const struct dce110_aux_registers_mask aux_mask = { 783 DCN_AUX_MASK_SH_LIST(_MASK) 784 }; 785 786 static struct dce_aux *dcn302_aux_engine_create(struct dc_context *ctx, uint32_t inst) 787 { 788 struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 789 790 if (!aux_engine) 791 return NULL; 792 793 dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 794 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support); 795 796 return &aux_engine->base; 797 } 798 799 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 800 801 static const struct dce_i2c_registers i2c_hw_regs[] = { 802 i2c_inst_regs(1), 803 i2c_inst_regs(2), 804 i2c_inst_regs(3), 805 i2c_inst_regs(4), 806 i2c_inst_regs(5) 807 }; 808 809 static const struct dce_i2c_shift i2c_shifts = { 810 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 811 }; 812 813 static const struct dce_i2c_mask i2c_masks = { 814 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 815 }; 816 817 static struct dce_i2c_hw *dcn302_i2c_hw_create(struct dc_context *ctx, uint32_t inst) 818 { 819 struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 820 821 if (!dce_i2c_hw) 822 return NULL; 823 824 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 825 826 return dce_i2c_hw; 827 } 828 829 static const struct encoder_feature_support link_enc_feature = { 830 .max_hdmi_deep_color = COLOR_DEPTH_121212, 831 .max_hdmi_pixel_clock = 600000, 832 .hdmi_ycbcr420_supported = true, 833 .dp_ycbcr420_supported = true, 834 .fec_supported = true, 835 .flags.bits.IS_HBR2_CAPABLE = true, 836 .flags.bits.IS_HBR3_CAPABLE = true, 837 .flags.bits.IS_TPS3_CAPABLE = true, 838 .flags.bits.IS_TPS4_CAPABLE = true 839 }; 840 841 #define link_regs(id, phyid)\ 842 [id] = {\ 843 LE_DCN3_REG_LIST(id), \ 844 UNIPHY_DCN2_REG_LIST(phyid), \ 845 DPCS_DCN2_REG_LIST(id), \ 846 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 847 } 848 849 static const struct dcn10_link_enc_registers link_enc_regs[] = { 850 link_regs(0, A), 851 link_regs(1, B), 852 link_regs(2, C), 853 link_regs(3, D), 854 link_regs(4, E) 855 }; 856 857 static const struct dcn10_link_enc_shift le_shift = { 858 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT), 859 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 860 }; 861 862 static const struct dcn10_link_enc_mask le_mask = { 863 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK), 864 DPCS_DCN2_MASK_SH_LIST(_MASK) 865 }; 866 867 #define aux_regs(id)\ 868 [id] = { DCN2_AUX_REG_LIST(id) } 869 870 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 871 aux_regs(0), 872 aux_regs(1), 873 aux_regs(2), 874 aux_regs(3), 875 aux_regs(4) 876 }; 877 878 #define hpd_regs(id)\ 879 [id] = { HPD_REG_LIST(id) } 880 881 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 882 hpd_regs(0), 883 hpd_regs(1), 884 hpd_regs(2), 885 hpd_regs(3), 886 hpd_regs(4) 887 }; 888 889 static struct link_encoder *dcn302_link_encoder_create( 890 struct dc_context *ctx, 891 const struct encoder_init_data *enc_init_data) 892 { 893 struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 894 895 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) 896 return NULL; 897 898 dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature, 899 &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1], 900 &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask); 901 902 return &enc20->enc10.base; 903 } 904 905 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 906 { DCN_PANEL_CNTL_REG_LIST() } 907 }; 908 909 static const struct dce_panel_cntl_shift panel_cntl_shift = { 910 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 911 }; 912 913 static const struct dce_panel_cntl_mask panel_cntl_mask = { 914 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 915 }; 916 917 static struct panel_cntl *dcn302_panel_cntl_create(const struct panel_cntl_init_data *init_data) 918 { 919 struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 920 921 if (!panel_cntl) 922 return NULL; 923 924 dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst], 925 &panel_cntl_shift, &panel_cntl_mask); 926 927 return &panel_cntl->base; 928 } 929 930 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps) 931 { 932 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 933 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 934 } 935 936 static const struct resource_create_funcs res_create_funcs = { 937 .read_dce_straps = read_dce_straps, 938 .create_audio = dcn302_create_audio, 939 .create_stream_encoder = dcn302_stream_encoder_create, 940 .create_hwseq = dcn302_hwseq_create, 941 }; 942 943 static bool is_soc_bounding_box_valid(struct dc *dc) 944 { 945 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; 946 947 if (ASICREV_IS_DIMGREY_CAVEFISH_P(hw_internal_rev)) 948 return true; 949 950 return false; 951 } 952 953 static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool) 954 { 955 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_02_soc; 956 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_02_ip; 957 958 DC_LOGGER_INIT(dc->ctx->logger); 959 960 if (!is_soc_bounding_box_valid(dc)) { 961 DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__); 962 return false; 963 } 964 965 loaded_ip->max_num_otg = pool->pipe_count; 966 loaded_ip->max_num_dpp = pool->pipe_count; 967 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 968 DC_FP_START(); 969 dcn20_patch_bounding_box(dc, loaded_bb); 970 DC_FP_END(); 971 972 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 973 struct bp_soc_bb_info bb_info = { 0 }; 974 975 if (dc->ctx->dc_bios->funcs->get_soc_bb_info( 976 dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 977 978 DC_FP_START(); 979 dcn302_fpu_init_soc_bounding_box(bb_info); 980 DC_FP_END(); 981 } 982 } 983 984 return true; 985 } 986 987 static void dcn302_resource_destruct(struct resource_pool *pool) 988 { 989 unsigned int i; 990 991 for (i = 0; i < pool->stream_enc_count; i++) { 992 if (pool->stream_enc[i] != NULL) { 993 if (pool->stream_enc[i]->vpg != NULL) { 994 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg)); 995 pool->stream_enc[i]->vpg = NULL; 996 } 997 if (pool->stream_enc[i]->afmt != NULL) { 998 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt)); 999 pool->stream_enc[i]->afmt = NULL; 1000 } 1001 kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i])); 1002 pool->stream_enc[i] = NULL; 1003 } 1004 } 1005 1006 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1007 if (pool->dscs[i] != NULL) 1008 dcn20_dsc_destroy(&pool->dscs[i]); 1009 } 1010 1011 if (pool->mpc != NULL) { 1012 kfree(TO_DCN20_MPC(pool->mpc)); 1013 pool->mpc = NULL; 1014 } 1015 1016 if (pool->hubbub != NULL) { 1017 kfree(pool->hubbub); 1018 pool->hubbub = NULL; 1019 } 1020 1021 for (i = 0; i < pool->pipe_count; i++) { 1022 if (pool->dpps[i] != NULL) { 1023 kfree(TO_DCN20_DPP(pool->dpps[i])); 1024 pool->dpps[i] = NULL; 1025 } 1026 1027 if (pool->hubps[i] != NULL) { 1028 kfree(TO_DCN20_HUBP(pool->hubps[i])); 1029 pool->hubps[i] = NULL; 1030 } 1031 1032 if (pool->irqs != NULL) 1033 dal_irq_service_destroy(&pool->irqs); 1034 } 1035 1036 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1037 if (pool->engines[i] != NULL) 1038 dce110_engine_destroy(&pool->engines[i]); 1039 if (pool->hw_i2cs[i] != NULL) { 1040 kfree(pool->hw_i2cs[i]); 1041 pool->hw_i2cs[i] = NULL; 1042 } 1043 if (pool->sw_i2cs[i] != NULL) { 1044 kfree(pool->sw_i2cs[i]); 1045 pool->sw_i2cs[i] = NULL; 1046 } 1047 } 1048 1049 for (i = 0; i < pool->res_cap->num_opp; i++) { 1050 if (pool->opps[i] != NULL) 1051 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]); 1052 } 1053 1054 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1055 if (pool->timing_generators[i] != NULL) { 1056 kfree(DCN10TG_FROM_TG(pool->timing_generators[i])); 1057 pool->timing_generators[i] = NULL; 1058 } 1059 } 1060 1061 for (i = 0; i < pool->res_cap->num_dwb; i++) { 1062 if (pool->dwbc[i] != NULL) { 1063 kfree(TO_DCN30_DWBC(pool->dwbc[i])); 1064 pool->dwbc[i] = NULL; 1065 } 1066 if (pool->mcif_wb[i] != NULL) { 1067 kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i])); 1068 pool->mcif_wb[i] = NULL; 1069 } 1070 } 1071 1072 for (i = 0; i < pool->audio_count; i++) { 1073 if (pool->audios[i]) 1074 dce_aud_destroy(&pool->audios[i]); 1075 } 1076 1077 for (i = 0; i < pool->clk_src_count; i++) { 1078 if (pool->clock_sources[i] != NULL) 1079 dcn20_clock_source_destroy(&pool->clock_sources[i]); 1080 } 1081 1082 if (pool->dp_clock_source != NULL) 1083 dcn20_clock_source_destroy(&pool->dp_clock_source); 1084 1085 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1086 if (pool->mpc_lut[i] != NULL) { 1087 dc_3dlut_func_release(pool->mpc_lut[i]); 1088 pool->mpc_lut[i] = NULL; 1089 } 1090 if (pool->mpc_shaper[i] != NULL) { 1091 dc_transfer_func_release(pool->mpc_shaper[i]); 1092 pool->mpc_shaper[i] = NULL; 1093 } 1094 } 1095 1096 for (i = 0; i < pool->pipe_count; i++) { 1097 if (pool->multiple_abms[i] != NULL) 1098 dce_abm_destroy(&pool->multiple_abms[i]); 1099 } 1100 1101 if (pool->psr != NULL) 1102 dmub_psr_destroy(&pool->psr); 1103 1104 if (pool->dccg != NULL) 1105 dcn_dccg_destroy(&pool->dccg); 1106 1107 if (pool->oem_device != NULL) { 1108 struct dc *dc = pool->oem_device->ctx->dc; 1109 1110 dc->link_srv->destroy_ddc_service(&pool->oem_device); 1111 } 1112 } 1113 1114 static void dcn302_destroy_resource_pool(struct resource_pool **pool) 1115 { 1116 dcn302_resource_destruct(*pool); 1117 kfree(*pool); 1118 *pool = NULL; 1119 } 1120 1121 void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1122 { 1123 DC_FP_START(); 1124 dcn302_fpu_update_bw_bounding_box(dc, bw_params); 1125 DC_FP_END(); 1126 } 1127 1128 static void dcn302_get_panel_config_defaults(struct dc_panel_config *panel_config) 1129 { 1130 *panel_config = panel_config_defaults; 1131 } 1132 1133 static struct resource_funcs dcn302_res_pool_funcs = { 1134 .destroy = dcn302_destroy_resource_pool, 1135 .link_enc_create = dcn302_link_encoder_create, 1136 .panel_cntl_create = dcn302_panel_cntl_create, 1137 .validate_bandwidth = dcn30_validate_bandwidth, 1138 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, 1139 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1140 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, 1141 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, 1142 .release_pipe = dcn20_release_pipe, 1143 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1144 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1145 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1146 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1147 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1148 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1149 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1150 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1151 .update_bw_bounding_box = dcn302_update_bw_bounding_box, 1152 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1153 .get_panel_config_defaults = dcn302_get_panel_config_defaults, 1154 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe 1155 }; 1156 1157 static struct dc_cap_funcs cap_funcs = { 1158 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1159 }; 1160 1161 static const struct bios_registers bios_regs = { 1162 NBIO_SR(BIOS_SCRATCH_3), 1163 NBIO_SR(BIOS_SCRATCH_6) 1164 }; 1165 1166 static const struct dccg_registers dccg_regs = { 1167 DCCG_REG_LIST_DCN3_02() 1168 }; 1169 1170 static const struct dccg_shift dccg_shift = { 1171 DCCG_MASK_SH_LIST_DCN3_02(__SHIFT) 1172 }; 1173 1174 static const struct dccg_mask dccg_mask = { 1175 DCCG_MASK_SH_LIST_DCN3_02(_MASK) 1176 }; 1177 1178 #define abm_regs(id)\ 1179 [id] = { ABM_DCN302_REG_LIST(id) } 1180 1181 static const struct dce_abm_registers abm_regs[] = { 1182 abm_regs(0), 1183 abm_regs(1), 1184 abm_regs(2), 1185 abm_regs(3), 1186 abm_regs(4) 1187 }; 1188 1189 static const struct dce_abm_shift abm_shift = { 1190 ABM_MASK_SH_LIST_DCN30(__SHIFT) 1191 }; 1192 1193 static const struct dce_abm_mask abm_mask = { 1194 ABM_MASK_SH_LIST_DCN30(_MASK) 1195 }; 1196 1197 static bool dcn302_resource_construct( 1198 uint8_t num_virtual_links, 1199 struct dc *dc, 1200 struct resource_pool *pool) 1201 { 1202 int i; 1203 struct dc_context *ctx = dc->ctx; 1204 struct irq_service_init_data init_data; 1205 struct ddc_service_init_data ddc_init_data = {0}; 1206 1207 ctx->dc_bios->regs = &bios_regs; 1208 1209 pool->res_cap = &res_cap_dcn302; 1210 1211 pool->funcs = &dcn302_res_pool_funcs; 1212 1213 /************************************************* 1214 * Resource + asic cap harcoding * 1215 *************************************************/ 1216 pool->underlay_pipe_index = NO_UNDERLAY_PIPE; 1217 pool->pipe_count = pool->res_cap->num_timing_generator; 1218 pool->mpcc_count = pool->res_cap->num_timing_generator; 1219 dc->caps.max_downscale_ratio = 600; 1220 dc->caps.i2c_speed_in_khz = 100; 1221 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/ 1222 dc->caps.max_cursor_size = 256; 1223 dc->caps.min_horizontal_blanking_period = 80; 1224 dc->caps.dmdata_alloc_size = 2048; 1225 dc->caps.mall_size_per_mem_channel = 4; 1226 /* total size = mall per channel * num channels * 1024 * 1024 */ 1227 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576; 1228 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 1229 dc->caps.max_slave_planes = 2; 1230 dc->caps.max_slave_yuv_planes = 2; 1231 dc->caps.max_slave_rgb_planes = 2; 1232 dc->caps.post_blend_color_processing = true; 1233 dc->caps.force_dp_tps4_for_cp2520 = true; 1234 dc->caps.extended_aux_timeout_support = true; 1235 dc->caps.dmcub_support = true; 1236 dc->caps.max_v_total = (1 << 15) - 1; 1237 dc->caps.vtotal_limited_by_fp2 = true; 1238 1239 /* Color pipeline capabilities */ 1240 dc->caps.color.dpp.dcn_arch = 1; 1241 dc->caps.color.dpp.input_lut_shared = 0; 1242 dc->caps.color.dpp.icsc = 1; 1243 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1244 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1245 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1246 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1247 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1248 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1249 dc->caps.color.dpp.post_csc = 1; 1250 dc->caps.color.dpp.gamma_corr = 1; 1251 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1252 1253 dc->caps.color.dpp.hw_3d_lut = 1; 1254 dc->caps.color.dpp.ogam_ram = 1; 1255 // no OGAM ROM on DCN3 1256 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1257 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1258 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1259 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1260 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1261 dc->caps.color.dpp.ocsc = 0; 1262 1263 dc->caps.color.mpc.gamut_remap = 1; 1264 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 1265 dc->caps.color.mpc.ogam_ram = 1; 1266 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1267 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1268 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1269 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1270 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1271 dc->caps.color.mpc.ocsc = 1; 1272 1273 dc->caps.dp_hdmi21_pcon_support = true; 1274 1275 /* read VBIOS LTTPR caps */ 1276 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1277 enum bp_result bp_query_result; 1278 uint8_t is_vbios_lttpr_enable = 0; 1279 1280 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1281 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1282 } 1283 1284 if (ctx->dc_bios->funcs->get_lttpr_interop) { 1285 enum bp_result bp_query_result; 1286 uint8_t is_vbios_interop_enabled = 0; 1287 1288 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, 1289 &is_vbios_interop_enabled); 1290 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled; 1291 } 1292 1293 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1294 dc->debug = debug_defaults_drv; 1295 1296 // Init the vm_helper 1297 if (dc->vm_helper) 1298 vm_helper_init(dc->vm_helper, 16); 1299 1300 /************************************************* 1301 * Create resources * 1302 *************************************************/ 1303 1304 /* Clock Sources for Pixel Clock*/ 1305 pool->clock_sources[DCN302_CLK_SRC_PLL0] = 1306 dcn302_clock_source_create(ctx, ctx->dc_bios, 1307 CLOCK_SOURCE_COMBO_PHY_PLL0, 1308 &clk_src_regs[0], false); 1309 pool->clock_sources[DCN302_CLK_SRC_PLL1] = 1310 dcn302_clock_source_create(ctx, ctx->dc_bios, 1311 CLOCK_SOURCE_COMBO_PHY_PLL1, 1312 &clk_src_regs[1], false); 1313 pool->clock_sources[DCN302_CLK_SRC_PLL2] = 1314 dcn302_clock_source_create(ctx, ctx->dc_bios, 1315 CLOCK_SOURCE_COMBO_PHY_PLL2, 1316 &clk_src_regs[2], false); 1317 pool->clock_sources[DCN302_CLK_SRC_PLL3] = 1318 dcn302_clock_source_create(ctx, ctx->dc_bios, 1319 CLOCK_SOURCE_COMBO_PHY_PLL3, 1320 &clk_src_regs[3], false); 1321 pool->clock_sources[DCN302_CLK_SRC_PLL4] = 1322 dcn302_clock_source_create(ctx, ctx->dc_bios, 1323 CLOCK_SOURCE_COMBO_PHY_PLL4, 1324 &clk_src_regs[4], false); 1325 1326 pool->clk_src_count = DCN302_CLK_SRC_TOTAL; 1327 1328 /* todo: not reuse phy_pll registers */ 1329 pool->dp_clock_source = 1330 dcn302_clock_source_create(ctx, ctx->dc_bios, 1331 CLOCK_SOURCE_ID_DP_DTO, 1332 &clk_src_regs[0], true); 1333 1334 for (i = 0; i < pool->clk_src_count; i++) { 1335 if (pool->clock_sources[i] == NULL) { 1336 dm_error("DC: failed to create clock sources!\n"); 1337 BREAK_TO_DEBUGGER(); 1338 goto create_fail; 1339 } 1340 } 1341 1342 /* DCCG */ 1343 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1344 if (pool->dccg == NULL) { 1345 dm_error("DC: failed to create dccg!\n"); 1346 BREAK_TO_DEBUGGER(); 1347 goto create_fail; 1348 } 1349 1350 /* PP Lib and SMU interfaces */ 1351 init_soc_bounding_box(dc, pool); 1352 1353 /* DML */ 1354 dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); 1355 1356 /* IRQ */ 1357 init_data.ctx = dc->ctx; 1358 pool->irqs = dal_irq_service_dcn302_create(&init_data); 1359 if (!pool->irqs) 1360 goto create_fail; 1361 1362 /* HUBBUB */ 1363 pool->hubbub = dcn302_hubbub_create(ctx); 1364 if (pool->hubbub == NULL) { 1365 BREAK_TO_DEBUGGER(); 1366 dm_error("DC: failed to create hubbub!\n"); 1367 goto create_fail; 1368 } 1369 1370 /* HUBPs, DPPs, OPPs and TGs */ 1371 for (i = 0; i < pool->pipe_count; i++) { 1372 pool->hubps[i] = dcn302_hubp_create(ctx, i); 1373 if (pool->hubps[i] == NULL) { 1374 BREAK_TO_DEBUGGER(); 1375 dm_error("DC: failed to create hubps!\n"); 1376 goto create_fail; 1377 } 1378 1379 pool->dpps[i] = dcn302_dpp_create(ctx, i); 1380 if (pool->dpps[i] == NULL) { 1381 BREAK_TO_DEBUGGER(); 1382 dm_error("DC: failed to create dpps!\n"); 1383 goto create_fail; 1384 } 1385 } 1386 1387 for (i = 0; i < pool->res_cap->num_opp; i++) { 1388 pool->opps[i] = dcn302_opp_create(ctx, i); 1389 if (pool->opps[i] == NULL) { 1390 BREAK_TO_DEBUGGER(); 1391 dm_error("DC: failed to create output pixel processor!\n"); 1392 goto create_fail; 1393 } 1394 } 1395 1396 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1397 pool->timing_generators[i] = dcn302_timing_generator_create(ctx, i); 1398 if (pool->timing_generators[i] == NULL) { 1399 BREAK_TO_DEBUGGER(); 1400 dm_error("DC: failed to create tg!\n"); 1401 goto create_fail; 1402 } 1403 } 1404 pool->timing_generator_count = i; 1405 1406 /* PSR */ 1407 pool->psr = dmub_psr_create(ctx); 1408 if (pool->psr == NULL) { 1409 dm_error("DC: failed to create psr!\n"); 1410 BREAK_TO_DEBUGGER(); 1411 goto create_fail; 1412 } 1413 1414 /* ABMs */ 1415 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1416 pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask); 1417 if (pool->multiple_abms[i] == NULL) { 1418 dm_error("DC: failed to create abm for pipe %d!\n", i); 1419 BREAK_TO_DEBUGGER(); 1420 goto create_fail; 1421 } 1422 } 1423 1424 /* MPC and DSC */ 1425 pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut); 1426 if (pool->mpc == NULL) { 1427 BREAK_TO_DEBUGGER(); 1428 dm_error("DC: failed to create mpc!\n"); 1429 goto create_fail; 1430 } 1431 1432 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1433 pool->dscs[i] = dcn302_dsc_create(ctx, i); 1434 if (pool->dscs[i] == NULL) { 1435 BREAK_TO_DEBUGGER(); 1436 dm_error("DC: failed to create display stream compressor %d!\n", i); 1437 goto create_fail; 1438 } 1439 } 1440 1441 /* DWB and MMHUBBUB */ 1442 if (!dcn302_dwbc_create(ctx, pool)) { 1443 BREAK_TO_DEBUGGER(); 1444 dm_error("DC: failed to create dwbc!\n"); 1445 goto create_fail; 1446 } 1447 1448 if (!dcn302_mmhubbub_create(ctx, pool)) { 1449 BREAK_TO_DEBUGGER(); 1450 dm_error("DC: failed to create mcif_wb!\n"); 1451 goto create_fail; 1452 } 1453 1454 /* AUX and I2C */ 1455 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1456 pool->engines[i] = dcn302_aux_engine_create(ctx, i); 1457 if (pool->engines[i] == NULL) { 1458 BREAK_TO_DEBUGGER(); 1459 dm_error("DC:failed to create aux engine!!\n"); 1460 goto create_fail; 1461 } 1462 pool->hw_i2cs[i] = dcn302_i2c_hw_create(ctx, i); 1463 if (pool->hw_i2cs[i] == NULL) { 1464 BREAK_TO_DEBUGGER(); 1465 dm_error("DC:failed to create hw i2c!!\n"); 1466 goto create_fail; 1467 } 1468 pool->sw_i2cs[i] = NULL; 1469 } 1470 1471 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1472 if (!resource_construct(num_virtual_links, dc, pool, 1473 &res_create_funcs)) 1474 goto create_fail; 1475 1476 /* HW Sequencer and Plane caps */ 1477 dcn302_hw_sequencer_construct(dc); 1478 1479 dc->caps.max_planes = pool->pipe_count; 1480 1481 for (i = 0; i < dc->caps.max_planes; ++i) 1482 dc->caps.planes[i] = plane_cap; 1483 1484 dc->cap_funcs = cap_funcs; 1485 1486 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 1487 ddc_init_data.ctx = dc->ctx; 1488 ddc_init_data.link = NULL; 1489 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 1490 ddc_init_data.id.enum_id = 0; 1491 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 1492 pool->oem_device = dc->link_srv->create_ddc_service(&ddc_init_data); 1493 } else { 1494 pool->oem_device = NULL; 1495 } 1496 1497 return true; 1498 1499 create_fail: 1500 1501 dcn302_resource_destruct(pool); 1502 1503 return false; 1504 } 1505 1506 struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc) 1507 { 1508 struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL); 1509 1510 if (!pool) 1511 return NULL; 1512 1513 if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool)) 1514 return pool; 1515 1516 BREAK_TO_DEBUGGER(); 1517 kfree(pool); 1518 return NULL; 1519 } 1520