1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "core_status.h" 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn10/dcn10_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn10/dcn10_resource.h" 35 #include "dcn10/dcn10_ipp.h" 36 #include "dcn10/dcn10_mpc.h" 37 38 #include "dcn10/dcn10_dwb.h" 39 40 #include "irq/dcn10/irq_service_dcn10.h" 41 #include "dcn10/dcn10_dpp.h" 42 #include "dcn10/dcn10_optc.h" 43 #include "dcn10/dcn10_hwseq.h" 44 #include "dce110/dce110_hwseq.h" 45 #include "dcn10/dcn10_opp.h" 46 #include "dcn10/dcn10_link_encoder.h" 47 #include "dcn10/dcn10_stream_encoder.h" 48 #include "dce/dce_clock_source.h" 49 #include "dce/dce_audio.h" 50 #include "dce/dce_hwseq.h" 51 #include "virtual/virtual_stream_encoder.h" 52 #include "dce110/dce110_resource.h" 53 #include "dce112/dce112_resource.h" 54 #include "dcn10/dcn10_hubp.h" 55 #include "dcn10/dcn10_hubbub.h" 56 #include "dce/dce_panel_cntl.h" 57 58 #include "soc15_hw_ip.h" 59 #include "vega10_ip_offset.h" 60 61 #include "dcn/dcn_1_0_offset.h" 62 #include "dcn/dcn_1_0_sh_mask.h" 63 64 #include "nbio/nbio_7_0_offset.h" 65 66 #include "mmhub/mmhub_9_1_offset.h" 67 #include "mmhub/mmhub_9_1_sh_mask.h" 68 69 #include "reg_helper.h" 70 #include "dce/dce_abm.h" 71 #include "dce/dce_dmcu.h" 72 #include "dce/dce_aux.h" 73 #include "dce/dce_i2c.h" 74 75 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 76 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 77 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 78 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 79 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 80 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 81 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 82 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 83 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 84 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 85 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 86 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 87 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 88 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 89 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 90 #endif 91 92 93 enum dcn10_clk_src_array_id { 94 DCN10_CLK_SRC_PLL0, 95 DCN10_CLK_SRC_PLL1, 96 DCN10_CLK_SRC_PLL2, 97 DCN10_CLK_SRC_PLL3, 98 DCN10_CLK_SRC_TOTAL, 99 DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3 100 }; 101 102 /* begin ********************* 103 * macros to expend register list macro defined in HW object header file */ 104 105 /* DCN */ 106 #define BASE_INNER(seg) \ 107 DCE_BASE__INST0_SEG ## seg 108 109 #define BASE(seg) \ 110 BASE_INNER(seg) 111 112 #define SR(reg_name)\ 113 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 114 mm ## reg_name 115 116 #define SRI(reg_name, block, id)\ 117 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 118 mm ## block ## id ## _ ## reg_name 119 120 121 #define SRII(reg_name, block, id)\ 122 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 123 mm ## block ## id ## _ ## reg_name 124 125 #define VUPDATE_SRII(reg_name, block, id)\ 126 .reg_name[id] = BASE(mm ## reg_name ## 0 ## _ ## block ## id ## _BASE_IDX) + \ 127 mm ## reg_name ## 0 ## _ ## block ## id 128 129 /* set field/register/bitfield name */ 130 #define SFRB(field_name, reg_name, bitfield, post_fix)\ 131 .field_name = reg_name ## __ ## bitfield ## post_fix 132 133 /* NBIO */ 134 #define NBIO_BASE_INNER(seg) \ 135 NBIF_BASE__INST0_SEG ## seg 136 137 #define NBIO_BASE(seg) \ 138 NBIO_BASE_INNER(seg) 139 140 #define NBIO_SR(reg_name)\ 141 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 142 mm ## reg_name 143 144 /* MMHUB */ 145 #define MMHUB_BASE_INNER(seg) \ 146 MMHUB_BASE__INST0_SEG ## seg 147 148 #define MMHUB_BASE(seg) \ 149 MMHUB_BASE_INNER(seg) 150 151 #define MMHUB_SR(reg_name)\ 152 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 153 mm ## reg_name 154 155 /* macros to expend register list macro defined in HW object header file 156 * end *********************/ 157 158 159 static const struct dce_dmcu_registers dmcu_regs = { 160 DMCU_DCN10_REG_LIST() 161 }; 162 163 static const struct dce_dmcu_shift dmcu_shift = { 164 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 165 }; 166 167 static const struct dce_dmcu_mask dmcu_mask = { 168 DMCU_MASK_SH_LIST_DCN10(_MASK) 169 }; 170 171 static const struct dce_abm_registers abm_regs = { 172 ABM_DCN10_REG_LIST(0) 173 }; 174 175 static const struct dce_abm_shift abm_shift = { 176 ABM_MASK_SH_LIST_DCN10(__SHIFT) 177 }; 178 179 static const struct dce_abm_mask abm_mask = { 180 ABM_MASK_SH_LIST_DCN10(_MASK) 181 }; 182 183 #define stream_enc_regs(id)\ 184 [id] = {\ 185 SE_DCN_REG_LIST(id)\ 186 } 187 188 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 189 stream_enc_regs(0), 190 stream_enc_regs(1), 191 stream_enc_regs(2), 192 stream_enc_regs(3), 193 }; 194 195 static const struct dcn10_stream_encoder_shift se_shift = { 196 SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT) 197 }; 198 199 static const struct dcn10_stream_encoder_mask se_mask = { 200 SE_COMMON_MASK_SH_LIST_DCN10(_MASK) 201 }; 202 203 #define audio_regs(id)\ 204 [id] = {\ 205 AUD_COMMON_REG_LIST(id)\ 206 } 207 208 static const struct dce_audio_registers audio_regs[] = { 209 audio_regs(0), 210 audio_regs(1), 211 audio_regs(2), 212 audio_regs(3), 213 }; 214 215 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 216 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 217 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 218 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 219 220 static const struct dce_audio_shift audio_shift = { 221 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 222 }; 223 224 static const struct dce_audio_mask audio_mask = { 225 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 226 }; 227 228 #define aux_regs(id)\ 229 [id] = {\ 230 AUX_REG_LIST(id)\ 231 } 232 233 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 234 aux_regs(0), 235 aux_regs(1), 236 aux_regs(2), 237 aux_regs(3) 238 }; 239 240 #define hpd_regs(id)\ 241 [id] = {\ 242 HPD_REG_LIST(id)\ 243 } 244 245 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 246 hpd_regs(0), 247 hpd_regs(1), 248 hpd_regs(2), 249 hpd_regs(3) 250 }; 251 252 #define link_regs(id)\ 253 [id] = {\ 254 LE_DCN10_REG_LIST(id), \ 255 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 256 } 257 258 static const struct dcn10_link_enc_registers link_enc_regs[] = { 259 link_regs(0), 260 link_regs(1), 261 link_regs(2), 262 link_regs(3) 263 }; 264 265 static const struct dcn10_link_enc_shift le_shift = { 266 LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT) 267 }; 268 269 static const struct dcn10_link_enc_mask le_mask = { 270 LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK) 271 }; 272 273 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 274 { DCN_PANEL_CNTL_REG_LIST() } 275 }; 276 277 static const struct dce_panel_cntl_shift panel_cntl_shift = { 278 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 279 }; 280 281 static const struct dce_panel_cntl_mask panel_cntl_mask = { 282 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 283 }; 284 285 static const struct dce110_aux_registers_shift aux_shift = { 286 DCN10_AUX_MASK_SH_LIST(__SHIFT) 287 }; 288 289 static const struct dce110_aux_registers_mask aux_mask = { 290 DCN10_AUX_MASK_SH_LIST(_MASK) 291 }; 292 293 #define ipp_regs(id)\ 294 [id] = {\ 295 IPP_REG_LIST_DCN10(id),\ 296 } 297 298 static const struct dcn10_ipp_registers ipp_regs[] = { 299 ipp_regs(0), 300 ipp_regs(1), 301 ipp_regs(2), 302 ipp_regs(3), 303 }; 304 305 static const struct dcn10_ipp_shift ipp_shift = { 306 IPP_MASK_SH_LIST_DCN10(__SHIFT) 307 }; 308 309 static const struct dcn10_ipp_mask ipp_mask = { 310 IPP_MASK_SH_LIST_DCN10(_MASK), 311 }; 312 313 #define opp_regs(id)\ 314 [id] = {\ 315 OPP_REG_LIST_DCN10(id),\ 316 } 317 318 static const struct dcn10_opp_registers opp_regs[] = { 319 opp_regs(0), 320 opp_regs(1), 321 opp_regs(2), 322 opp_regs(3), 323 }; 324 325 static const struct dcn10_opp_shift opp_shift = { 326 OPP_MASK_SH_LIST_DCN10(__SHIFT) 327 }; 328 329 static const struct dcn10_opp_mask opp_mask = { 330 OPP_MASK_SH_LIST_DCN10(_MASK), 331 }; 332 333 #define aux_engine_regs(id)\ 334 [id] = {\ 335 AUX_COMMON_REG_LIST(id), \ 336 .AUX_RESET_MASK = 0 \ 337 } 338 339 static const struct dce110_aux_registers aux_engine_regs[] = { 340 aux_engine_regs(0), 341 aux_engine_regs(1), 342 aux_engine_regs(2), 343 aux_engine_regs(3), 344 aux_engine_regs(4), 345 aux_engine_regs(5) 346 }; 347 348 #define tf_regs(id)\ 349 [id] = {\ 350 TF_REG_LIST_DCN10(id),\ 351 } 352 353 static const struct dcn_dpp_registers tf_regs[] = { 354 tf_regs(0), 355 tf_regs(1), 356 tf_regs(2), 357 tf_regs(3), 358 }; 359 360 static const struct dcn_dpp_shift tf_shift = { 361 TF_REG_LIST_SH_MASK_DCN10(__SHIFT), 362 TF_DEBUG_REG_LIST_SH_DCN10 363 364 }; 365 366 static const struct dcn_dpp_mask tf_mask = { 367 TF_REG_LIST_SH_MASK_DCN10(_MASK), 368 TF_DEBUG_REG_LIST_MASK_DCN10 369 }; 370 371 static const struct dcn_mpc_registers mpc_regs = { 372 MPC_COMMON_REG_LIST_DCN1_0(0), 373 MPC_COMMON_REG_LIST_DCN1_0(1), 374 MPC_COMMON_REG_LIST_DCN1_0(2), 375 MPC_COMMON_REG_LIST_DCN1_0(3), 376 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0), 377 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1), 378 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2), 379 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3) 380 }; 381 382 static const struct dcn_mpc_shift mpc_shift = { 383 MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT),\ 384 SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, __SHIFT) 385 }; 386 387 static const struct dcn_mpc_mask mpc_mask = { 388 MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK),\ 389 SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, _MASK) 390 }; 391 392 #define tg_regs(id)\ 393 [id] = {TG_COMMON_REG_LIST_DCN1_0(id)} 394 395 static const struct dcn_optc_registers tg_regs[] = { 396 tg_regs(0), 397 tg_regs(1), 398 tg_regs(2), 399 tg_regs(3), 400 }; 401 402 static const struct dcn_optc_shift tg_shift = { 403 TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 404 }; 405 406 static const struct dcn_optc_mask tg_mask = { 407 TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK) 408 }; 409 410 static const struct bios_registers bios_regs = { 411 NBIO_SR(BIOS_SCRATCH_3), 412 NBIO_SR(BIOS_SCRATCH_6) 413 }; 414 415 #define hubp_regs(id)\ 416 [id] = {\ 417 HUBP_REG_LIST_DCN10(id)\ 418 } 419 420 static const struct dcn_mi_registers hubp_regs[] = { 421 hubp_regs(0), 422 hubp_regs(1), 423 hubp_regs(2), 424 hubp_regs(3), 425 }; 426 427 static const struct dcn_mi_shift hubp_shift = { 428 HUBP_MASK_SH_LIST_DCN10(__SHIFT) 429 }; 430 431 static const struct dcn_mi_mask hubp_mask = { 432 HUBP_MASK_SH_LIST_DCN10(_MASK) 433 }; 434 435 static const struct dcn_hubbub_registers hubbub_reg = { 436 HUBBUB_REG_LIST_DCN10(0) 437 }; 438 439 static const struct dcn_hubbub_shift hubbub_shift = { 440 HUBBUB_MASK_SH_LIST_DCN10(__SHIFT) 441 }; 442 443 static const struct dcn_hubbub_mask hubbub_mask = { 444 HUBBUB_MASK_SH_LIST_DCN10(_MASK) 445 }; 446 447 static int map_transmitter_id_to_phy_instance( 448 enum transmitter transmitter) 449 { 450 switch (transmitter) { 451 case TRANSMITTER_UNIPHY_A: 452 return 0; 453 break; 454 case TRANSMITTER_UNIPHY_B: 455 return 1; 456 break; 457 case TRANSMITTER_UNIPHY_C: 458 return 2; 459 break; 460 case TRANSMITTER_UNIPHY_D: 461 return 3; 462 break; 463 default: 464 ASSERT(0); 465 return 0; 466 } 467 } 468 469 #define clk_src_regs(index, pllid)\ 470 [index] = {\ 471 CS_COMMON_REG_LIST_DCN1_0(index, pllid),\ 472 } 473 474 static const struct dce110_clk_src_regs clk_src_regs[] = { 475 clk_src_regs(0, A), 476 clk_src_regs(1, B), 477 clk_src_regs(2, C), 478 clk_src_regs(3, D) 479 }; 480 481 static const struct dce110_clk_src_shift cs_shift = { 482 CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 483 }; 484 485 static const struct dce110_clk_src_mask cs_mask = { 486 CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK) 487 }; 488 489 static const struct resource_caps res_cap = { 490 .num_timing_generator = 4, 491 .num_opp = 4, 492 .num_video_plane = 4, 493 .num_audio = 4, 494 .num_stream_encoder = 4, 495 .num_pll = 4, 496 .num_ddc = 4, 497 }; 498 499 static const struct resource_caps rv2_res_cap = { 500 .num_timing_generator = 3, 501 .num_opp = 3, 502 .num_video_plane = 3, 503 .num_audio = 3, 504 .num_stream_encoder = 3, 505 .num_pll = 3, 506 .num_ddc = 4, 507 }; 508 509 static const struct dc_plane_cap plane_cap = { 510 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 511 .per_pixel_alpha = true, 512 513 .pixel_format_support = { 514 .argb8888 = true, 515 .nv12 = true, 516 .fp16 = true, 517 .p010 = false 518 }, 519 520 .max_upscale_factor = { 521 .argb8888 = 16000, 522 .nv12 = 16000, 523 .fp16 = 1 524 }, 525 526 .max_downscale_factor = { 527 .argb8888 = 250, 528 .nv12 = 250, 529 .fp16 = 1 530 } 531 }; 532 533 static const struct dc_debug_options debug_defaults_drv = { 534 .sanity_checks = true, 535 .disable_dmcu = false, 536 .force_abm_enable = false, 537 .clock_trace = true, 538 539 /* raven smu dones't allow 0 disp clk, 540 * smu min disp clk limit is 50Mhz 541 * keep min disp clk 100Mhz avoid smu hang 542 */ 543 .min_disp_clk_khz = 100000, 544 545 .disable_pplib_clock_request = false, 546 .disable_pplib_wm_range = false, 547 .pplib_wm_report_mode = WM_REPORT_DEFAULT, 548 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 549 .force_single_disp_pipe_split = true, 550 .disable_dcc = DCC_ENABLE, 551 .voltage_align_fclk = true, 552 .disable_stereo_support = true, 553 .vsr_support = true, 554 .performance_trace = false, 555 .az_endpoint_mute_only = true, 556 .recovery_enabled = false, /*enable this by default after testing.*/ 557 .max_downscale_src_width = 3840, 558 .underflow_assert_delay_us = 0xFFFFFFFF, 559 .enable_legacy_fast_update = true, 560 .using_dml2 = false, 561 }; 562 563 static void dcn10_dpp_destroy(struct dpp **dpp) 564 { 565 kfree(TO_DCN10_DPP(*dpp)); 566 *dpp = NULL; 567 } 568 569 static struct dpp *dcn10_dpp_create( 570 struct dc_context *ctx, 571 uint32_t inst) 572 { 573 struct dcn10_dpp *dpp = 574 kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL); 575 576 if (!dpp) 577 return NULL; 578 579 dpp1_construct(dpp, ctx, inst, 580 &tf_regs[inst], &tf_shift, &tf_mask); 581 return &dpp->base; 582 } 583 584 static struct input_pixel_processor *dcn10_ipp_create( 585 struct dc_context *ctx, uint32_t inst) 586 { 587 struct dcn10_ipp *ipp = 588 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 589 590 if (!ipp) { 591 BREAK_TO_DEBUGGER(); 592 return NULL; 593 } 594 595 dcn10_ipp_construct(ipp, ctx, inst, 596 &ipp_regs[inst], &ipp_shift, &ipp_mask); 597 return &ipp->base; 598 } 599 600 601 static struct output_pixel_processor *dcn10_opp_create( 602 struct dc_context *ctx, uint32_t inst) 603 { 604 struct dcn10_opp *opp = 605 kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL); 606 607 if (!opp) { 608 BREAK_TO_DEBUGGER(); 609 return NULL; 610 } 611 612 dcn10_opp_construct(opp, ctx, inst, 613 &opp_regs[inst], &opp_shift, &opp_mask); 614 return &opp->base; 615 } 616 617 static struct dce_aux *dcn10_aux_engine_create(struct dc_context *ctx, 618 uint32_t inst) 619 { 620 struct aux_engine_dce110 *aux_engine = 621 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 622 623 if (!aux_engine) 624 return NULL; 625 626 dce110_aux_engine_construct(aux_engine, ctx, inst, 627 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 628 &aux_engine_regs[inst], 629 &aux_mask, 630 &aux_shift, 631 ctx->dc->caps.extended_aux_timeout_support); 632 633 return &aux_engine->base; 634 } 635 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 636 637 static const struct dce_i2c_registers i2c_hw_regs[] = { 638 i2c_inst_regs(1), 639 i2c_inst_regs(2), 640 i2c_inst_regs(3), 641 i2c_inst_regs(4), 642 i2c_inst_regs(5), 643 i2c_inst_regs(6), 644 }; 645 646 static const struct dce_i2c_shift i2c_shifts = { 647 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 648 }; 649 650 static const struct dce_i2c_mask i2c_masks = { 651 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 652 }; 653 654 static struct dce_i2c_hw *dcn10_i2c_hw_create(struct dc_context *ctx, 655 uint32_t inst) 656 { 657 struct dce_i2c_hw *dce_i2c_hw = 658 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 659 660 if (!dce_i2c_hw) 661 return NULL; 662 663 dcn1_i2c_hw_construct(dce_i2c_hw, ctx, inst, 664 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 665 666 return dce_i2c_hw; 667 } 668 static struct mpc *dcn10_mpc_create(struct dc_context *ctx) 669 { 670 struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc), 671 GFP_KERNEL); 672 673 if (!mpc10) 674 return NULL; 675 676 dcn10_mpc_construct(mpc10, ctx, 677 &mpc_regs, 678 &mpc_shift, 679 &mpc_mask, 680 4); 681 682 return &mpc10->base; 683 } 684 685 static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx) 686 { 687 struct dcn10_hubbub *dcn10_hubbub = kzalloc(sizeof(struct dcn10_hubbub), 688 GFP_KERNEL); 689 690 if (!dcn10_hubbub) 691 return NULL; 692 693 hubbub1_construct(&dcn10_hubbub->base, ctx, 694 &hubbub_reg, 695 &hubbub_shift, 696 &hubbub_mask); 697 698 return &dcn10_hubbub->base; 699 } 700 701 static struct timing_generator *dcn10_timing_generator_create( 702 struct dc_context *ctx, 703 uint32_t instance) 704 { 705 struct optc *tgn10 = 706 kzalloc(sizeof(struct optc), GFP_KERNEL); 707 708 if (!tgn10) 709 return NULL; 710 711 tgn10->base.inst = instance; 712 tgn10->base.ctx = ctx; 713 714 tgn10->tg_regs = &tg_regs[instance]; 715 tgn10->tg_shift = &tg_shift; 716 tgn10->tg_mask = &tg_mask; 717 718 dcn10_timing_generator_init(tgn10); 719 720 return &tgn10->base; 721 } 722 723 static const struct encoder_feature_support link_enc_feature = { 724 .max_hdmi_deep_color = COLOR_DEPTH_121212, 725 .max_hdmi_pixel_clock = 600000, 726 .hdmi_ycbcr420_supported = true, 727 .dp_ycbcr420_supported = true, 728 .flags.bits.IS_HBR2_CAPABLE = true, 729 .flags.bits.IS_HBR3_CAPABLE = true, 730 .flags.bits.IS_TPS3_CAPABLE = true, 731 .flags.bits.IS_TPS4_CAPABLE = true 732 }; 733 734 static struct link_encoder *dcn10_link_encoder_create( 735 struct dc_context *ctx, 736 const struct encoder_init_data *enc_init_data) 737 { 738 struct dcn10_link_encoder *enc10 = 739 kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL); 740 int link_regs_id; 741 742 if (!enc10 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) 743 return NULL; 744 745 link_regs_id = 746 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 747 748 dcn10_link_encoder_construct(enc10, 749 enc_init_data, 750 &link_enc_feature, 751 &link_enc_regs[link_regs_id], 752 &link_enc_aux_regs[enc_init_data->channel - 1], 753 &link_enc_hpd_regs[enc_init_data->hpd_source], 754 &le_shift, 755 &le_mask); 756 757 return &enc10->base; 758 } 759 760 static struct panel_cntl *dcn10_panel_cntl_create(const struct panel_cntl_init_data *init_data) 761 { 762 struct dce_panel_cntl *panel_cntl = 763 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 764 765 if (!panel_cntl) 766 return NULL; 767 768 dce_panel_cntl_construct(panel_cntl, 769 init_data, 770 &panel_cntl_regs[init_data->inst], 771 &panel_cntl_shift, 772 &panel_cntl_mask); 773 774 return &panel_cntl->base; 775 } 776 777 static struct clock_source *dcn10_clock_source_create( 778 struct dc_context *ctx, 779 struct dc_bios *bios, 780 enum clock_source_id id, 781 const struct dce110_clk_src_regs *regs, 782 bool dp_clk_src) 783 { 784 struct dce110_clk_src *clk_src = 785 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 786 787 if (!clk_src) 788 return NULL; 789 790 if (dce112_clk_src_construct(clk_src, ctx, bios, id, 791 regs, &cs_shift, &cs_mask)) { 792 clk_src->base.dp_clk_src = dp_clk_src; 793 return &clk_src->base; 794 } 795 796 kfree(clk_src); 797 BREAK_TO_DEBUGGER(); 798 return NULL; 799 } 800 801 static void read_dce_straps( 802 struct dc_context *ctx, 803 struct resource_straps *straps) 804 { 805 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 806 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 807 } 808 809 static struct audio *create_audio( 810 struct dc_context *ctx, unsigned int inst) 811 { 812 return dce_audio_create(ctx, inst, 813 &audio_regs[inst], &audio_shift, &audio_mask); 814 } 815 816 static struct stream_encoder *dcn10_stream_encoder_create( 817 enum engine_id eng_id, 818 struct dc_context *ctx) 819 { 820 struct dcn10_stream_encoder *enc1 = 821 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 822 823 if (!enc1) 824 return NULL; 825 826 dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 827 &stream_enc_regs[eng_id], 828 &se_shift, &se_mask); 829 return &enc1->base; 830 } 831 832 static const struct dce_hwseq_registers hwseq_reg = { 833 HWSEQ_DCN1_REG_LIST() 834 }; 835 836 static const struct dce_hwseq_shift hwseq_shift = { 837 HWSEQ_DCN1_MASK_SH_LIST(__SHIFT) 838 }; 839 840 static const struct dce_hwseq_mask hwseq_mask = { 841 HWSEQ_DCN1_MASK_SH_LIST(_MASK) 842 }; 843 844 static struct dce_hwseq *dcn10_hwseq_create( 845 struct dc_context *ctx) 846 { 847 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 848 849 if (hws) { 850 hws->ctx = ctx; 851 hws->regs = &hwseq_reg; 852 hws->shifts = &hwseq_shift; 853 hws->masks = &hwseq_mask; 854 hws->wa.DEGVIDCN10_253 = true; 855 hws->wa.false_optc_underflow = true; 856 hws->wa.DEGVIDCN10_254 = true; 857 858 if ((ctx->asic_id.chip_family == FAMILY_RV) && 859 ASICREV_IS_RAVEN2(ctx->asic_id.hw_internal_rev)) 860 switch (ctx->asic_id.pci_revision_id) { 861 case PRID_POLLOCK_94: 862 case PRID_POLLOCK_95: 863 case PRID_POLLOCK_E9: 864 case PRID_POLLOCK_EA: 865 case PRID_POLLOCK_EB: 866 hws->wa.wait_hubpret_read_start_during_mpo_transition = true; 867 break; 868 default: 869 hws->wa.wait_hubpret_read_start_during_mpo_transition = false; 870 break; 871 } 872 } 873 return hws; 874 } 875 876 static const struct resource_create_funcs res_create_funcs = { 877 .read_dce_straps = read_dce_straps, 878 .create_audio = create_audio, 879 .create_stream_encoder = dcn10_stream_encoder_create, 880 .create_hwseq = dcn10_hwseq_create, 881 }; 882 883 static void dcn10_clock_source_destroy(struct clock_source **clk_src) 884 { 885 kfree(TO_DCE110_CLK_SRC(*clk_src)); 886 *clk_src = NULL; 887 } 888 889 static struct pp_smu_funcs *dcn10_pp_smu_create(struct dc_context *ctx) 890 { 891 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 892 893 if (!pp_smu) 894 return pp_smu; 895 896 dm_pp_get_funcs(ctx, pp_smu); 897 return pp_smu; 898 } 899 900 static void dcn10_resource_destruct(struct dcn10_resource_pool *pool) 901 { 902 unsigned int i; 903 904 for (i = 0; i < pool->base.stream_enc_count; i++) { 905 if (pool->base.stream_enc[i] != NULL) { 906 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 907 pool->base.stream_enc[i] = NULL; 908 } 909 } 910 911 if (pool->base.mpc != NULL) { 912 kfree(TO_DCN10_MPC(pool->base.mpc)); 913 pool->base.mpc = NULL; 914 } 915 916 kfree(pool->base.hubbub); 917 pool->base.hubbub = NULL; 918 919 for (i = 0; i < pool->base.pipe_count; i++) { 920 if (pool->base.opps[i] != NULL) 921 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 922 923 if (pool->base.dpps[i] != NULL) 924 dcn10_dpp_destroy(&pool->base.dpps[i]); 925 926 if (pool->base.ipps[i] != NULL) 927 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 928 929 if (pool->base.hubps[i] != NULL) { 930 kfree(TO_DCN10_HUBP(pool->base.hubps[i])); 931 pool->base.hubps[i] = NULL; 932 } 933 934 if (pool->base.irqs != NULL) { 935 dal_irq_service_destroy(&pool->base.irqs); 936 } 937 938 if (pool->base.timing_generators[i] != NULL) { 939 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 940 pool->base.timing_generators[i] = NULL; 941 } 942 } 943 944 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 945 if (pool->base.engines[i] != NULL) 946 dce110_engine_destroy(&pool->base.engines[i]); 947 kfree(pool->base.hw_i2cs[i]); 948 pool->base.hw_i2cs[i] = NULL; 949 kfree(pool->base.sw_i2cs[i]); 950 pool->base.sw_i2cs[i] = NULL; 951 } 952 953 for (i = 0; i < pool->base.audio_count; i++) { 954 if (pool->base.audios[i]) 955 dce_aud_destroy(&pool->base.audios[i]); 956 } 957 958 for (i = 0; i < pool->base.clk_src_count; i++) { 959 if (pool->base.clock_sources[i] != NULL) { 960 dcn10_clock_source_destroy(&pool->base.clock_sources[i]); 961 pool->base.clock_sources[i] = NULL; 962 } 963 } 964 965 if (pool->base.dp_clock_source != NULL) { 966 dcn10_clock_source_destroy(&pool->base.dp_clock_source); 967 pool->base.dp_clock_source = NULL; 968 } 969 970 if (pool->base.abm != NULL) 971 dce_abm_destroy(&pool->base.abm); 972 973 if (pool->base.dmcu != NULL) 974 dce_dmcu_destroy(&pool->base.dmcu); 975 976 kfree(pool->base.pp_smu); 977 } 978 979 static struct hubp *dcn10_hubp_create( 980 struct dc_context *ctx, 981 uint32_t inst) 982 { 983 struct dcn10_hubp *hubp1 = 984 kzalloc(sizeof(struct dcn10_hubp), GFP_KERNEL); 985 986 if (!hubp1) 987 return NULL; 988 989 dcn10_hubp_construct(hubp1, ctx, inst, 990 &hubp_regs[inst], &hubp_shift, &hubp_mask); 991 return &hubp1->base; 992 } 993 994 static void get_pixel_clock_parameters( 995 const struct pipe_ctx *pipe_ctx, 996 struct pixel_clk_params *pixel_clk_params) 997 { 998 const struct dc_stream_state *stream = pipe_ctx->stream; 999 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 1000 pixel_clk_params->encoder_object_id = stream->link->link_enc->id; 1001 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 1002 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 1003 /* TODO: un-hardcode*/ 1004 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 1005 LINK_RATE_REF_FREQ_IN_KHZ; 1006 pixel_clk_params->flags.ENABLE_SS = 0; 1007 pixel_clk_params->color_depth = 1008 stream->timing.display_color_depth; 1009 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 1010 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 1011 1012 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 1013 pixel_clk_params->color_depth = COLOR_DEPTH_888; 1014 1015 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 1016 pixel_clk_params->requested_pix_clk_100hz /= 2; 1017 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 1018 pixel_clk_params->requested_pix_clk_100hz *= 2; 1019 1020 } 1021 1022 static void build_clamping_params(struct dc_stream_state *stream) 1023 { 1024 stream->clamping.clamping_level = CLAMPING_FULL_RANGE; 1025 stream->clamping.c_depth = stream->timing.display_color_depth; 1026 stream->clamping.pixel_encoding = stream->timing.pixel_encoding; 1027 } 1028 1029 static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 1030 { 1031 1032 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 1033 1034 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 1035 pipe_ctx->clock_source, 1036 &pipe_ctx->stream_res.pix_clk_params, 1037 &pipe_ctx->pll_settings); 1038 1039 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 1040 1041 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 1042 &pipe_ctx->stream->bit_depth_params); 1043 build_clamping_params(pipe_ctx->stream); 1044 } 1045 1046 static enum dc_status build_mapped_resource( 1047 const struct dc *dc, 1048 struct dc_state *context, 1049 struct dc_stream_state *stream) 1050 { 1051 struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream); 1052 1053 if (!pipe_ctx) 1054 return DC_ERROR_UNEXPECTED; 1055 1056 build_pipe_hw_param(pipe_ctx); 1057 return DC_OK; 1058 } 1059 1060 static enum dc_status dcn10_add_stream_to_ctx( 1061 struct dc *dc, 1062 struct dc_state *new_ctx, 1063 struct dc_stream_state *dc_stream) 1064 { 1065 enum dc_status result = DC_ERROR_UNEXPECTED; 1066 1067 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 1068 1069 if (result == DC_OK) 1070 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 1071 1072 1073 if (result == DC_OK) 1074 result = build_mapped_resource(dc, new_ctx, dc_stream); 1075 1076 return result; 1077 } 1078 1079 static struct pipe_ctx *dcn10_acquire_free_pipe_for_layer( 1080 const struct dc_state *cur_ctx, 1081 struct dc_state *new_ctx, 1082 const struct resource_pool *pool, 1083 const struct pipe_ctx *opp_head_pipe) 1084 { 1085 struct resource_context *res_ctx = &new_ctx->res_ctx; 1086 struct pipe_ctx *head_pipe = resource_get_otg_master_for_stream(res_ctx, opp_head_pipe->stream); 1087 struct pipe_ctx *idle_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, head_pipe); 1088 1089 if (!head_pipe) { 1090 ASSERT(0); 1091 return NULL; 1092 } 1093 1094 if (!idle_pipe) 1095 return NULL; 1096 1097 idle_pipe->stream = head_pipe->stream; 1098 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 1099 idle_pipe->stream_res.abm = head_pipe->stream_res.abm; 1100 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 1101 1102 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 1103 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 1104 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 1105 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 1106 1107 return idle_pipe; 1108 } 1109 1110 static bool dcn10_get_dcc_compression_cap(const struct dc *dc, 1111 const struct dc_dcc_surface_param *input, 1112 struct dc_surface_dcc_cap *output) 1113 { 1114 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap( 1115 dc->res_pool->hubbub, 1116 input, 1117 output); 1118 } 1119 1120 static void dcn10_destroy_resource_pool(struct resource_pool **pool) 1121 { 1122 struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool); 1123 1124 dcn10_resource_destruct(dcn10_pool); 1125 kfree(dcn10_pool); 1126 *pool = NULL; 1127 } 1128 1129 static enum dc_status dcn10_validate_bandwidth( 1130 struct dc *dc, 1131 struct dc_state *context, 1132 bool fast_validate) 1133 { 1134 bool voltage_supported; 1135 1136 DC_FP_START(); 1137 voltage_supported = dcn_validate_bandwidth(dc, context, fast_validate); 1138 DC_FP_END(); 1139 1140 return voltage_supported ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; 1141 } 1142 1143 static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) 1144 { 1145 if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN 1146 && caps->max_video_width != 0 1147 && plane_state->src_rect.width > caps->max_video_width) 1148 return DC_FAIL_SURFACE_VALIDATE; 1149 1150 return DC_OK; 1151 } 1152 1153 static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *context) 1154 { 1155 int i, j; 1156 bool video_down_scaled = false; 1157 bool video_large = false; 1158 bool desktop_large = false; 1159 bool dcc_disabled = false; 1160 bool mpo_enabled = false; 1161 1162 for (i = 0; i < context->stream_count; i++) { 1163 if (context->stream_status[i].plane_count == 0) 1164 continue; 1165 1166 if (context->stream_status[i].plane_count > 2) 1167 return DC_FAIL_UNSUPPORTED_1; 1168 1169 if (context->stream_status[i].plane_count > 1) 1170 mpo_enabled = true; 1171 1172 for (j = 0; j < context->stream_status[i].plane_count; j++) { 1173 struct dc_plane_state *plane = 1174 context->stream_status[i].plane_states[j]; 1175 1176 1177 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 1178 1179 if (plane->src_rect.width > plane->dst_rect.width || 1180 plane->src_rect.height > plane->dst_rect.height) 1181 video_down_scaled = true; 1182 1183 if (plane->src_rect.width >= 3840) 1184 video_large = true; 1185 1186 } else { 1187 if (plane->src_rect.width >= 3840) 1188 desktop_large = true; 1189 if (!plane->dcc.enable) 1190 dcc_disabled = true; 1191 } 1192 } 1193 } 1194 1195 /* Disable MPO in multi-display configurations. */ 1196 if (context->stream_count > 1 && mpo_enabled) 1197 return DC_FAIL_UNSUPPORTED_1; 1198 1199 /* 1200 * Workaround: On DCN10 there is UMC issue that causes underflow when 1201 * playing 4k video on 4k desktop with video downscaled and single channel 1202 * memory 1203 */ 1204 if (video_large && desktop_large && video_down_scaled && dcc_disabled && 1205 dc->dcn_soc->number_of_channels == 1) 1206 return DC_FAIL_SURFACE_VALIDATE; 1207 1208 return DC_OK; 1209 } 1210 1211 static enum dc_status dcn10_patch_unknown_plane_state(struct dc_plane_state *plane_state) 1212 { 1213 enum surface_pixel_format surf_pix_format = plane_state->format; 1214 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format); 1215 1216 enum swizzle_mode_values swizzle = DC_SW_LINEAR; 1217 1218 if (bpp == 64) 1219 swizzle = DC_SW_64KB_D; 1220 else 1221 swizzle = DC_SW_64KB_S; 1222 1223 plane_state->tiling_info.gfx9.swizzle = swizzle; 1224 return DC_OK; 1225 } 1226 1227 struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link( 1228 struct resource_context *res_ctx, 1229 const struct resource_pool *pool, 1230 struct dc_stream_state *stream) 1231 { 1232 int i; 1233 int j = -1; 1234 struct dc_link *link = stream->link; 1235 1236 for (i = 0; i < pool->stream_enc_count; i++) { 1237 if (!res_ctx->is_stream_enc_acquired[i] && 1238 pool->stream_enc[i]) { 1239 /* Store first available for MST second display 1240 * in daisy chain use case 1241 */ 1242 1243 if (pool->stream_enc[i]->id != ENGINE_ID_VIRTUAL) 1244 j = i; 1245 1246 if (link->ep_type == DISPLAY_ENDPOINT_PHY && pool->stream_enc[i]->id == 1247 link->link_enc->preferred_engine) 1248 return pool->stream_enc[i]; 1249 1250 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && pool->stream_enc[i]->id == 1251 link->dpia_preferred_eng_id) 1252 return pool->stream_enc[i]; 1253 } 1254 } 1255 1256 /* 1257 * For CZ and later, we can allow DIG FE and BE to differ for all display types 1258 */ 1259 1260 if (j >= 0) 1261 return pool->stream_enc[j]; 1262 1263 return NULL; 1264 } 1265 1266 unsigned int dcn10_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx) 1267 { 1268 return pipe_ctx->pipe_dlg_param.vstartup_start; 1269 } 1270 1271 static const struct dc_cap_funcs cap_funcs = { 1272 .get_dcc_compression_cap = dcn10_get_dcc_compression_cap 1273 }; 1274 1275 static const struct resource_funcs dcn10_res_pool_funcs = { 1276 .destroy = dcn10_destroy_resource_pool, 1277 .link_enc_create = dcn10_link_encoder_create, 1278 .panel_cntl_create = dcn10_panel_cntl_create, 1279 .validate_bandwidth = dcn10_validate_bandwidth, 1280 .acquire_free_pipe_as_secondary_dpp_pipe = dcn10_acquire_free_pipe_for_layer, 1281 .validate_plane = dcn10_validate_plane, 1282 .validate_global = dcn10_validate_global, 1283 .add_stream_to_ctx = dcn10_add_stream_to_ctx, 1284 .patch_unknown_plane_state = dcn10_patch_unknown_plane_state, 1285 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1286 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe 1287 }; 1288 1289 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1290 { 1291 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); 1292 /* RV1 support max 4 pipes */ 1293 value = value & 0xf; 1294 return value; 1295 } 1296 1297 static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks) 1298 { 1299 int i; 1300 1301 if (clks->num_levels == 0) 1302 return false; 1303 1304 for (i = 0; i < clks->num_levels; i++) 1305 /* Ensure that the result is sane */ 1306 if (clks->data[i].clocks_in_khz == 0) 1307 return false; 1308 1309 return true; 1310 } 1311 1312 static bool dcn10_resource_construct( 1313 uint8_t num_virtual_links, 1314 struct dc *dc, 1315 struct dcn10_resource_pool *pool) 1316 { 1317 int i; 1318 int j; 1319 struct dc_context *ctx = dc->ctx; 1320 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1321 struct dm_pp_clock_levels_with_voltage fclks = {0}, dcfclks = {0}; 1322 int min_fclk_khz, min_dcfclk_khz, socclk_khz; 1323 bool res; 1324 1325 ctx->dc_bios->regs = &bios_regs; 1326 1327 if (ctx->dce_version == DCN_VERSION_1_01) 1328 pool->base.res_cap = &rv2_res_cap; 1329 else 1330 pool->base.res_cap = &res_cap; 1331 pool->base.funcs = &dcn10_res_pool_funcs; 1332 1333 /* 1334 * TODO fill in from actual raven resource when we create 1335 * more than virtual encoder 1336 */ 1337 1338 /************************************************* 1339 * Resource + asic cap harcoding * 1340 *************************************************/ 1341 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1342 1343 /* max pipe num for ASIC before check pipe fuses */ 1344 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1345 1346 if (dc->ctx->dce_version == DCN_VERSION_1_01) 1347 pool->base.pipe_count = 3; 1348 dc->caps.max_video_width = 3840; 1349 dc->caps.max_downscale_ratio = 200; 1350 dc->caps.i2c_speed_in_khz = 100; 1351 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/ 1352 dc->caps.max_cursor_size = 256; 1353 dc->caps.min_horizontal_blanking_period = 80; 1354 dc->caps.max_slave_planes = 1; 1355 dc->caps.max_slave_yuv_planes = 1; 1356 dc->caps.max_slave_rgb_planes = 0; 1357 dc->caps.is_apu = true; 1358 dc->caps.post_blend_color_processing = false; 1359 dc->caps.extended_aux_timeout_support = false; 1360 1361 /* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */ 1362 dc->caps.force_dp_tps4_for_cp2520 = true; 1363 1364 /* Color pipeline capabilities */ 1365 dc->caps.color.dpp.dcn_arch = 1; 1366 dc->caps.color.dpp.input_lut_shared = 1; 1367 dc->caps.color.dpp.icsc = 1; 1368 dc->caps.color.dpp.dgam_ram = 1; 1369 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1370 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1371 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0; 1372 dc->caps.color.dpp.dgam_rom_caps.pq = 0; 1373 dc->caps.color.dpp.dgam_rom_caps.hlg = 0; 1374 dc->caps.color.dpp.post_csc = 0; 1375 dc->caps.color.dpp.gamma_corr = 0; 1376 dc->caps.color.dpp.dgam_rom_for_yuv = 1; 1377 1378 dc->caps.color.dpp.hw_3d_lut = 0; 1379 dc->caps.color.dpp.ogam_ram = 1; // RGAM on DCN1 1380 dc->caps.color.dpp.ogam_rom_caps.srgb = 1; 1381 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 1; 1382 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1383 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1384 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1385 dc->caps.color.dpp.ocsc = 1; 1386 1387 /* no post-blend color operations */ 1388 dc->caps.color.mpc.gamut_remap = 0; 1389 dc->caps.color.mpc.num_3dluts = 0; 1390 dc->caps.color.mpc.shared_3d_lut = 0; 1391 dc->caps.color.mpc.ogam_ram = 0; 1392 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1393 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1394 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1395 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1396 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1397 dc->caps.color.mpc.ocsc = 0; 1398 1399 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1400 dc->debug = debug_defaults_drv; 1401 1402 /************************************************* 1403 * Create resources * 1404 *************************************************/ 1405 1406 pool->base.clock_sources[DCN10_CLK_SRC_PLL0] = 1407 dcn10_clock_source_create(ctx, ctx->dc_bios, 1408 CLOCK_SOURCE_COMBO_PHY_PLL0, 1409 &clk_src_regs[0], false); 1410 pool->base.clock_sources[DCN10_CLK_SRC_PLL1] = 1411 dcn10_clock_source_create(ctx, ctx->dc_bios, 1412 CLOCK_SOURCE_COMBO_PHY_PLL1, 1413 &clk_src_regs[1], false); 1414 pool->base.clock_sources[DCN10_CLK_SRC_PLL2] = 1415 dcn10_clock_source_create(ctx, ctx->dc_bios, 1416 CLOCK_SOURCE_COMBO_PHY_PLL2, 1417 &clk_src_regs[2], false); 1418 1419 if (dc->ctx->dce_version == DCN_VERSION_1_0) { 1420 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] = 1421 dcn10_clock_source_create(ctx, ctx->dc_bios, 1422 CLOCK_SOURCE_COMBO_PHY_PLL3, 1423 &clk_src_regs[3], false); 1424 } 1425 1426 pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL; 1427 1428 if (dc->ctx->dce_version == DCN_VERSION_1_01) 1429 pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL; 1430 1431 pool->base.dp_clock_source = 1432 dcn10_clock_source_create(ctx, ctx->dc_bios, 1433 CLOCK_SOURCE_ID_DP_DTO, 1434 /* todo: not reuse phy_pll registers */ 1435 &clk_src_regs[0], true); 1436 1437 for (i = 0; i < pool->base.clk_src_count; i++) { 1438 if (pool->base.clock_sources[i] == NULL) { 1439 dm_error("DC: failed to create clock sources!\n"); 1440 BREAK_TO_DEBUGGER(); 1441 goto fail; 1442 } 1443 } 1444 1445 pool->base.dmcu = dcn10_dmcu_create(ctx, 1446 &dmcu_regs, 1447 &dmcu_shift, 1448 &dmcu_mask); 1449 if (pool->base.dmcu == NULL) { 1450 dm_error("DC: failed to create dmcu!\n"); 1451 BREAK_TO_DEBUGGER(); 1452 goto fail; 1453 } 1454 1455 pool->base.abm = dce_abm_create(ctx, 1456 &abm_regs, 1457 &abm_shift, 1458 &abm_mask); 1459 if (pool->base.abm == NULL) { 1460 dm_error("DC: failed to create abm!\n"); 1461 BREAK_TO_DEBUGGER(); 1462 goto fail; 1463 } 1464 1465 dml_init_instance(&dc->dml, &dcn1_0_soc, &dcn1_0_ip, DML_PROJECT_RAVEN1); 1466 memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults)); 1467 memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults)); 1468 1469 DC_FP_START(); 1470 dcn10_resource_construct_fp(dc); 1471 DC_FP_END(); 1472 1473 if (!dc->config.is_vmin_only_asic) 1474 if (ASICREV_IS_RAVEN2(dc->ctx->asic_id.hw_internal_rev)) 1475 switch (dc->ctx->asic_id.pci_revision_id) { 1476 case PRID_DALI_DE: 1477 case PRID_DALI_DF: 1478 case PRID_DALI_E3: 1479 case PRID_DALI_E4: 1480 case PRID_POLLOCK_94: 1481 case PRID_POLLOCK_95: 1482 case PRID_POLLOCK_E9: 1483 case PRID_POLLOCK_EA: 1484 case PRID_POLLOCK_EB: 1485 dc->config.is_vmin_only_asic = true; 1486 break; 1487 default: 1488 break; 1489 } 1490 1491 pool->base.pp_smu = dcn10_pp_smu_create(ctx); 1492 1493 /* 1494 * Right now SMU/PPLIB and DAL all have the AZ D3 force PME notification * 1495 * implemented. So AZ D3 should work.For issue 197007. * 1496 */ 1497 if (pool->base.pp_smu != NULL 1498 && pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL) 1499 dc->debug.az_endpoint_mute_only = false; 1500 1501 1502 if (!dc->debug.disable_pplib_clock_request) { 1503 /* 1504 * TODO: This is not the proper way to obtain 1505 * fabric_and_dram_bandwidth, should be min(fclk, memclk). 1506 */ 1507 res = dm_pp_get_clock_levels_by_type_with_voltage( 1508 ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks); 1509 1510 DC_FP_START(); 1511 1512 if (res) 1513 res = verify_clock_values(&fclks); 1514 1515 if (res) 1516 dcn_bw_update_from_pplib_fclks(dc, &fclks); 1517 else 1518 BREAK_TO_DEBUGGER(); 1519 1520 DC_FP_END(); 1521 1522 res = dm_pp_get_clock_levels_by_type_with_voltage( 1523 ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks); 1524 1525 DC_FP_START(); 1526 1527 if (res) 1528 res = verify_clock_values(&dcfclks); 1529 1530 if (res) 1531 dcn_bw_update_from_pplib_dcfclks(dc, &dcfclks); 1532 else 1533 BREAK_TO_DEBUGGER(); 1534 1535 DC_FP_END(); 1536 } 1537 1538 dcn_bw_sync_calcs_and_dml(dc); 1539 if (!dc->debug.disable_pplib_wm_range) { 1540 dc->res_pool = &pool->base; 1541 DC_FP_START(); 1542 dcn_get_soc_clks( 1543 dc, &min_fclk_khz, &min_dcfclk_khz, &socclk_khz); 1544 DC_FP_END(); 1545 dcn_bw_notify_pplib_of_wm_ranges( 1546 dc, min_fclk_khz, min_dcfclk_khz, socclk_khz); 1547 } 1548 1549 { 1550 struct irq_service_init_data init_data; 1551 init_data.ctx = dc->ctx; 1552 pool->base.irqs = dal_irq_service_dcn10_create(&init_data); 1553 if (!pool->base.irqs) 1554 goto fail; 1555 } 1556 1557 /* index to valid pipe resource */ 1558 j = 0; 1559 /* mem input -> ipp -> dpp -> opp -> TG */ 1560 for (i = 0; i < pool->base.pipe_count; i++) { 1561 /* if pipe is disabled, skip instance of HW pipe, 1562 * i.e, skip ASIC register instance 1563 */ 1564 if ((pipe_fuses & (1 << i)) != 0) 1565 continue; 1566 1567 pool->base.hubps[j] = dcn10_hubp_create(ctx, i); 1568 if (pool->base.hubps[j] == NULL) { 1569 BREAK_TO_DEBUGGER(); 1570 dm_error( 1571 "DC: failed to create memory input!\n"); 1572 goto fail; 1573 } 1574 1575 pool->base.ipps[j] = dcn10_ipp_create(ctx, i); 1576 if (pool->base.ipps[j] == NULL) { 1577 BREAK_TO_DEBUGGER(); 1578 dm_error( 1579 "DC: failed to create input pixel processor!\n"); 1580 goto fail; 1581 } 1582 1583 pool->base.dpps[j] = dcn10_dpp_create(ctx, i); 1584 if (pool->base.dpps[j] == NULL) { 1585 BREAK_TO_DEBUGGER(); 1586 dm_error( 1587 "DC: failed to create dpp!\n"); 1588 goto fail; 1589 } 1590 1591 pool->base.opps[j] = dcn10_opp_create(ctx, i); 1592 if (pool->base.opps[j] == NULL) { 1593 BREAK_TO_DEBUGGER(); 1594 dm_error( 1595 "DC: failed to create output pixel processor!\n"); 1596 goto fail; 1597 } 1598 1599 pool->base.timing_generators[j] = dcn10_timing_generator_create( 1600 ctx, i); 1601 if (pool->base.timing_generators[j] == NULL) { 1602 BREAK_TO_DEBUGGER(); 1603 dm_error("DC: failed to create tg!\n"); 1604 goto fail; 1605 } 1606 /* check next valid pipe */ 1607 j++; 1608 } 1609 1610 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1611 pool->base.engines[i] = dcn10_aux_engine_create(ctx, i); 1612 if (pool->base.engines[i] == NULL) { 1613 BREAK_TO_DEBUGGER(); 1614 dm_error( 1615 "DC:failed to create aux engine!!\n"); 1616 goto fail; 1617 } 1618 pool->base.hw_i2cs[i] = dcn10_i2c_hw_create(ctx, i); 1619 if (pool->base.hw_i2cs[i] == NULL) { 1620 BREAK_TO_DEBUGGER(); 1621 dm_error( 1622 "DC:failed to create hw i2c!!\n"); 1623 goto fail; 1624 } 1625 pool->base.sw_i2cs[i] = NULL; 1626 } 1627 1628 /* valid pipe num */ 1629 pool->base.pipe_count = j; 1630 pool->base.timing_generator_count = j; 1631 pool->base.mpcc_count = j; 1632 1633 /* within dml lib, it is hard code to 4. If ASIC pipe is fused, 1634 * the value may be changed 1635 */ 1636 dc->dml.ip.max_num_dpp = pool->base.pipe_count; 1637 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; 1638 1639 pool->base.mpc = dcn10_mpc_create(ctx); 1640 if (pool->base.mpc == NULL) { 1641 BREAK_TO_DEBUGGER(); 1642 dm_error("DC: failed to create mpc!\n"); 1643 goto fail; 1644 } 1645 1646 pool->base.hubbub = dcn10_hubbub_create(ctx); 1647 if (pool->base.hubbub == NULL) { 1648 BREAK_TO_DEBUGGER(); 1649 dm_error("DC: failed to create hubbub!\n"); 1650 goto fail; 1651 } 1652 1653 if (!resource_construct(num_virtual_links, dc, &pool->base, 1654 &res_create_funcs)) 1655 goto fail; 1656 1657 dcn10_hw_sequencer_construct(dc); 1658 dc->caps.max_planes = pool->base.pipe_count; 1659 1660 for (i = 0; i < dc->caps.max_planes; ++i) 1661 dc->caps.planes[i] = plane_cap; 1662 1663 dc->cap_funcs = cap_funcs; 1664 1665 return true; 1666 1667 fail: 1668 1669 dcn10_resource_destruct(pool); 1670 1671 return false; 1672 } 1673 1674 struct resource_pool *dcn10_create_resource_pool( 1675 const struct dc_init_data *init_data, 1676 struct dc *dc) 1677 { 1678 struct dcn10_resource_pool *pool = 1679 kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL); 1680 1681 if (!pool) 1682 return NULL; 1683 1684 if (dcn10_resource_construct(init_data->num_virtual_links, dc, pool)) 1685 return &pool->base; 1686 1687 kfree(pool); 1688 BREAK_TO_DEBUGGER(); 1689 return NULL; 1690 } 1691