1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dce/dce_8_0_d.h" 27 #include "dce/dce_8_0_sh_mask.h" 28 29 #include "dm_services.h" 30 31 #include "link_encoder.h" 32 #include "stream_encoder.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "irq/dce80/irq_service_dce80.h" 37 #include "dce110/dce110_timing_generator.h" 38 #include "dce110/dce110_resource.h" 39 #include "dce80/dce80_timing_generator.h" 40 #include "dce/dce_mem_input.h" 41 #include "dce/dce_link_encoder.h" 42 #include "dce/dce_stream_encoder.h" 43 #include "dce/dce_ipp.h" 44 #include "dce/dce_transform.h" 45 #include "dce/dce_opp.h" 46 #include "dce/dce_clock_source.h" 47 #include "dce/dce_audio.h" 48 #include "dce/dce_hwseq.h" 49 #include "dce80/dce80_hwseq.h" 50 #include "dce100/dce100_resource.h" 51 #include "dce/dce_panel_cntl.h" 52 53 #include "reg_helper.h" 54 55 #include "dce/dce_dmcu.h" 56 #include "dce/dce_aux.h" 57 #include "dce/dce_abm.h" 58 #include "dce/dce_i2c.h" 59 60 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 61 #include "gmc/gmc_7_1_d.h" 62 #include "gmc/gmc_7_1_sh_mask.h" 63 #endif 64 65 #include "dce80/dce80_resource.h" 66 67 #ifndef mmDP_DPHY_INTERNAL_CTRL 68 #define mmDP_DPHY_INTERNAL_CTRL 0x1CDE 69 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE 70 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE 71 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE 72 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE 73 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE 74 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE 75 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x4EDE 76 #endif 77 78 79 #ifndef mmBIOS_SCRATCH_2 80 #define mmBIOS_SCRATCH_2 0x05CB 81 #define mmBIOS_SCRATCH_3 0x05CC 82 #define mmBIOS_SCRATCH_6 0x05CF 83 #endif 84 85 #ifndef mmDP_DPHY_FAST_TRAINING 86 #define mmDP_DPHY_FAST_TRAINING 0x1CCE 87 #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE 88 #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE 89 #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE 90 #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE 91 #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE 92 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE 93 #define mmDP6_DP_DPHY_FAST_TRAINING 0x4ECE 94 #endif 95 96 97 #ifndef mmHPD_DC_HPD_CONTROL 98 #define mmHPD_DC_HPD_CONTROL 0x189A 99 #define mmHPD0_DC_HPD_CONTROL 0x189A 100 #define mmHPD1_DC_HPD_CONTROL 0x18A2 101 #define mmHPD2_DC_HPD_CONTROL 0x18AA 102 #define mmHPD3_DC_HPD_CONTROL 0x18B2 103 #define mmHPD4_DC_HPD_CONTROL 0x18BA 104 #define mmHPD5_DC_HPD_CONTROL 0x18C2 105 #endif 106 107 #define DCE11_DIG_FE_CNTL 0x4a00 108 #define DCE11_DIG_BE_CNTL 0x4a47 109 #define DCE11_DP_SEC 0x4ac3 110 111 static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = { 112 { 113 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 114 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL), 115 .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 116 - mmDPG_WATERMARK_MASK_CONTROL), 117 }, 118 { 119 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 120 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 121 .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 122 - mmDPG_WATERMARK_MASK_CONTROL), 123 }, 124 { 125 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 126 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 127 .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 128 - mmDPG_WATERMARK_MASK_CONTROL), 129 }, 130 { 131 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 132 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 133 .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 134 - mmDPG_WATERMARK_MASK_CONTROL), 135 }, 136 { 137 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 138 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 139 .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 140 - mmDPG_WATERMARK_MASK_CONTROL), 141 }, 142 { 143 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 144 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 145 .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 146 - mmDPG_WATERMARK_MASK_CONTROL), 147 } 148 }; 149 150 /* set register offset */ 151 #define SR(reg_name)\ 152 .reg_name = mm ## reg_name 153 154 /* set register offset with instance */ 155 #define SRI(reg_name, block, id)\ 156 .reg_name = mm ## block ## id ## _ ## reg_name 157 158 #define ipp_regs(id)\ 159 [id] = {\ 160 IPP_COMMON_REG_LIST_DCE_BASE(id)\ 161 } 162 163 static const struct dce_ipp_registers ipp_regs[] = { 164 ipp_regs(0), 165 ipp_regs(1), 166 ipp_regs(2), 167 ipp_regs(3), 168 ipp_regs(4), 169 ipp_regs(5) 170 }; 171 172 static const struct dce_ipp_shift ipp_shift = { 173 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 174 }; 175 176 static const struct dce_ipp_mask ipp_mask = { 177 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 178 }; 179 180 #define transform_regs(id)\ 181 [id] = {\ 182 XFM_COMMON_REG_LIST_DCE80(id)\ 183 } 184 185 static const struct dce_transform_registers xfm_regs[] = { 186 transform_regs(0), 187 transform_regs(1), 188 transform_regs(2), 189 transform_regs(3), 190 transform_regs(4), 191 transform_regs(5) 192 }; 193 194 static const struct dce_transform_shift xfm_shift = { 195 XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT) 196 }; 197 198 static const struct dce_transform_mask xfm_mask = { 199 XFM_COMMON_MASK_SH_LIST_DCE80(_MASK) 200 }; 201 202 #define aux_regs(id)\ 203 [id] = {\ 204 AUX_REG_LIST(id)\ 205 } 206 207 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 208 aux_regs(0), 209 aux_regs(1), 210 aux_regs(2), 211 aux_regs(3), 212 aux_regs(4), 213 aux_regs(5) 214 }; 215 216 #define hpd_regs(id)\ 217 [id] = {\ 218 HPD_REG_LIST(id)\ 219 } 220 221 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 222 hpd_regs(0), 223 hpd_regs(1), 224 hpd_regs(2), 225 hpd_regs(3), 226 hpd_regs(4), 227 hpd_regs(5) 228 }; 229 230 #define link_regs(id)\ 231 [id] = {\ 232 LE_DCE80_REG_LIST(id)\ 233 } 234 235 static const struct dce110_link_enc_registers link_enc_regs[] = { 236 link_regs(0), 237 link_regs(1), 238 link_regs(2), 239 link_regs(3), 240 link_regs(4), 241 link_regs(5), 242 link_regs(6), 243 }; 244 245 #define stream_enc_regs(id)\ 246 [id] = {\ 247 SE_COMMON_REG_LIST_DCE_BASE(id),\ 248 .AFMT_CNTL = 0,\ 249 } 250 251 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 252 stream_enc_regs(0), 253 stream_enc_regs(1), 254 stream_enc_regs(2), 255 stream_enc_regs(3), 256 stream_enc_regs(4), 257 stream_enc_regs(5), 258 stream_enc_regs(6) 259 }; 260 261 static const struct dce_stream_encoder_shift se_shift = { 262 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT) 263 }; 264 265 static const struct dce_stream_encoder_mask se_mask = { 266 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) 267 }; 268 269 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 270 { DCE_PANEL_CNTL_REG_LIST() } 271 }; 272 273 static const struct dce_panel_cntl_shift panel_cntl_shift = { 274 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 275 }; 276 277 static const struct dce_panel_cntl_mask panel_cntl_mask = { 278 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 279 }; 280 281 #define opp_regs(id)\ 282 [id] = {\ 283 OPP_DCE_80_REG_LIST(id),\ 284 } 285 286 static const struct dce_opp_registers opp_regs[] = { 287 opp_regs(0), 288 opp_regs(1), 289 opp_regs(2), 290 opp_regs(3), 291 opp_regs(4), 292 opp_regs(5) 293 }; 294 295 static const struct dce_opp_shift opp_shift = { 296 OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT) 297 }; 298 299 static const struct dce_opp_mask opp_mask = { 300 OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK) 301 }; 302 303 static const struct dce110_aux_registers_shift aux_shift = { 304 DCE10_AUX_MASK_SH_LIST(__SHIFT) 305 }; 306 307 static const struct dce110_aux_registers_mask aux_mask = { 308 DCE10_AUX_MASK_SH_LIST(_MASK) 309 }; 310 311 #define aux_engine_regs(id)\ 312 [id] = {\ 313 AUX_COMMON_REG_LIST(id), \ 314 .AUX_RESET_MASK = 0 \ 315 } 316 317 static const struct dce110_aux_registers aux_engine_regs[] = { 318 aux_engine_regs(0), 319 aux_engine_regs(1), 320 aux_engine_regs(2), 321 aux_engine_regs(3), 322 aux_engine_regs(4), 323 aux_engine_regs(5) 324 }; 325 326 #define audio_regs(id)\ 327 [id] = {\ 328 AUD_COMMON_REG_LIST(id)\ 329 } 330 331 static const struct dce_audio_registers audio_regs[] = { 332 audio_regs(0), 333 audio_regs(1), 334 audio_regs(2), 335 audio_regs(3), 336 audio_regs(4), 337 audio_regs(5), 338 audio_regs(6), 339 }; 340 341 static const struct dce_audio_shift audio_shift = { 342 AUD_COMMON_MASK_SH_LIST(__SHIFT) 343 }; 344 345 static const struct dce_audio_mask audio_mask = { 346 AUD_COMMON_MASK_SH_LIST(_MASK) 347 }; 348 349 #define clk_src_regs(id)\ 350 [id] = {\ 351 CS_COMMON_REG_LIST_DCE_80(id),\ 352 } 353 354 355 static const struct dce110_clk_src_regs clk_src_regs[] = { 356 clk_src_regs(0), 357 clk_src_regs(1), 358 clk_src_regs(2) 359 }; 360 361 static const struct dce110_clk_src_shift cs_shift = { 362 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 363 }; 364 365 static const struct dce110_clk_src_mask cs_mask = { 366 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 367 }; 368 369 static const struct bios_registers bios_regs = { 370 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 371 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 372 }; 373 374 static const struct resource_caps res_cap = { 375 .num_timing_generator = 6, 376 .num_audio = 6, 377 .num_stream_encoder = 6, 378 .num_pll = 3, 379 .num_ddc = 6, 380 }; 381 382 static const struct resource_caps res_cap_81 = { 383 .num_timing_generator = 4, 384 .num_audio = 7, 385 .num_stream_encoder = 7, 386 .num_pll = 3, 387 .num_ddc = 6, 388 }; 389 390 static const struct resource_caps res_cap_83 = { 391 .num_timing_generator = 2, 392 .num_audio = 6, 393 .num_stream_encoder = 6, 394 .num_pll = 2, 395 .num_ddc = 2, 396 }; 397 398 static const struct dc_plane_cap plane_cap = { 399 .type = DC_PLANE_TYPE_DCE_RGB, 400 401 .pixel_format_support = { 402 .argb8888 = true, 403 .nv12 = false, 404 .fp16 = true 405 }, 406 407 .max_upscale_factor = { 408 .argb8888 = 16000, 409 .nv12 = 1, 410 .fp16 = 1 411 }, 412 413 .max_downscale_factor = { 414 .argb8888 = 250, 415 .nv12 = 1, 416 .fp16 = 1 417 } 418 }; 419 420 static const struct dc_debug_options debug_defaults = { 421 .enable_legacy_fast_update = true, 422 }; 423 424 static const struct dce_dmcu_registers dmcu_regs = { 425 DMCU_DCE80_REG_LIST() 426 }; 427 428 static const struct dce_dmcu_shift dmcu_shift = { 429 DMCU_MASK_SH_LIST_DCE80(__SHIFT) 430 }; 431 432 static const struct dce_dmcu_mask dmcu_mask = { 433 DMCU_MASK_SH_LIST_DCE80(_MASK) 434 }; 435 static const struct dce_abm_registers abm_regs = { 436 ABM_DCE110_COMMON_REG_LIST() 437 }; 438 439 static const struct dce_abm_shift abm_shift = { 440 ABM_MASK_SH_LIST_DCE110(__SHIFT) 441 }; 442 443 static const struct dce_abm_mask abm_mask = { 444 ABM_MASK_SH_LIST_DCE110(_MASK) 445 }; 446 447 #define CTX ctx 448 #define REG(reg) mm ## reg 449 450 #ifndef mmCC_DC_HDMI_STRAPS 451 #define mmCC_DC_HDMI_STRAPS 0x1918 452 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 453 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 454 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 455 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 456 #endif 457 458 static int map_transmitter_id_to_phy_instance( 459 enum transmitter transmitter) 460 { 461 switch (transmitter) { 462 case TRANSMITTER_UNIPHY_A: 463 return 0; 464 case TRANSMITTER_UNIPHY_B: 465 return 1; 466 case TRANSMITTER_UNIPHY_C: 467 return 2; 468 case TRANSMITTER_UNIPHY_D: 469 return 3; 470 case TRANSMITTER_UNIPHY_E: 471 return 4; 472 case TRANSMITTER_UNIPHY_F: 473 return 5; 474 case TRANSMITTER_UNIPHY_G: 475 return 6; 476 default: 477 ASSERT(0); 478 return 0; 479 } 480 } 481 482 static void read_dce_straps( 483 struct dc_context *ctx, 484 struct resource_straps *straps) 485 { 486 REG_GET_2(CC_DC_HDMI_STRAPS, 487 HDMI_DISABLE, &straps->hdmi_disable, 488 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 489 490 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 491 } 492 493 static struct audio *create_audio( 494 struct dc_context *ctx, unsigned int inst) 495 { 496 return dce_audio_create(ctx, inst, 497 &audio_regs[inst], &audio_shift, &audio_mask); 498 } 499 500 static struct timing_generator *dce80_timing_generator_create( 501 struct dc_context *ctx, 502 uint32_t instance, 503 const struct dce110_timing_generator_offsets *offsets) 504 { 505 struct dce110_timing_generator *tg110 = 506 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 507 508 if (!tg110) 509 return NULL; 510 511 dce80_timing_generator_construct(tg110, ctx, instance, offsets); 512 return &tg110->base; 513 } 514 515 static struct output_pixel_processor *dce80_opp_create( 516 struct dc_context *ctx, 517 uint32_t inst) 518 { 519 struct dce110_opp *opp = 520 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 521 522 if (!opp) 523 return NULL; 524 525 dce110_opp_construct(opp, 526 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 527 return &opp->base; 528 } 529 530 static struct dce_aux *dce80_aux_engine_create( 531 struct dc_context *ctx, 532 uint32_t inst) 533 { 534 struct aux_engine_dce110 *aux_engine = 535 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 536 537 if (!aux_engine) 538 return NULL; 539 540 dce110_aux_engine_construct(aux_engine, ctx, inst, 541 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 542 &aux_engine_regs[inst], 543 &aux_mask, 544 &aux_shift, 545 ctx->dc->caps.extended_aux_timeout_support); 546 547 return &aux_engine->base; 548 } 549 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 550 551 static const struct dce_i2c_registers i2c_hw_regs[] = { 552 i2c_inst_regs(1), 553 i2c_inst_regs(2), 554 i2c_inst_regs(3), 555 i2c_inst_regs(4), 556 i2c_inst_regs(5), 557 i2c_inst_regs(6), 558 }; 559 560 static const struct dce_i2c_shift i2c_shifts = { 561 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 562 }; 563 564 static const struct dce_i2c_mask i2c_masks = { 565 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 566 }; 567 568 static struct dce_i2c_hw *dce80_i2c_hw_create( 569 struct dc_context *ctx, 570 uint32_t inst) 571 { 572 struct dce_i2c_hw *dce_i2c_hw = 573 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 574 575 if (!dce_i2c_hw) 576 return NULL; 577 578 dce_i2c_hw_construct(dce_i2c_hw, ctx, inst, 579 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 580 581 return dce_i2c_hw; 582 } 583 584 static struct dce_i2c_sw *dce80_i2c_sw_create( 585 struct dc_context *ctx) 586 { 587 struct dce_i2c_sw *dce_i2c_sw = 588 kzalloc(sizeof(struct dce_i2c_sw), GFP_KERNEL); 589 590 if (!dce_i2c_sw) 591 return NULL; 592 593 dce_i2c_sw_construct(dce_i2c_sw, ctx); 594 595 return dce_i2c_sw; 596 } 597 static struct stream_encoder *dce80_stream_encoder_create( 598 enum engine_id eng_id, 599 struct dc_context *ctx) 600 { 601 struct dce110_stream_encoder *enc110 = 602 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 603 604 if (!enc110) 605 return NULL; 606 607 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 608 &stream_enc_regs[eng_id], 609 &se_shift, &se_mask); 610 return &enc110->base; 611 } 612 613 #define SRII(reg_name, block, id)\ 614 .reg_name[id] = mm ## block ## id ## _ ## reg_name 615 616 static const struct dce_hwseq_registers hwseq_reg = { 617 HWSEQ_DCE8_REG_LIST() 618 }; 619 620 static const struct dce_hwseq_shift hwseq_shift = { 621 HWSEQ_DCE8_MASK_SH_LIST(__SHIFT) 622 }; 623 624 static const struct dce_hwseq_mask hwseq_mask = { 625 HWSEQ_DCE8_MASK_SH_LIST(_MASK) 626 }; 627 628 static struct dce_hwseq *dce80_hwseq_create( 629 struct dc_context *ctx) 630 { 631 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 632 633 if (hws) { 634 hws->ctx = ctx; 635 hws->regs = &hwseq_reg; 636 hws->shifts = &hwseq_shift; 637 hws->masks = &hwseq_mask; 638 } 639 return hws; 640 } 641 642 static const struct resource_create_funcs res_create_funcs = { 643 .read_dce_straps = read_dce_straps, 644 .create_audio = create_audio, 645 .create_stream_encoder = dce80_stream_encoder_create, 646 .create_hwseq = dce80_hwseq_create, 647 }; 648 649 #define mi_inst_regs(id) { \ 650 MI_DCE8_REG_LIST(id), \ 651 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 652 } 653 static const struct dce_mem_input_registers mi_regs[] = { 654 mi_inst_regs(0), 655 mi_inst_regs(1), 656 mi_inst_regs(2), 657 mi_inst_regs(3), 658 mi_inst_regs(4), 659 mi_inst_regs(5), 660 }; 661 662 static const struct dce_mem_input_shift mi_shifts = { 663 MI_DCE8_MASK_SH_LIST(__SHIFT), 664 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 665 }; 666 667 static const struct dce_mem_input_mask mi_masks = { 668 MI_DCE8_MASK_SH_LIST(_MASK), 669 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 670 }; 671 672 static struct mem_input *dce80_mem_input_create( 673 struct dc_context *ctx, 674 uint32_t inst) 675 { 676 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 677 GFP_KERNEL); 678 679 if (!dce_mi) { 680 BREAK_TO_DEBUGGER(); 681 return NULL; 682 } 683 684 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 685 dce_mi->wa.single_head_rdreq_dmif_limit = 2; 686 return &dce_mi->base; 687 } 688 689 static void dce80_transform_destroy(struct transform **xfm) 690 { 691 kfree(TO_DCE_TRANSFORM(*xfm)); 692 *xfm = NULL; 693 } 694 695 static struct transform *dce80_transform_create( 696 struct dc_context *ctx, 697 uint32_t inst) 698 { 699 struct dce_transform *transform = 700 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 701 702 if (!transform) 703 return NULL; 704 705 dce_transform_construct(transform, ctx, inst, 706 &xfm_regs[inst], &xfm_shift, &xfm_mask); 707 transform->prescaler_on = false; 708 return &transform->base; 709 } 710 711 static const struct encoder_feature_support link_enc_feature = { 712 .max_hdmi_deep_color = COLOR_DEPTH_121212, 713 .max_hdmi_pixel_clock = 297000, 714 .flags.bits.IS_HBR2_CAPABLE = true, 715 .flags.bits.IS_TPS3_CAPABLE = true 716 }; 717 718 static struct link_encoder *dce80_link_encoder_create( 719 struct dc_context *ctx, 720 const struct encoder_init_data *enc_init_data) 721 { 722 struct dce110_link_encoder *enc110 = 723 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 724 int link_regs_id; 725 726 if (!enc110 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) 727 return NULL; 728 729 link_regs_id = 730 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 731 732 dce110_link_encoder_construct(enc110, 733 enc_init_data, 734 &link_enc_feature, 735 &link_enc_regs[link_regs_id], 736 &link_enc_aux_regs[enc_init_data->channel - 1], 737 &link_enc_hpd_regs[enc_init_data->hpd_source]); 738 return &enc110->base; 739 } 740 741 static struct panel_cntl *dce80_panel_cntl_create(const struct panel_cntl_init_data *init_data) 742 { 743 struct dce_panel_cntl *panel_cntl = 744 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 745 746 if (!panel_cntl) 747 return NULL; 748 749 dce_panel_cntl_construct(panel_cntl, 750 init_data, 751 &panel_cntl_regs[init_data->inst], 752 &panel_cntl_shift, 753 &panel_cntl_mask); 754 755 return &panel_cntl->base; 756 } 757 758 static struct clock_source *dce80_clock_source_create( 759 struct dc_context *ctx, 760 struct dc_bios *bios, 761 enum clock_source_id id, 762 const struct dce110_clk_src_regs *regs, 763 bool dp_clk_src) 764 { 765 struct dce110_clk_src *clk_src = 766 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 767 768 if (!clk_src) 769 return NULL; 770 771 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 772 regs, &cs_shift, &cs_mask)) { 773 clk_src->base.dp_clk_src = dp_clk_src; 774 return &clk_src->base; 775 } 776 777 kfree(clk_src); 778 BREAK_TO_DEBUGGER(); 779 return NULL; 780 } 781 782 static void dce80_clock_source_destroy(struct clock_source **clk_src) 783 { 784 kfree(TO_DCE110_CLK_SRC(*clk_src)); 785 *clk_src = NULL; 786 } 787 788 static struct input_pixel_processor *dce80_ipp_create( 789 struct dc_context *ctx, uint32_t inst) 790 { 791 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 792 793 if (!ipp) { 794 BREAK_TO_DEBUGGER(); 795 return NULL; 796 } 797 798 dce_ipp_construct(ipp, ctx, inst, 799 &ipp_regs[inst], &ipp_shift, &ipp_mask); 800 return &ipp->base; 801 } 802 803 static void dce80_resource_destruct(struct dce110_resource_pool *pool) 804 { 805 unsigned int i; 806 807 for (i = 0; i < pool->base.pipe_count; i++) { 808 if (pool->base.opps[i] != NULL) 809 dce110_opp_destroy(&pool->base.opps[i]); 810 811 if (pool->base.transforms[i] != NULL) 812 dce80_transform_destroy(&pool->base.transforms[i]); 813 814 if (pool->base.ipps[i] != NULL) 815 dce_ipp_destroy(&pool->base.ipps[i]); 816 817 if (pool->base.mis[i] != NULL) { 818 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 819 pool->base.mis[i] = NULL; 820 } 821 822 if (pool->base.timing_generators[i] != NULL) { 823 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 824 pool->base.timing_generators[i] = NULL; 825 } 826 } 827 828 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 829 if (pool->base.engines[i] != NULL) 830 dce110_engine_destroy(&pool->base.engines[i]); 831 if (pool->base.hw_i2cs[i] != NULL) { 832 kfree(pool->base.hw_i2cs[i]); 833 pool->base.hw_i2cs[i] = NULL; 834 } 835 if (pool->base.sw_i2cs[i] != NULL) { 836 kfree(pool->base.sw_i2cs[i]); 837 pool->base.sw_i2cs[i] = NULL; 838 } 839 } 840 841 for (i = 0; i < pool->base.stream_enc_count; i++) { 842 if (pool->base.stream_enc[i] != NULL) 843 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 844 } 845 846 for (i = 0; i < pool->base.clk_src_count; i++) { 847 if (pool->base.clock_sources[i] != NULL) { 848 dce80_clock_source_destroy(&pool->base.clock_sources[i]); 849 } 850 } 851 852 if (pool->base.abm != NULL) 853 dce_abm_destroy(&pool->base.abm); 854 855 if (pool->base.dmcu != NULL) 856 dce_dmcu_destroy(&pool->base.dmcu); 857 858 if (pool->base.dp_clock_source != NULL) 859 dce80_clock_source_destroy(&pool->base.dp_clock_source); 860 861 for (i = 0; i < pool->base.audio_count; i++) { 862 if (pool->base.audios[i] != NULL) { 863 dce_aud_destroy(&pool->base.audios[i]); 864 } 865 } 866 867 if (pool->base.irqs != NULL) { 868 dal_irq_service_destroy(&pool->base.irqs); 869 } 870 } 871 872 static bool dce80_validate_bandwidth( 873 struct dc *dc, 874 struct dc_state *context, 875 bool fast_validate) 876 { 877 int i; 878 bool at_least_one_pipe = false; 879 880 for (i = 0; i < dc->res_pool->pipe_count; i++) { 881 if (context->res_ctx.pipe_ctx[i].stream) 882 at_least_one_pipe = true; 883 } 884 885 if (at_least_one_pipe) { 886 /* TODO implement when needed but for now hardcode max value*/ 887 context->bw_ctx.bw.dce.dispclk_khz = 681000; 888 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ; 889 } else { 890 context->bw_ctx.bw.dce.dispclk_khz = 0; 891 context->bw_ctx.bw.dce.yclk_khz = 0; 892 } 893 894 return true; 895 } 896 897 static bool dce80_validate_surface_sets( 898 struct dc_state *context) 899 { 900 int i; 901 902 for (i = 0; i < context->stream_count; i++) { 903 if (context->stream_status[i].plane_count == 0) 904 continue; 905 906 if (context->stream_status[i].plane_count > 1) 907 return false; 908 909 if (context->stream_status[i].plane_states[0]->format 910 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 911 return false; 912 } 913 914 return true; 915 } 916 917 static enum dc_status dce80_validate_global( 918 struct dc *dc, 919 struct dc_state *context) 920 { 921 if (!dce80_validate_surface_sets(context)) 922 return DC_FAIL_SURFACE_VALIDATE; 923 924 return DC_OK; 925 } 926 927 static void dce80_destroy_resource_pool(struct resource_pool **pool) 928 { 929 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 930 931 dce80_resource_destruct(dce110_pool); 932 kfree(dce110_pool); 933 *pool = NULL; 934 } 935 936 static const struct resource_funcs dce80_res_pool_funcs = { 937 .destroy = dce80_destroy_resource_pool, 938 .link_enc_create = dce80_link_encoder_create, 939 .panel_cntl_create = dce80_panel_cntl_create, 940 .validate_bandwidth = dce80_validate_bandwidth, 941 .validate_plane = dce100_validate_plane, 942 .add_stream_to_ctx = dce100_add_stream_to_ctx, 943 .validate_global = dce80_validate_global, 944 .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link 945 }; 946 947 static bool dce80_construct( 948 uint8_t num_virtual_links, 949 struct dc *dc, 950 struct dce110_resource_pool *pool) 951 { 952 unsigned int i; 953 struct dc_context *ctx = dc->ctx; 954 struct dc_bios *bp; 955 956 ctx->dc_bios->regs = &bios_regs; 957 958 pool->base.res_cap = &res_cap; 959 pool->base.funcs = &dce80_res_pool_funcs; 960 961 962 /************************************************* 963 * Resource + asic cap harcoding * 964 *************************************************/ 965 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 966 pool->base.pipe_count = res_cap.num_timing_generator; 967 pool->base.timing_generator_count = res_cap.num_timing_generator; 968 dc->caps.max_downscale_ratio = 200; 969 dc->caps.i2c_speed_in_khz = 40; 970 dc->caps.i2c_speed_in_khz_hdcp = 40; 971 dc->caps.max_cursor_size = 128; 972 dc->caps.min_horizontal_blanking_period = 80; 973 dc->caps.dual_link_dvi = true; 974 dc->caps.extended_aux_timeout_support = false; 975 dc->debug = debug_defaults; 976 977 /************************************************* 978 * Create resources * 979 *************************************************/ 980 981 bp = ctx->dc_bios; 982 983 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { 984 pool->base.dp_clock_source = 985 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 986 987 pool->base.clock_sources[0] = 988 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 989 pool->base.clock_sources[1] = 990 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 991 pool->base.clock_sources[2] = 992 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 993 pool->base.clk_src_count = 3; 994 995 } else { 996 pool->base.dp_clock_source = 997 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 998 999 pool->base.clock_sources[0] = 1000 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1001 pool->base.clock_sources[1] = 1002 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1003 pool->base.clk_src_count = 2; 1004 } 1005 1006 if (pool->base.dp_clock_source == NULL) { 1007 dm_error("DC: failed to create dp clock source!\n"); 1008 BREAK_TO_DEBUGGER(); 1009 goto res_create_fail; 1010 } 1011 1012 for (i = 0; i < pool->base.clk_src_count; i++) { 1013 if (pool->base.clock_sources[i] == NULL) { 1014 dm_error("DC: failed to create clock sources!\n"); 1015 BREAK_TO_DEBUGGER(); 1016 goto res_create_fail; 1017 } 1018 } 1019 1020 pool->base.dmcu = dce_dmcu_create(ctx, 1021 &dmcu_regs, 1022 &dmcu_shift, 1023 &dmcu_mask); 1024 if (pool->base.dmcu == NULL) { 1025 dm_error("DC: failed to create dmcu!\n"); 1026 BREAK_TO_DEBUGGER(); 1027 goto res_create_fail; 1028 } 1029 1030 pool->base.abm = dce_abm_create(ctx, 1031 &abm_regs, 1032 &abm_shift, 1033 &abm_mask); 1034 if (pool->base.abm == NULL) { 1035 dm_error("DC: failed to create abm!\n"); 1036 BREAK_TO_DEBUGGER(); 1037 goto res_create_fail; 1038 } 1039 1040 { 1041 struct irq_service_init_data init_data; 1042 init_data.ctx = dc->ctx; 1043 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1044 if (!pool->base.irqs) 1045 goto res_create_fail; 1046 } 1047 1048 for (i = 0; i < pool->base.pipe_count; i++) { 1049 pool->base.timing_generators[i] = dce80_timing_generator_create( 1050 ctx, i, &dce80_tg_offsets[i]); 1051 if (pool->base.timing_generators[i] == NULL) { 1052 BREAK_TO_DEBUGGER(); 1053 dm_error("DC: failed to create tg!\n"); 1054 goto res_create_fail; 1055 } 1056 1057 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1058 if (pool->base.mis[i] == NULL) { 1059 BREAK_TO_DEBUGGER(); 1060 dm_error("DC: failed to create memory input!\n"); 1061 goto res_create_fail; 1062 } 1063 1064 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1065 if (pool->base.ipps[i] == NULL) { 1066 BREAK_TO_DEBUGGER(); 1067 dm_error("DC: failed to create input pixel processor!\n"); 1068 goto res_create_fail; 1069 } 1070 1071 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1072 if (pool->base.transforms[i] == NULL) { 1073 BREAK_TO_DEBUGGER(); 1074 dm_error("DC: failed to create transform!\n"); 1075 goto res_create_fail; 1076 } 1077 1078 pool->base.opps[i] = dce80_opp_create(ctx, i); 1079 if (pool->base.opps[i] == NULL) { 1080 BREAK_TO_DEBUGGER(); 1081 dm_error("DC: failed to create output pixel processor!\n"); 1082 goto res_create_fail; 1083 } 1084 } 1085 1086 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1087 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 1088 if (pool->base.engines[i] == NULL) { 1089 BREAK_TO_DEBUGGER(); 1090 dm_error( 1091 "DC:failed to create aux engine!!\n"); 1092 goto res_create_fail; 1093 } 1094 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); 1095 if (pool->base.hw_i2cs[i] == NULL) { 1096 BREAK_TO_DEBUGGER(); 1097 dm_error( 1098 "DC:failed to create i2c engine!!\n"); 1099 goto res_create_fail; 1100 } 1101 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); 1102 if (pool->base.sw_i2cs[i] == NULL) { 1103 BREAK_TO_DEBUGGER(); 1104 dm_error( 1105 "DC:failed to create sw i2c!!\n"); 1106 goto res_create_fail; 1107 } 1108 } 1109 1110 dc->caps.max_planes = pool->base.pipe_count; 1111 1112 for (i = 0; i < dc->caps.max_planes; ++i) 1113 dc->caps.planes[i] = plane_cap; 1114 1115 dc->caps.disable_dp_clk_share = true; 1116 1117 if (!resource_construct(num_virtual_links, dc, &pool->base, 1118 &res_create_funcs)) 1119 goto res_create_fail; 1120 1121 /* Create hardware sequencer */ 1122 dce80_hw_sequencer_construct(dc); 1123 1124 return true; 1125 1126 res_create_fail: 1127 dce80_resource_destruct(pool); 1128 return false; 1129 } 1130 1131 struct resource_pool *dce80_create_resource_pool( 1132 uint8_t num_virtual_links, 1133 struct dc *dc) 1134 { 1135 struct dce110_resource_pool *pool = 1136 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1137 1138 if (!pool) 1139 return NULL; 1140 1141 if (dce80_construct(num_virtual_links, dc, pool)) 1142 return &pool->base; 1143 1144 kfree(pool); 1145 BREAK_TO_DEBUGGER(); 1146 return NULL; 1147 } 1148 1149 static bool dce81_construct( 1150 uint8_t num_virtual_links, 1151 struct dc *dc, 1152 struct dce110_resource_pool *pool) 1153 { 1154 unsigned int i; 1155 struct dc_context *ctx = dc->ctx; 1156 struct dc_bios *bp; 1157 1158 ctx->dc_bios->regs = &bios_regs; 1159 1160 pool->base.res_cap = &res_cap_81; 1161 pool->base.funcs = &dce80_res_pool_funcs; 1162 1163 1164 /************************************************* 1165 * Resource + asic cap harcoding * 1166 *************************************************/ 1167 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1168 pool->base.pipe_count = res_cap_81.num_timing_generator; 1169 pool->base.timing_generator_count = res_cap_81.num_timing_generator; 1170 dc->caps.max_downscale_ratio = 200; 1171 dc->caps.i2c_speed_in_khz = 40; 1172 dc->caps.i2c_speed_in_khz_hdcp = 40; 1173 dc->caps.max_cursor_size = 128; 1174 dc->caps.min_horizontal_blanking_period = 80; 1175 dc->caps.is_apu = true; 1176 1177 /************************************************* 1178 * Create resources * 1179 *************************************************/ 1180 1181 bp = ctx->dc_bios; 1182 1183 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { 1184 pool->base.dp_clock_source = 1185 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1186 1187 pool->base.clock_sources[0] = 1188 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 1189 pool->base.clock_sources[1] = 1190 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1191 pool->base.clock_sources[2] = 1192 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1193 pool->base.clk_src_count = 3; 1194 1195 } else { 1196 pool->base.dp_clock_source = 1197 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 1198 1199 pool->base.clock_sources[0] = 1200 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1201 pool->base.clock_sources[1] = 1202 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1203 pool->base.clk_src_count = 2; 1204 } 1205 1206 if (pool->base.dp_clock_source == NULL) { 1207 dm_error("DC: failed to create dp clock source!\n"); 1208 BREAK_TO_DEBUGGER(); 1209 goto res_create_fail; 1210 } 1211 1212 for (i = 0; i < pool->base.clk_src_count; i++) { 1213 if (pool->base.clock_sources[i] == NULL) { 1214 dm_error("DC: failed to create clock sources!\n"); 1215 BREAK_TO_DEBUGGER(); 1216 goto res_create_fail; 1217 } 1218 } 1219 1220 pool->base.dmcu = dce_dmcu_create(ctx, 1221 &dmcu_regs, 1222 &dmcu_shift, 1223 &dmcu_mask); 1224 if (pool->base.dmcu == NULL) { 1225 dm_error("DC: failed to create dmcu!\n"); 1226 BREAK_TO_DEBUGGER(); 1227 goto res_create_fail; 1228 } 1229 1230 pool->base.abm = dce_abm_create(ctx, 1231 &abm_regs, 1232 &abm_shift, 1233 &abm_mask); 1234 if (pool->base.abm == NULL) { 1235 dm_error("DC: failed to create abm!\n"); 1236 BREAK_TO_DEBUGGER(); 1237 goto res_create_fail; 1238 } 1239 1240 { 1241 struct irq_service_init_data init_data; 1242 init_data.ctx = dc->ctx; 1243 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1244 if (!pool->base.irqs) 1245 goto res_create_fail; 1246 } 1247 1248 for (i = 0; i < pool->base.pipe_count; i++) { 1249 pool->base.timing_generators[i] = dce80_timing_generator_create( 1250 ctx, i, &dce80_tg_offsets[i]); 1251 if (pool->base.timing_generators[i] == NULL) { 1252 BREAK_TO_DEBUGGER(); 1253 dm_error("DC: failed to create tg!\n"); 1254 goto res_create_fail; 1255 } 1256 1257 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1258 if (pool->base.mis[i] == NULL) { 1259 BREAK_TO_DEBUGGER(); 1260 dm_error("DC: failed to create memory input!\n"); 1261 goto res_create_fail; 1262 } 1263 1264 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1265 if (pool->base.ipps[i] == NULL) { 1266 BREAK_TO_DEBUGGER(); 1267 dm_error("DC: failed to create input pixel processor!\n"); 1268 goto res_create_fail; 1269 } 1270 1271 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1272 if (pool->base.transforms[i] == NULL) { 1273 BREAK_TO_DEBUGGER(); 1274 dm_error("DC: failed to create transform!\n"); 1275 goto res_create_fail; 1276 } 1277 1278 pool->base.opps[i] = dce80_opp_create(ctx, i); 1279 if (pool->base.opps[i] == NULL) { 1280 BREAK_TO_DEBUGGER(); 1281 dm_error("DC: failed to create output pixel processor!\n"); 1282 goto res_create_fail; 1283 } 1284 } 1285 1286 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1287 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 1288 if (pool->base.engines[i] == NULL) { 1289 BREAK_TO_DEBUGGER(); 1290 dm_error( 1291 "DC:failed to create aux engine!!\n"); 1292 goto res_create_fail; 1293 } 1294 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); 1295 if (pool->base.hw_i2cs[i] == NULL) { 1296 BREAK_TO_DEBUGGER(); 1297 dm_error( 1298 "DC:failed to create i2c engine!!\n"); 1299 goto res_create_fail; 1300 } 1301 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); 1302 if (pool->base.sw_i2cs[i] == NULL) { 1303 BREAK_TO_DEBUGGER(); 1304 dm_error( 1305 "DC:failed to create sw i2c!!\n"); 1306 goto res_create_fail; 1307 } 1308 } 1309 1310 dc->caps.max_planes = pool->base.pipe_count; 1311 1312 for (i = 0; i < dc->caps.max_planes; ++i) 1313 dc->caps.planes[i] = plane_cap; 1314 1315 dc->caps.disable_dp_clk_share = true; 1316 1317 if (!resource_construct(num_virtual_links, dc, &pool->base, 1318 &res_create_funcs)) 1319 goto res_create_fail; 1320 1321 /* Create hardware sequencer */ 1322 dce80_hw_sequencer_construct(dc); 1323 1324 return true; 1325 1326 res_create_fail: 1327 dce80_resource_destruct(pool); 1328 return false; 1329 } 1330 1331 struct resource_pool *dce81_create_resource_pool( 1332 uint8_t num_virtual_links, 1333 struct dc *dc) 1334 { 1335 struct dce110_resource_pool *pool = 1336 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1337 1338 if (!pool) 1339 return NULL; 1340 1341 if (dce81_construct(num_virtual_links, dc, pool)) 1342 return &pool->base; 1343 1344 kfree(pool); 1345 BREAK_TO_DEBUGGER(); 1346 return NULL; 1347 } 1348 1349 static bool dce83_construct( 1350 uint8_t num_virtual_links, 1351 struct dc *dc, 1352 struct dce110_resource_pool *pool) 1353 { 1354 unsigned int i; 1355 struct dc_context *ctx = dc->ctx; 1356 struct dc_bios *bp; 1357 1358 ctx->dc_bios->regs = &bios_regs; 1359 1360 pool->base.res_cap = &res_cap_83; 1361 pool->base.funcs = &dce80_res_pool_funcs; 1362 1363 1364 /************************************************* 1365 * Resource + asic cap harcoding * 1366 *************************************************/ 1367 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1368 pool->base.pipe_count = res_cap_83.num_timing_generator; 1369 pool->base.timing_generator_count = res_cap_83.num_timing_generator; 1370 dc->caps.max_downscale_ratio = 200; 1371 dc->caps.i2c_speed_in_khz = 40; 1372 dc->caps.i2c_speed_in_khz_hdcp = 40; 1373 dc->caps.max_cursor_size = 128; 1374 dc->caps.min_horizontal_blanking_period = 80; 1375 dc->caps.is_apu = true; 1376 dc->debug = debug_defaults; 1377 1378 /************************************************* 1379 * Create resources * 1380 *************************************************/ 1381 1382 bp = ctx->dc_bios; 1383 1384 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { 1385 pool->base.dp_clock_source = 1386 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1387 1388 pool->base.clock_sources[0] = 1389 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false); 1390 pool->base.clock_sources[1] = 1391 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1392 pool->base.clk_src_count = 2; 1393 1394 } else { 1395 pool->base.dp_clock_source = 1396 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true); 1397 1398 pool->base.clock_sources[0] = 1399 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1400 pool->base.clk_src_count = 1; 1401 } 1402 1403 if (pool->base.dp_clock_source == NULL) { 1404 dm_error("DC: failed to create dp clock source!\n"); 1405 BREAK_TO_DEBUGGER(); 1406 goto res_create_fail; 1407 } 1408 1409 for (i = 0; i < pool->base.clk_src_count; i++) { 1410 if (pool->base.clock_sources[i] == NULL) { 1411 dm_error("DC: failed to create clock sources!\n"); 1412 BREAK_TO_DEBUGGER(); 1413 goto res_create_fail; 1414 } 1415 } 1416 1417 pool->base.dmcu = dce_dmcu_create(ctx, 1418 &dmcu_regs, 1419 &dmcu_shift, 1420 &dmcu_mask); 1421 if (pool->base.dmcu == NULL) { 1422 dm_error("DC: failed to create dmcu!\n"); 1423 BREAK_TO_DEBUGGER(); 1424 goto res_create_fail; 1425 } 1426 1427 pool->base.abm = dce_abm_create(ctx, 1428 &abm_regs, 1429 &abm_shift, 1430 &abm_mask); 1431 if (pool->base.abm == NULL) { 1432 dm_error("DC: failed to create abm!\n"); 1433 BREAK_TO_DEBUGGER(); 1434 goto res_create_fail; 1435 } 1436 1437 { 1438 struct irq_service_init_data init_data; 1439 init_data.ctx = dc->ctx; 1440 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1441 if (!pool->base.irqs) 1442 goto res_create_fail; 1443 } 1444 1445 for (i = 0; i < pool->base.pipe_count; i++) { 1446 pool->base.timing_generators[i] = dce80_timing_generator_create( 1447 ctx, i, &dce80_tg_offsets[i]); 1448 if (pool->base.timing_generators[i] == NULL) { 1449 BREAK_TO_DEBUGGER(); 1450 dm_error("DC: failed to create tg!\n"); 1451 goto res_create_fail; 1452 } 1453 1454 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1455 if (pool->base.mis[i] == NULL) { 1456 BREAK_TO_DEBUGGER(); 1457 dm_error("DC: failed to create memory input!\n"); 1458 goto res_create_fail; 1459 } 1460 1461 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1462 if (pool->base.ipps[i] == NULL) { 1463 BREAK_TO_DEBUGGER(); 1464 dm_error("DC: failed to create input pixel processor!\n"); 1465 goto res_create_fail; 1466 } 1467 1468 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1469 if (pool->base.transforms[i] == NULL) { 1470 BREAK_TO_DEBUGGER(); 1471 dm_error("DC: failed to create transform!\n"); 1472 goto res_create_fail; 1473 } 1474 1475 pool->base.opps[i] = dce80_opp_create(ctx, i); 1476 if (pool->base.opps[i] == NULL) { 1477 BREAK_TO_DEBUGGER(); 1478 dm_error("DC: failed to create output pixel processor!\n"); 1479 goto res_create_fail; 1480 } 1481 } 1482 1483 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1484 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 1485 if (pool->base.engines[i] == NULL) { 1486 BREAK_TO_DEBUGGER(); 1487 dm_error( 1488 "DC:failed to create aux engine!!\n"); 1489 goto res_create_fail; 1490 } 1491 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); 1492 if (pool->base.hw_i2cs[i] == NULL) { 1493 BREAK_TO_DEBUGGER(); 1494 dm_error( 1495 "DC:failed to create i2c engine!!\n"); 1496 goto res_create_fail; 1497 } 1498 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); 1499 if (pool->base.sw_i2cs[i] == NULL) { 1500 BREAK_TO_DEBUGGER(); 1501 dm_error( 1502 "DC:failed to create sw i2c!!\n"); 1503 goto res_create_fail; 1504 } 1505 } 1506 1507 dc->caps.max_planes = pool->base.pipe_count; 1508 1509 for (i = 0; i < dc->caps.max_planes; ++i) 1510 dc->caps.planes[i] = plane_cap; 1511 1512 dc->caps.disable_dp_clk_share = true; 1513 1514 if (!resource_construct(num_virtual_links, dc, &pool->base, 1515 &res_create_funcs)) 1516 goto res_create_fail; 1517 1518 /* Create hardware sequencer */ 1519 dce80_hw_sequencer_construct(dc); 1520 1521 return true; 1522 1523 res_create_fail: 1524 dce80_resource_destruct(pool); 1525 return false; 1526 } 1527 1528 struct resource_pool *dce83_create_resource_pool( 1529 uint8_t num_virtual_links, 1530 struct dc *dc) 1531 { 1532 struct dce110_resource_pool *pool = 1533 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1534 1535 if (!pool) 1536 return NULL; 1537 1538 if (dce83_construct(num_virtual_links, dc, pool)) 1539 return &pool->base; 1540 1541 kfree(pool); 1542 BREAK_TO_DEBUGGER(); 1543 return NULL; 1544 } 1545