1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "dce_calcs.h" 28 #include "reg_helper.h" 29 #include "basics/conversion.h" 30 #include "dcn401_hubp.h" 31 #include "dal_asic_id.h" 32 33 #define REG(reg)\ 34 hubp2->hubp_regs->reg 35 36 #define CTX \ 37 hubp2->base.ctx 38 39 #undef FN 40 #define FN(reg_name, field_name) \ 41 hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name 42 43 void hubp401_program_3dlut_fl_addr(struct hubp *hubp, 44 const struct dc_plane_address address) 45 { 46 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 47 48 REG_UPDATE(HUBP_3DLUT_ADDRESS_HIGH, HUBP_3DLUT_ADDRESS_HIGH, address.lut3d.addr.high_part); 49 REG_WRITE(HUBP_3DLUT_ADDRESS_LOW, address.lut3d.addr.low_part); 50 } 51 52 void hubp401_program_3dlut_fl_dlg_param(struct hubp *hubp, int refcyc_per_3dlut_group) 53 { 54 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 55 56 REG_UPDATE(HUBP_3DLUT_DLG_PARAM, REFCYC_PER_3DLUT_GROUP, refcyc_per_3dlut_group); 57 } 58 59 void hubp401_enable_3dlut_fl(struct hubp *hubp, bool enable) 60 { 61 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 62 63 REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_ENABLE, enable ? 1 : 0); 64 } 65 66 int hubp401_get_3dlut_fl_done(struct hubp *hubp) 67 { 68 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 69 int ret; 70 71 REG_GET(HUBP_3DLUT_CONTROL, HUBP_3DLUT_DONE, &ret); 72 return ret; 73 } 74 75 void hubp401_program_3dlut_fl_addressing_mode(struct hubp *hubp, enum hubp_3dlut_fl_addressing_mode addr_mode) 76 { 77 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 78 79 REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_ADDRESSING_MODE, addr_mode); 80 } 81 82 void hubp401_program_3dlut_fl_width(struct hubp *hubp, enum hubp_3dlut_fl_width width) 83 { 84 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 85 86 REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_WIDTH, width); 87 } 88 89 void hubp401_program_3dlut_fl_tmz_protected(struct hubp *hubp, bool protection_enabled) 90 { 91 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 92 93 REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_TMZ, protection_enabled ? 1 : 0); 94 } 95 96 void hubp401_program_3dlut_fl_crossbar(struct hubp *hubp, 97 enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_y_g, 98 enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b, 99 enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r) 100 { 101 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 102 103 REG_UPDATE_3(HUBP_3DLUT_CONTROL, 104 HUBP_3DLUT_CROSSBAR_SELECT_Y_G, bit_slice_y_g, 105 HUBP_3DLUT_CROSSBAR_SELECT_CB_B, bit_slice_cb_b, 106 HUBP_3DLUT_CROSSBAR_SELECT_CR_R, bit_slice_cr_r); 107 } 108 109 void hubp401_update_3dlut_fl_bias_scale(struct hubp *hubp, uint16_t bias, uint16_t scale) 110 { 111 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 112 113 REG_UPDATE_2(_3DLUT_FL_BIAS_SCALE, HUBP0_3DLUT_FL_BIAS, bias, HUBP0_3DLUT_FL_SCALE, scale); 114 } 115 116 void hubp401_program_3dlut_fl_mode(struct hubp *hubp, enum hubp_3dlut_fl_mode mode) 117 { 118 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 119 120 REG_UPDATE(_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_MODE, mode); 121 } 122 123 void hubp401_program_3dlut_fl_format(struct hubp *hubp, enum hubp_3dlut_fl_format format) 124 { 125 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 126 127 REG_UPDATE(_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_FORMAT, format); 128 } 129 130 void hubp401_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor) 131 { 132 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 133 134 // Also cache cursor in MALL if using MALL for SS 135 REG_UPDATE_2(DCHUBP_MALL_CONFIG, USE_MALL_SEL, mall_sel, 136 USE_MALL_FOR_CURSOR, c_cursor); 137 138 REG_UPDATE_2(DCHUBP_MALL_CONFIG, MALL_PREF_CMD_TYPE, 1, MALL_PREF_MODE, 0); 139 } 140 141 142 void hubp401_init(struct hubp *hubp) 143 { 144 hubp_reset(hubp); 145 } 146 147 void hubp401_vready_at_or_After_vsync(struct hubp *hubp, 148 union dml2_global_sync_programming *pipe_global_sync, 149 struct dc_crtc_timing *timing) 150 { 151 unsigned int vstartup_lines = pipe_global_sync->dcn4x.vstartup_lines; 152 unsigned int vupdate_offset_pixels = pipe_global_sync->dcn4x.vupdate_offset_pixels; 153 unsigned int vupdate_width_pixels = pipe_global_sync->dcn4x.vupdate_vupdate_width_pixels; 154 unsigned int vready_offset_pixels = pipe_global_sync->dcn4x.vready_offset_pixels; 155 unsigned int htotal = timing->h_total; 156 unsigned int vblank_start = 0; 157 unsigned int vblank_end = 0; 158 unsigned int pixel_width = 0; 159 uint32_t reg_value = 0; 160 bool is_vready_at_or_after_vsync = false; 161 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 162 163 /* 164 * if (VSTARTUP_START - (VREADY_OFFSET+VUPDATE_WIDTH+VUPDATE_OFFSET)/htotal) <= OTG_V_BLANK_END 165 * Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 1 166 * else 167 * Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 0 168 */ 169 if (htotal != 0) { 170 vblank_start = timing->v_total - timing->v_front_porch; 171 vblank_end = vblank_start - timing->v_addressable - timing->v_border_top - timing->v_border_bottom; 172 pixel_width = vready_offset_pixels + vupdate_width_pixels + vupdate_offset_pixels; 173 174 is_vready_at_or_after_vsync = (vstartup_lines - pixel_width / htotal) <= vblank_end; 175 176 if (is_vready_at_or_after_vsync) 177 reg_value = 1; 178 } 179 180 REG_UPDATE(DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, reg_value); 181 } 182 183 void hubp401_program_requestor( 184 struct hubp *hubp, 185 struct dml2_display_rq_regs *rq_regs) 186 { 187 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 188 189 REG_UPDATE(HUBPRET_CONTROL, 190 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); 191 REG_SET_4(DCN_EXPANSION_MODE, 0, 192 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, 193 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, 194 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, 195 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); 196 REG_SET_6(DCHUBP_REQ_SIZE_CONFIG, 0, 197 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, 198 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, 199 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, 200 VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, 201 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, 202 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); 203 REG_SET_5(DCHUBP_REQ_SIZE_CONFIG_C, 0, 204 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, 205 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, 206 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, 207 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, 208 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); 209 } 210 211 void hubp401_program_deadline( 212 struct hubp *hubp, 213 struct dml2_display_dlg_regs *dlg_attr, 214 struct dml2_display_ttu_regs *ttu_attr) 215 { 216 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 217 218 /* put DLG in mission mode */ 219 REG_WRITE(HUBPREQ_DEBUG_DB, 1 << 8); 220 221 /* DLG - Per hubp */ 222 REG_SET_2(BLANK_OFFSET_0, 0, 223 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, 224 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); 225 226 REG_SET(BLANK_OFFSET_1, 0, 227 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start); 228 229 REG_SET(DST_DIMENSIONS, 0, 230 REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal); 231 232 REG_SET_2(DST_AFTER_SCALER, 0, 233 REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler, 234 DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler); 235 236 REG_SET(REF_FREQ_TO_PIX_FREQ, 0, 237 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq); 238 239 /* DLG - Per luma/chroma */ 240 REG_SET(VBLANK_PARAMETERS_1, 0, 241 REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l); 242 243 if (REG(NOM_PARAMETERS_0)) 244 REG_SET(NOM_PARAMETERS_0, 0, 245 DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l); 246 247 if (REG(NOM_PARAMETERS_1)) 248 REG_SET(NOM_PARAMETERS_1, 0, 249 REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l); 250 251 REG_SET(NOM_PARAMETERS_4, 0, 252 DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l); 253 254 REG_SET(NOM_PARAMETERS_5, 0, 255 REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l); 256 257 REG_SET_2(PER_LINE_DELIVERY, 0, 258 REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l, 259 REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c); 260 261 REG_SET(VBLANK_PARAMETERS_2, 0, 262 REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c); 263 264 if (REG(NOM_PARAMETERS_2)) 265 REG_SET(NOM_PARAMETERS_2, 0, 266 DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c); 267 268 if (REG(NOM_PARAMETERS_3)) 269 REG_SET(NOM_PARAMETERS_3, 0, 270 REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c); 271 272 REG_SET(NOM_PARAMETERS_6, 0, 273 DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c); 274 275 REG_SET(NOM_PARAMETERS_7, 0, 276 REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c); 277 278 /* TTU - per hubp */ 279 REG_SET_2(DCN_TTU_QOS_WM, 0, 280 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm, 281 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm); 282 283 /* TTU - per luma/chroma */ 284 /* Assumed surf0 is luma and 1 is chroma */ 285 286 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, 287 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l, 288 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l, 289 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l); 290 291 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, 292 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c, 293 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c, 294 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c); 295 296 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, 297 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0, 298 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0, 299 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0); 300 301 REG_SET(FLIP_PARAMETERS_1, 0, 302 REFCYC_PER_PTE_GROUP_FLIP_L, dlg_attr->refcyc_per_pte_group_flip_l); 303 REG_SET(HUBP_3DLUT_DLG_PARAM, 0, REFCYC_PER_3DLUT_GROUP, dlg_attr->refcyc_per_tdlut_group); 304 305 REG_UPDATE(DCN_DMDATA_VM_CNTL, 306 REFCYC_PER_VM_DMDATA, dlg_attr->refcyc_per_vm_dmdata); 307 } 308 309 void hubp401_setup( 310 struct hubp *hubp, 311 struct dml2_dchub_per_pipe_register_set *pipe_regs, 312 union dml2_global_sync_programming *pipe_global_sync, 313 struct dc_crtc_timing *timing) 314 { 315 /* otg is locked when this func is called. Register are double buffered. 316 * disable the requestors is not needed 317 */ 318 hubp401_vready_at_or_After_vsync(hubp, pipe_global_sync, timing); 319 hubp401_program_requestor(hubp, &pipe_regs->rq_regs); 320 hubp401_program_deadline(hubp, &pipe_regs->dlg_regs, &pipe_regs->ttu_regs); 321 } 322 323 void hubp401_setup_interdependent( 324 struct hubp *hubp, 325 struct dml2_dchub_per_pipe_register_set *pipe_regs) 326 { 327 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 328 329 REG_SET_2(PREFETCH_SETTINGS, 0, 330 DST_Y_PREFETCH, pipe_regs->dlg_regs.dst_y_prefetch, 331 VRATIO_PREFETCH, pipe_regs->dlg_regs.vratio_prefetch); 332 333 REG_SET(PREFETCH_SETTINGS_C, 0, 334 VRATIO_PREFETCH_C, pipe_regs->dlg_regs.vratio_prefetch_c); 335 336 REG_SET_2(VBLANK_PARAMETERS_0, 0, 337 DST_Y_PER_VM_VBLANK, pipe_regs->dlg_regs.dst_y_per_vm_vblank, 338 DST_Y_PER_ROW_VBLANK, pipe_regs->dlg_regs.dst_y_per_row_vblank); 339 340 REG_SET_2(FLIP_PARAMETERS_0, 0, 341 DST_Y_PER_VM_FLIP, pipe_regs->dlg_regs.dst_y_per_vm_flip, 342 DST_Y_PER_ROW_FLIP, pipe_regs->dlg_regs.dst_y_per_row_flip); 343 344 REG_SET(VBLANK_PARAMETERS_3, 0, 345 REFCYC_PER_META_CHUNK_VBLANK_L, pipe_regs->dlg_regs.refcyc_per_meta_chunk_vblank_l); 346 347 REG_SET(VBLANK_PARAMETERS_4, 0, 348 REFCYC_PER_META_CHUNK_VBLANK_C, pipe_regs->dlg_regs.refcyc_per_meta_chunk_vblank_c); 349 350 REG_SET(FLIP_PARAMETERS_2, 0, 351 REFCYC_PER_META_CHUNK_FLIP_L, pipe_regs->dlg_regs.refcyc_per_meta_chunk_flip_l); 352 353 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, 354 REFCYC_PER_LINE_DELIVERY_PRE_L, pipe_regs->dlg_regs.refcyc_per_line_delivery_pre_l, 355 REFCYC_PER_LINE_DELIVERY_PRE_C, pipe_regs->dlg_regs.refcyc_per_line_delivery_pre_c); 356 357 REG_SET(DCN_SURF0_TTU_CNTL1, 0, 358 REFCYC_PER_REQ_DELIVERY_PRE, 359 pipe_regs->ttu_regs.refcyc_per_req_delivery_pre_l); 360 REG_SET(DCN_SURF1_TTU_CNTL1, 0, 361 REFCYC_PER_REQ_DELIVERY_PRE, 362 pipe_regs->ttu_regs.refcyc_per_req_delivery_pre_c); 363 REG_SET(DCN_CUR0_TTU_CNTL1, 0, 364 REFCYC_PER_REQ_DELIVERY_PRE, pipe_regs->ttu_regs.refcyc_per_req_delivery_pre_cur0); 365 366 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, 367 MIN_TTU_VBLANK, pipe_regs->ttu_regs.min_ttu_vblank, 368 QoS_LEVEL_FLIP, pipe_regs->ttu_regs.qos_level_flip); 369 } 370 371 372 bool hubp401_program_surface_flip_and_addr( 373 struct hubp *hubp, 374 const struct dc_plane_address *address, 375 bool flip_immediate) 376 { 377 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 378 379 //program flip type 380 REG_UPDATE(DCSURF_FLIP_CONTROL, 381 SURFACE_FLIP_TYPE, flip_immediate); 382 383 // Program VMID reg 384 if (flip_immediate == 0) 385 REG_UPDATE(VMID_SETTINGS_0, 386 VMID, address->vmid); 387 388 if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) { 389 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0); 390 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1); 391 392 } else { 393 // turn off stereo if not in stereo 394 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0); 395 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0); 396 } 397 398 /* HW automatically latch rest of address register on write to 399 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used 400 * 401 * program high first and then the low addr, order matters! 402 */ 403 switch (address->type) { 404 case PLN_ADDR_TYPE_GRAPHICS: 405 if (address->grph.addr.quad_part == 0) 406 break; 407 408 REG_UPDATE(DCSURF_SURFACE_CONTROL, 409 PRIMARY_SURFACE_TMZ, address->tmz_surface); 410 411 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 412 PRIMARY_SURFACE_ADDRESS_HIGH, 413 address->grph.addr.high_part); 414 415 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 416 PRIMARY_SURFACE_ADDRESS, 417 address->grph.addr.low_part); 418 break; 419 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: 420 if (address->video_progressive.luma_addr.quad_part == 0 421 || address->video_progressive.chroma_addr.quad_part == 0) 422 break; 423 424 REG_UPDATE_2(DCSURF_SURFACE_CONTROL, 425 PRIMARY_SURFACE_TMZ, address->tmz_surface, 426 PRIMARY_SURFACE_TMZ_C, address->tmz_surface); 427 428 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, 429 PRIMARY_SURFACE_ADDRESS_HIGH_C, 430 address->video_progressive.chroma_addr.high_part); 431 432 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, 433 PRIMARY_SURFACE_ADDRESS_C, 434 address->video_progressive.chroma_addr.low_part); 435 436 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 437 PRIMARY_SURFACE_ADDRESS_HIGH, 438 address->video_progressive.luma_addr.high_part); 439 440 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 441 PRIMARY_SURFACE_ADDRESS, 442 address->video_progressive.luma_addr.low_part); 443 break; 444 case PLN_ADDR_TYPE_GRPH_STEREO: 445 if (address->grph_stereo.left_addr.quad_part == 0) 446 break; 447 if (address->grph_stereo.right_addr.quad_part == 0) 448 break; 449 450 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 451 PRIMARY_SURFACE_TMZ, address->tmz_surface, 452 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 453 SECONDARY_SURFACE_TMZ, address->tmz_surface, 454 SECONDARY_SURFACE_TMZ_C, address->tmz_surface); 455 456 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, 0, 457 SECONDARY_SURFACE_ADDRESS_HIGH_C, 458 address->grph_stereo.right_alpha_addr.high_part); 459 460 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_C, 0, 461 SECONDARY_SURFACE_ADDRESS_C, 462 address->grph_stereo.right_alpha_addr.low_part); 463 464 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, 465 SECONDARY_SURFACE_ADDRESS_HIGH, 466 address->grph_stereo.right_addr.high_part); 467 468 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, 469 SECONDARY_SURFACE_ADDRESS, 470 address->grph_stereo.right_addr.low_part); 471 472 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, 473 PRIMARY_SURFACE_ADDRESS_HIGH_C, 474 address->grph_stereo.left_alpha_addr.high_part); 475 476 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, 477 PRIMARY_SURFACE_ADDRESS_C, 478 address->grph_stereo.left_alpha_addr.low_part); 479 480 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 481 PRIMARY_SURFACE_ADDRESS_HIGH, 482 address->grph_stereo.left_addr.high_part); 483 484 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 485 PRIMARY_SURFACE_ADDRESS, 486 address->grph_stereo.left_addr.low_part); 487 break; 488 case PLN_ADDR_TYPE_RGBEA: 489 if (address->rgbea.addr.quad_part == 0 490 || address->rgbea.alpha_addr.quad_part == 0) 491 break; 492 493 REG_UPDATE_2(DCSURF_SURFACE_CONTROL, 494 PRIMARY_SURFACE_TMZ, address->tmz_surface, 495 PRIMARY_SURFACE_TMZ_C, address->tmz_surface); 496 497 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, 498 PRIMARY_SURFACE_ADDRESS_HIGH_C, 499 address->rgbea.alpha_addr.high_part); 500 501 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, 502 PRIMARY_SURFACE_ADDRESS_C, 503 address->rgbea.alpha_addr.low_part); 504 505 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 506 PRIMARY_SURFACE_ADDRESS_HIGH, 507 address->rgbea.addr.high_part); 508 509 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 510 PRIMARY_SURFACE_ADDRESS, 511 address->rgbea.addr.low_part); 512 break; 513 default: 514 BREAK_TO_DEBUGGER(); 515 break; 516 } 517 518 hubp->request_address = *address; 519 520 return true; 521 } 522 523 void hubp401_clear_tiling(struct hubp *hubp) 524 { 525 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 526 527 REG_UPDATE(DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, 0); 528 REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR); 529 530 REG_UPDATE_2(DCSURF_SURFACE_CONTROL, 531 PRIMARY_SURFACE_DCC_EN, 0, 532 SECONDARY_SURFACE_DCC_EN, 0); 533 } 534 535 void hubp401_dcc_control(struct hubp *hubp, 536 struct dc_plane_dcc_param *dcc) 537 { 538 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 539 540 REG_UPDATE_2(DCSURF_SURFACE_CONTROL, 541 PRIMARY_SURFACE_DCC_EN, dcc->enable, 542 SECONDARY_SURFACE_DCC_EN, dcc->enable); 543 } 544 545 void hubp401_program_tiling( 546 struct dcn20_hubp *hubp2, 547 const struct dc_tiling_info *info, 548 const enum surface_pixel_format pixel_format) 549 { 550 /* DCSURF_ADDR_CONFIG still shows up in reg spec, but does not need to be programmed for DCN4x 551 * All 4 fields NUM_PIPES, PIPE_INTERLEAVE, MAX_COMPRESSED_FRAGS and NUM_PKRS are irrelevant. 552 * 553 * DIM_TYPE field in DCSURF_TILING for Display is always 1 (2D dimension) which is HW default. 554 */ 555 REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, info->gfx_addr3.swizzle); 556 } 557 558 void hubp401_program_size( 559 struct hubp *hubp, 560 enum surface_pixel_format format, 561 const struct plane_size *plane_size, 562 struct dc_plane_dcc_param *dcc) 563 { 564 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 565 uint32_t pitch, pitch_c; 566 bool use_pitch_c = false; 567 568 /* Program data pitch (calculation from addrlib) 569 * 444 or 420 luma 570 */ 571 use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN 572 && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END; 573 use_pitch_c = use_pitch_c 574 || (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA); 575 if (use_pitch_c) { 576 ASSERT(plane_size->chroma_pitch != 0); 577 /* Chroma pitch zero can cause system hang! */ 578 579 pitch = plane_size->surface_pitch - 1; 580 pitch_c = plane_size->chroma_pitch - 1; 581 } else { 582 pitch = plane_size->surface_pitch - 1; 583 pitch_c = 0; 584 } 585 586 REG_UPDATE(DCSURF_SURFACE_PITCH, PITCH, pitch); 587 588 if (use_pitch_c) 589 REG_UPDATE(DCSURF_SURFACE_PITCH_C, PITCH_C, pitch_c); 590 } 591 592 void hubp401_program_surface_config( 593 struct hubp *hubp, 594 enum surface_pixel_format format, 595 struct dc_tiling_info *tiling_info, 596 struct plane_size *plane_size, 597 enum dc_rotation_angle rotation, 598 struct dc_plane_dcc_param *dcc, 599 bool horizontal_mirror, 600 unsigned int compat_level) 601 { 602 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 603 604 hubp401_dcc_control(hubp, dcc); 605 hubp401_program_tiling(hubp2, tiling_info, format); 606 hubp401_program_size(hubp, format, plane_size, dcc); 607 hubp2_program_rotation(hubp, rotation, horizontal_mirror); 608 hubp2_program_pixel_format(hubp, format); 609 } 610 611 void hubp401_set_viewport( 612 struct hubp *hubp, 613 const struct rect *viewport, 614 const struct rect *viewport_c) 615 { 616 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 617 618 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0, 619 PRI_VIEWPORT_WIDTH, viewport->width, 620 PRI_VIEWPORT_HEIGHT, viewport->height); 621 622 REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0, 623 PRI_VIEWPORT_X_START, viewport->x, 624 PRI_VIEWPORT_Y_START, viewport->y); 625 626 /*for stereo*/ 627 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0, 628 SEC_VIEWPORT_WIDTH, viewport->width, 629 SEC_VIEWPORT_HEIGHT, viewport->height); 630 631 REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0, 632 SEC_VIEWPORT_X_START, viewport->x, 633 SEC_VIEWPORT_Y_START, viewport->y); 634 635 /* DC supports NV12 only at the moment */ 636 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0, 637 PRI_VIEWPORT_WIDTH_C, viewport_c->width, 638 PRI_VIEWPORT_HEIGHT_C, viewport_c->height); 639 640 REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0, 641 PRI_VIEWPORT_X_START_C, viewport_c->x, 642 PRI_VIEWPORT_Y_START_C, viewport_c->y); 643 644 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0, 645 SEC_VIEWPORT_WIDTH_C, viewport_c->width, 646 SEC_VIEWPORT_HEIGHT_C, viewport_c->height); 647 648 REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0, 649 SEC_VIEWPORT_X_START_C, viewport_c->x, 650 SEC_VIEWPORT_Y_START_C, viewport_c->y); 651 } 652 653 void hubp401_program_mcache_id_and_split_coordinate( 654 struct hubp *hubp, 655 struct dml2_hubp_pipe_mcache_regs *mcache_regs) 656 { 657 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 658 659 REG_SET_8(DCHUBP_MCACHEID_CONFIG, 0, 660 MCACHEID_REG_READ_1H_P0, mcache_regs->main.p0.mcache_id_first, 661 MCACHEID_REG_READ_2H_P0, mcache_regs->main.p0.mcache_id_second, 662 MCACHEID_REG_READ_1H_P1, mcache_regs->main.p1.mcache_id_first, 663 MCACHEID_REG_READ_2H_P1, mcache_regs->main.p1.mcache_id_second, 664 MCACHEID_MALL_PREF_1H_P0, mcache_regs->mall.p0.mcache_id_first, 665 MCACHEID_MALL_PREF_2H_P0, mcache_regs->mall.p0.mcache_id_second, 666 MCACHEID_MALL_PREF_1H_P1, mcache_regs->mall.p1.mcache_id_first, 667 MCACHEID_MALL_PREF_2H_P1, mcache_regs->mall.p1.mcache_id_second); 668 669 REG_SET_2(DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE, 0, 670 VIEWPORT_MCACHE_SPLIT_COORDINATE, mcache_regs->main.p0.split_location, 671 VIEWPORT_MCACHE_SPLIT_COORDINATE_C, mcache_regs->main.p1.split_location); 672 } 673 void hubp401_set_flip_int(struct hubp *hubp) 674 { 675 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 676 677 REG_UPDATE(DCSURF_SURFACE_FLIP_INTERRUPT, 678 SURFACE_FLIP_INT_MASK, 1); 679 680 return; 681 } 682 683 bool hubp401_in_blank(struct hubp *hubp) 684 { 685 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 686 uint32_t in_blank; 687 688 REG_GET(DCHUBP_CNTL, HUBP_IN_BLANK, &in_blank); 689 return in_blank ? true : false; 690 } 691 692 693 void hubp401_cursor_set_position( 694 struct hubp *hubp, 695 const struct dc_cursor_position *pos, 696 const struct dc_cursor_mi_param *param) 697 { 698 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 699 int x_pos = pos->x - param->recout.x; 700 int y_pos = pos->y - param->recout.y; 701 int rec_x_offset = x_pos - pos->x_hotspot; 702 int rec_y_offset = y_pos - pos->y_hotspot; 703 int dst_x_offset; 704 int x_pos_viewport = 0; 705 int x_hot_viewport = 0; 706 uint32_t cur_en = pos->enable ? 1 : 0; 707 708 hubp->curs_pos = *pos; 709 710 /* Recout is zero for pipes if the entire dst_rect is contained 711 * within preceeding ODM slices. 712 */ 713 if (param->recout.width) { 714 x_pos_viewport = x_pos * param->viewport.width / param->recout.width; 715 x_hot_viewport = pos->x_hotspot * param->viewport.width / param->recout.width; 716 } else { 717 ASSERT(!cur_en || x_pos == 0); 718 ASSERT(!cur_en || pos->x_hotspot == 0); 719 } 720 721 /* 722 * Guard aganst cursor_set_position() from being called with invalid 723 * attributes 724 */ 725 if (hubp->curs_attr.address.quad_part == 0) 726 return; 727 728 /* Translate the x position of the cursor from rect 729 * space into viewport space. CURSOR_DST_X_OFFSET 730 * is the offset relative to viewport start position. 731 */ 732 dst_x_offset = x_pos_viewport - x_hot_viewport * 733 (1 + hubp->curs_attr.attribute_flags.bits.ENABLE_MAGNIFICATION); 734 dst_x_offset = (dst_x_offset >= 0) ? dst_x_offset : 0; 735 dst_x_offset *= param->ref_clk_khz; 736 dst_x_offset /= param->pixel_clk_khz; 737 738 ASSERT(param->h_scale_ratio.value); 739 740 if (param->h_scale_ratio.value) 741 dst_x_offset = dc_fixpt_floor(dc_fixpt_div( 742 dc_fixpt_from_int(dst_x_offset), 743 param->h_scale_ratio)); 744 745 if (hubp->pos.cur_ctl.bits.cur_enable != cur_en) { 746 if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0) 747 hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr); 748 749 REG_UPDATE(CURSOR_CONTROL, 750 CURSOR_ENABLE, cur_en); 751 } 752 753 REG_SET_2(CURSOR_POSITION, 0, 754 CURSOR_X_POSITION, x_pos, 755 CURSOR_Y_POSITION, y_pos); 756 757 REG_SET_2(CURSOR_HOT_SPOT, 0, 758 CURSOR_HOT_SPOT_X, pos->x_hotspot, 759 CURSOR_HOT_SPOT_Y, pos->y_hotspot); 760 761 REG_SET(CURSOR_DST_OFFSET, 0, 762 CURSOR_DST_X_OFFSET, dst_x_offset); 763 764 /* Cursor Position Register Config */ 765 hubp->pos.cur_ctl.bits.cur_enable = cur_en; 766 hubp->pos.position.bits.x_pos = pos->x; 767 hubp->pos.position.bits.y_pos = pos->y; 768 hubp->pos.hot_spot.bits.x_hot = pos->x_hotspot; 769 hubp->pos.hot_spot.bits.y_hot = pos->y_hotspot; 770 hubp->pos.dst_offset.bits.dst_x_offset = dst_x_offset; 771 /* Cursor Rectangle Cache 772 * Cursor bitmaps have different hotspot values 773 * There's a possibility that the above logic returns a negative value, 774 * so we clamp them to 0 775 */ 776 if (rec_x_offset < 0) 777 rec_x_offset = 0; 778 if (rec_y_offset < 0) 779 rec_y_offset = 0; 780 /* Save necessary cursor info x, y position. w, h is saved in attribute func. */ 781 hubp->cur_rect.x = rec_x_offset + param->recout.x; 782 hubp->cur_rect.y = rec_y_offset + param->recout.y; 783 } 784 785 void hubp401_read_state(struct hubp *hubp) 786 { 787 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 788 struct dcn_hubp_state *s = &hubp2->state; 789 struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr; 790 struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr; 791 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 792 793 /* Requester */ 794 REG_GET(HUBPRET_CONTROL, 795 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address); 796 REG_GET_4(DCN_EXPANSION_MODE, 797 DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode, 798 PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode, 799 MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode, 800 CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode); 801 802 REG_GET_5(DCHUBP_REQ_SIZE_CONFIG, 803 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, 804 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, 805 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, 806 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, 807 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); 808 809 REG_GET_5(DCHUBP_REQ_SIZE_CONFIG_C, 810 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, 811 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, 812 DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size, 813 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, 814 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); 815 816 REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 817 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, &rq_regs->aperture_high_addr); 818 819 REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 820 MC_VM_SYSTEM_APERTURE_LOW_ADDR, &rq_regs->aperture_low_addr); 821 822 /* DLG - Per hubp */ 823 REG_GET_2(BLANK_OFFSET_0, 824 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end, 825 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end); 826 827 REG_GET(BLANK_OFFSET_1, 828 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start); 829 830 REG_GET(DST_DIMENSIONS, 831 REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal); 832 833 REG_GET_2(DST_AFTER_SCALER, 834 REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler, 835 DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler); 836 837 REG_GET_2(PREFETCH_SETTINGS, 838 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 839 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 840 841 REG_GET_2(VBLANK_PARAMETERS_0, 842 DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank, 843 DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank); 844 845 REG_GET(REF_FREQ_TO_PIX_FREQ, 846 REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq); 847 848 /* DLG - Per luma/chroma */ 849 REG_GET(VBLANK_PARAMETERS_1, 850 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l); 851 852 REG_GET(VBLANK_PARAMETERS_3, 853 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); 854 855 REG_GET(NOM_PARAMETERS_0, 856 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l); 857 858 REG_GET(NOM_PARAMETERS_1, 859 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l); 860 861 REG_GET(NOM_PARAMETERS_4, 862 DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l); 863 864 REG_GET(NOM_PARAMETERS_5, 865 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l); 866 867 REG_GET_2(PER_LINE_DELIVERY_PRE, 868 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l, 869 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c); 870 871 REG_GET_2(PER_LINE_DELIVERY, 872 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l, 873 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c); 874 875 REG_GET(PREFETCH_SETTINGS_C, 876 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 877 878 REG_GET(VBLANK_PARAMETERS_2, 879 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c); 880 881 REG_GET(VBLANK_PARAMETERS_4, 882 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c); 883 884 REG_GET(NOM_PARAMETERS_2, 885 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c); 886 887 REG_GET(NOM_PARAMETERS_3, 888 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c); 889 890 REG_GET(NOM_PARAMETERS_6, 891 DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c); 892 893 REG_GET(NOM_PARAMETERS_7, 894 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c); 895 896 /* TTU - per hubp */ 897 REG_GET_2(DCN_TTU_QOS_WM, 898 QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm, 899 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm); 900 901 REG_GET_2(DCN_GLOBAL_TTU_CNTL, 902 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank, 903 QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip); 904 905 /* TTU - per luma/chroma */ 906 /* Assumed surf0 is luma and 1 is chroma */ 907 908 REG_GET_3(DCN_SURF0_TTU_CNTL0, 909 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l, 910 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l, 911 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l); 912 913 REG_GET(DCN_SURF0_TTU_CNTL1, 914 REFCYC_PER_REQ_DELIVERY_PRE, 915 &ttu_attr->refcyc_per_req_delivery_pre_l); 916 917 REG_GET_3(DCN_SURF1_TTU_CNTL0, 918 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c, 919 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c, 920 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c); 921 922 REG_GET(DCN_SURF1_TTU_CNTL1, 923 REFCYC_PER_REQ_DELIVERY_PRE, 924 &ttu_attr->refcyc_per_req_delivery_pre_c); 925 926 /* Rest of hubp */ 927 REG_GET(DCSURF_SURFACE_CONFIG, 928 SURFACE_PIXEL_FORMAT, &s->pixel_format); 929 930 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 931 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi); 932 933 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 934 SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo); 935 936 REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 937 PRI_VIEWPORT_WIDTH, &s->viewport_width, 938 PRI_VIEWPORT_HEIGHT, &s->viewport_height); 939 940 REG_GET_2(DCSURF_SURFACE_CONFIG, 941 ROTATION_ANGLE, &s->rotation_angle, 942 H_MIRROR_EN, &s->h_mirror_en); 943 944 REG_GET(DCSURF_TILING_CONFIG, 945 SW_MODE, &s->sw_mode); 946 947 REG_GET(DCSURF_SURFACE_CONTROL, 948 PRIMARY_SURFACE_DCC_EN, &s->dcc_en); 949 950 REG_GET_3(DCHUBP_CNTL, 951 HUBP_BLANK_EN, &s->blank_en, 952 HUBP_TTU_DISABLE, &s->ttu_disable, 953 HUBP_UNDERFLOW_STATUS, &s->underflow_status); 954 955 REG_GET(HUBP_CLK_CNTL, 956 HUBP_CLOCK_ENABLE, &s->clock_en); 957 958 REG_GET(DCN_GLOBAL_TTU_CNTL, 959 MIN_TTU_VBLANK, &s->min_ttu_vblank); 960 961 REG_GET_2(DCN_TTU_QOS_WM, 962 QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, 963 QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm); 964 965 REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS, 966 PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_lo); 967 968 REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 969 PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_hi); 970 971 s->uclk_pstate_force = REG_READ(UCLK_PSTATE_FORCE); 972 973 s->hubp_cntl = REG_READ(DCHUBP_CNTL); 974 s->flip_control = REG_READ(DCSURF_FLIP_CONTROL); 975 } 976 977 void hubp401_set_unbounded_requesting(struct hubp *hubp, bool enable) 978 { 979 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 980 981 REG_UPDATE(DCHUBP_CNTL, HUBP_UNBOUNDED_REQ_MODE, enable); 982 983 /* To ensure that cursor fetching starts as early as possible in 984 * the display prefetch, set CURSOR_REQ_MODE = 1 always. 985 * The setting of CURSOR_REQ_MODE = 0 is no longer supported in 986 * DCN4x as a fall back to legacy behavior of fetching cursor 987 * just before it appears on the screen. 988 */ 989 REG_UPDATE(CURSOR_CONTROL, CURSOR_REQ_MODE, 1); 990 } 991 992 static struct hubp_funcs dcn401_hubp_funcs = { 993 .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, 994 .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, 995 .hubp_program_surface_flip_and_addr = hubp401_program_surface_flip_and_addr, 996 .hubp_program_surface_config = hubp401_program_surface_config, 997 .hubp_is_flip_pending = hubp2_is_flip_pending, 998 .hubp_setup2 = hubp401_setup, 999 .hubp_setup_interdependent2 = hubp401_setup_interdependent, 1000 .hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings, 1001 .set_blank = hubp2_set_blank, 1002 .set_blank_regs = hubp2_set_blank_regs, 1003 .hubp_reset = hubp_reset, 1004 .mem_program_viewport = hubp401_set_viewport, 1005 .set_cursor_attributes = hubp32_cursor_set_attributes, 1006 .set_cursor_position = hubp401_cursor_set_position, 1007 .hubp_clk_cntl = hubp2_clk_cntl, 1008 .hubp_vtg_sel = hubp2_vtg_sel, 1009 .dmdata_set_attributes = hubp3_dmdata_set_attributes, 1010 .dmdata_load = hubp2_dmdata_load, 1011 .dmdata_status_done = hubp2_dmdata_status_done, 1012 .hubp_read_state = hubp401_read_state, 1013 .hubp_clear_underflow = hubp2_clear_underflow, 1014 .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, 1015 .hubp_init = hubp401_init, 1016 .set_unbounded_requesting = hubp401_set_unbounded_requesting, 1017 .hubp_soft_reset = hubp31_soft_reset, 1018 .hubp_set_flip_int = hubp401_set_flip_int, 1019 .hubp_in_blank = hubp401_in_blank, 1020 .phantom_hubp_post_enable = hubp32_phantom_hubp_post_enable, 1021 .hubp_update_mall_sel = hubp401_update_mall_sel, 1022 .hubp_prepare_subvp_buffering = hubp32_prepare_subvp_buffering, 1023 .hubp_program_mcache_id_and_split_coordinate = hubp401_program_mcache_id_and_split_coordinate, 1024 .hubp_update_3dlut_fl_bias_scale = hubp401_update_3dlut_fl_bias_scale, 1025 .hubp_program_3dlut_fl_mode = hubp401_program_3dlut_fl_mode, 1026 .hubp_program_3dlut_fl_format = hubp401_program_3dlut_fl_format, 1027 .hubp_program_3dlut_fl_addr = hubp401_program_3dlut_fl_addr, 1028 .hubp_program_3dlut_fl_dlg_param = hubp401_program_3dlut_fl_dlg_param, 1029 .hubp_enable_3dlut_fl = hubp401_enable_3dlut_fl, 1030 .hubp_program_3dlut_fl_addressing_mode = hubp401_program_3dlut_fl_addressing_mode, 1031 .hubp_program_3dlut_fl_width = hubp401_program_3dlut_fl_width, 1032 .hubp_program_3dlut_fl_tmz_protected = hubp401_program_3dlut_fl_tmz_protected, 1033 .hubp_program_3dlut_fl_crossbar = hubp401_program_3dlut_fl_crossbar, 1034 .hubp_get_3dlut_fl_done = hubp401_get_3dlut_fl_done, 1035 .hubp_clear_tiling = hubp401_clear_tiling, 1036 }; 1037 1038 bool hubp401_construct( 1039 struct dcn20_hubp *hubp2, 1040 struct dc_context *ctx, 1041 uint32_t inst, 1042 const struct dcn_hubp2_registers *hubp_regs, 1043 const struct dcn_hubp2_shift *hubp_shift, 1044 const struct dcn_hubp2_mask *hubp_mask) 1045 { 1046 hubp2->base.funcs = &dcn401_hubp_funcs; 1047 hubp2->base.ctx = ctx; 1048 hubp2->hubp_regs = hubp_regs; 1049 hubp2->hubp_shift = hubp_shift; 1050 hubp2->hubp_mask = hubp_mask; 1051 hubp2->base.inst = inst; 1052 hubp2->base.opp_id = OPP_ID_INVALID; 1053 hubp2->base.mpcc_id = 0xf; 1054 1055 return true; 1056 } 1057